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16-BIT DIGITAL-TO-ANALOG CONVERTERS

FEATURES

l HIGH-SPEED 16-BIT PARALLEL, 8-BIT (BYTE) PARALLEL, AND SERIAL INPUT MODES l DOUBLE-BUFFERED INPUT REGISTER CONFIGURATION l VOUT AND IOUT MODELS l HIGH ACCURACY: Linearity Error ±0.003% of FSR max Differential Linearity Error ±0.006% of FSR max l MONOTONIC (TO 14 BITS) OVER SPECIFIED TEMPERATURE RANGE l HERMETICALLY SEALED l LOW COST PLASTIC VERSIONS AVAILABLE (DAC707JP/KP)

DESCRIPTION

The DAC708 and DAC709 are 16-bit converters de- signed to interface to an 8-bit microprocessor bus. 16- bit data is loaded in two successive 8-bit bytes into parallel 8-bit latches before being transferred into the D/A latch. The DAC708 and DAC709 are current and voltage output models respectively and are in 24-pin hermetic DIPs. Input coding is Binary Two’s Comple- ment (bipolar) or Unipolar Straight Binary (unipolar, when an external logic inverter is used to invert the MSB). In addition, the DAC708/709 can be loaded serially (MSB first). The DAC707 is designed to interface to a 16-bit bus. Data is written into a 16-bit latch and subsequently the D/A latch. The DAC707 has bipolar voltage output and input coding is Binary Two’s Complement (BTC). All models have Write and Clear control lines as well as input latch enable lines. In addition, DAC708 and DAC709 have Chip Select control lines. In the bipolar mode, the Clear input sets the D/A latch to give zero voltage or current output. They are all 14-bit accurate and are complete with reference, and for the DAC707, and DAC709, a voltage output amplifier. All models are available with an optional burn-in screening. DAC707/708/709 Block Diagram High Byte Latch Latch Enables/ Mode Select Control Logic CLEAR WRITE CHIP SELECT 16-Bit D/A Con- verter DAC707 or DAC709 Only Summing Junction (708, 709) 10V Range (708, 709) VOUT Reference Circuit Bipolar Offset Low Byte Latch D/A Latch Serial (DAC708, 709) 8-Bit (DAC708, 709) or 16-Bit (DAC707) Serial Data PDS-557H International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 DAC707 DAC708 DAC709 SBAS145

At TA = +25°C, VCC = ±15V, VDD = +5V, and after a 10-minute warm-up, unless otherwise noted. DAC707/708/709KH, DAC707/708/ DAC707JP DAC707KP 709BH, SH PRODUCT MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS INPUT DIGITAL INPUT Resolution 16 * * Bits Bipolar Input Code (all models) Binary Two’s Complement * * Unipolar Input Code(1) (DAC708/709 only) Unipolar Straight Binary * Logic Levels(2): VIH +2.0 +5.5 * * * * V IIH (VI = +2.7V) 1 * * µA IIL (VI = +0.4V) 1 * * µA TRANSFER CHARACTERISTICS ACCURACY (3) Linearity Error ±0.003 ±0.006 ±0.0015 ±0.003 * * % of FSR (4) Differential Linearity Error(5) ±0.0045 ±0.012 ±0.003 ±0.006 * * % of FSR at Bipolar Zero(5, 6) ±0.003 ±0.006 ±0.0015 ±0.003 % of FSR Zero Error(7) ±0.05 ±0.1 * * * * % of FSR Monotonicity Over Spec Temp Range 13 14 14 Bits Power Supply Sensitivity: +VCC, –VCC ±0.0015 ±0.006 * * * ±0.003 % of FSR/%V CC VDD ±0.0001 ±0.001 * * * * % of FSR/%V DD DRIFT (Over Spec Temp Range(3)) Total Error Over Temp Range(8) ±0.08 * ±0.15 * ±0.10 % of FSR Total Full Scale Drift ±10 * ±25 * ±15 ppm of FSR/ °C Gain Drift ±10 ±30 * ±25 ±7 ±15 ppm/ °C Zero Drift: Unipolar (DAC708/709 only) ±2.5 ±5 ±1.5 ±3 ppm of FSR/ °C Bipolar (all models) ±5 ±15 * ±12 ±4 ±10 ppm of FSR/ °C Differential Linearity Over Temp(5) ±0.012 +0.009, * –0.006 % of FSR Linearity Error Over Temp(5) ±0.012 ±0.006 * % of FSR SETTLING TIME (to ±0.003% of FSR)(9) Voltage Output Models Full Scale Step (2kΩ load) 4 * 8 * 8 µs 1LSB Step at Worst Case Code(10) 2.5 * 4 * 4 µs Slew Rate 10 * * V/ µs Current Output Models Full Scale Step (2mA): 10 to 100Ω Load 350 * ns 1kΩ Load 1 * µs OUTPUT VOLTAGE OUTPUT MODELS Output Voltage Range DAC709: Unipolar (USB Code) 0 to +10 * V Bipolar (BTC Code) ±5, ±10 * V DAC707 Bipolar (BTC Code) ±10 * * V Output Current ±5* * m A Output Impedance 0.15 * * Ω Short Circuit to Common Duration Indefinite * * CURRENT OUTPUT MODELS Output Current Range (±30% typ) DAC708: Unipolar (USB Code) 0 to –2 * mA Bipolar (BTC Code) ±1* m A Unipolar Output Impedance (±30% typ) 4.0 * k Ω Bipolar Output Impedance (±30% typ) 2.45 * k Ω Compliance Voltage ±2.5 * V The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

PRODUCT PACKAGE NUMBER (1) DAC707JP 28-Pin Plastic DBL Wide DIP 215 DAC707KP 28-Pin Plastic DBL Wide DIP 215 DAC707BH 28LD Side Brazed 149 Hermetic Dip DAC707KH 28LD Side Brazed 149 Hermetic DIP DAC707SH 28LD Side Brazed 149 Hermetic DIP DAC708BH 24LD Side Brazed 165 Hermetic DIP DAC708KH 24LD Side Brazed 165 Hermetic DIP DAC708SH 24LD Side Brazed 165 Hermetic DIP DAC709BH 24LD Side Brazed 165 Hermetic DIP DAC709KH 24LD Side Brazed 165 Hermetic DIP DAC709SH 24LD Side Brazed 165 Hermetic DIP NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. DAC707/708/709KH, DAC707/708/ DAC707JP DAC707KP 709BH, SH PRODUCT MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS At TA = +25°C, VCC = ±15V, VDD = +5V, and after a 10-minute warm-up, unless otherwise noted. ELECTRICAL (CONT) *Specification same as for models in column to the left. NOTES: (1) MSB must be inverted externally prior to DAC708/709 input. (2) Digital inputs are TTL, LSTTL, 54/74C, 54/74HC and 54/74HTC compatible over the specified temperature range. (3) DAC708 (current-output models) are specified and tested with an external output operational amplifier connected using the internal feedback resistor in all tests. (4) FSR means Full Scale Range. For example, for ±10V output, FSR = 20V. (5) ±0.0015% of Full Scale Range is equal to 1 LSB in 16-bit resolution, (For unipolar connection on DAC708/709, the MSB must be inverted externally prior to D/A input.) (7) Adjustable to zero with external trim potentiometer. Adjusting the gain potentiometer rotates the transfer function around the bipolar zero point. (8) With gain and zero errors adjusted to zero at +25°C. (9) Maximum represents the 3σ limit. Not 100% tested for this parameter. (10) The bipolar worst-case code change is FFFFH to 0000H and 0000H to FFFFH . For unipolar (DAC708/709 only) it is 7FFFH to 8000H and 8000H to 7FFFH . POWER SUPPLY REQUIREMENTS Voltage (all models): +VCC +13.5 +15 +16.5 * * * * * * V Current (No Load, +15V Supplies) Current Output Models: +VCC +10 +25 * * mA VDD +5 +10 * * mA Voltage Output Models: +VCC +16 +30 * * * * mA Power Dissipation (±15V supplies) Current Output Models 370 800 * * mW Voltage Output Models 535 * 950 * * mW TEMPERATURE RANGE Specification: BH Grades –25 +85 °C JP, KP, KH Grades 0 +70 * * °C SH Grades –55 +125 °C Storage: Ceramic –65 +150 –65 +150 °C Plastic –60 +100 * * °C PACKAGE INFORMATION ABSOLUTE MAXIMUM RATINGS External Voltage Applied to D/A Output Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

A A A D7 (D15) D6 (D14) D5 (D13) D4 (D12) D3 (D11) D2 (D10) D1 (D9) D0 (D8)/S1 DCOM V CS WR CLR GA BPO SJ ACOM V R DD CC F CC DDV+ (2) (2) (2)(3) + CC CC (1) (1) 3.9M 270k Offset Adjust Gain Adjust Ω Ω Control Lines Connect for bipolar operation. Connect for 10V range. Leave pin 13 open for 20V range. ΩΩ 10kΩ DAC709 Only 16-Bit Ladder Resistor Network and Current Switches Reference Circuit D/A Latch Low Byte Latch High Byte Latch D0 (LSB) D10 D11 D12 D13 R 16-Bit Ladder Resistor Network and Current Switches D/A Latch Input Latch Digital Inputs V V CLR WR A A (2) (3) (1) 3.9M 270k Ω Ω NOTES: (1) Potentiometers are 10k to 100k . (2) Decoupling capcitors are 0.1µF to 1.0µF. (3) Bypass, 0.0022µF to 0.01µF. DD CC–V CC+V (2) Digital Inputs Latch Enable Lines Control Lines Gain Adjust Analog Common CC Offset Adjust Digital Common (2) VDD OUT NOTES: (1) Potentiometer is 10k to 100k . (2) Decoupling capcitors are 0.1µF to 1.0µF. DAC708/709 DAC707 Register Enable Lines Data Inputs DCOM ACOM SJ GA (MSB) D15 D14 ΩΩ 10kΩ CC

ORDERING INFORMATION

PRODUCT RANGE CONFIGURATION CONFIGURATION DAC707JP 0 °C to +70°C 16-bit port ±10V output DAC707JP-BI(1) 0°C to +70°C 16-bit port ±10V output DAC707KP 0 °C to +70°C 16-bit port ±10V output DAC707KP-BI (1) 0°C to +70°C 16-bit port ±10V output DAC707KH 0 °C to +70°C 16-bit port ±10V output DAC707KH-BI (1) 0°C to +70°C 16-bit port ±10V output DAC707BH –25 °C to +85°C 16-bit port ±10V output DAC707BH-BI (1) –25°C to +85°C 16-bit port ±10V output DAC707SH –55 °C to +125°C 16-bit port ±10V output DAC707SH-BI (1) –55°C to +125°C 16-bit port ±10V output DAC708KH 0 °C to +70°C 8-bit port ±1mA output DAC708BH –25 °C to +85°C 8-bit port ±1mA output DAC708SH –55 °C to +125°C 8-bit port ±1mA output DAC709KH 0 °C to +70°C 8-bit port ±10V output DAC709BH –25 °C to +85°C 8-bit port ±10V output DAC709SH –55 °C to +125°C 8-bit port ±10V output NOTE: (1) 25 piece minimum order.

DESCRIPTION OF PIN FUNCTIONS DAC707 Pin DAC708/709 DESIGNATOR DESCRIPTION # DESIGNATOR DESCRIPTION VOUT Voltage output for DAC707 (±10V) 1 A 2 Latch enable for D/A latch (Active low) VDD Logic supply (+5V) 2 A 0 Latch enable for “low byte” input (Active low). When both A0 and A1 are logic “0”, the serial input mode is selected and the serial input is enabled. DCOM Digital common 3 A 1 Latch enable for “high byte” input (Active low). When both A0 and A1 are logic “0”, the serial input mode is selected and the serial input is enabled. ACOM Analog common 4 D7 (D15) Input for data bit 7 if enabling low byte (LB) latch or data bit 15 if enabling the high byte (HB) latch. SJ Summing junction of the internal output op amp for the 5 D6 (D14) Input for data bit 6 if enabling LB latch or data bit 14 if DAC707. Offset adjust circuit is connected to the enabling the HB latch. summing junction of the output amplifier. Refer to Block Diagram. GA Gain adjust pin. Refer to Connection Diagram for gain 6 D5 (D13) Data bit 5 (LB) or data bit 13 (HB) adjust circuit. +VCC Positive supply voltage (+15V) 7 D4 (D12) Data bit 4 (LB) or data bit 12 (HB) –VCC Negative supply voltage (–15V) 8 D3 (D11) Data bit 3 (LB) or data bit 11 (HB) CLR Clear line. Sets the input latch to zero and sets the D/A 9 D2 (D10) Data bit 2 (LB) or data bit 10 (HB) latch to the input code that gives bipolar zero on the D/A output (Active low) WR Write control line (Active low) 10 D1 (D9) Data bit 1 (LB) or data bit 9 (HB) A1 Enable for D/A converter latch (Active low) 11 D0 (D8)/SI Data bit 0 (LB) or data bit 8 (HB). Serial input when serial mode is selected. A0 Enable for input latch (Active low) 12 DCOM Digital common D15 (MSB) Data bit 15 (Most Significant Bit) 13 R F2 Feedback resistor for internal or external operational amplifier. Connect to pin 14 when a 10V output range is desired. Leave open for a 20V output range. D14 Data bit 14 14 V OUT Voltage output for DAC709 or feedback resistor for R F1 (DAC708) use with an external output op amp for the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708. D13 Data bit 13 15 ACOM Analog common D12 Data bit 12 16 SJ (DAC709) Summing junction of the internal output op amp for the IOUT (DAC708) DAC709, or the current output for the DAC708. Refer to Connection Diagram for connection of external op amp to DAC708. D11 Data bit 11 17 BPO Bipolar offset. Connect to pin 16 when operating in the bipolar mode. Leave open for unipolar mode. D10 Data bit 10 18 GA Gain adjust pin D9 Data bit 9 19 +V CC Positive supply voltage (+15V) D8 Data bit 8 20 –V CC Negative supply voltage (–15V) D7 Data bit 7 21 CLR Clear line. Sets the high and low byte input registers to zero and, for bipolar operation, sets the D/A register to the input code that gives bipolar zero on the D/A output. (In the unipolar mode, invert the MSB prior to the D/A.) D6 Data bit 6 22 WR Write control line D5 Data bit 5 23 CS Chip select control line D4 Data bit 4 24 V DD Logic supply (+5V) D3 Data bit 3 25 No pin D2 Data bit 2 26 No pin (The DAC708 and DAC709 are in 24-pin packages) D1 Data bit 1 27 No pin D0 (LSB) Data bit 0 (Least Significant Bit) 28 No pin

an external inverter. See Table I. typical values for this family of products. FIGURE 1. Final-Value Error Band Versus Full-Scale Range factor in determining settling time for large resistive loads. pin while still being able to maintain specified accuracy. TABLE I. Digital Input Codes. lution) insures monotonicity. over the entire specification temperature range. and (3) dividing by the temperature change.

TABLE II. Digital Input and Analog Output Voltage/Current Relationships. NOTE: (1) MSB assumed to be inverted externally. the latch or latches which have been enabled. going to logic “0” the same as in the parallel input mode. null, or zero, at the output of the D/A in the bipolar mode. to go to one-half of full scale. into the input shift register is 10MHz. The timing of the control signals is given in Figure 6. FIGURE 6. Logic Timing Diagram. mode and no CHIP SELECT (CS) line. long would cause a 1LSB error.

signal lines need to be isolated. The data is applied to pin 11 in a serial bit stream, MSB first. The WR input is used as a data strobe, clocking in each data bit. A RESET signal is provided for system startup and reset. These three signals are each optically isolated. Once the 16 bits of serial data have been strobed into the input register pair, the data is strobed through to the D/A register by the “carry” signal out of a 4-bit binary synchronous counter that has counted the 16 WR pulses used to clock in the data. The circuit diagram is given in Figure 10. CONNECTING MULTIPLE DAC707s TO A 16-BIT MICROPROCESSOR BUS Figure 11 illustrates the method of connecting multiple DAC707s to a 16-bit microprocessor bus. The circuit shown has two DAC707s and uses only one address line to select either the input register or the D/A register. An external address decoder selects the desired converter. BURN-IN SCREENING Burn-in screening is an option available for the DAC707. Burn-in duration is 160 hours at the temperature shown below (or equivalent combination of time and temperature). Product Temp. Range Burn-In Screening DAC707JP-BI 0 °C to 70°C 100 °C DAC707KP-BI 0 °C to 70°C 100 °C DAC707KH-BI –25 °C to +85°C 125 °C DAC707BH-BI –25 °C to +85°C 125 °C DAC707SH-BI –55 °C to +125°C 125 °C All units are tested after burn-in to ensure that grade speci- fications are met.

APPLICATIONS

LOADING THE DAC709 SERIALLY ACROSS AN ISOLATION BARRIER A very useful application of the DAC709 is in achieving low-cost isolation that preserves high accuracy. Using the serial input feature of the input register pair, only three

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) DAC707JP NRND PDIP NTD 28 13 TBD CU SNPB N / A for Pkg Type DAC707JP-BI OBSOLETE PDIP NTD 28 TBD Call TI Call TI DAC707KP NRND PDIP NTD 28 13 TBD CU SNPB N / A for Pkg Type DAC707KP-5 OBSOLETE PDIP NTD 28 TBD Call TI Call TI DAC707KP-7 OBSOLETE PDIP NTD 28 TBD Call TI Call TI DAC707KP-BI OBSOLETE PDIP NTD 28 TBD Call TI Call TI DAC709KH OBSOLETE CDIP SB JDM 24 TBD Call TI Call TI DAC709KH-2 OBSOLETE CDIP SB JDM 24 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 3-Jul-2009 Addendum-Page 1

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