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DAC701, 702, 703 Monolithic 16-Bit DIGITAL-TO-ANALOG CONVERTERS
FEATURES
l HIGH ACCURACY: Linearity Error ±0.0015% of FSR max Differential Linearity Error ±0.003% of FSR max DAC701 DAC702 DAC703 16-Bit Ladder Resistor Network And Current Switches Digital Inputs Reference Circuit Reference Output Summing Junction Output Common Gain Adjust V CC CC DD Voltage Models Only International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 l MONOTONIC (at 15 bits) OVER FULL SPECIFICATION TEMPERATURE RANGE l PIN-COMPATIBLE WITH DAC70, DAC71, DAC72 l DUAL-IN-LINE PLASTIC AND HERMETIC CERAMIC AND SOIC
DESCRIPTION
The DAC70X family comprise of complete 16-bit digital-to-analog converters that includes a precision buried-zener voltage reference and a low-noise, fast- settling output operational amplifier (voltage output models), all on one small monolithic chip. A combina- tion of current-switch design techniques accomplishes not only 15-bit monotonicity over the entire specified temperature range, but also a maximum end-point linearity error of ±0.0015% of full-scale range. Total full-scale gain drift is limited to ±10ppm/°C maximum (LH and CH grades). Digital inputs are complementary binary coded and are TTL-, LSTTL-, 54/74C- and 54/74HC-compatible over the entire temperature range. Outputs of 0 to +10V, ±10V, 0 to –2mA, and ±1mA are available. These D/A converters are packaged in hermetic 24-pin ceramic side-brazed or molded plastic. The DIP-pack- aged parts are pin-compatible with the voltage and current output DAC71 and DAC72 model families. The DAC702 is also pin-compatible with the DAC70 model family. In addition, the DAC703 is offered in a 24-pin SOIC package for surface mount applications. © 1983 Burr-Brown Corporation PDS-494M Printed in U.S.A. March, 1998 DAC701 DAC702 DAC703 SBAS143
DAC701, 702, 703 SPECIFICATIONS At +25°C and rated power supplies, unless otherwise noted. DAC702/703J DAC701/702/703K DAC701/702/703B, S DAC701/702/703L, C PARAMETER MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS INPUT DIGITAL INPUT Resolution 16 [[ [ Bits Digital Inputs (1) VIH +2.4 +V CC [[ [ [ [ [ V IIH, VI = +2.7V +40 [[ [ µA TRANSFER CHARACTERISTICS ACCURACY (2) Differential Linearity Differential Linearity Error at Bipolar Zero (DAC702/703) Zero Error(5, 6) ±0.05 ±0.10 [ [ [[ [[ % of FSR Monotonicity Over Spec. Temp Range 13 14 [ 15 Bits DRIFT (over specification temperature range) Total Error Over Temperature Range (all models)(7) ±0.08 [ ±0.15 ±0.05 ±0.10 [[ % of FSR Total Full Scale Drift: DAC701 ±10 [ ±30 ±8.5 ±18 ±6 ±13 ppm of FSR/ °C DAC702/703 ±10 [ ±25 ±7 ±15 [[ ppm of FSR/°C Gain Drift (all models) ±10 ±30 [ ±25 ±7 ±15 ±5 ±10 ppm/ °C Zero Drift: DAC701 ±2.5 ±5 ±1.5 ±3 [[ ppm of FSR/°C DAC702/703 ±5 ±15 [ ±12 ±4 ±10 ±2.5 ±5 ppm of FSR/ °C Differential Linearity Over Temp.(4) ±0.012 +0.009, [ +0.006, % of FSR –0.006 –0.003 Linearity Error Over Temp. SETTLING TIME (to ±0.003% of FSR)(8) DAC701/703 (VOUT Models) Full Scale Step, 2kΩ Load 4 [ 8 [[ [[ µs 1LSB Step at Worst-Case Code(9) 2.5 [[ [ µs Slew Rate 10 [[ [ V/µs DAC702 (IOUT Models) Full Scale Step (2mA), 10 to 100Ω Load 350 [ 1000 [[ [[ ns 1kΩ Load 1 [ 3 [[ [[ µs OUTPUT VOLTAGE OUTPUT MODELS DAC701 (CSB Code) 0 to +10 [ V DAC703 (COB Code) ±10 [[ [ V Output Current ±5 [[ [ mA Output Impedance 0.15 [[ [ Ω Short Circuit to Common Duration Indefinite [[ [ CURRENT OUTPUT MODELS DAC702 (COB Code)(10) ±1 [[ [ mA Output Impedance(10) 2.45 [[ [ kΩ Compliance Voltage ±2.5 [[ [ V
DAC701, 702, 703 The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. DAC702/703J DAC701/702/703K DAC701/702/703B, S DAC701/702/703L, C PARAMETER MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS REFERENCE VOLTAGE Source Current Available for External Loads +2.5 +1.5 [[ [ [ [ mA Temperature Coefficient ±10 [ ±25 [ ±15 [[ ppm/°C Short Circuit to Common Duration Indefinite [[ [ POWER SUPPLY REQUIREMENTS Voltage: +VCC 13.5 15 16.5 [ [[[[[ [[ [ V Current (No Load): DAC702 (IOUT Models) DAC701/703 (VOUT Models) Power Dissipation: (VDD = +5.0V)(11) DAC702 365 [ 790 [ 630 [[ mW DAC701/703 530 [ 940 [ 780 [[ mW Power Supply Rejection: VDD ±0.0001 ±0.001 [[ [[ [ [ % of FSR/%VDD TEMPERATURE RANGE Specification: B, C Grades –25 +85 [[ °C S Grades –55 +125 °C J, K, L Grades 0 +70 [[ 0 +70 °C Storage: Ceramic –60 +150 [[ [ [ °C Plastic, SOIC –60 +100 [[ °C [ Specification same as model to the left. NOTES: (1) Digital inputs are TTL, LSTTL, 54/74C, 54/74HC, and 54/74HTC compatible over the operating voltage range of VDD = +5V to +15V and over the specified temperature range. The input switching threshold remains at the TTL threshold of 1.4V over the supply range of VDD = +5V to +15V. As logic “0” and logic “1” inputs vary over 0V to +0.8V and +2.4V to +10V respectively, the change in the D/A converter output voltage will not exceed ±0.0015% of FSR for the LH and CH grades, ±0.003% of FSR for the BH grade and ±0.006% of FSR for the KG grade. (2) DAC702 (current-output models) is specified and tested with an external output operational amplifier connected using the internal feedback resistor in all parameters except settling time. (3) FSR means full-scale range and is 20V for the ±10V range (DAC703), 10V for the 0 to +10V range 1LSB in 14-bit resolution. ±0.006% of full-scale range is equivalent to 1LSB in 13-bit resolution. (5) Adjustable to zero with external trim potentiometer. Adjusting the gain potentiometer rotates the transfer function around the zero point. (6) Error at input code FFFFH for DAC701, 7FFFH for DAC702 and DAC703. (7) With gain and zero errors adjusted to zero at +25°C. (8) Maximum represents the 3σ limit. Not 100% tested for this parameter. (9) At the major carry, 7FFFH to 8000H and 8000H to 7FFFH . (10) Tolerance on output impedance and output current is ±30%. (11) Power dissipation is an additional 40mW when VDD is operated at +15V. SPECIFICATIONS (CONT) At +25°C and rated power supplies, unless otherwise noted.
DAC701, 702, 703 CONNECTION DIAGRAMS MSB 16-Bit Ladder Resistor Network and Current Switches Digital Inputs Reference Circuit R F (4) Voltage Models Only LSB Digital Inputs (2) +VCC 270kΩ 3.9MΩ (3) (3) 0.0022µF (2) (2) V DD CC (1) NOTES: (1) Can be tied to +VCC instead of having separate VDD supply. (2) Decoupling capacitors are 0.1µF to 1.0µF. (3) Potentiometers are 10kΩ to 100kΩ . (4) 5kΩ (DAC701), 10kΩ (DAC702/703). ALL PACKAGES PIN # DAC702 DAC701/703
1 Bit 1 (MSB) Bit 1 (MSB)
2 Bit 2 Bit 2
3 Bit 3 Bit 3
4 Bit 4 Bit 4
5 Bit 5 Bit 5
6 Bit 6 Bit 6
7 Bit 7 Bit 7
8 Bit 8 Bit 8
9 Bit 9 Bit 9
10 Bit 10 Bit 10
11 Bit 11 Bit 11
12 Bit 12 Bit 12
13 Bit 13 Bit 13
14 Bit 14 Bit 14
15 Bit 15 Bit 15
16 Bit 16 (LSB) Bit 16 (LSB)
18 V DD VDD
19 –V CC –VCC
20 Common Common
21 I OUT Summing Junction (Zero Adjust)
22 Gain Adjust Gain Adjust
24 +6.3V Reference Output +6.3V Reference Output ABSOLUTE MAXIMUM RATINGS (1) External Voltage Applied to R NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PIN ASSIGNMENTS ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DAC701, 702, 703 PACKAGE/ORDERING INFORMATION LINEARITY GAIN PACKAGE ERROR, MAX DRIFT, DRAWING OUTPUT TEMPERATURE AT+25 °C MAX PRODUCT PACKAGE NUMBER (1) CONFIGURATION RANGE (% of FSR) (ppm/ °C) DAC703JP 24-Pin Plastic DIP 167 ±1mA, ±10V 0 °C to +70°C ±0.006 ±30 DAC703KP 24-Pin Plastic DIP 167 ±1mA, ±10V 0 °C to +70°C ±0.003 ±25 DAC701KH 24-Pin Ceramic DIP 165 0 to –2mA, 0 to +10V 0 °C to +70°C ±0.003 ±25 DAC702KH 24-Pin Ceramic DIP 165 ±1mA, ±10V 0 °C to +70°C ±0.003 ±25 DAC703KH 24-Pin Ceramic DIP 165 ±1mA, ±10V 0 °C to +70°C ±0.003 ±25 DAC701BH 24-Pin Ceramic DIP 165 0 to –2mA, 0 to +10V –25 °C to +85°C ±0.003 ±15 DAC702BH 24-Pin Ceramic DIP 165 ±1mA, ±10V –25 °C to +85°C ±0.003 ±15 DAC703BH 24-Pin Ceramic DIP 165 ±1mA, ±10V –25 °C to +85°C ±0.003 ±15 DAC701LH 24-Pin Ceramic DIP 165 0 to –2mA, 0 to +10V 0 °C to +70°C ±0.0015 ±10 DAC702LH 24-Pin Ceramic DIP 165 ±1mA, ±10V 0 °C to +70°C ±0.0015 ±10 DAC703LH 24-Pin Ceramic DIP 165 ±1mA, ±10V 0 °C to +70°C ±0.0015 ±10 DAC701CH 24-Pin Ceramic DIP 165 0 to –2mA, 0 to +10V –25 °C to +85°C ±0.0015 ±10 DAC702CH 24-Pin Ceramic DIP 165 ±1mA, ±10V –25 °C to +85°C ±0.0015 ±10 DAC703CH 24-Pin Ceramic DIP 165 ±1mA, ±10V –25 °C to +85°C ±0.0015 ±10 DAC701SH 24-Pin Ceramic DIP 165 0 to –2mA, 0 to +10V –55 °C to +125°C ±0.003 ±15 DAC702SH 24-Pin Ceramic DIP 165 ±1mA, ±10V –55 °C to +125°C ±0.003 ±15 DAC703SH 24-Pin Ceramic DIP 165 ±1mA, ±10V –55 °C to +125°C ±0.003 ±15 DAC703JU 24-Pin SOIC 239 ±10V 0 °C to +70°C ±0.006 ±30 DAC703KU 24-Pin SOIC 239 ±10V 0 °C to +70°C ±0.003 ±25 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
scale range per degree centigrade (ppm of FSR/°C). typical values for this family of products. factor in determining settling time for large resistive loads. TABLE I. Digital Input Codes. resolution) insures monotonicity. over the entire specification temperature range. +25°C value; and (3) dividing by the temperature change. FIGURE 1. Final-Value Error Band vs Full-Scale Range pin while still being able to maintain specified accuracy.
nominal power supply voltages (see Figure 2). frequency changes in power supply voltages. FIGURE 2. Power Supply Rejection vs Power Supply Ripple external load should remain constant. the reference) from load variations. located close to the D/A converter. adjustments to unipolar and bipolar D/A converters.FIGURE 3. Equivalent Resistances. FIGURE 4. Relationship of Zero and Gain Adjustments for Unipolar D/A Converters, DAC701.
0000 MSB on All
FIGURE 5. Relationship of Zero and Gain Adjustments for Bipolar D/A Converters, DAC702 and DAC703.
point) is shown in Figures 6, 7, and 8. and is therefore greatly reduced by the loop gain. adjust the zero potentiometer for zero output. tion should be made before gain calibration. FIGURE 6. Output Circuit for Voltage Models.
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