Power Management

DAC60508MYZFR

Texas Instruments

Octal, 16-, 14-, 12-Bit, SPI, Voltage Output DAC with Internal Reference

Manufacturer: Texas Instruments

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GND Copyright © 2017, Texas Instruments Incorporated BUF Channel 3 OUT3 Channel 4 OUT4 Channel 5 OUT5 Channel 6 OUT6 Channel 7 OUT7 +1 OR +2 Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. DAC80508,DAC70508,DAC60508 SLASEL1C –JUNE 2017–REVISED APRIL 2018 DACx0508Octal,16-,14-,12-Bit,SPI,VoltageOutputDACwithInternalReference

1 Features

1• Performance – INL: ±1 LSB Maximum at 16-Bit Resolution – TUE: ±0.14% of FSR Maximum

Integrated 2.5 V Precision Internal Reference – Initial Accuracy: ±5 mV Maximum – Low Drift: 5 ppm/°C Typical
High Drive Capability: 20 mA with 0.5 V from Supply Rails
Flexible Output Configuration – User Selectable Gain: 2, 1 or ½ – Reset to Zero Scale or Midscale
Wide Operating Range – Power Supply: 2.7 V to 5.5 V – Temperature Range: –40˚C to 125˚C
50 MHz SPI Compatible Serial Interface – 4-Wire Mode, 1.7 V to 5.5 V Operation – Daisy Chain Operation – CRC Error Check
Low Power: 0.6 mA/Channel at 5.5 V
Small Packages: – 3 mm × 3 mm, 16-Pin WQFN – 2.4 mm x 2.4 mm, 16-Pin DSBGA

2 Applications

Optical Networking
Wireless Infrastructure
Industrial Automation
Data Acquisition Systems

3 Description

The DACx0508 is a pin-compatible family of low power, eight-channel, buffered voltage-output, digital- to-analog converters (DACs) with 16-, 14- and 12-bit resolution. The DACx0508 includes a 2.5-V, 5- ppm/°C internal reference, eliminating the need for an external precision reference in most applications. A user selectable gain configuration provides full-scale output voltages of 1.25 V (gain = ½), 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7-V to 5.5-V supply, is specified monotonic and provides high linearity of ±1 LSB INL. Communication to the DACx0508 is performed through a 4-wire serial interface that operates at clock rates up to 50 MHz. The VIO pin enables serial interface operation from 1.7 V to 5.5 V. The DACx0508 flexible interface enables operation with a wide range of industry-standard microprocessors and microcontrollers. The DACx0508 incorporates a power-on-reset circuit that powers up and maintains the DAC outptus at either zero scale or midscale until a valid code is written to the device. The device consumes low current of 0.6 mA/channel at 5.5 V, making it suitable for battery-operated equipment. A per-channel power- down feature reduces the device current consumption to 15 µA. The DACx0508 is characterized for operation over the temperature range of –40°C to 125°C and is available in small packages. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DACx0508(2) WQFN (16) 3.00 mm × 3.00 mm DSBGA (16) 2.40 mm x 2.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) DAC80508 Product Preview Simplified Block Diagram

12.2 Receiving Notification of Documentation Updates 42

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (January 2018) to Revision C Page

Changed DAC80508Z, DAC70508Z, DAC60508Z, DAC80508M, DAC70508M, DAC60508M to DAC80508, Changes from Revision A (December 2017) to Revision B Page Changes from Original (June 2017) to Revision A Page

5 Device Comparison Table

DEVICE RESOLUTION REFERENCE RESET DAC80508Z(1) 16-Bit Internal (default) / External Zero DAC80508M(1) Midscale DAC70508Z 14-Bit Internal (default) / External Zero DAC70508M Midscale DAC60508Z 12-Bit Internal (default) / External Zero DAC60508M Midscale

A B C D Not to scale OUT3 GND VDD OUT4 OUT1 OUT2 OUT6 OUT5 REF OUT0 OUT7 CS VIO SDO/ALARM SDI SCLK

16 VIO 5OUT3

15 SDO/ALARM6GND

14 SDI7VDD

13 SCLK8OUT4

6 Pin Configuration and Functions

NO. DSBGA NO. REF 1 C1 I/O When using internal reference, this is the reference output voltage pin (default). When using an external reference, this is the reference input pin to the device. OUT0 2 C2 O Analog output voltage from DAC 0. OUT1 3 B1 O Analog output voltage from DAC 1. OUT2 4 B2 O Analog output voltage from DAC 2. OUT3 5 A1 O Analog output voltage from DAC 3. GND 6 A2 GND Ground reference point for all circuitry on the device. VDD 7 A3 PWR Analog supply voltage (2.7 V to 5.5 V). OUT4 8 A4 O Analog output voltage from DAC 4. OUT5 9 B4 O Analog output voltage from DAC 5. OUT6 10 B3 O Analog output voltage from DAC 6. OUT7 11 C3 O Analog output voltage from DAC 7. CS 12 C4 I Active low serial data enable. This input is the frame synchronization signal for the serial data. When the signal goes low, it enables the serial interface input shift register. SCLK 13 D4 I Serial interface clock. SDI 14 D3 I Serial interface data input. Data are clocked into the input shift register on each falling edge of the SCLK pin. SDO/ALARM 15 D2 O Serial interface data output (default). The SDO pin is in high impedance when CS pin is high. Data are clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified by the FSDO bit. Alternatively the pin can be configured as an ALARM open-drain output to indicate a CRC or reference alarm event. If configured as ALARM a 10 kΩ, pull-up resistor to VIO is required. VIO 16 D1 PWR IO supply voltage (1.7 V to 5.5 V). This pin sets the I/O operating voltage for the serial interface. Thermal Pad – – – The thermal pad is located on the bottom-side of the WQFN package. The thermal pad should be connected to any internal PCB ground plane using multiple vias for good thermal performance.

DAC80508,DAC70508,DAC60508 www.ti.com SLASEL1C –JUNE 2017–REVISED APRIL 2018 Product Folder Links: DAC80508 DAC70508 DAC60508 Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Suppy voltage VDD to GND –0.3 6 V VIO to GND –0.3 6 Pin voltage DAC outputs to GND –0.3 VDD + 0.3 VREF to GND –0.3 VDD + 0.3 SCLK, SDI, SDO/ALARM and CS to GND –0.3 VIO + 0.3 Input current Input current to any pin except supply pins –10 10 mA Temperature Operating free-air, TA -40 125 °CJunction, TJ –40 150 Storage, Tstg –60 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per JEDEC Standard 22 Test Method A114- C.01(1) ±3000 V Charged-device model (CDM), per JEDEC Standard 22 Test Method C101, all pins(2) ±1000

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT POWER SUPPLY VDD Analog supply voltage 2.7 5.5 V VIO IO supply voltage 1.7 5.5 DIGITAL INPUTS Digital input voltage 0 VIO V REFERENCE INPUT VREFIN VDD = 2.7 V to 3.3 V Reference divider disabled 1.2 (VDD – 0.2)/2 V Reference divider enabled 2.4 VDD – 0.2 VDD = 3.3 V to 5.5 V Reference divider disabled 1.2 VDD/2 Reference divider enabled 2.4 VDD TEMPERATURE TA Operating free-air temperature –40 125 °C

DAC80508,DAC70508,DAC60508 SLASEL1C –JUNE 2017–REVISED APRIL 2018 www.ti.com Product Folder Links: DAC80508 DAC70508 DAC60508 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information

THERMAL METRIC(1) DACx0508 UNITRTE (WQFN) YZF (DSBGA)

16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 33.3 68.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 29.5 0.3 °C/W RθJB Junction-to-board thermal resistance 7.3 16.9 °C/W ψJT Junction-to-top characterization parameter 0.2 0.2 °C/W ψJB Junction-to-board characterization parameter 7.4 16.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 n/a °C/W (1) Static performance specified with DAC outputs unloaded for all gain options, unless otherwise noted. End point fit between codes. 16- bit: Code 256 to 65280, 14-bit: Code 128 to 16127, 12-bit: Code 16 to 4031

7.5 Electrical Characteristics

to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, TA = –40°C to 125°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE(1) Resolution DAC80508 16 BitsDAC70508 14 DAC60508 12 INL Integral nonlinearity DAC80508 ±0.5 ±1 LSBDAC70508 ±0.5 ±1 DAC60508 ±0.5 ±1 DNL Differential nonlinearity DAC80508. Specified 16-bit monotonic ±0.5 ±1 LSBDAC70508. Specified 14-bit monotonic ±0.5 ±1 DAC60508. Specified 12-bit monotonic ±0.5 ±1 TUE Total unadjusted error Gain = 1 and Gain = 2 ±0.06 ±0.14 %FSR Gain = ½ ±0.1 ±0.2 Offset error WQFN package: Gain = 1, Gain = 2 and Gain = ½. DSBGA package: Gain = 2 ±0.75 ±1.5 mV DSBGA package: Gain = 1 and Gain = ½ ±0.75 ±2.5 Zero-code error DAC code = zero scale 0.5 1.5 mV Full-scale error Gain = 1 and Gain = 2 ±0.075 ±0.14 % FSR Gain error ±0.05 ±0.14 % FSR Offset error drift ±1 µV/°C Zero-code error drift ±2 µV/°C Full-scale error drift ±2 ppm of FSR/°C Gain error drift ±1 ppm of FSR/°C Output voltage drift over time TA = 25°C, DAC code = midscale, 1600 hours 20 ppm of FSR

DAC80508,DAC70508,DAC60508 www.ti.com SLASEL1C –JUNE 2017–REVISED APRIL 2018 Product Folder Links: DAC80508 DAC70508 DAC60508 Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated Electrical Characteristics (continued) to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, TA = –40°C to 125°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (2) Temporary overload condition protection. Junction temperature can be exceeded during current limit. Operation above the specified maximum junction temperature may impair device reliability. (3) Specified by design and characterization. Not tested during production. (4) Time to exit DAC power-down mode. Measured from CS rising edge to 90% of DAC final value. OUTPUT CHARACTERISTICS Voltage range Gain = 2 (BUFF-GAIN = 1, REF-DIV = 0) 0 2 × VREF VGain = 1 (BUFF-GAIN = 1, REF-DIV = 1) 0 VREF Gain = ½ (BUFF-GAIN = 0, REF-DIV = 1) 0 ½ × VREF Output voltage headroom to GND or VDD (unloaded) 0.004 V to GND or VDD (-5 mA ≤ IOUT ≤ 5 mA) 0.15 to GND or VDD (-10 mA ≤ IOUT ≤ 10 mA) 0.3 to GND or VDD (-20 mA ≤ IOUT ≤ 20 mA) 0.5 Short circuit current(2) DAC code = full scale. Output shorted to GND 35 mA DAC code = zero scale. Output shorted to VDD 30 Load regulation DAC code = midscale, -10 mA ≤ IOUT ≤ 10 mA 85 µV/mA Maximum capacitive load(3) RLOAD = ∞ 0 2 nF RLOAD = 2 kΩ 0 10 DC output impedance DAC code = midscale 0.085 Ω DAC output at GND or VDD 15 DYNAMIC PERFORMANCE Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling time to ±2 LSB, VDD = 5.5 V, VREFIN = 2.5 V, Gain = 2 5 µs Slew rate VDD = 5.5 V, VREFIN = 2.5 V, Gain = 2 1.8 V/µs Power-up time DACx-PWDWN 1 to 0 transition. DAC code = full scale. VDD = 5.5 V, VREFIN = 2.5 V, Gain = 2(4) 12 µs Power-up glitch magnitude DAC code = zero scale. VDD = 5.5 V, VREFIN = 2.5 V, Gain = 2. CLOAD = 50 pF 25 mV Output noise 0.1 Hz to 10 Hz, DAC code = midscale, VDD = 5.5 V, VREFIN = 2.5 V, Gain = 2 14 µVpp Output noise density 1 kHz, DAC code = midscale, VDD = 5.5 V, VREFIN =

2.5 V, Gain = 2 78

nV/√Hz 10 kHz, DAC code = midscale, VDD = 5.5 V, VREFIN =

2.5 V, Gain = 2 74

1 kHz, DAC code = full scale, VDD = 5.5 V, VREFIN =

2.5 V, Gain = 1 55

10 kHz, DAC code = full scale, VDD = 5.5 V, VREFIN =

2.5 V, Gain = 1 50

AC PSRR DAC code = midscale, frequency = 60 Hz, amplitude = 200 mVPP superimposed on VDD 85 dB DC PSRR DAC code = midscale, VDD = 5 V ± 10% 10 µV/V Code change glitch impulse 1 LSB change around major carrier 4 nV-s Channel to Channel AC crosstalk DAC code = midscale. Code 32 to full-scale swing on adjacent channel 0.2 nV-s Channel to Channel DC crosstalk Measured channel at midscale. Adjacent channel at full scale. 10 µV Measured channel at midscale. All other channels at full scale. 80 Digital feedthrough DAC code = midscale. fSCLK = 1 MHz, SDO disabled 0.1 nV-s EXTERNAL REFERENCE INPUT Reference input current VREFIN = 2.5 V 25 µA Reference input impedance 100 kΩ Reference input capacitance 5 pF

DAC80508,DAC70508,DAC60508 SLASEL1C –JUNE 2017–REVISED APRIL 2018 www.ti.com Product Folder Links: DAC80508 DAC70508 DAC60508 Submit Documentation Feedback Copyright © 2017–2018, Texas Instruments Incorporated Electrical Characteristics (continued) to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, TA = –40°C to 125°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL REFERENCE Reference output voltage, VREFOUT TA = 25°C 2.495 2.5 2.505 V Reference output drift 5 8 ppm/°C Reference output impedance 0.1 Ω Reference output noise 0.1 Hz to 10 Hz 15 µVpp Reference output noise density 10 kHz, REFLOAD = 10 nF 130 nV/√Hz Reference load current ±5 mA Referencel load regulation Source and sink 100 µV/mA Reference line regulation 20 µV/V Reference output drift over time TA = 25°C, 1600 hours 4.8 ppm Reference thermal hysteresis First cycle 190 ppm Additional cycle 18 DIGITAL INPUTS VIH High-level input voltage 0.7 × VIO V VIL Low-level input voltage 0.3 × VIO V Input current ±2 µA Input pin capacitance 2 pF DIGITAL OUTPUTS VOH High-level output voltage ILOAD = 0.2 mA VIO – 0.4 V VOL Low-level output voltage ILOAD = -0.2 mA 0.4 V Output pin capacitance 4 pF POWER SUPPLY REQUIREMENTS IDD VDD supply current Active mode. Internal reference enabled. Gain = 1. DAC code = full scale. Outputs unloaded. SPI static 5 6 mA Active mode. Internal reference disabled. Gain = 1. DAC code = full scale. Outputs unloaded. SPI static 4.5 5.5 Power-down 15 30 µA IIO VIO supply current 2 3 µA

7.6 Typical Characteristics

At TA = 25°C, VDD = 5.5 V, Internal Reference = 2.5 V, Gain = 2, DAC outputs unloaded, unless otherwise noted. Figure 1. Integral Linearity Error vs Digital Input Code Figure 2. Differential Linearity Error vs Digital Input Code Figure 3. Total Unadjusted Error vs Digital Input Code Figure 4. Integral Linearity Error vs Temperature Figure 5. Differential Linearity Error vs Temperature Figure 6. Total Unadjusted Error vs Temperature

At TA = 25°C, VDD = 5.5 V, Internal Reference = 2.5 V, Gain = 2, DAC outputs unloaded, unless otherwise noted. Figure 49. DAC Output Noise with External Reference

0.1 Hz to 10 Hz

Figure 50. DAC Output Noise with Internal Reference Figure 51. Internal Reference Voltage vs Temperature Figure 52. Internal Reference Voltage vs Supply Voltage Figure 53. Internal Reference Voltage vs Time Figure 54. Internal Reference Noise Density vs Frequency

At TA = 25°C, VDD = 5.5 V, Internal Reference = 2.5 V, Gain = 2, DAC outputs unloaded, unless otherwise noted. Figure 55. Internal Reference Noise Figure 56. Internal Reference Temperature Drift Histogram

GND Copyright © 2017, Texas Instruments Incorporated BUF Channel 3 OUT3 Channel 4 OUT4 Channel 5 OUT5 Channel 6 OUT6 Channel 7 OUT7 +1 OR +2 DAC80508,DAC70508,DAC60508 www.ti.com SLASEL1C –JUNE 2017–REVISED APRIL 2018 Product Folder Links: DAC80508 DAC70508 DAC60508 Submit Documentation FeedbackCopyright © 2017–2018, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The DACx0508 is a pin-compatible family of low-power, eight-channel, buffered voltage-output digital-to-analog converters (DACs) with 16-, 14- and 12-bit resolution. The DACx0508 includes a 2.5 V internal reference and user selectable gain configuration providing full scale output voltages of 1.25 V (gain = ½), 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is specified monotonic, and provides high linearity of ±1 LSB INL. Communication to the DACx0508 is performed through a 4-wire serial interface that supports stand-alone and daisy-chain operation. The optional frame-error checking provides added robustness to the DACx0508 serial interface. The DACx0508 incorporates a power-on-reset circuit that powers up and maintains the DAC outputs at either zero scale or midscale until a valid code is written to the device.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Digital-to-Analog Converter (DAC) Architecture

amplifier. Figure 57 shows a block diagram of the DAC architecture. Figure 57. DACx0508 DAC Block Diagram

8.3.1.1 DAC Transfer Function

DAC transfer function is given by Equation 1. DIV = 1 or 2 as set by the REF-DIV bit in the GAIN register. Set to 1 by default. DACx0508Z and to 2 in DACx0508M.

8.3.1.2 Output Amplifiers

output voltage ranges for each DAC output. Table 1. DAC Output Range Configuration

8.3.1.3 DAC Register Structure

buffer register is returned (not the value held in the DAC active register).

8.3.1.3.1 DAC Register Synchronous and Asynchronous Updates

8.3.1.3.2 Broadcast DAC Register

synchronous mode configuration.

8.3.2 Internal Reference

externally available at the REF pin. A minimum 150 nF capacitor is recommended between the reference output and GND for noise filtering.

8.3.2.1 Reference Divider

the Recommended Operating Conditions table for more information.

8.3.2.2 Solder Heat Reflow

the effect of solder heat reflow for the DACx0508 internal reference. Figure 58. Solder Heat Reflow Reference Voltage Shift

8.3.3 Device Reset Options

8.3.3.1 Power-on-Reset (POR)

DAC channel remains at the power-up voltage until a valid command is written to it. Figure 59. Threshold Levels for VDD POR Circuit Figure 60. Threshold Levels for VIO POR Circuit

8.3.3.2 Software Reset

8.4 Device Functional Modes

8.4.1 Stand-Alone Operation

high, the SCLK and SDI signals are blocked and the SDO pin is in a Hi-Z state. cycle form the data cycle, as shown in Table 2. Table 2. Serial Interface Access Cycle write operation. R/W = 1 sets a read operation. 22:20 Reserved Reserved bits. Must be filled with zeros. 19:16 A[3:0] Register address. Specifies the register to be accessed during the read or write operation. address A[3:0]. If a read command, the data cycle bits are don’t care values. the falling edge or rising edge of SCLK according to the FSDO bit in the CONFIG register. Table 3. SDO Output Access Cycle 23 RW Echo RW from previous access cycle. 22:20 Reserved Echo bits 22:20 from previous access cycle (all zeros). 19:16 A[3:0] Echo address from previous access cycle. 15:0 DO[15:0] Readback data requested on previous access cycle.

8.4.2 Daisy-Chain Operation

together. Daisy-chain operation is useful in reducing the number of serial interface lines.

Figure 61. Daisy-Chain Layout

8.4.3 Frame Error Checking

The error checking scheme is based on the CRC-8-ATM (HEC) polynomial x8 + x2 + x + 1 (that is, 100000111). Table 4. In all serial interface readback operations the CRC polynomial is output on the SDO pin as part of the Table 4. Error Checking Serial Interface Access Cycle write operation. R/W = 1 sets a read operation. 30 CRC-ERROR Reserved bit. Set to zero. 29:28 Reserved Reserved bits. Must be filled with zeros. 27:24 A[3:0] Register address. Specifies the register to be accessed during the read or write operation. address A[3:0]. If a read command, the data cycle bits are don’t care values. 7:0 CRC 8-bit CRC polynomial. exists, the CRC remainder is zero and data are accepted by the device. SDO/ALARM pin is configured as a CRC alarm pin. Table 5. Write Operation Error Checking Cycle 31 RW Echo RW from previous access cycle (RW = 0). 30 CRC-ERROR Returns a 1 when a CRC error is detected, 0 otherwise. 29:28 Reserved Echo bits 29:28 from previous access cycle (all zeros). 27:24 A[3:0] Echo address from previous access cycle. 23:8 DO[15:0] Echo data from previous access cycle. 7:0 CRC Calculated CRC value of bits 31:8.

be used to indicate a read command CRC failure. Table 6. Read Operation Error Checking Cycle 31 RW Echo RW from previous access cycle (RW = 1). 30 CRC-ERROR Returns a 1 when a CRC error is detected, 0 otherwise. 29:28 Reserved Echo bits 29:28 from previous access cycle (all zeros). 27:24 A[3:0] Echo address from previous access cycle. 23:8 DO[15:0] Readback data requested on previous access cycle. 7:0 CRC Calculated CRC value of bits 31:8.

8.4.4 Power-Down Mode

output channel in power-down mode is connected internally to GND through a 1 kΩ resistor.

8.5 Programming

timing diagrams, respectively. Table 7. Programming Timing Requirements(1)

8.6 Register Map

Table 8. Register Map

8.6.1 NOP Register (address = 0x00) [reset = 0x0000]

Figure 64. NOP Register Table 9. NOP Register Field Descriptions

8.6.2 DEVICE ID Register (address = 0x01) [reset = 0x---]

Figure 65. DEVICE ID Register Table 10. DEVICE ID Field Descriptions

8.6.3 SYNC Register (address = 0x2) [reset = 0xFF00]

Figure 66. SYNC Register Table 11. SYNC Register Field Descriptions

15 DAC7-BRDCAST-EN R/W 1 When set to 1 the corresponding DAC is set to update its output

after a serial interface write to the BRDCAST register.

14 DAC6-BRDCAST-EN R/W 1

13 DAC5-BRDCAST-EN R/W 1

12 DAC4-BRDCAST-EN R/W 1

11 DAC3-BRDCAST-EN R/W 1

10 DAC2-BRDCAST-EN R/W 1

9 DAC1-BRDCAST-EN R/W 1

8 DAC0-BRDCAST-EN R/W 1

7 DAC7-SYNC-EN R/W 0 When set to 1 the corresponding DAC output is set to update in

response to an LDAC trigger (synchronous mode). update immediately on a CS rising edge (asynchronous mode).

6 DAC6-SYNC-EN R/W 0

5 DAC5-SYNC-EN R/W 0

4 DAC4-SYNC-EN R/W 0

3 DAC3-SYNC-EN R/W 0

2 DAC2-SYNC-EN R/W 0

1 DAC1-SYNC-EN R/W 0

0 DAC0-SYNC-EN R/W 0

8.6.4 CONFIG Register (address = 0x3) [reset = 0x0000]

Figure 67. CONFIG Register Table 12. CONFIG Register Field Descriptions 13 ALM-SEL R/W 0 ALARM select. resistor to VIO is required. FSDO and DSDO bits are ignored. during an SCLK falling edge.

8 REF-PWDWN R/W 0 When set to 1 disables the device internal reference

7 DAC7-PWDWN R/W 0 When set to 1 the corresponding DAC is set in power-down

5 DAC5-PWDWN R/W 0

4 DAC4-PWDWN R/W 0

3 DAC3-PWDWN R/W 0

2 DAC2-PWDWN R/W 0

1 DAC1-PWDWN R/W 0

0 DAC0-PWDWN R/W 0

8.6.5 GAIN Register (address = 0x04) [reset = 0x---]

Figure 68. GAIN Register Table 13. GAIN Register Field Descriptions 15:9 Reserved — 0 Reserved for factory use.

8 REFDIV-EN R/W 0/1 When set to 1 the reference voltage is internally divided by a

When cleared to 0 the reference voltage is unaffected.

7 BUFF7-GAIN R/W 0/1 When set to 1 the buffer amplifier for corresponding DAC has a

gain of 2. Default value for the DACx0508M devices. has a gain of 1. Default value for the DACx0508Z devices.

6 BUFF6-GAIN R/W 0/1

5 BUFF5-GAIN R/W 0/1

4 BUFF4-GAIN R/W 0/1

3 BUFF3-GAIN R/W 0/1

2 BUFF2-GAIN R/W 0/1

1 BUFF1-GAIN R/W 0/1

0 BUFF0-GAIN R/W 0/1

8.6.6 TRIGGER Register (address = 0x05) [reset = 0x0000]

Figure 69. TRIGGER Register Table 14. TRIGGER Register Field Descriptions 15:5 Reserved — 0 Reserved for factory use.

4 LDAC W 0 Set this bit to 1 to synchronously load those DACs that have

been set in synchronous mode in the SYNC register.

8.6.7 BRDCAST Register (address = 0x6) [reset = 0x0000]

Figure 70. BRDCAST Register Table 15. BRDCAST Register Field Descriptions their active data register with the BRDCAST-DATA value.

8.6.8 STATUS Register (address = 0x7) [reset = 0x0000]

Figure 71. STATUS Register Table 16. STATUS Register Field Descriptions 15:1 Reserved — 0 Reserved for factory use. threshold. Reads 0 otherwise.

8.6.9 DACx Register (address = 0x8 to 0xF) [reset = 0x0000 or 0x8000]

Figure 72. DACx Register Table 17. DACx Register Field Descriptions

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

DAC output voltages of 1.25 V, 2.5 V, or 5 V.

9.1.1 Interfacing to Microcontroller

the MSB as the first bit received. Figure 73. Typical Serial Interface

9.1.2 Programmable Current Source Circuit

features of the circuit. With a matched resistor network, the load current of the circuit is shown by Equation 2. value of several pF is suggested. Figure 74. Programmable Bidirectional Current Source Circuit

NOTE: Some pins omitted for clarity.

9.2 Typical Application

Figure 75. Bipolar Operation Using the DACx0508

9.2.1 Design Requirements

VOUT(CODE) = output voltage versus code
CODE = 0 to 2n – 1. This is the digital code loaded to the DAC
VREF = reference voltage applied to the DACx0508
n = resolution in bits. Either 12 (DAC60508), 14 (DAC70508) or 16 (DAC80508)

Table 18. Design Parameters

9.2.2 Detailed Design Procedure

±10 V the calculation is as follows.

which in this case is –10 V to 9.995 V.

9.2.3 Application Curve

tolerance resistors were used in evaluating bipolar operation. Figure 76. Bipolar Operation

10 Power Supply Recommendations

The DACx0508 operates within the specified VDD supply range of 2.7 V to 5.5 V and VIO supply range of 1.7 V to 5.5 V. The DACx0508 does not require specific supply sequencing. The VDD supply must be well-regulated and low-noise. Switching power supplies and dc/dc converters often have high frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high frequency spikes. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. In order to further minimize noise from the power supply, include a 1- μF to 10-μF capacitor and 0.1-μF bypass capacitor. The current consumption on the VDD pin, the short-circuit current limit, and the load current for the device is listed in the Electrical Characteristics. The power supply must meet the aforementioned current requirements.

11 Layout

11.1 Layout Guidelines

Bypass all power supply pins to ground with a low ESR ceramic bypass capacitor. The typical recommended bypass capacitance is 0.1- to 0.22-µF ceramic with a X7R or NP0 dielectric.
Place power supplies and REF bypass capacitors close to the pins to minimize inductance and optimize performance.
Use a high-quality ceramic type NP0 or X7R for its optimal performance across temperature, and very low dissipation factor.
The digital and analog sections must have proper placement with respect to the digital pins and analog pins of the DACx0508 device. The separation of analog and digital blocks minimizes coupling into neighboring blocks, as well as interaction between analog and digital return currents.

11.2 Layout Examples

Figure 77. DACx0508 QFN Layout Example

Figure 78. DACx0508 DSBGA Layout Example

12 Device and Documentation Support

12.1 Related Links

resources, tools and software, and quick access to sample or buy. Table 19. Related Links

12.2 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

solve problems with fellow engineers. contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 24-Aug-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DAC60508MCRTER PREVIEW WQFN RTE 16 3000 TBD Call TI Call TI -40 to 125 658MC DAC60508MCRTET PREVIEW WQFN RTE 16 250 TBD Call TI Call TI -40 to 125 658MC DAC60508MCYZFR PREVIEW DSBGA YZF 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 65MC DAC60508MCYZFT PREVIEW DSBGA YZF 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 65MC DAC60508MRTER ACTIVE WQFN RTE 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 658M DAC60508MRTET ACTIVE WQFN RTE 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 658M DAC60508MYZFR ACTIVE DSBGA YZF 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 65M DAC60508MYZFT ACTIVE DSBGA YZF 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 65M DAC60508ZCRTER PREVIEW WQFN RTE 16 3000 TBD Call TI Call TI -40 to 125 658ZC DAC60508ZCRTET PREVIEW WQFN RTE 16 250 TBD Call TI Call TI -40 to 125 658ZC DAC60508ZCYZFR PREVIEW DSBGA YZF 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 65ZC DAC60508ZCYZFT PREVIEW DSBGA YZF 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 65ZC DAC60508ZRTER ACTIVE WQFN RTE 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 658Z DAC60508ZRTET ACTIVE WQFN RTE 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 658Z DAC60508ZYZFR ACTIVE DSBGA YZF 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 65Z DAC60508ZYZFT ACTIVE DSBGA YZF 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 65Z DAC70508MRTER ACTIVE WQFN RTE 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 758M DAC70508MRTET ACTIVE WQFN RTE 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 758M DAC70508MYZFR ACTIVE DSBGA YZF 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 75M

www.ti.com 24-Aug-2018 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DAC70508MYZFT ACTIVE DSBGA YZF 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 75M DAC70508ZRTER ACTIVE WQFN RTE 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 758Z DAC70508ZRTET ACTIVE WQFN RTE 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 758Z DAC70508ZYZFR ACTIVE DSBGA YZF 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 75Z DAC70508ZYZFT ACTIVE DSBGA YZF 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 75Z DAC80508MCRTER PREVIEW WQFN RTE 16 3000 TBD Call TI Call TI -40 to 125 858MC DAC80508MCRTET PREVIEW WQFN RTE 16 250 TBD Call TI Call TI -40 to 125 858MC DAC80508MCYZFR PREVIEW DSBGA YZF 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 85MC DAC80508MCYZFT PREVIEW DSBGA YZF 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 85MC DAC80508MRTER PREVIEW WQFN RTE 16 3000 TBD Call TI Call TI -40 to 125 858M DAC80508MRTET PREVIEW WQFN RTE 16 250 TBD Call TI Call TI -40 to 125 858M DAC80508MYZFR PREVIEW DSBGA YZF 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 85M DAC80508MYZFT PREVIEW DSBGA YZF 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 85M DAC80508ZCRTER PREVIEW WQFN RTE 16 3000 TBD Call TI Call TI -40 to 125 858ZC DAC80508ZCRTET PREVIEW WQFN RTE 16 250 TBD Call TI Call TI -40 to 125 858ZC DAC80508ZCYZFR PREVIEW DSBGA YZF 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 85ZC DAC80508ZCYZFT PREVIEW DSBGA YZF 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 85ZC DAC80508ZRTER PREVIEW WQFN RTE 16 3000 TBD Call TI Call TI -40 to 125 858Z DAC80508ZRTET PREVIEW WQFN RTE 16 250 TBD Call TI Call TI -40 to 125 858Z DAC80508ZYZFR PREVIEW DSBGA YZF 16 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 85Z DAC80508ZYZFT PREVIEW DSBGA YZF 16 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 125 85Z

www.ti.com 24-Aug-2018 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples XDAC80508ZRTET ACTIVE WQFN RTE 16 250 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 25-Aug-2018 Pack Materials-Page 1

(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC60508MCYZFR DSBGA YZF 16 3000 182.0 182.0 20.0 DAC60508MCYZFT DSBGA YZF 16 250 182.0 182.0 20.0 DAC60508MRTER WQFN RTE 16 3000 370.0 355.0 55.0 DAC60508MRTET WQFN RTE 16 250 195.0 200.0 45.0 DAC60508MYZFR DSBGA YZF 16 3000 182.0 182.0 20.0 DAC60508MYZFT DSBGA YZF 16 250 182.0 182.0 20.0 DAC60508ZCYZFR DSBGA YZF 16 3000 182.0 182.0 20.0 PACKAGE MATERIALS INFORMATION www.ti.com 25-Aug-2018 Pack Materials-Page 2

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC60508ZCYZFT DSBGA YZF 16 250 182.0 182.0 20.0 DAC60508ZRTER WQFN RTE 16 3000 370.0 355.0 55.0 DAC60508ZRTET WQFN RTE 16 250 195.0 200.0 45.0 DAC60508ZYZFR DSBGA YZF 16 3000 182.0 182.0 20.0 DAC60508ZYZFT DSBGA YZF 16 250 182.0 182.0 20.0 DAC70508MRTER WQFN RTE 16 3000 370.0 355.0 55.0 DAC70508MRTET WQFN RTE 16 250 195.0 200.0 45.0 DAC70508MYZFR DSBGA YZF 16 3000 182.0 182.0 20.0 DAC70508MYZFT DSBGA YZF 16 250 182.0 182.0 20.0 DAC70508ZRTER WQFN RTE 16 3000 370.0 355.0 55.0 DAC70508ZRTET WQFN RTE 16 250 195.0 200.0 45.0 DAC70508ZYZFR DSBGA YZF 16 3000 182.0 182.0 20.0 DAC70508ZYZFT DSBGA YZF 16 250 182.0 182.0 20.0 DAC80508MCYZFR DSBGA YZF 16 3000 182.0 182.0 20.0 DAC80508MCYZFT DSBGA YZF 16 250 182.0 182.0 20.0 DAC80508MYZFR DSBGA YZF 16 3000 182.0 182.0 20.0 DAC80508MYZFT DSBGA YZF 16 250 182.0 182.0 20.0 DAC80508ZCYZFR DSBGA YZF 16 3000 182.0 182.0 20.0 DAC80508ZCYZFT DSBGA YZF 16 250 182.0 182.0 20.0 DAC80508ZYZFR DSBGA YZF 16 3000 182.0 182.0 20.0 DAC80508ZYZFT DSBGA YZF 16 250 182.0 182.0 20.0 PACKAGE MATERIALS INFORMATION www.ti.com 25-Aug-2018 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C0.625 MAX 0.35 0.15 1.5 TYP

0.5 TYP

16X 0.35 0.25 0.5 TYP

1.5 TYP

D 4222182/A 08/2015 DSBGA - 0.625 mm max heightYZF0016 DIE SIZE BALL GRID ARRAY NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. NanoFree TM package configuration. NanoFree Is a trademark of Texas Instruments. BALL A1 CORNER SEATING PLANE BALL TYP 0.05 C A 1 3

0.015 C A B

C B D SCALE 6.500 D: Max = E: Max = 2.42 mm, Min = 2.42 mm, Min = 2.36 mm 2.36 mm

www.ti.com EXAMPLE BOARD LAYOUT 16X ( ) 0.245 (0.5) TYP (0.5) TYP ( ) METAL 0.245 0.05 MAX SOLDER MASK OPENING METAL UNDER SOLDER MASK ( ) SOLDER MASK OPENING 0.245

0.05 MIN

DSBGA - 0.625 mm max heightYZF0016 DIE SIZE BALL GRID ARRAY NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009). SYMM SYMM LAND PATTERN EXAMPLE SCALE:30X 1 2 A B C 3 4 D NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (0.5) TYP (0.5) TYP 16X ( 0.25) (R ) TYP 0.05 METAL TYP 4222182/A 08/2015 DSBGA - 0.625 mm max heightYZF0016 DIE SIZE BALL GRID ARRAY NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 1 2 A B C D

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Product Information

DAC60508MYZFR specifications and overview.

Summary

Octal, 16-, 14-, 12-Bit, SPI, Voltage Output DAC with Internal Reference

Description

Octal, 16-, 14-, 12-Bit, SPI, Voltage Output DAC with Internal Reference

Source title DAC60508MYZFR Datasheet(PDF) - Texas Instruments

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