Power Management

DAC60504BRTER

Texas Instruments

DACx0504 Quad, 16-, 14-, 12-bit, SPI voltage output DACs with internal reference REVISED JANUARY 2019

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÷1 or ÷2 GAIN GAIN ×1 or ×2 GND LDAC REFDIV Copyright © 2017, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC80504,DAC70504,DAC60504 SBAS871C –AUGUST 2017–REVISED JANUARY 2019 DACx0504Quad,16-,14-,12-bit,SPIvoltageoutputDACswithinternalreference

1 Features

1• Performance – INL: ±1 LSB Maximum at 16-Bit Resolution – TUE: ±0.1% of FSR Maximum

Integrated 2.5 V Precision Internal Reference – Initial Accuracy: ±5 mV, Maximum – Low Drift: 2 ppm/°C Typical
High Drive Capability: 20 mA With 0.5 V From Supply Rails
Flexible Output Configuration – User Selectable Gain: 2, 1 or ½ – Reset to Zero Scale or Midscale
Wide Operating Range – Power Supply: 2.7 V to 5.5 V – Temperature: –40˚C to +125˚C
50-MHz, SPI-Compatible Serial Interface – 4-Wire Mode, 1.7 V to 5.5 V Operation – Daisy-Chain Operation – CRC Error Check
Low Power: 0.7 mA/Channel at 5.5 V
Small Package: 3-mm × 3-mm, 16-Pin WQFN

2 Applications

Optical Networking
Wireless Infrastructure
Industrial Automation
Data Acquisition Systems

3 Description

The DAC80504, DAC70504, and DAC60504 (DACx0504) are a pin-compatible family of low- power, four-channel, buffered voltage-output, digital- to-analog converters (DACs) with 16-, 14-, and 12-bit resolution. The DACx0504 includes a low drift, 2.5-V internal reference, eliminating the need for an external precision reference in most applications. A user-selectable gain configuration provides full-scale output voltages of 1.25 V (gain = ½), 2.5 V (gain = 1), or 5 V (gain = 2). These devices operate from a single 2.7-V to 5.5-V supply, are specified monotonic, and provide high linearity of ±1 LSB INL. Communication to the DACx0504 is performed through a 4-wire serial interface that operates at clock rates of up to 50 MHz. The VIO pin enables serial interface operation from 1.7 V to 5.5 V. The DACx0504 flexible interface enables operation with a wide range of industry-standard microprocessors and microcontrollers. The DACx0504 incorporate a power-on-reset circuit that powers up and maintains the DAC outputs at either zero scale or midscale until a valid code is written to the device. These device consume a low current of 0.7 mA/channel at 5.5 V, making these devices an excellent choice for battery-operated equipment. A per-channel power-down feature reduces the device current consumption to 15 µA. The DACx0504 is characterized for operation over the temperature range of –40°C to +125°C, and is available in a small, 3-mm × 3-mm QFN package. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DACx0504 WQFN (16) 3.00 mm × 3.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Simplified Block Diagram

12.3 Receiving Notification of Documentation Updates 41

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (September 2018) to Revision C Page Changes from Revision A (December 2017) to Revision B Page

Changed Short circuit current, DAC code = full scale, output shorted to GND in Electrical CharacteristicsTYP from
Changed Short circuit current, DAC code = zero scale, output shorted to VDD in Electrical Characteristics TYP from
Added Channel-to channel dc crosstalk, Measured channel at midscale. Adjacent channel at full scale. DAC80504

Added Channel-to-channel crosstalk, Measured channel at midscale. All other channels at full scale. DAC80504 in Changes from Original (August 2017) to Revision A Page

5 Device Comparison Table

DEVICE RESOLUTION REFERENCE DAC80504 16-Bit Internal (default) or External DAC70504 14-Bit Internal (default) or External DAC60504 12-Bit Internal (default) or External

16 VIO5OUT3

15 SDO/ALARM6GND

14 SDI7VDD

13 SCLK8GAIN

6 Pin Configuration and Functions

NAME NO. REF 1 I/O When using internal reference, this is the reference output voltage pin (default). When using an external reference, this is the reference input pin to the device. OUT0 2 O Analog output voltage from DAC 0. OUT1 3 O Analog output voltage from DAC 1. OUT2 4 O Analog output voltage from DAC 2. OUT3 5 O Analog output voltage from DAC 3. GND 6 GND Ground reference point for all circuitry on the device. VDD 7 PWR Analog supply voltage (2.7 V to 5.5 V). GAIN 8 I Sets the gain configuration after a power-up or reset event. When tied to GND, the initial buffer amplifier gain for all four channels is set to 1. When tied to VIO the initial buffer amplifier gain is 2. Changing the state of this pin after power-up does not affect the device operation. RSTSEL 9 I Reset select pin. When tied to GND all four DACs reset to zero scale. When connected to VIO all four DACs reset to midscale. REFDIV 10 I Sets the reference divider configuration after a power-up or reset event. When tied to GND, the reference voltage is not divided down. When tied to VIO the reference voltage is divided by 2. Changing the state of this pin after power-up does not affect the device operation. LDAC 11 I A high-to-low transition on the LDAC pin causes the DAC outputs of those channels configured in synchronous mode to update simultaneously. The pin can be tied permanently to GND. CS 12 I Active low serial data enable. This input is the frame synchronization signal for the serial data. When the signal goes low, it enables the serial interface input shift register. SCLK 13 I Serial interface clock. SDI 14 I Serial interface data input. Data are clocked into the input shift register on each falling edge of the SCLK pin. SDO/ALARM 15 O Serial interface data output (default). The SDO pin is in high impedance when CS pin is high. Data are clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified by the FSDO bit. Alternatively the pin can be configured as an ALARM open-drain output to indicate a CRC or reference alarm event. If configured as ALARM a 10 kΩ, pull-up resistor to VIO is required. VIO 16 PWR IO supply voltage (1.7 V to 5.5 V). This pin sets the I/O operating voltage for the serial interface. Thermal Pad – – The thermal pad is located on the bottom-side of the QFN package. The thermal pad should be connected to any internal PCB ground plane using multiple vias for good thermal performance.

DAC80504,DAC70504,DAC60504 SBAS871C –AUGUST 2017–REVISED JANUARY 2019 www.ti.com Product Folder Links: DAC80504 DAC70504 DAC60504 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Suppy voltage VDD to GND –0.3 6 V VIO to GND –0.3 6 Pin voltage DAC outputs to GND –0.3 VDD + 0.3 VREF to GND –0.3 VDD + 0.3 Digital pins to GND –0.3 VIO + 0.3 Input current Input current to any pin except supply pins –10 10 mA Temperature Operating free-air, TA –40 125 °CJunction, TJ –40 150 Storage, Tstg –60 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±3000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT POWER SUPPLY VDD Analog supply voltage 2.7 5.5 V VIO IO supply voltage 1.7 5.5 DIGITAL INPUTS Digital input voltage 0 VIO V REFERENCE INPUT VREFIN VDD = 2.7 V to 3.3 V Reference divider disabled 1.2 (VDD – 0.2)/2 V Reference divider enabled 2.4 VDD – 0.2 VDD = 3.3 V to 5.5 V Reference divider disabled 1.2 VDD/2 Reference divider enabled 2.4 VDD TEMPERATURE TA Operating free-air temperature –40 125 °C

DAC80504,DAC70504,DAC60504 www.ti.com SBAS871C –AUGUST 2017–REVISED JANUARY 2019 Product Folder Links: DAC80504 DAC70504 DAC60504 Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information

THERMAL METRIC(1) DACx0504 UNITRTE (WQFN)

16 PINS

RθJA Junction-to-ambient thermal resistance 33.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 29.5 °C/W RθJB Junction-to-board thermal resistance 7.3 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 7.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W (1) Static performance specified with DAC outputs unloaded for all gain options, unless otherwise noted. End point fit between codes. 16- bit: Code 256 to 65280, 14-bit: Code 128 to 16127, 12-bit: Code 16 to 4031.

7.5 Electrical Characteristics

to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, and TA = –40°C to +125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE(1) Resolution DAC80504 16 BitsDAC70504 14 DAC60504 12 INL Integral nonlinearity DAC80504 ±0.5 ±1 LSBDAC70504 ±0.5 ±1 DAC60504 ±0.5 ±1 DNL Differential nonlinearity DAC80504, specified 16-bit monotonic ±0.5 ±1 LSBDAC70504, specified 14-bit monotonic ±0.5 ±1 DAC60504, specified 12-bit monotonic ±0.5 ±1 TUE Total unadjusted error ±0.05 ±0.1 %FSR Offset error ±0.75 ±1.5 mV Zero-code error DAC code = zero scale 0.5 1.5 mV Full-scale error ±0.05 ±0.1 %FSR Gain error ±0.05 ±0.1 %FSR Offset error drift ±1 µV/°C Zero-code error drift ±2 µV/°C Full-scale error drift ±2 ppm of FSR/°C Gain error drift ±1 ppm of FSR/°C Output voltage drift over time TA = 25°C, DAC code = midscale, 1600 hours 20 ppm of FSR

DAC80504,DAC70504,DAC60504 SBAS871C –AUGUST 2017–REVISED JANUARY 2019 www.ti.com Product Folder Links: DAC80504 DAC70504 DAC60504 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated Electrical Characteristics (continued) to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, and TA = –40°C to +125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (2) Temporary overload condition protection. Junction temperature can be exceeded during current limit. Operation above the specified maximum junction temperature may impair device reliability. (3) Specified by design and characterization. Not tested during production. (4) Time to exit DAC power-down mode. Measured from CS rising edge to 90% of DAC final value. OUTPUT CHARACTERISTICS Voltage range Gain = 2 (BUFF-GAIN = 1, REF-DIV = 0) 0 2 × VREF VGain = 1 (BUFF-GAIN = 1, REF-DIV = 1) 0 VREF Gain = ½ (BUFF-GAIN = 0, REF-DIV = 1) 0 ½ × VREF Output voltage headroom to GND or VDD (unloaded) 0.004 V to GND or VDD (–5 mA ≤ IOUT ≤ 5 mA) 0.15 to GND or VDD (–10 mA ≤ IOUT ≤ 10 mA) 0.3 to GND or VDD (–20 mA ≤ IOUT ≤ 20 mA) 0.5 Short circuit current(2) DAC code = full scale, output shorted to GND 30 mA DAC code = zero scale, output shorted to VDD 35 Load regulation DAC code = midscale, -10 mA ≤ IOUT ≤ 10 mA 85 µV/mA Maximum capacitive load(3) RLOAD = ∞ 0 2 nF RLOAD = 2 kΩ 0 10 DC output impedance DAC code = midscale 0.085 Ω DAC code at GND or VDD 15 DYNAMIC PERFORMANCE Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling time to ±2 LSB, VDD = 5.5 V, VREFIN = 2.5 V, gain = 2 5 µs Slew rate VDD = 5.5 V, VREFIN = 2.5 V, gain = 2 1.8 V/µs Power-up time DACx-PWDWN 1 to 0 transition, DAC code = full scale, VDD = 5.5 V, VREFIN = 2.5 V, gain = 2(4) 12 µs Power-up glitch magnitude DAC code = zero scale, VDD = 5.5 V, VREFIN = 2.5 V, gain = 2. CLOAD = 50 pF 25 mV Output noise 0.1 Hz to 10 Hz, DAC code = midscale, VDD = 5.5 V, VREFIN = 2.5 V, gain = 2 14 µVPP Output noise density 1 kHz, DAC code = midscale, VDD = 5.5 V, VREFIN =

2.5 V, gain = 2 78

nV/√Hz 10 kHz, DAC code = midscale, VDD = 5.5 V, VREFIN =

2.5 V, gain = 2 74

1 kHz, DAC code = full scale, VDD = 5.5 V, VREFIN =

2.5 V, gain = 1 55

10 kHz, DAC code = full scale, VDD = 5.5 V, VREFIN =

2.5 V, gain = 1 50

AC PSRR DAC code = midscale, frequency = 60 Hz, amplitude = 200 mVPP superimposed on VDD 85 dB DC PSRR DAC code = midscale, VDD = 5 V ± 10% 10 µV/V Code change glitch impulse 1 LSB change around major carrier 4 nV-s Channel-to-channel ac crosstalk DAC code = midscale. Code 32 to full-scale swing on adjacent channel 0.2 nV-s Channel-to-channel dc crosstalk Measured channel at midscale, adjacent channel at full scale 5 µV Measured channel at midscale, all other channels at full scale 10 Digital feedthrough DAC code = midscale. fSCLK = 1 MHz, SDO disabled 0.1 nV-s EXTERNAL REFERENCE INPUT Reference input current VREFIN = 2.5 V 25 µA Reference input impedance 100 kΩ Reference input capacitance 5 pF

DAC80504,DAC70504,DAC60504 www.ti.com SBAS871C –AUGUST 2017–REVISED JANUARY 2019 Product Folder Links: DAC80504 DAC70504 DAC60504 Submit Documentation FeedbackCopyright © 2017–2019, Texas Instruments Incorporated Electrical Characteristics (continued) to GND, CLOAD = 200 pF to GND, digital inputs at VIO or GND, and TA = –40°C to +125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL REFERENCE VREFOUT Reference output voltage TA = 25°C 2.495 2.5 2.505 V Reference output drift 2 5 ppm/°C Reference output impedance 0.1 Ω Reference output noise 0.1 Hz to 10 Hz 15 µVPP Reference output noise density 10 kHz, REFLOAD = 10 nF 130 nV/√Hz Reference load current ±5 mA Reference load regulation Source and sink 100 µV/mA Reference line regulation 20 µV/V Reference output drift over time TA = 25°C, 1600 hours 4.8 ppm Reference thermal hysteresis First cycle 50 ppm Additional cycle 18 DIGITAL INPUTS VIH High-level input voltage 0.7 × VIO V VIL Low-level input voltage 0.3 × VIO V Input current ±2 µA Input pin capacitance 2 pF DIGITAL OUTPUTS VOH High-level output voltage ILOAD = 0.2 mA VIO – 0.4 V VOL Low-level output voltage ILOAD = –0.2 mA 0.4 V Output pin capacitance 4 pF POWER SUPPLY REQUIREMENTS IDD VDD supply current Active mode, internal reference enabled, gain = 1, DAC code = full scale, outputs unloaded, SPI static 2.8 3.6 mA Active mode, internal reference disabled, gain = 1, DAC code = full scale, outputs unloaded, SPI static 2.3 3 Power-down 15 µA IIO VIO supply current 2 3 µA

7.6 Typical Characteristics

Figure 1. Integral Linearity Error vs Digital Input Code Figure 2. Differential Linearity Error vs Digital Input Code Figure 3. Total Unadjusted Error vs Digital Input Code Figure 4. Integral Linearity Error vs Temperature Figure 5. Differential Linearity Error vs Temperature Figure 6. Total Unadjusted Error vs Temperature

Figure 49. DAC Output Noise With External Reference

0.1 Hz to 10 Hz

Figure 50. DAC Output Noise With Internal Reference Figure 51. Internal Reference Voltage vs Temperature Figure 52. Internal Reference Voltage vs Supply Voltage Figure 53. Internal Reference Voltage vs Time Figure 54. Internal Reference Noise Density vs Frequency

Figure 55. Internal Reference Noise Figure 56. Internal Reference Temperature Drift Histogram

÷1 or ÷2 GAIN GAIN ×1 or ×2 GND LDAC REFDIV Copyright © 2017, Texas Instruments Incorporated DAC80504,DAC70504,DAC60504 SBAS871C –AUGUST 2017–REVISED JANUARY 2019 www.ti.com Product Folder Links: DAC80504 DAC70504 DAC60504 Submit Documentation Feedback Copyright © 2017–2019, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The DACx0504 is a pin-compatible family of low-power, four-channel, buffered voltage-output digital-to-analog converters (DACs) with 16-, 14-, and 12-bit resolution. The DACx0504 include a 2.5-V internal reference and user-selectable gain configuration. providing full-scale output voltages of 1.25 V (gain = ½), 2.5 V (gain = 1), or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is specified monotonic, and provides high linearity of ±1 LSB INL. Communication to the DACx0504 is performed through a 4-wire serial interface that supports stand-alone and daisy-chain operation. The optional frame-error checking provides added robustness to the DACx0504 serial interface. The DACx0504 incorporates a power-on-reset circuit and RSTSEL pin that powers up and maintains the DAC outputs at either zero scale or midscale until a valid code is written to the device.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Digital-to-Analog Converter (DAC)

amplifier. Figure 57 shows a block diagram of the DAC architecture. Figure 57. DACx0504 DAC Block Diagram

8.3.1.1 DAC Transfer Function

reset event, all DAC registers are set to either zero code or midscale code, as determined by the RSTSEL pin. The DAC transfer function is given by Equation 1.

CODE = decimal equivalent of the binary code that is loaded to the DAC register. CODE ranges from 0 to 2n –
VREF = DAC reference voltage. Either VREFOUT from the internal 2.5 V reference or VREFIN if using an external one.
n = resolution in bits. Either 16 (DAC80504), 14 (DAC70504), or 12 (DAC60504).
DIV = 1 or 2 as set by the REFDIV pin after a reset event or by the REF-DIV bit in the GAIN register.
GAIN = 1 or 2 as set by the GAIN pin after a reset event or by the BUFF-GAIN bit for that DAC channel in the GAIN register. (1)

8.3.1.2 Output Amplifiers

output voltage ranges for each DAC output. Table 1. DAC Output Range Configuration

8.3.1.3 DAC Register Structure

buffer register is returned (not the value held in the DAC active register).

8.3.1.3.1 DAC Register Synchronous and Asynchronous Updates

of 1 µs is required between DAC output updates.

8.3.1.3.2 Broadcast DAC Register

synchronous mode configuration.

8.3.2 Internal Reference

externally available at the REF pin. A minimum 150 nF capacitor is recommended between the reference output and GND for noise filtering.

8.3.2.1 Reference Divider

8.3.2.2 Solder Heat Reflow

the effect of solder heat reflow for the DACx0504 internal reference. Figure 58. Solder Heat Reflow Reference Voltage Shift

8.3.3 Device Reset Options

8.3.3.1 Power-on-Reset (POR)

remains at the power-up voltage until a valid command is written to it. Figure 59. Threshold Levels for VDD POR Circuit Figure 60. Threshold Levels for VIO POR Circuit

8.3.3.2 Software Reset

8.4 Device Functional Modes

8.4.1 Stand-Alone Operation

contains more than the minimum clock edges are present, only the last 24 or 32 bits are used by the device. When CS is high, the SCLK and SDI signals are blocked and the SDO pin is in a Hi-Z state. cycle form the data cycle, as shown in Table 2. Table 2. Serial Interface Access Cycle write operation. R/W = 1 sets a read operation. 22:20 Reserved Reserved bits. Must be filled with zeros. 19:16 A[3:0] Register address. Specifies the register to be accessed during the read or write operation. address A[3:0]. If a read command, the data cycle bits are don’t care values. the falling edge or rising edge of SCLK according to the FSDO bit in the CONFIG register. Table 3. SDO Output Access Cycle 23 RW Echo RW from previous access cycle. 22:20 Reserved Echo bits 22:20 from previous access cycle (all zeros). 19:16 A[3:0] Echo address from previous access cycle. 15:0 DO[15:0] Readback data requested on previous access cycle.

8.4.2 Daisy-Chain Operation

together. Daisy-chain operation is useful in reducing the number of serial interface lines. Figure 61. Daisy-Chain Layout

8.4.3 Frame Error Checking

The error checking scheme is based on the CRC-8-ATM (HEC) polynomial x8 + x2 + x + 1 (that is, 100000111). Table 4. In all serial interface readback operations the CRC polynomial is output on the SDO pin as part of the Table 4. Error Checking Serial Interface Access Cycle write operation. R/W = 1 sets a read operation. 30 CRC-ERROR Reserved bit. Set to zero. 29:28 Reserved Reserved bits. Must be filled with zeros. 27:24 A[3:0] Register address. Specifies the register to be accessed during the read or write operation. address A[3:0]. If a read command, the data cycle bits are don’t care values. 7:0 CRC 8-bit CRC polynomial.

exists, the CRC remainder is zero and data are accepted by the device. SDO/ALARM pin is configured as a CRC alarm pin. Table 5. Write Operation Error Checking Cycle 31 RW Echo RW from previous access cycle (RW = 0). 30 CRC-ERROR Returns a 1 when a CRC error is detected, 0 otherwise. 29:28 Reserved Echo bits 29:28 from previous access cycle (all zeros). 27:24 A[3:0] Echo address from previous access cycle. 23:8 DO[15:0] Echo data from previous access cycle. 7:0 CRC Calculated CRC value of bits 31:8. be used to indicate a read command CRC failure. Table 6. Read Operation Error Checking Cycle 31 RW Echo RW from previous access cycle (RW = 1). 30 CRC-ERROR Returns a 1 when a CRC error is detected, 0 otherwise. 29:28 Reserved Echo bits 29:28 from previous access cycle (all zeros). 27:24 A[3:0] Echo address from previous access cycle. 23:8 DO[15:0] Readback data requested on previous access cycle. 7:0 CRC Calculated CRC value of bits 31:8.

8.4.4 Power-Down Mode

output channel in power-down mode is connected internally to GND through a 1-kΩ resistor.

8.5 Programming

timing diagrams, respectively. Figure 64 shows the digital logic timing diagram. Table 7. Programming Timing Requirements(1)

8.6 Register Map

Table 8. Register Map

8.6.1 NOP Register (address = 0x00) [reset = 0x0000]

Figure 65. NOP Register Table 9. NOP Register Field Descriptions

8.6.2 DEVICE ID Register (address = 0x01) [reset = 0x---]

Figure 66. DEVICE ID Register Table 10. DEVICE ID Field Descriptions

8.6.3 SYNC Register (address = 0x2) [reset = 0xFF00]

Figure 67. SYNC Register Table 11. SYNC Register Field Descriptions

11 DAC3-BRDCAST-EN R/W 1 When set to 1 the corresponding DAC is set to update its output

after a serial interface write to the BRDCAST register.

10 DAC2-BRDCAST-EN R/W 1

9 DAC1-BRDCAST-EN R/W 1

8 DAC0-BRDCAST-EN R/W 1

3 DAC3-SYNC-EN R/W 0 When set to 1 the corresponding DAC output is set to update in

response to an LDAC trigger (synchronous mode). update immediately on a CS rising edge (asynchronous mode).

2 DAC2-SYNC-EN R/W 0

1 DAC1-SYNC-EN R/W 0

0 DAC0-SYNC-EN R/W 0

8.6.4 CONFIG Register (address = 0x3) [reset = 0x0000]

Figure 68. CONFIG Register Table 12. CONFIG Register Field Descriptions 13 ALM-SEL R/W 0 ALARM select. resistor to VIO is required. FSDO and DSDO bits are ignored. during an SCLK falling edge.

8 REF-PWDWN R/W 0 When set to 1 disables the device internal reference

3 DAC3-PWDWN R/W 0 When set to 1 the corresponding DAC is set in power-down

1 DAC1-PWDWN R/W 0

0 DAC0-PWDWN R/W 0

8.6.5 GAIN Register (address = 0x04) [reset = 0x---]

Figure 69. GAIN Register Table 13. GAIN Register Field Descriptions 15:9 Reserved — 0 Reserved for factory use.

8 REFDIV-EN R/W 0/1 When set to 1 the reference voltage is internally divided by a

When cleared to 0 the reference voltage is unaffected. Default value is determined by the REFDIV pin.

3 BUFF3-GAIN R/W 0/1 When set to 1 the buffer amplifier for corresponding DAC has a

Default value is determined by the GAIN pin.

2 BUFF2-GAIN R/W 0/1

1 BUFF1-GAIN R/W 0/1

0 BUFF0-GAIN R/W 0/1

8.6.6 TRIGGER Register (address = 0x05) [reset = 0x0000]

Figure 70. TRIGGER Register Table 14. TRIGGER Register Field Descriptions 15:5 Reserved — 0 Reserved for factory use.

4 LDAC W 0 Set this bit to 1 to synchronously load those DACs that have

been set in synchronous mode in the SYNC register.

8.6.7 BRDCAST Register (address = 0x6) [reset = 0x0000]

Figure 71. BRDCAST Register Table 15. BRDCAST Register Field Descriptions their active data register with the BRDCAST-DATA value.

8.6.8 STATUS Register (address = 0x7) [reset = 0x0000]

Figure 72. STATUS Register Table 16. STATUS Register Field Descriptions 15:1 Reserved — 0 Reserved for factory use. threshold. Reads 0 otherwise.

8.6.9 DACx Register (address = 0x8 to 0xF) [reset = 0x0000 or 0x8000]

Figure 73. DACx Register Table 17. DACx Register Field Descriptions

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

DAC output voltages of 1.25 V, 2.5 V, or 5 V.

9.1.1 Interfacing to a Microcontroller

the MSB as the first bit received. Figure 74. Typical Serial Interface

9.1.2 Programmable Current Source Circuit

features of the circuit. With a matched resistor network, the load current of the circuit is shown by Equation 2. value of several pF is suggested. Figure 75. Programmable Bidirectional Current Source Circuit

9.2 Typical Application

Figure 76. Bipolar Operation Using the DACx0504

9.2.1 Design Requirements

VOUT(CODE) = output voltage versus code
CODE = 0 to 2n – 1. This is the digital code loaded to the DAC
VREF = reference voltage applied to the DACx0504
n = resolution in bits (4)

Table 18. Design Parameters

9.2.2 Detailed Design Procedure

±10 V the calculation is as follows. which in this case is –10 V to 9.995 V.

9.2.3 Application Curve

example, 1% tolerance resistors were used in evaluating bipolar operation. Figure 77. Bipolar Operation

10 Power Supply Recommendations

5.5 V. The DACx0504 does not require specific supply sequencing. meet the aforementioned current requirements.

11 Layout

11.1 Layout Guidelines

Bypass all power supply pins to ground with a low-ESR ceramic bypass capacitor. The typical recommended bypass capacitance is 0.1-µF to 0.22-µF ceramic with a X7R or NP0 dielectric.
Place power supplies and REF bypass capacitors close to the pins to minimize inductance and optimize performance.
Use a high-quality ceramic type NP0 or X7R for its optimal performance across temperature, and very low dissipation factor.
The digital and analog sections must have proper placement with respect to the digital pins and analog pins of the DACx0504 device. The separation of analog and digital blocks minimizes coupling into neighboring blocks, as well as interaction between analog and digital return currents.

11.2 Layout Example

Figure 78. DACx0504 Layout Example

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

12.2 Related Links

tools and software, and quick access to order now. Table 19. Related Links

12.3 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

solve problems with fellow engineers. contact information for technical support.

12.5 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

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www.ti.com 17-Jun-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DAC60504BRTER Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 654B DAC60504BRTER.A Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 654B DAC60504BRTER.B Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 654B DAC60504BRTERG4 Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 654B DAC60504BRTERG4.A Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 654B DAC60504BRTERG4.B Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 654B DAC60504BRTET Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 654B DAC60504BRTET.A Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 654B DAC60504BRTET.B Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 654B DAC70504RTER Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 70504 DAC70504RTER.A Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 70504 DAC70504RTER.B Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 70504 DAC70504RTET Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 70504 DAC70504RTET.A Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 70504 DAC70504RTET.B Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 70504 DAC80504RTER Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 (80504, 854) DAC80504RTER.B Active Production WQFN (RTE) | 16 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 (80504, 854) DAC80504RTET Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 (80504, 854) DAC80504RTET.B Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 (80504, 854) DAC80504RTETG4 Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 80504 DAC80504RTETG4.B Active Production WQFN (RTE) | 16 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 80504 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. Addendum-Page 1

www.ti.com 17-Jun-2025 (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC60504BRTER WQFN RTE 16 3000 367.0 367.0 38.0 DAC60504BRTERG4 WQFN RTE 16 3000 367.0 367.0 38.0 DAC60504BRTET WQFN RTE 16 250 213.0 191.0 35.0 DAC70504RTER WQFN RTE 16 3000 367.0 367.0 38.0 DAC70504RTET WQFN RTE 16 250 213.0 191.0 35.0 DAC80504RTER WQFN RTE 16 3000 367.0 367.0 38.0 DAC80504RTET WQFN RTE 16 250 213.0 191.0 35.0 DAC80504RTETG4 WQFN RTE 16 250 213.0 191.0 35.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightRTE 16 PLASTIC QUAD FLATPACK - NO LEAD3 x 3, 0.5 mm pitch 4225944/A

www.ti.com PACKAGE OUTLINE C 3.15 2.85 3.15 2.85 0.8 0.7 0.05 0.00 2X 1.5 12X 0.5 2X 1.5 16X 0.5 0.3 16X 0.30 0.18 0.8 0.1 (0.2) TYP WQFN - 0.8 mm max heightRTE0016D PLASTIC QUAD FLATPACK - NO LEAD 4219118/A 11/2018 0.08 C

0.1 C A B

0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMM EXPOSED THERMAL PAD SYMM 5 8 1316 SCALE 4.000 AB

www.ti.com EXAMPLE BOARD LAYOUT 12X (0.5) (R0.05) TYP

0.07 MAX

0.07 MIN

16X (0.6) 16X (0.24) (2.8) (2.8) ( 0.8) ( 0.2) TYP VIA WQFN - 0.8 mm max heightRTE0016D PLASTIC QUAD FLATPACK - NO LEAD 4219118/A 11/2018 SEE SOLDER MASK DETAIL NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X 5 8 1316 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 16X (0.6) 16X (0.24) 12X (0.5) (2.8) (2.8) ( 0.76) (R0.05) TYP WQFN - 0.8 mm max heightRTE0016D PLASTIC QUAD FLATPACK - NO LEAD 4219118/A 11/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 20X EXPOSED PAD 17 90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SYMM SYMM 5 8 1316

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Product Information

DAC60504BRTER specifications and overview.

Summary

DACx0504 Quad, 16-, 14-, 12-bit, SPI voltage output DACs with internal reference REVISED JANUARY 2019

Description

DACx0504 Quad, 16-, 14-, 12-bit, SPI voltage output DACs with internal reference REVISED JANUARY 2019

Source title DAC60504BRTER Datasheet(PDF) - Texas Instruments

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