DAC600

DAC600 BURR-BROWN | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 12

Technical content

DIGITAL-TO-ANALOG CONVERTER

FEATURES

l –73dB HARMONIC DISTORTION AT 10MHz l LASER TRIMMED ACCURACY: 1/2LSB l –5.2V SINGLE POWER SUPPLY l EDGE-TRIGGERED LATCH l LOW GLITCH: 5.6pVs l WIDEBAND MULTIPLYING REFERENCE INPUT l 50Ω OUTPUT IMPEDANCE

APPLICATIONS

l DIRECT DIGITAL SYNTHESIS l ARBITRARY WAVEFORM GENERATION l HIGH RESOLUTION GRAPHICS l COMMUNICATIONS LOCAL OSCILLATORS Spread Spectrum/Frequency Hopping Base Stations Digitally Tuned Receivers

DESCRIPTION

The DAC600 is a monolithic, high performance digi- tal-to-analog converter for high frequency waveform generation. The internal segmentation and latching minimize output glitch energy and maximizes AC performance. Resistor laser trimming provides for excellent DC linearity. The ECL compatibility provides for low digital noise at high update rates. The complementary 50Ω outputs and low output capacitance simplifies transmission line design and filtering at the output. The DAC600 combines precision thin film and bipolar technology to create a high performance, cost effec- tive solution for modern waveform synthesis. 50Ω 12-Bit ECL Lines –20mA CLKEdge Triggered Bit Latch 50Ω VOUT VOUT VREF R OFFSET Control Amplifier CLK LGND DAC600 DEMO BOARD AVAILABLE International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1992 Burr-Brown Corporation PDS-1153E Printed in U.S.A. November, 1996

[ Same as specification for DAC600AN. NOTES: (1) Linearity tests are measured into a virtual ground (op amp). (2) Gain error in % is calculated by: GE (%) = (3) Settling time is influenced by the load due to fast edge speeds. Use good transmission line techniques for best results. (4) Spurious free dynamic range is measured from the fundamental frequency to any harmonic or non-harmonic spurs within the bandwidth f CLK /2C , unless otherwise specified. SPECIFICATIONS ELECTRICAL At +25°C VREF = +1.0V, VEEA = VEED = –5.2V, unless otherwise noted. DAC600AN DAC600BN PARAMETER CONDITIONS TEMP MIN TYP MAX MIN TYP MAX UNITS DIGITAL INPUTS Logic 12 Parallel Input Lines, ECL Resolution 12 [ Bits ECL Logic Input Levels: VIL Logic “0” Full –1.48 –1.95 –2 [[[ V IIL Full 2 [ µA VIH Logic “1” Full –1.1 –0.75 0 [[[ V IIH Full 200 [ µA DIGITAL TIMING Input Data Rate Full DC 256 [[ MHz CLK Pulse Width High or Low Full 1.95 [ ns Set-up Time Full 1.5 1.0 [[ ns Hold Time (Referred to CLK) Full 1.9 1.7 [[ ns Propagation Delay Full 2 [ ns ANALOG OUTPUT Bipolar Output Current R L = 0Ω Full 19 20 21 [[[ mA Output Resistance Full 47.5 50 52.5 49 [ 51 Ω Output Capacitance Full 15 [ pF CONTROL AMPLIFIER Input Resistance Full 800 [ Ω Full Power Bandwidth –3dB Full 10 [ MHz Offset +25 °C0 ±10 ±0.5 mV Input Reference Range Full 100mV ±1.25 [[ V TRANSFER CHARACTERISTICS Integral Linearity Error(1): VOUT NOT Best Fit Straight Line +25 °C ±0.012 ±0.024 ±0.006 ±0.012 %FSR VOUT NOT Full ±0.024 ±0.036 ±0.012 ±0.024 %FSR VOUT +25°C ±0.1 ±0.1 %FSR Differential Linearity Error(1): VOUT NOT +25°C ±0.024 ±0.012 %FSR VOUT NOT Full ±0.036 ±0.024 %FSR VOUT +25°C ±0.1% ±0.1% %FSR 12-Bit Monotonicity +25 °C Guaranteed Guaranteed Full Typical Guaranteed Output Offset Current: VOUT NOT Bits 1-12 HIGH +25 °C 75 150 50 100 µA VOUT NOT Full 57 150 50 100 µA Output Leakage Current V REF = 0V, Bits 1-12 LOW, VOUT NOT +25°C1 0 7 5 5 5 0 µA TIME DOMAIN PERFORMANCE Glitch Energy Major Carry +25 °C 5.6 [ pVs Fall Time 90% to 10% +25 °C 510 [ ps Rise Time 10% to 90% +25 °C 770 [ ps Settling Time(3) ±0.1% FSR Major Carry, 1 LSB Change Full 4 [ ns ±0.024% FSR Full 15 [ ns DYNAMIC PERFORMANCE Spurious Free Dynamic Range (4) fO = 1MHz f CLOCK = 50MHz +25 °C 74 70 77 dBFS (3) fO = 10MHz f CLOCK = 50MHz +25 °C 71 64 73 dBFS fO = 1MHz f CLOCK = 100MHz +25 °C 72 70 75 dBFS fO = 10MHz f CLOCK = 100MHz +25 °C 68 66 70 dBFS fO = 20MHz f CLOCK = 100MHz +25 °C 61 58 62 dBFS fO = 10MHz f CLOCK = 200MHz +25 °C 66 66 70 dBFS fO = 20MHz f CLOCK = 200MHz +25 °C 58 62 67 dBFS fO = 50MHz f CLOCK = 200MHz +25 °C 52 50 55 dBFS Output Noise Bits 1-12 HIGH +25 °C 10.6 [ nV/√Hz POWER SUPPLIES Supply Voltages: VEE Full –4.5 –5.2 –5.5 [[[ V Supply Currents: IEEA Pins 33 and 34 Full 30 46 60 [[[ mA IEED Pins 5 and 55 Full 110 150 190 [[[ mA Power Consumption Operating Full 900mW 1.3 [[ W TEMPERATURE RANGE Specification: DAC600AN, BN Ambient Full –40 +85 [[ °C θJA 30 [ °C/W VMEASURED (FS) –VIDEAL (FS) X 100 VIDEAL (FS)

This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Stresses above these ratings may permanently damage the device. TEMPERATURE PRODUCT DESCRIPTION RANGE (AMBIENT) DAC600AN, BN 68-Pin Plastic QUAD –40 °C to +85°C

ORDERING INFORMATION

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

PACKAGE INFORMATION

PRODUCT PACKAGE NUMBER (1) DAC600AN, BN 68-Pin Plastic QUAD 312-1 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. PIN # DESIGNATION DESCRIPTION

35 V REF2 Analog Reference Voltage Center Tap

38 V REF Analog Reference Voltage

39 V REF Analog Reference Voltage

42 R OFFSET Offset Compensation

44 BYPASS 0.1 µF Bypass to Ground 45 NC 46 NC

47 ALTCOMPC Control Amp PTAT Reference Compensation (2)

48 AGND Analog Signal Ground

50 LBIAS Ladder Bias Alternate Compensation (2)

54 Bit 1 MSB

55 DV EE Digital –5.2V Supply

56 DGND Digital Signal Ground

57 DGND Digital Signal Ground

58 Bit 2

59 Bit 3

60 Bit 4

62 Bit 5

63 DGND Digital Ground

64 Bit 6

65 Bit 7

66 DGND Digital Ground

67 Bit 8

PIN # DESIGNATION DESCRIPTION

1 BYPASS Disables Latching of Data

2 CLK CLOCK

3 CLKNOT CLOCKNOT

4 DGND Digital Ground

5D V EE (1) –5.2V Supply

6 Bit 9

7 Bit 10

8 Bit 11

9 Bit 12 LSB

14 V OUT DAC Output

15 LGND Ladder Ground

16 LGND Ladder Ground

OUTNOT DAC Output Complement

18 V OUTNOT DAC Output Complement

20 AGND Analog Ground

26 BYPASS 0.1 µF Bypass to Ground 27 NC

28 ALTCOMPIB PTAT-IB Reference Compensation

(2)

29 AGND Analog Ground

30 AGND Analog Ground

32 LOOPCRNT DAC Reference Alt. Loop Current (Connect to AGND) 33 V EE (1) –5.2V Supply 34 V EE (1) –5.2V Supply NC: no connect NOTE: (1) Pins 5 and 55 typically draw 150mA of current. Pins 33 and 34 combined typically draw 46mA. (2) Connect bypass capacitor to VEE .

Substrate Bias: Negative Supply –VCC . NC = Do not connect. PAD FUNCTION

1 Bypass

2 CLK

3 CLKNOT

4 DGND

8 Bit 10

9 Bit 11

10 Bit 12

12 V OUT

13 LGND

14 LGND

16 V OUTNOT

18 AGND

27 ALTCOMPIB

28 AGND

29 AGND

31 LOOPCRNT

33 AV EE

34 V REF2

37 V REF

38 V REF

46 ALTCOMPC

47 AGND

49 LBIAS

53 Bit 1 (MSB)

55 DGND

56 DGND

57 Bit 2

58 Bit 3

59 Bit 4

63 Bit 5

64 DGND

65 Bit 6

66 Bit 7

67 DGND

68 Bit 8

MILS (0.001") MILLIMETERS Die Size 160 x 140 ±5 4.06 x 3.56 ±0.13 Die Thickness 20 ±3 0.51 ±0.08 Min. Pad Size 4 x 4 0.10 x 0.10 Backing Gold Metallization Gold DICE INFORMATION

DIFFERENTIAL NON-LINEARITY (–40°C) Code % of FSR 0 1000 3000 4000 0.012 0.0 –0.012 –0.024 2000 0.024 DIFFERENTIAL NON-LINEARITY (+85°C) Code % of FSR 0 1000 3000 4000 0.012 0.0 –0.012 –0.024 2000 0.024 INTEGRAL NON-LINEARITY (–40°C) Code % of FSR 0 1000 3000 4000 0.024 0.0 –0.024 –0.048 2000 0.048 INTEGRAL NON-LINEARITY (+25°C) Code % of FSR 0 1000 3000 4000 0.024 0.0 –0.024 –0.048 2000 0.048 INTEGRAL NON-LINEARITY (+85°C) Code % of FSR 0 1000 3000 4000 0.024 0.0 –0.024 –0.048 2000 0.048 DIFFERENTIAL NON-LINEARITY (+25°C) Code % of FSR 0 1000 3000 4000 0.012 0.0 –0.012 –0.024 2000 0.024 TYPICAL PERFORMANCE CURVES At TCASE = +25°C, VREF = +1.0V, measured at VOUT NOT . Spurious free dynamic range includes all harmonic or non-harmonic spurs in the bandwidth fCLK /2, unless otherwise noted.

fCLK = 256MHz, fO = 83.1MHz –20 –40 –60 –80 –100 (MHz) 64 12832 96 Amplitude (dB) OUTPUT SPECTRUM AT fCLK = 256MHz, fO = 55.3MHz –20 –40 –60 –80 –100 (MHz) 64 12832 96 Amplitude (dB) OUTPUT SPECTRUM AT fCLK = 256MHz, fO = 33.8MHz –20 –40 –60 –80 –100 (MHz) 64 12832 96 Amplitude (dB) OUTPUT SPECTRUM AT fCLK = 128MHz, fOUT = 41.5MHz –20 –40 –60 –80 –100 (MHz) 32 6416 48 Amplitude (dB) OUTPUT SPECTRUM AT fCLK = 128MHz, fO = 21.9MHz –20 –40 –60 –80 –100 (MHz) 32 6416 48 Amplitude (dB) OUTPUT SPECTRUM AT fCLK = 128MHz, fO = 11MHz –20 –40 –60 –80 –100 (MHz) Amplitude (dB) 03 2 6 4 16 48 TYPICAL PERFORMANCE CURVES (CONT) At TCASE = +25°C, VREF = +1.0V, measured at VOUT NOT . Spurious free dynamic range includes all harmonic or non-harmonic spurs in the bandwidth fCLK /2, unless otherwise noted.

SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY fOUT (MHz) Spurious Free Dynamic Range (dBc) +80 +75 +70 +65 +60 +55 +50 +45 10 20 30 40 50 60 250MHz 300MHz 150MHz 200MHz SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY fOUT (MHz) Spurious Free Dynamic Range (dBc) +80 +75 +70 +65 +60 +55 +50 10 20 30 40 50 60 50MHz 100MHz 150MHz 200MHz 3RD HARMONIC vs CLOCK FREQUENCY (fOUT ≈ 1/4 fCLOCK ) fCLOCK (MHz) 3rd Harmonic (dBc) 0 50 350 100 150 200 250 300 –48 –50 –52 –54 –56 –58 –60 –62 –64 –66 HARMONIC DISTORTION vs CLOCK FREQUENCY (fOUT ≈ 1/3 fCLOCK ) fCLOCK (MHz) 2nd and 3rd Harmonic (dBc) 0 50 350 100 150 200 250 300 –40 –45 –50 –55 –60 –65 –70 Reflected 2nd Harmonic Reflected 3rd Harmonic SPURIOUS FREE DYNAMIC RANGE vs CLOCK FREQUENCY (f OUT ≈ 1/16 fCLOCK ) +80 +75 +70 +65 +60 +55 f CLOCK (MHz) Spurious Free Dynamic Range (dBc) 50 350 100 150 200 250 300 SPURIOUS FREE DYNAMIC RANGE vs CLOCK FREQUENCY +75 +70 +65 +60 +55 +50 +45 f CLOCK (MHz) Spurious Free Dynamic Range (dBc) 50 350 100 150 200 250 300 10MHz 20MHz 50MHz TYPICAL PERFORMANCE CURVES (CONT) At TCASE = +25°C, VREF = +1.0V, measured at VOUT NOT . Spurious free dynamic range includes all harmonic or non-harmonic spurs in the bandwidth fCLK /2, unless otherwise noted.

SPURIOUS FREE DYNAMIC RANGE vs REFERENCE FREQUENCY VREF (MHz) Spurious Free Dynamic Range (dB) +80 +75 +70 +65 +60 +55 +50 +45 246 1 2 108 VREF Amplitude +0.75V DC 100mVp-p AC (All Bits on, 47pF Pin 35) REFERENCE CONTROL AMPLIFIER FREQUENCY RESPONSE VREF (MHz) Delta VOUT (dB) 0.5 0.0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 51 0 1 5 3 0 2520 35 VREF Amplitude +0.75V DC 100mVp-p AC (All Bits on, 47pF Pin 35) HARMONIC DISTORTION vs REFERENCE VOLTAGE (fOUT ≈ 1/4 fCLOCK ) 0.4 VREF (V) 2nd and 3rd Harmonic (dBc) –56 –58 –60 –62 –64 –66 –68 1.1 2nd Harmonic 3rd Harmonic REFERENCE VOLTAGE vs DISTORTION (fCLK = 128MHz, fOUT = 21.9MHz) 0.75 VREF (V) 2nd and 3rd Harmonic (dBc) –64 –65 –66 –67 –68 –69 –70 2nd Harmonic 3rd Harmonic SPURIOUS FREE DYNAMIC RANGE vs TEMPERATURE –60 Temperature (°C) Largest Spur (dBc) –70 –65 –60 –55 –50 –45 –40 –20 0 60 100 804020 50MHz 20MHz 1MHz 10MHz SPURIOUS FREE DYNAMIC RANGE vs TEMPERATURE –60 Temperature (°C) Spurious Free Dynamic Range (dBc) +74 –40 –20 0 60 100 804020 +72 +70 +68 +66 +64 +62 +60 20MHz 10MHz TYPICAL PERFORMANCE CURVES (CONT) At TCASE = +25°C, VREF = +1.0V, measured at VOUT NOT . Spurious free dynamic range includes all harmonic or non-harmonic spurs in the bandwidth fCLK /2, unless otherwise noted.

current sources on (–20mA), the output voltage is at –1V. Transfer function information is given in Tables I and II. FIGURE 1. Basic DAC600 Architecture. TABLE II. Nominal Bit Weight Values. TABLE I. Input Code vs Output Voltage Relationships.

“folding back” into the passband. tion error of the phase accumulator/ROM combination. tor and ROM specify the SFDR of their digital algorithm. FIGURE 7. Typical DAC600 Connection Diagram.