DAC4813

DAC4813 BURR-BROWN | Alldatasheet

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Technical content

QUAD 12-BIT DIGITAL-TO-ANALOG CONVERTER (12-bit port interface) © 1992 Burr-Brown Corporation PDS-1148C Printed in U.S.A. May, 1997

FEATURES

l COMPLETE WITH REFERENCE AND OUTPUT AMPLIFIERS l 12-BIT PORT INTERFACE l ANALOG OUTPUT RANGE: ±10V l MONOTONICITY GUARANTEED OVER TEMPERATURE l INTEGRAL LINEARITY ERROR: ±1/2LSB max l ±12V to ±15V SUPPLIES l 28-PIN PLASTIC DIP PACKAGE

DESCRIPTION

DAC4813 is a complete quad 12-bit digital-to-analog converter with bus interface logic. Each package in- cludes a precision +10V voltage reference, double- buffered bus interface including a RESET function and 12-bit D/A converters with voltage-output opera- tional amplifiers. The double-buffered interface consists of a 12-bit input latch and a D/A latch for each D/A converter. A RESET control allows the D/A outputs to be asyn- chronously reset to bipolar zero, a feature useful for power-up reset, system initialization and recalibration. DAC4813 D/A converters are committed to the ±10V output range only. Gain and offset are not externally adjustable. DAC4813 is available with a integral linearity error of 1/2LSB and 12-bit monotonicity guaranteed over tem- perature. It is packaged in a 28-pin 0.6in. wide plastic DIP package and specified over –40oC to +85oC and 0°C to +70°C. VREF OUT VOUT 1 D/A 1 DB0 DB11 LSB MSB VOUT 2 D/A 2 VOUT 3 D/A 3 VOUT 4 D/A 4 DAC4813 10V Reference 12-bit Latches International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

TA = +25oC, +VCC = +12V or +15V, –VCC = –12V or –15V, unless otherwise noted. DAC4813AP, JP PARAMETER CONDITIONS MIN TYP MAX UNITS INPUTS DIGITAL INPUTS Over Temperature Input Code (1) Range Bipolar Offset Binary Logic Levels (2) VIH (3) +2 +5.5 V VIL 0 +0.8 V Logic Input Currents DB0-DB11, WR, LDAC, RESET,EN X IIH VI = +2.7V ±40 µA IIL VI = +0.4V ±40 µA TRANSFER CHARACTERISTICS ACCURACY Linearity Error ±1/4 ±1/2 LSB Differential Linearity Error ±1/2 ±1 LSB Gain Error ±0.05 ±0.2 % Bipolar Zero Error (5) ±0.05 ±0.2 %FSR (4) Power Supply Sensitivity Of Full Scale +VCC ±5 ±20 ppmFSR/%+V CC –VCC ±1 ±10 ppmFSR/%–V CC DRIFT Over Specification Temperature Range Gain ±5 ±30 ppm/ °C Bipolar Zero Drift ±5 ±15 ppmFSR/ °C Linearity Error over Temperature ±1/2 ±3/4 LSB Monotonicity Guaranteed DYNAMIC CHARACTERISTICS SETTLING TIME (6) To within ±0.012%FSR of Final Value 5kΩ || 500pF Load Full Scale Range Change 20V Range 4.5 6 µs 1LSB Output Step (7) At Major Carry 2 µs Slew Rate 10 V/ µs Crosstalk (8) 5kΩ Loads 0.2 LSB OUTPUT Output Voltage Range ±VCC ≥ ±11.4V ±10 V Output Current ±5m A Output Impedance 0.2 Ω Short Circuit to ACOM Duration at DC Indefinite REFERENCE VOLTAGE Voltage +9.95 +10.00 +10.05 V Source Current Available for External Loads 2 mA Impedance 0.2 Ω Temperature Coefficient ±5 ±25 ppm/ °C Short Circuit to Common Duration at DC Indefinite POWER SUPPLY REQUIREMENTS Voltage: +VCC +11.4 +15 +16.5 V Current: No Load ±VCC = ±15V +VCC 48 60 mA –VCC 24 28 mA Power Dissipation 1080 1320 mW Potential at DCOM with Respect to ACOM (9) –3 +3 V TEMPERATURE RANGES Specification: AP –40 +85 °C JP 0 +70 °C Storage –60 +100 °C Thermal Resistance, θJA,Plastic DIP 30 °C/W NOTES: (1) For Two’s Complement Input Coding invert the MSB with an external logic inverter. (2) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (3) Open DATA input lines will be pulled above +5.5V. See discussion under LOGIC INPUT COMPATIBILITY in the OPERATION section. (4) FSR means Full Scale Range. For example, for ±10V output, FSR = 20V. (5) Error at input code 800HEX . (6) Maximum represents the 3σ limit. Not 100% tested for this parameter. (7) For the worst-case code change: 7FFHEX to 800HEX and 800HEX to 7FFHEX . (8) Crosstalk is defined as the change in any output as a result of any other output being driven from –10V to +10V at rated output current. (9) The maximum voltage at which ACOM and DCOM may be separated without affecting accuracy specifications.

NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE DRAWING TEMPERATURE PRODUCT PACKAGE NUMBER (1) RANGE DAC4813AP 28-Pin Plastic DBL Wide DIP 215 –40 °C to +85°C DAC4813JP 28-Pin Plastic DBL Wide DIP 215 0 °C to +70°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. PACKAGE/ORDERING INFORMATION ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from per- formance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. TIMING DIAGRAMS > 5ns > 50ns > 50ns (Load first rank from Data Bus: LDAC = 1) DB11–DB0 WR > 50ns WRITE CYCLE #1 EN X tSETTLING ±1/2LSB LDAC WR > 50ns > 50ns V OUT WRITE CYCLE #2 (Load second rank from first rank: ENX = 1) ±1/2LSB Reset > 50ns+10V –10V tSETTLING VOUT RESET COMMAND (Bipolar Mode) EN X, LDAC, WR = Don’t Care TRUTH TABLE WR EN1 EN2 EN3 EN4 LDAC RESET OPERATION X X X X X X 0 Reset all D/A Latches

1 X X X X X 1 No Operation

X 1 1 1 1 1 1 No Operation 0 1 1 1 0 1 1 Load Data into First Rank for D/A 4 0 1 1 0 1 1 1 Load Data into First Rank for D/A 3 0 1 0 1 1 1 1 Load Data into First Rank for D/A 2 0 0 1 1 1 1 1 Load Data into First Rank for D/A 1 0 1 1 1 1 0 1 Load Second Rank from First Rank, All D/As 0 0 0 0 0 0 1 All Latches Transparent “X” = Don’t Care

1 DB11 DATA, MSB, positive true.

2 DB10 DATA

3 DB9 DATA

4 DB8 DATA

5 DB7 DATA

6 DB6 DATA

7 DB5 DATA

8 DB4 DATA

9 DB3 DATA

10 DB2 DATA

11 DB1 DATA

12 DB0 DATA, LSB. 13 RESET Resets output of all D/As to bipolar-zero. The D/A remains in this state until overwritten by a LDAC-WR command. RESET does not reset the input latch. After power–up and reset, input latches will be in an indeterminant state. 14 WR Write strobe. Must be low for data transfer to any latch (except RESET). 15 EN1 Enable for 12-bit input data latch of D/A1. NOTE: This logic path is slower than the WR/ path. 16 EN2 Enable for 12-bit input data latch of D/A2. NOTE: This logic path is slower than the WR/ path. 17 EN3 Enable for 12-bit input data latch of D/A3. NOTE: This logic path is slower than the WR /path. 18 EN4 Enable for 12-bit input data latch of D/A4. NOTE: This logic path is slower than the WR/ path. 19 LDAC Load DAC enable. Must be low with WR for data transfer to the D/A latch and simultaneous update of all D/A converters. 20 DCOM Digital common, logic currents return. 21 –V CC Analog supply input, nominally –12V or –15V referred to ACOM. 22 ACOM Analog common, +V CC , –VCC supply return. 23 +V CC Analog supply input, nominally +12V or +15V referred to ACOM. 24 V OUT 4 D/A 4 analog output. 25 V OUT 3 D/A 3 analog output. 26 V OUT 2 D/A 2 analog output. 27 V OUT 1 D/A 1 analog output. 28 V REF OUT +10V reference output. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

25kΩ 25kΩ 12-Bit D/A Converter 123456789 1 0 1 1 1 2 MSB DB11 50kΩ +10V Reference 22 23 21 +VCC –VCCACOMVREF OUT WR 14 EN 1 15 12-Bit Input Latch VOUT 1 0–800µA DCOM 25kΩ 25kΩ 12-Bit D/A Converter 2650kΩ EN 2 16 12-Bit Input Latch VOUT 2 0–800µA 25kΩ 25kΩ 12-Bit D/A Converter 2550kΩ EN 3 17 12-Bit Input Latch VOUT 3 0–800µA 25kΩ 25kΩ 12-Bit D/A Converter 2450kΩ EN 4 18 12-Bit Input Latch VOUT 4 0–800µALDAC 19 RESET 13 12-Bit D/A Latch 12-Bit D/A Latch 12-Bit D/A Latch 12-Bit D/A Latch NOTE: RESET does not reset input latches.

TYPICAL PERFORMANCE CURVES TA = +25°C, VCC = ±15V unless otherwise noted. Frequency (Hz) [Change in FSR]/[Change in Supply Voltage] 10 100 1k 10k 100k 1M POWER SUPPLY REJECTION vs POWER SUPPLY RIPPLE FREQUENCY (ppm of FSR/ %) 100 0.1 +VCC –VCC 12.0 9.6 7.2 4.8 2.4 –2.4 –4.8 –7.2 –9.6 –12.0 Input Current (µA) – 2 02468 Input Voltage (V) DIGITAL INPUT CURRENT vs INPUT VOLTAGE EN X DB 0-DB11: DAC4813 RESET, LDAC WR 0.5 –0.5 –60 –20 20 60 100 140 Temperature (°C) CHANGE OF GAIN AND OFFSET ERROR vs TEMPERATURE 0.8 0.4 –0.4 –0.8 Gain Error Bipolar Offset Unipolar Offset Bipolar/Unipolar Offset (%) (For 10V FSR; Double for 20V FSR) Δ Gain Error (%)Δ 0.5 –0.5 000 Input Code (Hexidecimal) INTEGRAL LINEARITY ERROR Linearity Error (LSB) 400 800 C00 FFF –10 –15 0 5 10 15 20 25 Time (µs) ± FULL SCALE OUTPUT SWING V (V)OUT WR VOUT WR (V) MAJOR CARRY GLITCH Time (µs) VOUT (mV) 250 200 150 100 – 2 02468 1 0 1 2 1 4 +10 WR (V)Data = 7FFH Data = 800H Data = 7FFH

TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VCC = ±15V unless otherwise noted. DISCUSSION OF SPECIFICATIONS LINEARITY ERROR Linearity error is defined as the deviation of the analog output from a straight line drawn between the end points (digital inputs all “1s” and all “0s”). DAC4813 linearity error is ±1/2LSB max at +25oC. DIFFERENTIAL LINEARITY ERROR Differential Linearity Error (DLE) is the deviation from a 1LSB output change from one adjacent state to the next. A DLE specification of 1/2LSB means that the output step size can range from 1/2LSB to 3/2LSB when the digital input code changes from one code word to the adjacent code word If the DLE is more positive than –1LSB, the D/A is said to be monotonic. MONOTONICITY A D/A converter is monotonic if the output either increases or remains the same for increasing digital input values. DAC4813 is monotonic over their specification temperature range –40oC to +85oC. DRIFT Gain Drift is a measure of the change in the Full Scale Range (FSR) output over the specification temperature range. Gain Drift is expressed in parts per million per degree Celsius (ppm/oC). Bipolar Zero Drift is measured with a data input of 800HEX . The D/A is configured for bipolar output. Bipolar Zero Drift is expressed in parts per million of Full Scale Range per degree Celsius (ppm of FSR/oC). SETTLING TIME Settling Time is the total time (including slew time) for the output to settle to within an error band around its final value after a change in input. Settling times are specified to ±0.01% of Full Scale Range (FSR) for two conditions: one for a FSR output change of 20V (25kΩ feedback) and one for a 1LSB change. The 1LSB change is measured at the Major Carry (7FFHEX to 800HEX , and 800HEX to 7FFHEX ), the input code transition at which worst-case settling time oc- curs. OPERATION INTERFACE LOGIC The bus interface logic of the DAC4813 consists of two independently addressable latches in two ranks for each D/A converter. The first rank consists of one 12-bit input latch which can be loaded directly from a 12- or 16-bit microprocessor/microcontroller bus. The input latch holds data temporarily before it is loaded into the second latch, the D/A latch. This double buffered organization permits simul- taneous update of all D/As. All latches are level-triggered. Data present when the con- trol signals are logic “0” will enter the latch. When the control signals return to logic “1”, the data is latched. CAUTION: DAC4813 was designed to use WR as the fast strobe. WR has a much faster logic path than ENX (or LDAC). Therefore, if one permanently wires WR to DCOM and uses only ENX to strobe data into the latches, the DATA HOLD time will be long, approximately 20ns to 30ns, and this time will vary considerably in this range from unit to unit. DATA HOLD time using WR is 5ns max. –10 –20 –40 VOUT Around +10V (mV) Time (µs) SETTLING TIME, –10V TO +10V WR (V) 02468 1 0 1 2 1 4 VOUT WR VOUT 1LSB = 4.88mV20 –10 –20 VOUT Around –10V (mV) Time (µs) SETTLING TIME, +10V TO –10V 0 2 4 6 8 10 12 WR (V) 1LSB = 4.88mVVOUT WR VOUT

DAC4813 has no Gain and Offset Adjustment option. time may be ale to use 0.01µF at –VCC as well as at +VCC . The capacitors should be located close to the package. also important to connect the load directly to the ACOM pin. while operating on supplies as low as ±12V ±5%. tional ranges are not pin programmable. data from the bus to each input latch by asserting WR low. neously by asserting LDAC and WR low. INPUT COMPATIBILITY section. output value that may be unwanted. equivalent circuit of a digital input is shown in Figure 1. should be connected to DCOM. through a 100kΩ resistor to limit the input current. FIGURE 1. Equivalent Digital Input Circuit. DAC4813 accepts positive-true binary input codes. logic inverter is used ahead of the MSB input (DB11).