DAC43401DSGR

DAC53401 TI | Alldatasheet

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L DACx3401 VDDVIN Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC53401, DAC43401 SLASES7A – JULY 2019–REVISED DECEMBER 2019 DACx340110-Bitand8-Bit,Voltage-OutputDigital-to-AnalogConvertersWithNonvolatile MemoryandPMBus™ CompatibleI2CInterfaceinTiny2×2WSON

1 Features

1• 1 LSB INL and DNL (10-bit and 8-bit)

• Wide operating range – Power supply: 1.8 V to 5.5 V – Temperature range: –40˚C to +125˚C
• PMBus™ compatible I2C interface – Standard, Fast, and Fast+ modes – Digital slew rate control – 1.62-V VIH with VDD = 5.5 V
• User-programmable nonvolatile memory (NVM/EEPROM) – Save and recall all register settings
• Programmable waveform generation: Square, ramp, and sawtooth
• Preprogrammed medical-alarm tone-generation mode: low, medium, and high priority alarms
• Internal reference
• Very low power: 0.2 mA at 1.8 V
• Flexible startup: High impedance or 10K-GND
• Tiny package: 8-pin WSON (2 mm × 2 mm)

2 Applications

• Rack server
• Exit and emergency lighting
• Automotive USB charge
• Barcode scanner
• Active antenna system mMIMO (AAS)
• CPU (PLC controller)

3 Description

The 10-bit DAC53401 and 8-bit DAC43401 (DACx3401) are a pin-compatible family of buffered voltage-output digital-to-analog converters (DACs). These devices consume very low power, and are available in a tiny 8-pin WSON package. The feature set combined with the tiny package and low power make the DACx3401 an excellent choice for applications such as LED and general-purpose bias point generation, power supply control, digitizers, PWM signal generation, and medical alarm tone generation. These devices have nonvolatile memory (NVM), an internal reference, and a PMBus-compatible I2C interface. The DACx3401 operates with either an internal reference or the power supply as a reference, and provides full-scale output of 1.8 V to 5.5 V. The devices communicate through the I2C interface. These devices support I2C standard mode, fast mode, and fast+ mode. The DACx3401 are feature rich, and include PMBus voltage margin commands, user-programmable power up to high impedance, standalone waveform generator, medical alarm tone generator, dedicated feedback pin, and more. The DACx3401 operate within the temperature range of –40°C to +125°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DAC53401 WSON (8) 2.00 mm × 2.00 mm DAC43401 (1) For all available packages, refer to the package option addendum at the end of the data sheet. Functional Block Diagram Power-Supply Control With the DACx3401

DAC53401, DAC43401 SLASES7A – JULY 2019– REVISED DECEMBER 2019 www.ti.com Product Folder Links: DAC53401 DAC43401 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Table of Contents 7.9 Typical Characteristics: VDD = 1.8 V (Reference = 7.10 Typical Characteristics: VDD = 5.5 V (Reference =

12.3 Receiving Notification of Documentation Updates 47

13 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Original (July 2019) to Revision A Page

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5 Device Comparison Table

6 Pin Configuration and Functions

NAME NO. A0 1 Input Four-state address input AGND 5 Ground Ground reference point for all circuitry on the device CAP 4 Input External capacitor for the internal LDO. Connect a capacitor (0.5 µF to 15 µF) between CAP and AGND. FB 7 Input Voltage feedback pin OUT 8 Output Analog output voltage from DAC SCL 2 Input Serial interface clock. This pin must be connected to the supply voltage with an external pullup resistor. SDA 3 Input/output Data are clocked into or out of the input register. This pin is a bidirectional, and must be connected to the supply voltage with an external pullup resistor. VDD 6 Power Analog supply voltage: 1.8 V to 5.5 V

DAC53401, DAC43401 SLASES7A – JULY 2019– REVISED DECEMBER 2019 www.ti.com Product Folder Links: DAC53401 DAC43401 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VDD Supply voltage, VDD to AGND –0.3 6 V Digital input(s) to AGND –0.3 VDD + 0.3 V CAP to AGND –0.3 1.65 VVFB to AGND –0.3 VDD + 0.3 VOUT to AGND –0.3 VDD + 0.3 Current into any pin –10 10 mA TJ Junction temperature –40 150 Tstg Storage temperature –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, Charged device model (CDM), per JEDEC specification JESD22-C101,

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Positive supply voltage to ground (AGND) 1.71 5.5 V VIH Digital input high voltage, 1.7 V < VDD ≤ 5.5 V 1.62 V VIL Digital input low voltage 0.4 V TA Ambient temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information

THERMAL METRIC(1) DACx3401 UNITDSG (WSON)

8 PINS

RθJA Junction-to-ambient thermal resistance 49 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50 °C/W RθJB Junction-to-board thermal resistance 24.1 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 24.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.7 °C/W

DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019– REVISED DECEMBER 2019 Product Folder Links: DAC53401 DAC43401 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated (1) Measured with DAC output unloaded. For external reference between end-point codes: 8d to 1016d for 10-bit resolution, 2d to 254d for 8-bit resolution. For internal reference VDD ≥ 1.21 x gain + 0.2 V, between end-point codes: 8d to 1016d for 10-bit resolution, 2d to 254d for 8-bit resolution. (2) Specified by design and characterization, not production tested.

7.5 Electrical Characteristics

all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤ VDD ≤ 5.5 V, DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE Resolution DAC53401 10 Bits DAC43401 8 INL Relative accuracy(1) –1 1 LSB DNL Differential nonlinearity(1) –1 1 LSB Zero code error Code 0d into DAC 6 12 mV Internal VREF, gain = 4x, VDD = 5.5 V 6 15 Zero code error temperature coefficient ±10 µV/°C Offset error(1) –0.5 0.25 0.5 %FSR Offset error temperature coefficient(1) ±0.0003 %FSR/°C Gain error(1) –0.5 0.25 0.5 %FSR Gain error temperature coefficient(1) ±0.0008 %FSR/°C Full scale error 1.8 V ≤ VDD ≺ 2.7 V, code 1023d into DAC, no headroom –1 0.5 1 %FSR 2.7 V ≤ VDD ≤ 5.5 V, code 1023d into DAC, no headroom –0.5 0.25 0.5 Full scale error temperature coefficient ±0.0008 %FSR/°C OUTPUT CHARACTERISTICS Output voltage Reference tied to VDD 0 5.5 V CL Capacitive load(2) RL = Infinite, phase margin = 30° 1 nF RL = 5 kΩ, phase margin = 30° 2 Load regulation DAC at midscale, –10 mA ≤ IOUT ≤ 10 mA, VDD = 5.5 V 0.4 mV/mA Short circuit current VDD = 1.8 V, full-scale output shorted to AGND or zero-scale output shorted to VDD mAVDD = 2.7 V, full-scale output shorted to AGND or zero-scale output shorted to VDD VDD = 5.5 V, full-scale output shorted to AGND or zero-scale output shorted to VDD Output voltage headroom(1) To VDD (DAC output unloaded, internal reference = 1.21 V), VDD ≥ 1.21 ☓ gain + 0.2 V 0.2 V To VDD (DAC output unloaded, reference tied to VDD) 0.8 %FSRTo VDD (ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V), DAC code = full scale VOUT dc output impedance DAC output enabled and DAC code = midscale 0.25 ΩDAC output enabled and DAC code = 4d 0.25 DAC output enabled and DAC code = 1016d 0.26

DAC53401, DAC43401 SLASES7A – JULY 2019– REVISED DECEMBER 2019 www.ti.com Product Folder Links: DAC53401 DAC43401 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤ VDD ≤ 5.5 V, DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (3) Specified with 200-mV headroom with respect to reference value when internal reference is used. ZO VFB dc output impedance(3) DAC output enabled, DAC reference tied to VDD (gain = 1x) or internal reference (gain = 1.5x or 2x) 160 200 240 kΩ DAC output enabled, internal VREF, gain = 3x or 4x 192 240 288 VOUT + VFB dc output leakage(2) At startup, measured when DAC output is disabled and held at VDD / 2 for VDD = 5.5 V 5 nA Power supply rejection ratio (dc) Internal VREF, gain = 2x, DAC at midscale; VDD = 5 V ±10% 0.25 mV/V DYNAMIC PERFORMANCE tsett Output voltage settling time 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V 8 µs 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V, internal VREF, gain = 4x 12 Slew rate VDD = 5.5 V 1 V/µs Power on glitch magnitude At startup (DAC output disabled), RL = 5 kΩ, CL = 200 pF 75 mV At startup (DAC output disabled), RL = 100 kΩ 200 Output enable glitch magnitude DAC output disabled to enabled (DAC registers at zero scale, RL = 100 kΩ 250 mV Vn Output noise voltage (peak to peak) 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 34 µVPPInternal VREF, gain = 4x, 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 70 Output noise density Measured at 1 kHz, DAC at midscale, VDD = 5.5 V 0.2 µV/√HzInternal VREF, gain = 4x,, measured at 1 kHz, DAC at midscale, VDD = 5.5 V 0.7 Power supply rejection ratio (ac)(3) Internal VREF, gain = 4x, 200-mV 50 or 60 Hz sine wave superimposed on power supply voltage, DAC at midscale –71 dB Code change glitch impulse ±1 LSB change around mid code (including feedthrough) 10 nV-s Code change glitch impulse magnitude ±1 LSB change around mid code (including feedthrough) 15 mV EEPROM Endurance –40°C ≤ TA ≤ 85°C 20000 Cycles 1000 Data retention(2) TA = 25°C 50 Years EEPROM programming write cycle time(2) 5 10 15 ms DIGITAL INPUTS Digital feedthrough DAC output static at midscale, fast+ mode, SCL toggling 20 nV-s Pin capacitance Per pin 10 pF POWER Load capacitor - CAP pin(2) 0.5 15 µF IDD Current flowing into VDD Normal mode, DACs at full scale, digital pins static 0.5 0.8 mA DAC power-down, internal reference power down 80 µA

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7.6 Timing Requirements: I2CTM Standard mode

all input signals are timed from VIL to 70% of VDD, 1.8 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, 1.8 V ≤ Vpull-up ≤ VDD V MIN NOM MAX UNIT fSCLK SCL frequency 0.1 MHz tBUF Bus free time between stop and start conditions 4.7 µs tHDSTA Hold time after repeated start 4 µs tSUSTA Repeated start setup time 4.7 µs tSUSTO Stop condition setup time 4 µs tHDDAT Data hold time 0 ns tSUDAT Data setup time 250 ns tLOW SCL clock low period 4700 ns tHIGH SCL clock high period 4000 ns tF Clock and data fall time 300 ns tR Clock and data rise time 1000 ns

7.7 Timing Requirements: I2CTM Fast mode

all input signals are timed from VIL to 70% of VDD, 1.8 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, 1.8 V ≤ Vpull-up ≤ VDD V MIN NOM MAX UNIT fSCLK SCL frequency 0.4 MHz tBUF Bus free time between stop and start conditions 1.3 µs tHDSTA Hold time after repeated start 0.6 µs tSUSTA Repeated start setup time 0.6 µs tSUSTO Stop condition setup time 0.6 µs tHDDAT Data hold time 0 ns tSUDAT Data setup time 100 ns tLOW SCL clock low period 1300 ns tHIGH SCL clock high period 600 ns tF Clock and data fall time 300 ns tR Clock and data rise time 300 ns

7.8 Timing Requirements: I2CTM Fast+ mode

Figure 1. Timing Diagram

7.11 Typical Characteristics

Figure 22. Integral Linearity Error vs Supply Voltage Figure 23. Differential Linearity Error vs Supply Voltage Figure 24. Total Unadjusted Error vs Supply Voltage Figure 25. Zero-Code Error vs Supply Voltage Figure 26. Offset Error vs Supply Voltage Figure 27. Gain Error vs Supply Voltage

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8 Detailed Description

8.1 Overview

The 10-bit DAC53401 and 8-bit DAC43401 (DACx3401) are a pin-compatible family of buffered voltage-output, digital-to-analog converters (DACs). These DACs contain nonvolatile memory (NVM), an internal reference, and a PMBus-compatible I2C interface. The DACx3401 operate with either an internal reference or with a power supply as the reference, and provide a full-scale output of 1.8 V to 5.5 V. The devices communicate through an I2C interface. These devices support I2C standard mode (100 kbps), fast mode (400 kbps), and fast+ mode (1 Mbps). These devices also support specific PMBus commands such as turn on/off, margin high/low, and more. The DACx3401 also include digital slew rate control, and support basic signal generation such as square, ramp, and sawtooth waveforms. The DACx3401 devices have a power-on-reset (POR) circuit that makes sure all the registers start with default or user-programmed settings using NVM. The DAC output powers on in high-impedance mode (default); this setting can be programmed to 10kΩ-GND using NVM.

8.2 Functional Block Diagram

DAC _ DATAV V GAIN u u OUT DD N DAC _ DATAV V u DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019– REVISED DECEMBER 2019 Product Folder Links: DAC53401 DAC43401 Submit Documentation FeedbackCopyright © 2019, Texas Instruments Incorporated

8.3 Feature Description

8.3.1 Digital-to-Analog Converter (DAC) Architecture

The DACx3401 family of devices consists of string architecture with an output buffer amplifier. The Functional Block Diagram section shows the DAC architecture within the block diagram. This DAC architecture operates supply. The DAC output pin starts up in high impedance mode making it an excellent choice for power-supply control applications. To change the power-up mode to 10kΩ-GND, program the DAC_PDN bit (address: D1h), and load these bits in the device NVM.

8.3.1.1 Reference Selection and DAC Transfer Function

The device writes the input data to the DAC data registers in straight-binary format. After a power-on or a reset event, the device sets all DAC registers to the values set in the NVM.

8.3.1.1.1 Power Supply as Reference

By default, the DACx3401 operate with the power-supply pin (VDD) as a reference. Equation 1 shows DAC transfer function when the power-supply pin is used as reference. where:

• N is the resolution in bits, either 8 (DAC43401) or 10 (DAC53401).
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC register.
• DAC_DATA ranges from 0 to 2N – 1.
• VDD is used as the DAC reference voltage. (1)

8.3.1.1.2 Internal Reference

The DACx3401 also contain an internal reference that is disabled by default. Enable the internal reference by writing 1 to REF_EN (address D1h). The internal reference generates a fixed 1.21-V voltage (typical). Using DAC_SPAN (address D1h) bits, gain of 1.5X, 2X, 3X, 4X can be achieved for the DAC output voltage (VOUT) Equation 2 shows DAC transfer function when the internal reference is used. where:

• N is the resolution in bits, either 8 (DAC43401) or 10 (DAC53401).
• DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC register
• DAC_DATA ranges from 0 to 2N – 1.
• VREF is the internal reference voltage = 1.21 V.
• GAIN = 1.5x, 2x, 3x, 4x based on DAC_SPAN (address D1h) bits. (2)

8.3.2 DAC Update

The DAC output pin (OUT) is updated at the end of I2C DAC write frame.

8.3.2.1 DAC Update Busy

completed (DAC_UPDATE_BUSY = 0), any of the DAC registers can be written.

8.3.3 Nonvolatile Memory (EEPROM or NVM)

operation, the NVM_BUSY bit is set to 1. Table 1. NVM Programmable Registers

13 DEVICE_LOCK

2 REF_EN

10 MED_ALARM_HP

9 MED_ALARM_MP

8 MED_ALARM_LP

8.3.3.1 NVM Cyclic Redundancy Check

are read from the device NVM.

8.3.3.2 NVM_CRC_ALARM_USER Bit

command, or cycle power to the DAC. Alternatively, cycle the power to reload the user-programmable NVM bits.

8.3.3.3 NVM_CRC_ALARM_INTERNAL Bit

8.3.4 Programmable Slew Rate

digital slew updates; CODE_STEP defines the amount by which the output value changes at each update. Table 2 and Table 3 show different settings for CODE_STEP and SLEW_RATE. DAC_DATA during the output slew. Table 2. Code Step

Table 3. Slew Rate

8.3.5 Power-on-Reset (POR)

value for all the registers in the DACx3401 is loaded from NVM as soon as the POR event is issued. VDD remains greater than 1.65 V, a POR does not occur. Figure 48. Threshold Levels for VDD POR Circuit

8.3.6 Software Reset

software reset initiates a POR event.

8.3.7 Device Lock Feature

DEVICE_LOCK setting, write 0101 to the DEVICE_UNLOCK_CODE bits (address D3h).

8.3.8 PMBus Compatibility

to enable the PMBus protocol. most significant byte first format (see Table 10). Figure 49. PMBus Connections

8.4 Device Functional Modes

8.4.1 Power Down Mode

(at power up), use the DAC_PDN bits (address D1h). The DAC power-up state can be programmed to any state (power-down or normal mode) using the NVM. Table 4 shows the DAC power-down bits. Table 4. DAC Power-Down Bits

8.4.2 Continuous Waveform Generation (CWG) Mode

OUT pin, high and low codes, and slew rate settings as shown in the following equations.

• SLEW_RATE is the programmable DAC slew rate specified in Table 3. (3) where:
• SLEW_RATE is the programmable DAC slew rate specified in Table 3.
• MARGIN_HIGH and MARGIN_LOW are the programmable DAC codes.
• CODE_STEP is the programmable DAC step code in Table 2. (4) where:
• SLEW_RATE is the programmable DAC slew rate specified in Table 3.
• MARGIN_HIGH and MARGIN_LOW are the programmable DAC codes.
• CODE_STEP is the programmable DAC step code in Table 2. (5)

Table 5. FUNC_CONFIG bits

8.4.3 PMBus Compatibility Mode

EN_PMBus bit (Bit 12, address D1h) must be set to 1 to enable the PMBus protocol. Table 6. PMBus Operation Commands To get the PMBus version, read the PMBUS_VERSION bits (address 98h).

8.4.4 Medical Alarm Generation Mode

simple circuit, and with no need for runtime software.

8.4.4.1 Low-Priority Alarm

abruptly end the alarm generation; the device stops only after completing the ongoing burst.

8.4.4.2 Medium-Priority Alarm

abruptly end the alarm generation; the device stops only after completing the ongoing burst.

8.4.4.3 High-Priority Alarm

abruptly end the alarm generation; the device stops only after completing the ongoing burst.

8.4.4.4 Interburst Time

Table 7. Interburst Time

8.4.4.5 Pulse Off Time

waveform. Table 8 lists the PULSE_OFF_TIME settings. Table 8. Pulse Off Time

8.4.4.6 Pulse On Time

The PULSE_ON_TIME bit (address D2h) controls the high period of trapezoid in a medical alarm waveform. Table 9 lists the PULSE_ON_TIME settings. Table 9. Pulse On Time

8.5 Programming

devices connect to the I2C bus through the open drain I/O pins, SDA and SCL. and write refer to the master device.

• Standard mode (100 kbps)
• Fast mode (400 kbps)
• Fast+ mode (1.0 Mbps) The data transfer protocol for standard and fast modes is exactly the same; therefore, both modes are referred to as F/S-mode in this document. The fast+ mode protocol is supported in terms of data transfer speed, but not output current. The low-level output current would be 3 mA; similar to the case of standard and fast modes. The DACx3401 family supports 7-bit addressing. The 10-bit addressing mode is not supported. The device supports the general call reset function. Sending the following sequence initiates a software reset within the device: start or repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the rising edge of the ACK bit, following the second byte. Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock cycle generates and detects an acknowledge signal. Acknowledge is when the SDA line is pulled low during the high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high period of the ninth clock cycle as shown in Figure 50.

Figure 50. Acknowledge and Not Acknowledge on the I2C Bus

8.5.1 F/S Mode Protocol

The following steps explain a complete transaction in F/S mode.

1. The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

recognize a start condition.

1. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit

Figure 52. All devices recognize the address sent by the master and compare the address to the respective detects this acknowledge, the communication link with a slave has been established.

1. The master generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the slave. In

consists of 8-data bits and 1 acknowledge-bit, and can continue as long as necessary.

1. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from

Figure 51. Start and Stop Conditions Figure 52. Bit Transfer on the I2C Bus

8.5.2 DACx3401 I2C Update Sequence

data bytes, as listed in Table 10. Table 10. Update Sequence Figure 53. I2C Bus Protocol on the falling edge of the acknowledge signal that follows the LSDB. the DACx3401 device releases the I2C bus and awaits a new start condition.

8.5.3 Address Byte

address pin, and consequently responds to that particular address according to Table 12. respond regardless of the states of the address pins. Broadcast is supported only in write mode.

Table 11. Address Byte Table 12. Address Format

000 AGND

001 VDD

010 SDA

011 SCL

8.5.4 Command Byte

Table 16 lists the command byte. Table 13. Command Byte (Register Names)

8.5.5 I2C Read Sequence

1. Send a start or repeated start command with a slave address and the R/W bit set to 0 for writing. The device
2. Send a command byte for the register to be read. The device acknowledges this event again.
3. Send a repeated start with the slave address and the R/W bit set to 1 for reading. The device acknowledges
4. The device writes the MSDB byte of the addressed register. The master must acknowledge this byte.
5. Finally, the device writes out the LSDB of the register.

Note that it is not possible to use the broadcast address for reading. Table 14. Read Sequence

8.6 Register Map

Table 15. Register Map

Table 16. Register Names Table 17. Access Type Codes

8.6.1 STATUS Register (address = D0h) (reset = 000Ch or 0014h)

Figure 54. STATUS Register Table 18. STATUS Register Field Descriptions

15 NVM_CRC_ALARM_USER R 0 0 : No CRC error in user NVM bits

14 NVM_CRC_ALARM_INTERNAL R 0 0 : No CRC error in internal NVM

13 NVM_BUSY R 0 0 : NVM write or load completed, Write to DAC registers

12 DAC_UPDATE_BUSY R 0 0 : DAC outputs updated, Write to DAC registers allowed

8.6.2 GENERAL_CONFIG Register (address = D1h) (reset = 01F0h)

Figure 55. GENERAL_CONFIG Register Table 19. GENERAL_CONFIG Register Field Descriptions slope defined by SLEW_RATE (address D1h) bits. and low period defined by SLEW_RATE (address D1h) bits.

13 DEVICE_LOCK W 0 0 : Device not locked

12 EN_PMBUS R/W 0 0: PMBus mode disabled

Table 19. GENERAL_CONFIG Register Field Descriptions (continued) 11 - 9 CODE_STEP R/W 000 Code step for programmable slew rate control. 8 - 5 SLEW_RATE R/W 1111 Slew rate for programmable slew rate control.

2 REF_EN R/W 0 0: Internal reference disabled, VDD is DAC reference voltage,

DAC output range from 0 to VDD. 1 - 0 DAC_SPAN R/W 00 Only applicable when internal reference is enabled.

8.6.3 MED_ALARM_CONFIG Register (address = D2h) (reset = 0000h)

Figure 56. MED_ALARM_CONFIG Register Table 20. MED_ALARM_CONFIG Register Field Descriptions

10 MED_ALARM_HP W 0 0: No medical alarm waveform generated

9 MED_ALARM_MP W 0 0: No medical alarm waveform generated

8 MED_ALARM_LP W 0 0: No medical alarm waveform generated

8.6.4 TRIGGER Register (address = D3h) (reset = 0008h)

Figure 57. TRIGGER Register Table 21. TRIGGER Register Field Descriptions 15 - 12 DEVICE_UNLOCK_CODE W 0000 Write 0101 to unlock the device to bypass DEVICE_LOCK bit.

9 DEVICE_CONFIG_RESET W 0 0: Device configuration reset not initiated

8 START_FUNC_GEN W 0 0: Continuous waveform generation mode disabled

7 PMBUS_MARGIN_HIGH R/W 0 0: PMBus margin high command not initiated

6 PMBUS_MARGIN_LOW R/W 0 0: PMBus margin low command not initiated

resets to 0 after the DAC code reaches MARGIN_LOW value.

5 NVM_RELOAD W 0 0: NVM reload not initiated

is in progress.. This is a self-resetting bit.

4 NVM_PROG W 0 0: NVM write not initiated

8.6.5 DAC_DATA Register (address = 21h) (reset = 0000h)

Figure 58. DAC_DATA Register Table 22. DAC_DATA Register Field Descriptions channel to update the active register data to the DAC_DATA.

8.6.6 DAC_MARGIN_HIGH Register (address = 25h) (reset = 0000h)

Figure 59. DAC_MARGIN_HIGH Register Table 23. DAC_MARGIN_HIGH Register Field Descriptions W 000h Margin high code for DAC output.

8.6.7 DAC_MARGIN_LOW Register (address = 26h) (reset = 0000h)

Figure 60. DAC_MARGIN_LOW Register Table 24. DAC_MARGIN_LOW Register Field Descriptions W 000h Margin low code for DAC output.

8.6.8 PMBUS_OPERATION Register (address = 01h) (reset = 0000h)

Figure 61. PMBUS_OPERATION Register Table 25. PMBUS_OPERATION Register Field Descriptions

8.6.9 PMBUS_STATUS_BYTE Register (address = 78h) (reset = 0000h)

Figure 62. PMBUS_STATUS_BYTE Register Table 26. PMBUS_STATUS_BYTE Register Field Descriptions

9 CML R/W 0 0: No communication Fault

reset this bit by writing 1.

8.6.10 PMBUS_VERSION Register (address = 98h) (reset = 2200h)

Figure 63. PMBUS_VERSION Register Table 27. PMBUS_VERSION Register Field Descriptions

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

smoke detectors, standalone PWM control loops, and offset and gain trimming in precision circuits).

9.2 Typical Applications

power-supply margining. and medical alarm generation.

9.2.1 Programmable LED Biasing

cycle. Figure 64 shows the circuit diagram for LED biasing. Figure 64. LED Biasing

9.2.1.1 Design Requirements

• DAC output range: 0 V to 2.4 V
• LED current range: 0 mA to 20 mA

9.2.1.2 Detailed Design Procedure

current, as compared to a BJT.

9.2.1.3 Application Curves

Figure 65. Triangular Waveform Figure 66. Sawtooth Waveform

9.2.2 Power-Supply Margining

test and measurement, and general-purpose power-supply modules. Figure 67. Power-Supply Margining

9.2.2.1 Design Requirements

• Power supply nominal output: 3.3 V
• Reference voltage of the converter (VFB): 0.6 V
• Margin: ±10% (that is, 2.97 V to 3.63 V)
• DAC output range: 1.8 V
• Nominal current through R1 and R2: 100 µA

9.2.2.2 Detailed Design Procedure

current through R3 even at power-up. Calculate R1 as (VOUT – VFB) / 100 µA = 27 kΩ. R1. Calculate the current from the DAC (IMARGIN) using Equation 7 as 12 µA.

• IMARGIN is the margin current sourced or sinked from the DAC.
• MARGIN is the percentage margin value divided by 100.
• INOMINAL is the nominal current through R1 and R2. (7) In order to calculate the value of R3, first decide the DAC output range, and make sure to avoid the codes near zero-scale and full-scale for safe operation in the linear region. A DAC output of 20 mV is a safe consideration as the minimum output, and (1.8 V – 0.6 V – 20 mV = 1.18 V) as the maximum output. When the DAC output is at 20 mV, the power supply goes to margin high, and when the DAC output is at 1.18 V, the power supply goes to margin low. Calculate the value of R3 usingEquation 8 as 48.3 kΩ. Choose a standard resistor value and adjust the DAC outputs. Choosing R3 = 47 kΩ makes the DAC margin high code as 1.164 V and the DAC margin low code as 36 mV.

the MARGIN HIGH value at the power-supply output.

9.2.2.3 Application Curves

Figure 68. Power-Supply Margin High Figure 69. Power Supply Margin Low

9.2.3 Medical Alarm Generation

There are three types of alarms with different timing requirements: low priority, medium priority, and high priority. manufacturers prefer using their signature melodies within the limits of the standard. Figure 70. Medical Alarm

9.2.3.1 Design Requirements

• Alarm envelope rise and fall time: 26 ms
• Alarm pulse frequency: 610 Hz

9.2.3.2 Detailed Design Procedure

alarm standard. The DACx3401 provide various options to program the pulse frequency and envelope timings.

9.2.3.3 Application Curves

Figure 71. Low Priority Alarm Figure 72. Medium Priority Alarm Figure 73. High-Priority Alarm Figure 74. Pulse Frequency

5 Decoupling

10 Power Supply Recommendations

greater than 1.5-µF for the CAP pin.

11 Layout

11.1 Layout Guidelines

integrity, separate the digital and analog traces, and place decoupling capacitors close to the device pins.

11.2 Layout Example

Figure 75 shows an example layout drawing with decoupling capacitors and pullup resistors. Figure 75. Layout Example

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

12.2 Related Links

tools and software, and quick access to order now. Table 28. Related Links

12.3 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

12.4 Support Resources

from the experts. Search existing answers or ask your own question to get the quick design help you need. not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

E2E is a trademark of Texas Instruments. PMBus is a trademark of SMIF, Inc. All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 14-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DAC43401DSGR Active Production WSON (DSG) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 4341 DAC43401DSGR.A Active Production WSON (DSG) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 4341 DAC43401DSGRG4 Active Production WSON (DSG) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 4341 DAC43401DSGRG4.A Active Production WSON (DSG) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 4341 DAC43401DSGT Active Production WSON (DSG) | 8 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 4341 DAC43401DSGT.A Active Production WSON (DSG) | 8 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 4341 DAC53401DSGR Active Production WSON (DSG) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 5341 DAC53401DSGR.A Active Production WSON (DSG) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 5341 DAC53401DSGRG4 Active Production WSON (DSG) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 5341 DAC53401DSGRG4.A Active Production WSON (DSG) | 8 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 5341 DAC53401DSGT Active Production WSON (DSG) | 8 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 5341 DAC53401DSGT.A Active Production WSON (DSG) | 8 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 5341 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 14-Oct-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF DAC43401, DAC53401 :

• Automotive : DAC43401-Q1 , DAC53401-Q1 NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC43401DSGR WSON DSG 8 3000 210.0 185.0 35.0 DAC43401DSGRG4 WSON DSG 8 3000 210.0 185.0 35.0 DAC43401DSGT WSON DSG 8 250 210.0 185.0 35.0 DAC53401DSGR WSON DSG 8 3000 210.0 185.0 35.0 DAC53401DSGRG4 WSON DSG 8 3000 210.0 185.0 35.0 DAC53401DSGT WSON DSG 8 250 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WSON - 0.8 mm max heightDSG 8 PLASTIC SMALL OUTLINE - NO LEAD2 x 2, 0.5 mm pitch 4224783/A

www.ti.com PACKAGE OUTLINE C 8X 0.32 0.18 1.6 0.1 1.5 0.9 0.1 6X 0.5 8X 0.4 0.2 0.05 0.00 0.8 0.7 A 2.1 1.9 B 2.1 1.9 0.32 0.18 0.4 0.2 (DIM A) TYP WSON - 0.8 mm max heightDSG0008A PLASTIC SMALL OUTLINE - NO LEAD 4218900/E 08/2022 SIDE WALL METAL THICKNESS DIM A OPTION 1 OPTION 2 0.1 0.2 PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5 X 0.25)(45 PIN 1 ID

0.1 C A B

0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 5.500 ALTERNATIVE TERMINAL SHAPE TYPICAL

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

8X (0.25) (1.6) (1.9) 6X (0.5) (0.9) ( 0.2) VIA TYP (0.55) 8X (0.5) (R0.05) TYP WSON - 0.8 mm max heightDSG0008A PLASTIC SMALL OUTLINE - NO LEAD 4218900/E 08/2022 SYMM 4 5 LAND PATTERN EXAMPLE SCALE:20X SYMM 9 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN (R0.05) TYP 8X (0.25) 8X (0.5) (0.9) (0.7) (1.9) (0.45) 6X (0.5) WSON - 0.8 mm max heightDSG0008A PLASTIC SMALL OUTLINE - NO LEAD 4218900/E 08/2022 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9: 87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:25X SYMM METAL SYMM

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