DAC34H84IZAYR

Texas Instruments

Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Quad-Channel,16-Bit,1.25GSPSDigital-to-AnalogConverter(DAC) Check forSamples: DAC34H84 1FEATURES DESCRIPTION The DAC34H84 isa very low power, high dynamic• Very Low Power: 1.4W at1.25GSPS range, quad-channel, 16-bit digital-to-analog• Multi-DACSynchronization converter(DAC) witha sample rateas highas 1.25

Selectable2x,4x,8x,16x InterpolationFilter GSPS. – Stop-Band Attenuation> 90 dBc The deviceincludesfeaturesthatsimplifythedesign
FlexibleOn-chip Complex Mixing of complex transmitarchitectures:2x to 16x digital interpolationfilterswith over 90 dB of stop-band– Two IndependentFineMixerswith32-bit attenuation simplify the data interface andNCOs reconstructionfilters.Independent complex mixers– Power Saving Coarse Mixers:± n×Fs/8 allowflexiblecarrierplacement.A high-performance
High Performance,Low JitterClock low jitterclockmultipliersimplifiesclockingof the device withoutsignificantimpact on the dynamicMultiplyingPLL range.The digitalQuadratureModulatorCorrection• DigitalIand Q Correction (QMC) enablescompleteIQ compensationforgain,– Gain,Phase, Offset,and Group Delay offset,phase and group delaybetween channelsin Correction directup-conversionapplications.
DigitalInverseSinc Filters Digitaldata is inputto the devicethrougha 32-bit
32-BitDDR FlexibleLVDS InputData Bus wide LVDS data bus withon-chiptermination.The wide bus allows the processing of very high– 8 Sample InputFIFO bandwidthsignals.The deviceincludesa FIFO, data– Supports Data Rates up to625 MSPS patternchecker and paritytestto ease the input – Data PatternChecker interface. The interface also allows full synchronizationofmultipledevices.– ParityCheck
Temperature Sensor The deviceis characterizedforoperationover the entireindustrialtemperaturerange of–40°C to85°C• DifferentialScalableOutput:10mA to30mA and isavailableina 196-ball,12x12mm, 0.8mm pitch• 196-Ball,12x12mm BGA (GREEN /Pb-Free) BGA package. The DAC34H84 very low power, high bandwidthAPPLICATIONS support,superiorcrosstalk,highdynamic range and• CellularBase Stations features are an ideal fitfor next generation
DiversityTransmit communicationsystems.
Wideband Communications spacing spacing spacing spacing spacing These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2011,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

PARITYCDP CD-Data Bus AB-Data Bus ISTR/PARITYABN PARITYCDN OSTRP OSTRN SDO SDIO SDENB SCLK TXENB RESETB AVDD GND LVDS LVPECL LVDS LVDS LVDS

8 Sample FIFO

(FMIX or CMIX) AB-QMC Gain and Phase 16-b DACB 16-b DACA IOUTA1 IOUTA2 IOUTB1 IOUTB2 QMC B-offset QMC A-offset x2 x2 x2 x2 x2 x2 x2 x2 FIR1FIR0 x sin(x) x sin(x) DAC Gain FIR3FIR2 AB-Channel FIR4 2x–16x Interpolation AB 32-Bit NCO cos sin CMIX Control (±n*Fs/8) 59 taps 23 taps 11 taps 11 taps 9 taps A-Group Delay B-Group Delay Clock Distribution EXTIO BIASJ DACCLKP DACCLKN DATACLKP DATACLKN CLKVDD DIGVDD VFUSE DACVDD LVPECL 100 LVDS Programmable Delay Low Jitter PLL LPF PLLAVDD 1.2-V Reference CD 32-Bit NCO cos sin Complex Mixer (FMIX or CMIX) CD-QMC Gain and Phase 16-b DACD 16-b DACC IOUTC1 IOUTC2 IOUTD1 IOUTD2 QMC D-offset QMC C-offset x2 x2 x2 x2 x2 x2 x2 x2 FIR1FIR0 x sin(x) x sin(x) FIR3FIR2 CD-Channel FIR4 59 taps 23 taps 11 taps 11 taps 9 taps C-Group Delay D-Group Delay DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM

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N GND SYNC N DAB 15N DAB 14N DAB 13N DAB 12N DAB 11N DAB 10N DAB OSTR P SYNC P GND DAC CLKP DAC CLKN GND DAB 15P DAB 14P DAB 13P DAB 12P DAB 11P DAB 10P DAB GND IOUT AP IOUT AN GND IOUT BN IOUT BP GND GND IOUT CP IOUT CN GND IOUT DN IOUT DP GND GND GND GND GND GND GND GND GND GND GND GND GND PLL AVDD LPF GND GND EXTIO BIASJ GND IO VDD2 GND ALARM SDO AVDD AVDD AVDD AVDD AVDD AVDD TEST MODE RESET B SDENBAVDD DAC VDD DAC VDD DAC VDD DAC VDD DAC VDD DAC VDD AVDD GND TXENA SCLKDAC VDD DAC VDDGND GND GND DAC VDD DAC VDD GND PLL AVDD CLK VDD GND GND GND GND SLEEP SDIO GND GND GND GND GND GND GND GND GND VFUSE DIG VDDGND GND GND DIG VDD VFUSE GNDGND GND GND PARITY CDP PARITY CDN DCD DCD GND IO VDD DIG VDD GND GNDGND GND DIG VDD IO VDD GND DCD DCD GND IO VDD DIG VDD DIG VDD IO VDD IO VDD DIG VDD DIG VDD IO VDD GND DCD DCD DAB DAB DAB DAB DAB DAB DAB DAB DAB DAB DAB DAB DAB DAB DAB DAB DAB DAB DCD 15P DCD 15N DCD 14P DCD 12P DCD 14N DCD 12N DCD 13P DCD 11P DCD 13N DCD 11N DCD 10P DCD DCD 10N DCD DCD DCD DCD DCD DCD DCD DCD DCD DCD DCD DCD DCD DATA CLKP DATA CLKN ISTR/ PARITY ABP ISTR/ PARITY ABN A B C D E F G H J K L M N P (Top View) DAC Output Clock Input Sync/Parity Input Data Input CMOS Pins Miscellaneous 3.3V Supply Ground P0134-01 CLK VDD 1.2V Supply (except for IOVDD2) DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 PINOUT Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. D10, E11, F11,G11,AVDD I Analogsupplyvoltage.(3.3V)H11, J11, K11,L10 CMOS outputforALARM condition.The ALARM outputfunctionalityisdefinedthroughtheconfig7 ALARM N12 O register.Defaultpolarityisactivehigh,butcan be changed toactivelowviaconfig0alarm_out_pol controlbit. Full-scaleoutputcurrentbias.For30mA full-scaleoutputcurrent,connect1.28kΩ toground.ChangeBIASJ H12 O thefull-scaleoutputcurrentthroughcoarse_dac(3:0)inconfig3,bit<15:12> Internalclockbuffersupplyvoltage.(1.2V).Itisrecommended toisolatethissupplyfromDIGVDDCLKVDD C12, K12 I and DACVDD. LVDS positiveinputdatabits0 through15 fortheAB-channelpath.Internal100 Ω terminationA7,A6,A5, resistor.Data formatrelativetoDATACLKP/N clockisDoubleData Rate (DDR).A4,A3,A2, A1,C4, C2, DAB15P ismost significantdatabit(MSB)DAB[15..0]P ID4, D2, E4, DAB0P isleastsignificantdatabit(LSB)E2,F4,F2, G4 The orderofthebus can be reversedviaconfig2revbusbit. B7,B6,B5, B4,B3,B2, B1,C3, C1, LVDS negativeinputdatabits0 through15 fortheAB-channelpath.(See DAB[15:0]PdescriptionDAB[15..0]N ID3, D1, E3, above) E1,F3,F1, H4, J4,J2, LVDS positiveinputdatabits0 through15 fortheCD-channelpath.Internal100 Ω termination K4,K2,L4, resistor.Data formatrelativetoDATACLKP/N clockisDoubleData Rate (DDR). L2,M4, M2, DCD15P ismost significantdatabit(MSB)DCD[15..0]P IN1, N2, N3, DCD0P isleastsignificantdatabit(LSB)N4, N5, N6, The orderofthebus can be reversedviaconfig2revbusbit.N7 H3, J3,J1, K3,K1,L3, L1,M3, M1, LVDS negativeinputdatabits0 through15 fortheCD-channelpath.(See DCD[15:0]PdescriptionDCD[15..0]N IP1,P2,P3, above) P4,P5,P6, DACCLKP A12 I PositiveexternalLVPECL clockinputforDAC corewitha self-bias. DACCLKN A11 I ComplementaryexternalLVPECL clockinputforDAC core.(seetheDACCLKP description) D9, E9,E10, F10,G10, DAC coresupplyvoltage.(1.2V).Itisrecommended toisolatethissupplyfromCLKVDD andDACVDD IH10, J10, DIGVDD. K10,K9,L9 LVDS positiveinputdataclock.Internal100 Ω terminationresistor.InputdataDAB[15:0]P/NandDATACLKP G2 I DCD[15:0]P/Narelatchedon bothedges ofDATACLKP/N (DoubleData Rate). DATACLKN G1 I LVDS negativeinputdataclock.(See DATACLKP description) E5,E6,E7, DIGVDD F5,J5,K5, I Digitalsupplyvoltage.(1.2V).Itisrecommended toisolatethissupplyfromCLKVDD and DACVDD. K6,K7 Used as externalreferenceinputwhen internalreferenceisdisabledthroughconfig27extref_ena= EXTIO G12 I/O ‘1’.Used as internalreferenceoutputwhen config27extref_ena= ‘0’ (default).Requiresa 0.1μF decouplingcapacitortoAGND when used as referenceoutput. LVDS inputstrobepositiveinput.Internal100 Ω terminationresistor. The main functionsofthisinputaretosynctheFIFO pointer,toprovidea syncsourcetothedigital blocks,and/ortoactas a parityinputfortheAB-databus.ISTRP/ H2 I These functionsarecapturedwiththerisingedge ofDATACLKP/N. ThissignalshouldbePARITYABP edge-alignedwithDAB[15:0]P/Nand DCD[15:0]P/N. The PARITY, SYNC, and ISTR inputsarerotatedtoallowcompletereversalofthedatainterface when settingtherev_interfacebitinregisterconfig1. ISTRN/ H1 I LVDS inputstropenegativeinput.(See theISTRP/PARITYABP description)PARITYABN

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 PIN FUNCTIONS (continued) PIN I/O DESCRIPTION NAME NO. A10,A13, A14,B10, B11,B12, B13,C5, C6, C7, C8, C9, C10, C13, D8, D13, D14, E8, E12,E13, F6,F7,F8, F9,F12,F13, G6, G7, G8, GND G9, G13, I These pinsaregroundforallsupplies. G14, H6, H7, H8, H9, H13, H14, J6,J7, J8,J9,J12, J13,K8,K13, L8,L13,L14, M5, M6, M7, M8, M9, M10, M11, M12, M13, N13, P13, P14 IOUTAP B14 O A-ChannelDAC currentoutput.Connectdirectlytogroundifunused. IOUTAN C14 O A-ChannelDAC complementarycurrentoutput.Connectdirectlytogroundifunused. IOUTBP F14 O B-ChannelDAC currentoutput.Connectdirectlytogroundifunused. IOUTBN E14 O B-ChannelDAC complementarycurrentoutput.Connectdirectlytogroundifunused. IOUTCP J14 O C-ChannelDAC currentoutput.Connectdirectlytogroundifunused. IOUTCN K14 O C-ChannelDAC complementarycurrentoutput.Connectdirectlytogroundifunused. IOUTDP N14 O D-ChannelDAC currentoutput.Connectdirectlytogroundifunused. IOUTDN M14 O D-ChannelDAC complementarycurrentoutput.Connectdirectlytogroundifunused. D5, D6, G5,IOVDD I SupplyvoltageforallLVDS I/O.(3.3V)H5, L5.L6 LPF D12 I/O PLL loopfilterconnection.IfnotusingtheclockmultiplyingPLL,theLPF pincan be leftunconnected. OptionalLVPECL outputstrobepositiveinput.Thispositive/negativepairiscapturedwiththerising OSTRP A9 I edge ofDACCLKP/N. Itisused tosyncthedivided-downclocksand FIFO outputpointerinDualSync SourcesMode. Ifunused itcan be leftunconnected. OSTRN B9 I OptionalLVPECL outputstrobenegativeinput.(See theOSTRP description) OptionalLVDS positiveinputparitybitfortheCD-databus.The PARITYCDP/N LVDS pairhas an internal100 Ω terminationresistor.Ifunused itcan be leftunconnected.PARITYCDP N8 I The PARITY, SYNC, and ISTR inputsarerotatedtoallowcompletereversalofthedatainterface when settingtherev_interfacebitinregisterconfig1. PARITYCDN P8 I OptionalLVDS negativeinputparitybitfortheCD-databus. PLLAVDD C11, D11 I PLL analogsupplyvoltage.(3.3V) SCLK P9 I Serialinterfaceclock.Internalpull-down. SDENB P10 I Activelowserialdataenable,alwaysan inputtotheDAC34H84. Internalpull-up. Serialinterfacedata.Bi-directionalin3-pinmode (default)and uni-directional4-pinmode. InternalSDIO P11 1/O pull-down. Uni-directionalserialinterfacedatain4-pinmode. The SDO pinistri-statedin3-pininterfacemodeSDO P12 O (default). SLEEP N11 I Activehighasynchronoushardwarepower-down input.Internalpull-down. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com PIN FUNCTIONS (continued) PIN I/O DESCRIPTION NAME NO. LVDS SYNC positiveinput.Internal100 Ω terminationresistor.Ifunused itcan be leftunconnected. SYNCP A8 I The PARITY, SYNC, and ISTR inputsarerotatedtoallowcompletereversalofthedatainterface when settingtherev_interfacebitinregisterconfig1. SYNCN B8 I LVDS SYNC negativeinput. RESETB N10 I ActivelowinputforchipRESET. Internalpull-up. Transmitenableactivehighinput.Internalpull-down. To enableanalogoutputdatatransmission,setsif_txenableinregisterconfig3to“1” or pullCMOS TXENA N9 I TXENA pintohigh. To disableanalogoutput,setsif_txenableto“0” and pullCMOS TXENA pintolow.The DAC output isforcedtomidscale. TESTMODE L11 I Thispinisused forfactorytesting.Internalpull-down.Leave unconnected fornormal operation. Digitalsupplyvoltage.Thissupplypinisalsoused forfactoryfuseprogramming.Connect toVFUSE D7, L7 I DACVDD or DIGVDD fornormal operation. ORDERING INFORMATION (1) TA ORDER CODE PACKAGE DRAWING/TYPE (2) TRANSPORT MEDIA QUANTITY DAC34H84IZAY Tray 160 –40°C to85°C ZAY /196 NFBGA DAC34H84IZAYR Tape and Reel 1000 (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orvisitthe deviceproductfolderatwww.ti.com. (2) MSL Peak Temperature:Level-3-260C-168HR ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) VALUE UNIT MIN MAX DACVDD, DIGVDD, CLKVDD –0.5 1.5 V VFUSE –0.5 1.5 VSupplyvoltage range(2) IOVDD, IOVDD2 –0.5 4 V AVDD, PLLAVDD –0.5 4 V DACCLKP/N, OSTRP/N –0.5 CLKVDD + 0.5 V ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TESTMODE, –0.5 IOVDD2 + 0.5 VPinvoltagerange(2) TXENA IOUTAP/N, IOUTBP/N, IOUTCP/N, IOUTDP/N –1.0 AVDD + 0.5 V EXTIO, BIASJ –0.5 AVDD + 0.5 V LPF –0.5 PLLAVDD + 0.5 V Peak inputcurrent(anyinput) 20 mA Peak totalinputcurrent(allinputs) –30 mA Operatingfree-airtemperaturerange,TA:DAC34H84 –40 85 °C Storagetemperaturerange –65 150 °C (1) Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings onlyand functionaloperationoftheseorany otherconditionsbeyond thoseindicatedunder“recommended operatingconditions” isnot implied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Measured withrespecttoGND.

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 THERMAL INFORMATION DAC34H84 THERMAL METRIC (1) BGA UNITS (196ball)PINS TJ Maximum junctiontemperature 125 °C θJA Junction-to-ambientthermalresistance(2) 37.6 θJCtop Junction-to-case(top)thermalresistance(3) 6.8 θJCbot Junction-to-case(bottom)thermalresistance(4) N/A °C/W θJB Junction-to-boardthermalresistance(5) 16.8 ψJT Junction-to-topcharacterizationparameter(6) 0.2 ψJB Junction-to-boardcharacterizationparameter(7) 16.4 (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953 . (2) The junction-to-ambientthermalresistanceundernaturalconvectionisobtainedina simulationon a JEDEC-standard,high-Kboard,as specifiedinJESD51-7,inan environmentdescribedinJESD51-2a. (3) The junction-to-case(top)thermalresistanceisobtainedby simulatinga coldplateteston thepackage top.No specific JEDEC-standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. (4) The junction-to-case(bottom)thermalresistanceisobtainedby simulatinga coldplateteston theexposed (power)pad.No specific JEDEC standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. (5) The junction-to-boardthermalresistanceisobtainedby simulatinginan environmentwitha ringcoldplatefixturetocontrolthePCB temperature,as describedinJESD51-8. (6) The junction-to-topcharacterizationparameter,ψJT,estimatesthejunctiontemperatureofa deviceina realsystemand isextracted fromthesimulationdataforobtainingθJA,usinga proceduredescribedinJESD51-2a (sections6 and 7). (7) The junction-to-boardcharacterizationparameter,ψJB,estimatesthejunctiontemperatureofa deviceina realsystemand isextracted fromthesimulationdataforobtainingθJA ,usinga proceduredescribedinJESD51-2a (sections6 and 7). Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS (1) overrecommended operatingfree-airtemperaturerange,nominalsupplies,IOUT FS = 20mA (unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 16 Bits DC ACCURACY DNL Differentialnonlinearity ±2 LSB

1 LSB = IOUT FS /216

INL Integralnonlinearity ±4 LSB ANALOG OUTPUT Coarse gainlinearity ±0.04 LSB Offseterror Mid code offset ±0.001 %FSR Withexternalreference ±2 %FSR Gain error Withinternalreference ±2 %FSR Gain mismatch Withinternalreference ±2 %FSR Fullscaleoutputcurrent 10 20 30 mA Outputcompliancerange –0.5 0.6 V Outputresistance 300 kΩ Outputcapacitance 5 pF REFERENCE OUTPUT VREF Referenceoutputvoltage 1.2 V Referenceoutputcurrent(2) 100 nA REFERENCE INPUT VEXTIO Inputvoltagerange 0.6 1.2 1.25 V ExternalReferenceMode Inputresistance 1 M Ω Smallsignalbandwidth 472 kHz Inputcapacitance 100 pF TEMPERATURE COEFFICIENTS Offsetdrift ±1 ppm/°C withexternalreference ±15 ppm/°C Gain drift withinternalreference ±30 ppm/°C Referencevoltagedrift ±8 ppm/°C POWER SUPPLY (3) AVDD, IOVDD, PLLAVDD 3.14 3.3 3.46 V CLKVDD, DACVDD, DIGVDD 1.14 1.2 1.26 V IOVDD2 1.71 3.3 3.45 V PSRR Power supplyrejectionratio DC tested ±0.25 %FSR/V POWER CONSUMPTION I(AVDD) Analogsupplycurrent(4) 135 165 mA MODE 1 (5)I(DIGVDD) Digitalsupplycurrent 740 820 mA fDAC = 1.25GSPS, 2x interpolation,Mixeron,I(DACVDD) DAC supplycurrent 40 60 mAQMC on,invsincon,PLL enabled,20mA FS I(CLKVDD) Clocksupplycurrent 100 120 mAoutput,IF= 200MHz P Power dissipation 1500 1750 mW (1) Measured differentiallyacrossIOUTP/N with25 Ω each toGND. (2) Use an externalbufferamplifierwithhighimpedance inputtodriveany externalload. (3) To ensurepower supplyaccuracyand toaccountforpower supplyfilternetworklossatoperatingconditions,theuse oftheATEST functioninregisterconfig27tochecktheinternalpower supplynodes isrecommended. (4) IncludesAVDD, PLLAVDD, and IOVDD (5) PLL operationof1.25GSPS inMode 1 isused formaximum power consumptionmeasurement only.Pleasefollowthemaximum DAC sample rate(FDAC )guidelineintheAC CharacteristicTableforproperDAC operation.

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS (1)(continued) overrecommended operatingfree-airtemperaturerange,nominalsupplies,IOUT FS = 20mA (unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(AVDD) Analogsupplycurrent(4) 125 mA MODE 2I(DIGVDD) Digitalsupplycurrent 740 mA fDAC = 1.25GSPS, 2x interpolation,Mixeron,I(DACVDD) DAC supplycurrent 45 mAQMC on,invsincon,PLL disabled,20mA FS I(CLKVDD) Clocksupplycurrent 75 mAoutput,IF= 200MHz P Power dissipation 1440 mW I(AVDD) Analogsupplycurrent(4) 120 mA MODE 3I(DIGVDD) Digitalsupplycurrent 370 mA fDAC = 625MSPS, 2x interpolation,Mixeron,I(DACVDD) DAC supplycurrent 25 mAQMC on,invsincoff,PLL disabled,20mA FS I(CLKVDD) Clocksupplycurrent 45 mAoutput,IF= 200MHz P Power dissipation 925 mW I(AVDD) Analogsupplycurrent(4) 50 mA MODE 4I(DIGVDD) Digitalsupplycurrent 750 mA fDAC = 1.25GSPS, 2x interpolation,Mixeron,I(DACVDD) DAC supplycurrent 40 mAQMC on,invsincon,PLL enabled,Channels I(CLKVDD) Clocksupplycurrent 100 mAA/B/C/Doutputsleep,IF= 200MHz, P Power dissipation 1240 mW I(AVDD) Analogsupplycurrent(4) 40 mA Mode 5I(DIGVDD) Digitalsupplycurrent 10 mAPower-Down mode: No clock,DAC on sleep I(DACVDD) DAC supplycurrent mode (clockreceiversleep), 5 mA ChannelsA/B/C/Doutputsleep,staticdataI(CLKVDD) Clocksupplycurrent 15 mApattern P Power dissipation 150 mW I(AVDD) Analogsupplycurrent(4) 140 mA Mode 6I(DIGVDD) Digitalsupplycurrent 360 mA fDAC = 1GSPS, 2x interpolation,Mixeroff,I(DACVDD) DAC supplycurrent 30 mAQMC off,invsincoff,PLL enabled,20mA FS I(CLKVDD) Clocksupplycurrent 90 mAoutput,IF= 200MHz P Power dissipation 1040 mW I(AVDD) Analogsupplycurrent(4) 120 mA Mode 7I(DIGVDD) Digitalsupplycurrent 370 mA fDAC = 1GSPS, 2x interpolation,Mixeroff,I(DACVDD) DAC supplycurrent 30 mAQMC off,invsincoff,PLL disabled,20mA FS I(CLKVDD) Clocksupplycurrent 65 mAoutput,IF= 200MHz P Power dissipation 960 mW OperatingRange –40 25 85 °C Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVDS INPUTS: DAB[15:0]P/N,DCD[15:0]P/N,DATACLKP/N, ISTRP/N,SYNCP/N, PARITYCDP/N (1) Logichighdifferential VA,B+ inputvoltage 200 mV threshold Logiclowdifferential VA,B– inputvoltage –200 mV threshold VCOM InputCommon Mode 1.0 1.2 1.6 V ZT Internaltermination 85 110 135 Ω LVDS InputC L 2 pFcapacitance InterleavedLVDSfINTERL 1250 MSPSdatatransferrate fDATA Inputdatarate 625 MSPS CLOCK INPUT (DACCLKP/N) Dutycycle 40% 60% Differentialvoltage(2) 0.4 1.0 V DACCLKP/N Input 1250 MHzFrequency OUTPUT STROBE (OSTRP/N) fOSTR = fDACCLK /(nx 8 x Interp)where n isany positive fDACCLK / fOSTR Frequency integer, (8x MHz fDACCLK isDACCLK frequencyinMHz interp) Dutycycle 50% Differentialvoltage 0.4 1.0 V CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENA High-levelinput 0.7xVIH Vvoltage IOVDD2 Low-levelinput 0.3xVIL Vvoltage IOVDD2 High-levelinputIIH -40 40 µAcurrent Low-levelinputIIL -40 40 µAcurrent CMOS InputC I 2 pFcapacitance IOVDD2 –Iload= –100 μA V0.2 VOH ALARM, SDO, SDIO 0.8xIload= –2 mA VIOVDD2 Iload= 100 μA 0.2 V VOL ALARM, SDO, SDIO Iload= 2 mA 0.5 V (1) See LVDS INPUTS sectionforterminology. (2) Drivingtheclockinputwitha differentialvoltagelowerthan1 V may resultindegradedperformance.

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT TIMING SPECIFICATIONS Timing LVDS inputs:DAB[15:0]P/N,DCD[15:0]P/N,ISTRP/N,SYNCP/N, PARITYCDP/N, double edge latching Config36Setting datadly clkdly 0 0 150 0 1 100 0 2 50 0 3 0 Setuptime, 0 4 –50 DAB[15:0]P/N, 0 5 –100DCD[15:0]P/N, ISTRP/N and SYNCP/N resetlatchedts(DATA) ISTRP/N,SYNCP/N, 0 6 –150 psonlyon risingedge ofDATACLKP/Nand PARITYCDP/N, 0 7 –200validtoeitheredge of 1 0 200DATACLKP/N 2 0 250 3 0 300 4 0 350 5 0 400 6 0 450 7 0 500 Config36Setting datadly clkdly 0 0 400 0 1 450 0 2 500 0 3 550 Holdtime, 0 4 600 DAB[15:0]P/N, 0 5 650DCD[15:0]P/N, ISTRP/N and SYNCP/N resetlatchedth(DATA) ISTRP/N,SYNCP/N 0 6 700 psonlyon risingedge ofDATACLKP/Nand PARITYCDP/N 0 7 750validaftereitheredge 1 0 350ofDATACLKP/N 2 0 300 3 0 250 4 0 200 5 0 150 6 0 100 7 0 50 ISTRP/N andt(ISTR_SYNC) fDATACLK isDATACLK frequencyinMHz 1/2fDATACLK nsSYNCP/N pulsewidth Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TIMING OUTPUT STROBE INPUT: DACCLKP/N risingedge LATCHING (3) Setuptime,OSTRP/N ts(OSTR) validtorisingedge of –100 ps DACCLKP/N Holdtime,OSTRP/N th(OSTR) validafterrisingedge 500 ps ofDACCLKP/N TIMING SYNC INPUT: DACCLKP/N risingedge LATCHING (4) Setuptime,SYNCP/N ts(SYNC_PLL) validtorisingedge of 200 ps DACCLKP/N Holdtime,SYNCP/N th(SYNC_PLL) validafterrisingedge 300 ps ofDACCLKP/N TIMING SERIAL PORT Setuptime,SDENB tots(SDENB) 20 nsrisingedge ofSCLK Setuptime,SDIO ts(SDIO) validtorisingedge of 10 ns SCLK Holdtime,SDIO valid th(SDIO) torisingedge of 5 ns SCLK Registerconfig6read(temperaturesensorread) 1 µs t(SCLK) PeriodofSCLK Allotherregisters 100 ns Data outputdelay td(Data) afterfallingedge of 10 ns SCLK Minimum RESETBtRESET 25 nspulsewidth (3) OSTR isrequiredinDualSync Sourcesmode. Inordertominimizetheskew itisrecommended touse thesame clockdistribution devicesuch as Texas InstrumentsCDCE62005 toprovidetheDACCLK and OSTR signalstoalltheDAC34H84 devicesinthesystem. Swap thepolarityoftheDACCLK outputswithrespecttotheOSTR ones toestablishproperphase relationship. (4) SYNC isrequiredtosynchronizethePLL circuitinmulitpledevices.The SYNC signalmust meet thetimingrelationshipwithrespectto thereferenceclock(DACCLKP/N) oftheon-chipPLL circuit.

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 ELECTRICAL CHARACTERISTICS – AC SPECIFICATIONS overrecommended operatingfree-airtemperaturerange,nominalsupplies,IOUT FS = 20mA (unlessotherwisenoted) PARAMETER TEST CONDITIONS /COMMENTS MIN TYP MAX UNIT ANALOG OUTPUT (1) PLL OFF 1250 fDAC Maximum DAC rate MSPS PLL ON 1000 ts(DAC) Outputsettlingtimeto0.1% Transition:Code 0x0000 to0xFFFF 10 ns DAC outputsareupdatedon thefallingedge ofDACtpd Outputpropagationdelay 2 nsclock.Does notincludeDigitalLatency(seebelow). tr(IOUT) Outputrisetime10% to90% 220 ps tf(IOUT) Outputfalltime90% to10% 220 ps No interpolation,FIFO on,Mixeroff,QMC off,Inverse 128sincoff 2x Interpolation 216 4x Interpolation 376 DAC clock8x Interpolation 726DigitalLatency cycles 16x Interpolation 1427 FineMixer 24 QMC 16 InverseSinc 20 DAC Wake-up Time IOUT currentsettlingto1% ofIOUT FS fromoutputsleep 2Power-up μsIOUT currentsettlingtolessthan1% ofIOUT FS inoutputTime DAC SleepTime 2sleep AC PERFORMANCE (2) fDAC = 1.25GSPS, fOUT = 20 MHz 73 SpuriousfreedynamicrangeSFDR fDAC = 1.25GSPS, fOUT = 50 MHz 70 dBc(0tofDAC /2)Tone at0 dBFS fDAC = 1.25GSPS, fOUT = 70 MHz 66 fDAC = 1.25MSPS, fOUT = 30 ± 0.5MHz 87Third-ordertwo-toneintermodulation distortionIMD3 fDAC = 1.25GSPS, fOUT = 50 ± 0.5MHz 85 dBc Each toneat–12 dBFS fDAC = 1.25GSPS, fOUT = 100 ± 0.5MHz 78 fDAC = 1.25GSPS, fOUT = 10 MHz 160NoiseSpectralDensity(3) NSD dBc/HzTone at0dBFS fDAC = 1.25GSPS, fOUT = 80 MHz 155 fDAC = 1.2288GSPS, fOUT = 30.72MHz 77Adjacentchannelleakageratio,single carrier fDAC = 1.2288GSPS, fOUT = 153.6MHz 74 ACLR (3) dBc fDAC = 1.2288GSPS, fOUT = 30.72MHz 82Alternatechannelleakageratio,single carrier fDAC = 1.2288GSPS, fOUT = 153.6MHz 80 ChannelIsolation fDAC = 1.25GSPS, fOUT = 10 MHz 95 dBc (1) Measured singleended into50 Ω load. (2) 4:1transformeroutputtermination,50 Ω doublyterminatedload (3) Singlecarrier,W-CDMA with3.84MHz BW, 5-MHz spacing,centeredatIF,PAR = 12dB.TESTMODEL 1,10 ms Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):DAC34H84

Integral Nonlinearity Error (LSB) 0 10k 20k 30k 40k 50k 60k Code Differential Nonlinearity Error (LSB) 100 0 100 200 300 400 500 600 Output Frequency (MHz) SFDR (dBc) 0 dBFS −6 dBFS −12 dBFS 100 0 100 200 300 400 500 600 Output Frequency (MHz) Second Harmonic Distortion (dBc) 0 dBFS −6 dBFS −12 dBFS 100 0 100 200 300 400 500 600 Output Frequency (MHz) Third Harmonic Distortion (dBc) 0 dBFS −6 dBFS −12 dBFS 100 0 100 200 300 400 500 600 Output Frequency (MHz) SFDR (dBc) fDATA = 625 MSPS, 1x Interpolation fDATA = 625 MSPS, 2x Interpolation fDATA = 312.5 MSPS, 4x Interpolation fDATA = 156.25MSPS, 8x Interpolation fDATA = 78.125MSPS, 16x Interpolation DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS Allplotsareat25°C, nominalsupplyvoltage,fDAC = 1250 MSPS, 2x interpolation,NCO enabled,MixerGain disabled,QMC enabledwithgainsetat1446 forbothI/Qchannels,0 dBFS digitalinput,20 mA full-scaleoutputcurrentwith4:1transformer (unlessotherwisenoted) Figure1.IntegralNonlinearity Figure2.DifferentialNonlinearity Figure3.SFDR vs Output Frequency Over InputScale Figure4.Second Harmonic Distortionvs Output Frequency Over InputScale Figure5.ThirdHarmonic Distortionvs Output Frequency Figure6.SFDR vs Output Frequency Over Interpolation Over InputScale

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Output Frequency (MHz) SFDR (dBc) fDAC = 600 MSPS fDAC = 800 MSPS fDAC = 1000 MSPS fDAC = 1250 MSPS 100 0 50 100 150 200 250 300 350 400 Output Frequency (MHz) SFDR (dBc) IOUT FS = 10 mA w/ 4:1 Transformer IOUT FS = 20 mA w/ 4:1 Transformer IOUT FS = 30 mA w/ 2:1 Transformer −90 −80 −70 −60 −50 −40 −30 −20 −10 0 100 200 300 400 500 600 Frequency (MHz) Power (dBm) NCO Bypassed QMC Bypassed fDAC = 1250 MSPS fOUT = 20 MHz −90 −80 −70 −60 −50 −40 −30 −20 −10 0 100 200 300 400 500 600 Frequency (MHz) Power (dBm) NCO Bypassed QMC Bypassed fDAC = 1250 MSPS fOUT = 70 MHz −90 −80 −70 −60 −50 −40 −30 −20 −10 0 100 200 300 400 500 600 Frequency (MHz) Power (dBm) fDAC = 1250 MSPS fOUT = 150 MHz −90 −80 −70 −60 −50 −40 −30 −20 −10 10 110 210 310 410 510 610 Frequency (MHz) Power (dBm) fDAC = 1250 MSPS fOUT = 200 MHz DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltage,fDAC = 1250 MSPS, 2x interpolation,NCO enabled,MixerGain disabled,QMC enabledwithgainsetat1446 forbothI/Qchannels,0 dBFS digitalinput,20 mA full-scaleoutputcurrentwith4:1transformer (unlessotherwisenoted) Figure7.SFDR vs Output Frequency Over fDAC Figure8.SFDR vs Output Frequency Over IOUT FS Figure9.SingleTone SpectralPlot Figure10.SingleTone SpectralPlot Figure11.SingleTone SpectralPlot Figure12.SingleTone SpectralPlot Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):DAC34H84

−90 −80 −70 −60 −50 −40 −30 −20 −10 10 110 210 310 410 510 610 Frequency (MHz) Power (dBm) PLL Enabled w/ PFD of 78.125 MHz fDAC = 1250 MSPS fOUT = 200 MHz 100 0 100 200 300 400 500 600 Output Frequency (MHz) IMD3 (dBc) 0 dBFS −6 dBFS −12 dBFS 100 0 100 200 300 400 500 600 Output Frequency (MHz) SFDR (dBc) fDATA = 625 MSPS, 1x Interpolation fDATA = 625 MSPS, 2x Interpolation fDATA = 312.5 MSPS, 4x Interpolation fDATA = 156.25 MSPS, 8x Interpolation fDATA = 78.125 MSPS, 16x Interpolation 100 0 100 200 300 400 500 600 Output Frequency (MHz) IMD3 (dBc) fDAC = 600 MSPS fDAC = 800 MSPS fDAC = 1000 MSPS fDAC = 1250 MSPS 100 0 50 100 150 200 250 300 350 400 Output Frequency (MHz) IMD3 (dBc) IOUT FS = 10 mA w/ 4:1 Transformer IOUT FS = 20 mA w/ 4:1 Transformer IOUT FS = 30 mA w/ 2:1 Transformer −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 65 66 67 68 69 70 71 72 73 74 75 Frequency (MHz) Power (dBm) NCO Bypassed QMC Bypassed fDAC = 1250 MSPS fOUT = 70 MHz Tone Spacing = 1 MHz DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltage,fDAC = 1250 MSPS, 2x interpolation,NCO enabled,MixerGain disabled,QMC enabledwithgainsetat1446 forbothI/Qchannels,0 dBFS digitalinput,20 mA full-scaleoutputcurrentwith4:1transformer (unlessotherwisenoted) Figure13.SingleTone SpectralPlot Figure14.IMD3 vs Output Frequency Over InputScale Figure15.IMD3 vs Output Frequency Over Interpolation Figure16.IMD3 vs Output Frequency Over fDAC Figure17.IMD3 vs Output Frequency Over IOUT FS Figure18.Two Tone SpectralPlot

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−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 195 196 197 198 199 200 201 202 203 204 205 Frequency (MHz) Power (dBm) fDAC = 1250 MSPS fOUT = 200 MHz Tone Spacing = 1 MHz 130 135 140 145 150 155 160 165 170 0 100 200 300 400 500 600 Output Frequency (MHz) NSD (dBc/Hz) 0 dBFS −6 dBFS −12 dBFS 130 135 140 145 150 155 160 165 170 0 100 200 300 400 500 600 Output Frequency (MHz) NSD (dBc/Hz) fDATA = 625 MSPS, 1x Interpolation fDATA = 625 MSPS, 2x Interpolation fDATA = 312.5 MSPS, 4x Interpolation fDATA = 156.25 MSPS, 8x Interpolation fDATA = 78.125 MSPS, 16x Interpolation 130 135 140 145 150 155 160 165 170 0 100 200 300 400 500 600 Output Frequency (MHz) NSD (dBc/Hz) fDAC = 600 MSPS fDAC = 800 MSPS fDAC = 1000 MSPS fDAC = 1250 MSPS 130 135 140 145 150 155 160 165 170 0 50 100 150 200 250 300 350 400 Output Frequency (MHz) NSD (dBc/Hz) IOUT FS = 10 mA w/ 4:1 Transformer IOUT FS = 20 mA w/ 4:1 Transformer IOUT FS = 30 mA w/ 2:1 Transformer 130 135 140 145 150 155 160 165 170 0 100 200 300 400 500 600 Output Frequency (MHz) NSD (dBc/Hz) PLL Bypassed PLL Enabled w/ PFD of 78.125 MHz DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltage,fDAC = 1250 MSPS, 2x interpolation,NCO enabled,MixerGain disabled,QMC enabledwithgainsetat1446 forbothI/Qchannels,0 dBFS digitalinput,20 mA full-scaleoutputcurrentwith4:1transformer (unlessotherwisenoted) Figure19.Two Tone SpectralPlot Figure20.NSD vs Output Frequency Over InputScale Figure21.NSD vs Output Frequency Over Interpolation Figure22.NSD vs Output Frequency Over fDAC Figure23.NSD vs Output Frequency Over IOUT FS Figure24.NSD vs Output Frequency Over Clocking Options Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):DAC34H84

Output Frequency (MHz) ACLR (dBc) PLL Disabled PLL Enabled 0 100 200 300 400 500 600 Output Frequency (MHz) ACLR (dBc) PLL Disabled PLL Enabled 2x Interpolation, 0 dBFS f = 1228.8 MSPS f = 70 MHz DAC OUT 2x Interpolation, 0 dBFS f = 1228.8 MSPS f = 120 MHz DAC OUT 2x Interpolation, 0 dBFS f = 1228.8 MSPS f = 200 MHz DAC OUT 2x Interpolation, 0 dBFS f = 1228.8 MSPS f = 70 MHz DAC OUT DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltage,fDAC = 1250 MSPS, 2x interpolation,NCO enabled,MixerGain disabled,QMC enabledwithgainsetat1446 forbothI/Qchannels,0 dBFS digitalinput,20 mA full-scaleoutputcurrentwith4:1transformer (unlessotherwisenoted) Figure25.SingleCarrierWCDMA ACLR (Adjacent)vs Figure26.SingleCarrierWCDMA ACLR (Alternate)vs Output Frequency Over ClockingOptions Output Frequency Over ClockingOptions Figure27.SingleCarrierW-CDMA TestModel 1 Figure28.SingleCarrierW-CDMA TestModel 1 Figure29.SingleCarrierW-CDMA TestModel 1 Figure30.Four CarrierW-CDMA TestModel 1

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2x Interpolation, 0 dBFS f = 1228.8 MSPS f = 200 MHz DAC OUT 2x Interpolation, 0 dBFS f = 1228.8 MSPS f = 120 MHz DAC OUT 2x Interpolation, 0 dBFS f = 1228.8 MSPS f = 140 MHz DAC OUT 2x Interpolation, 0 dBFS f = 1228.8 MSPS f = 240 MHz DAC OUT 2x Interpolation, 0 dBFS f = 1228.8 MSPS f = 140 MHz DAC OUT 2x Interpolation, 0 dBFS f = 1228.8 MSPS f = 240 MHz DAC OUT DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltage,fDAC = 1250 MSPS, 2x interpolation,NCO enabled,MixerGain disabled,QMC enabledwithgainsetat1446 forbothI/Qchannels,0 dBFS digitalinput,20 mA full-scaleoutputcurrentwith4:1transformer (unlessotherwisenoted) Figure31.Four CarrierW-CDMA TestModel 1 Figure32.Four CarrierW-CDMA TestModel 1 Figure33. 10 MHz SingleCarrierLTE TestModel 3.1 Figure34.10 MHz SingleCarrierLTE TestModel 3.1 Figure35.20 MHz SingleCarrierLTE TestModel 3.1 Figure36.20 MHz SingleCarrierLTE TestModel 3.1 Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):DAC34H84

0 200 400 600 800 1000 1200 fDAC (MSPS) Power Consumption (mW) 1x Interpolation 2x Interpolation 4x Interpolation 8x Interpolation 16x Interpolation Bandbase Input = 5 MHz NCO Disabled QMC Disabled CMIX Disabled 200 400 600 800 1000 1200 1400 0 200 400 600 800 1000 1200 fDAC (MSPS) Power Consumption (mW) 1x Interpolation 2x Interpolation 4x Interpolation 8x Interpolation 16x Interpolation Bandbase Input = 0 MHz NCO Enabled w/ 5 MHz Mixing QMC Enabled 100 120 140 160 0 200 400 600 800 1000 1200 fDAC (MSPS) Power Consumption (mW) NCO Enabled QMC Enabled 100 200 300 400 500 600 700 0 200 400 600 800 1000 1200 fDAC (MSPS) DIGVDD Current (mA) 1x Interpolation 2x Interpolation 4x Interpolation 8x Interpolation 16x Interpolation Bandbase Input = 5 MHz NCO Disabled QMC Disabled CMIX Disabled 100 200 300 400 500 600 700 0 200 400 600 800 1000 1200 fDAC (MSPS) DIGVDD Current (mA) 1x Interpolation 2x Interpolation 4x Interpolation 8x Interpolation 16x Interpolation Bandbase Input = 0 MHz NCO Enabled w/ 5 MHz Mixing QMC Enabled 100 120 140 160 0 200 400 600 800 1000 1200 fDAC (MSPS) DIGVDD Current (mA) NCO Enabled QMC Enabled DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltage,fDAC = 1250 MSPS, 2x interpolation,NCO enabled,MixerGain disabled,QMC enabledwithgainsetat1446 forbothI/Qchannels,0 dBFS digitalinput,20 mA full-scaleoutputcurrentwith4:1transformer (unlessotherwisenoted) Figure37.Power Consumption vs fDAC Over Interpolation Figure38.Power Consumption vs fDAC Over Interpolation Figure39.Power Consumption vs fDAC Over Digital Figure40.DIGVDD Currentvs fDAC Over Interpolation ProcessingFunctions Figure41.DIGVDD Currentvs fDAC Over Interpolation Figure42.DIGVDD Currentvs fDAC Over Digital ProcessingFunctions

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0 200 400 600 800 1000 1200 fDAC (MSPS) DACVDD Current (mA) 100 0 200 400 600 800 1000 1200 fDAC (MSPS) CLKVDD Current (mA) 100 120 140 0 200 400 600 800 1000 1200 fDAC (MSPS) AVDD Current (mA) 100 110 120 0 100 200 300 400 500 600 Output Frequency (MHz) Interference Level (dBc) Channel A Channel B Channel A/B Off Channel C/D Active 100 110 120 0 100 200 300 400 500 600 Output Frequency (MHz) Interference Level (dBc) Channel C Channel D Channel C/D Off Channel A/B Active 100 110 0 32 64 96 128 160 192 224 256 Step Code Group Delay (ps) Channel A Channel B Channel C Channel D fDAC = 614.4 MSPS fOUT = 138.4 MHz DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltage,fDAC = 1250 MSPS, 2x interpolation,NCO enabled,MixerGain disabled,QMC enabledwithgainsetat1446 forbothI/Qchannels,0 dBFS digitalinput,20 mA full-scaleoutputcurrentwith4:1transformer (unlessotherwisenoted) Figure43.DACVDD Currentvs fDAC Figure44.CLKVDD Currentvs fDAC Figure45.AVDD Currentvs fDAC Figure46.Channel Isolationvs Output Frequency Figure47.Channel Isolationvs Output Frequency Figure48.Group Delay vs Step Code Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com DEFINITION OF SPECIFICATIONS Adjacent CarrierLeakage Ratio(ACLR): Definedfora 3.84Mcps 3GPP W-CDMA inputsignalmeasured ina 3.84MHz bandwidthata 5MHz offsetfromthecarrierwitha 12dB peak-to-averageratio. Analog and DigitalPower Supply RejectionRatio(APSSR, DPSSR): Definedas thepercentageerrorinthe ratioofthedeltaIOUT and deltasupplyvoltagenormalizedwithrespecttotheidealIOUT current. DifferentialNonlinearity(DNL): Definedas the variationin analog outputassociatedwithan ideal1 LSB change inthedigitalinputcode. Gain Drift:Definedas themaximum change ingain,intermsofppm offull-scalerange(FSR) per°C, fromthe valueatambient(25°C) tovaluesoverthefulloperatingtemperaturerange. Gain Error:Definedas the percentageerror(inFSR%) forthe ratiobetween the measured full-scaleoutput currentand theidealfull-scaleoutputcurrent. IntegralNonlinearity(INL):Definedas themaximum deviationoftheactualanalogoutputfromtheidealoutput, determinedby a straightlinedrawn fromzeroscaletofullscale. IntermodulationDistortion(IMD3):The two-toneIMD3 is definedas the ratio(indBc) of the 3rd-order intermodulationdistortionproducttoeitherfundamentaloutputtone. OffsetDrift:Definedas themaximum change inDC offset,intermsofppm offull-scalerange (FSR) per °C, fromthevalueatambient(25°C) tovaluesoverthefulloperatingtemperaturerange. OffsetError:Definedas thepercentageerror(inFSR%) fortheratiobetween themeasured mid-scaleoutput currentand theidealmid-scaleoutputcurrent. Output Compliance Range: Definedas the minimum and maximum allowablevoltageat the outputof the current-outputDAC. Exceeding thislimitmay resultreduced reliabilityof the deviceor adverselyaffecting distortionperformance. Reference VoltageDrift:Definedas themaximum change ofthereferencevoltageinppm perdegreeCelsius fromvalueatambient(25°C) tovaluesoverthefulloperatingtemperaturerange. Spurious Free Dynamic Range (SFDR): Definedas thedifference(indBc) between thepeak amplitudeofthe outputsignaland thepeak spurioussignalwithinthefirstNyquistzone. Noise SpectralDensity (NSD): Definedas the differenceof power (indBc) between the outputtone signal power and thenoisefloorof1Hz bandwidthwithinthefirstNyquistzone. SERIAL INTERFACE The serialportof the DAC34H84 is a flexibleserialinterfacewhich communicates withindustrystandard microprocessorsand microcontrollers.The interfaceprovidesread/writeaccesstoallregistersused todefinethe operatingmodes ofDAC34H84. Itiscompatiblewithmost synchronoustransferformatsand can be configured as a 3 or4 pininterfaceby sif4_enainregisterconfig2.Inbothconfigurations,SCLK istheserialinterfaceinput clockand SDENB isserialinterfaceenable.For 3 pinconfiguration,SDIO isa bidirectionalpinforbothdatain and dataout.For4 pinconfiguration,SDIO isdatainonlyand SDO isdataoutonly.Data isinputintothedevice withtherisingedge ofSCLK. Data isoutputfromthedeviceon thefallingedge ofSCLK. Each read/writeoperationisframedby signalSDENB (SerialData EnableBar)assertedlow.The firstframebyte isthe instructioncyclewhich identifiesthe followingdata transfercycleas read or writeas wellas the 7-bit addresstobe accessed.Table1 indicatesthefunctionofeach bitintheinstructioncycleand isfollowedby a detaileddescriptionofeach bit.The datatransfercycleconsistsoftwo bytes Table1.InstructionByte oftheSerialInterface MSB LSB Bit 7 6 5 4 3 2 1 0 Description R/W A6 A5 A4 A3 A2 A1 A0

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 R/W Identifiesthefollowingdatatransfercycleas a readorwriteoperation.A highindicatesa read operationfromDAC34H84 and a lowindicatesa writeoperationtoDAC34H84. [A6 :A0] Identifiestheaddressoftheregistertobe accessedduringthereadorwriteoperation. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):DAC34H84

rwb A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 tS(SDENB) tH(SDIO) tS(SDIO) SDENB SCLK SDIO SDENB SCLK SDIO Instruction Cycle Data Transfer Cycle T0521-01 t(SCLK) DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Figure49 shows theserialinterfacetimingdiagramfora DAC34H84 writeoperation.SCLK istheserialinterfaceclockinputtoDAC34H84. Serialdata enableSDENB isan activelowinputtoDAC34H84. SDIO isserialdatain.InputdatatoDAC34H84 isclockedon therisingedges ofSCLK. Figure49. SerialInterfaceWriteTiming Diagram

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rwb A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 td(Data) SDENB SCLK SDIO SDO SDENB SCLK Instruction Cycle Data Transfer Cycle T0522-01 SDIO SDO Data n – 1Data n DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Figure50 shows theserialinterfacetimingdiagramfora DAC34H84 readoperation.SCLK istheserialinterfaceclockinputtoDAC34H84. Serialdata enableSDENB isan activelow inputtoDAC34H84. SDIO isserialdatainduringtheinstructioncycle.In3 pinconfiguration,SDIO isdataoutfromthe DAC34H84 duringthedatatransfercycle,whileSDO isina high-impedancestate.In4 pinconfiguration,SDO isdataoutfromtheDAC34H84 duringthe datatransfercycle.Attheend ofthedatatransfer,SDIO and SDO willoutputlowon thefinalfallingedge ofSCLK untiltherisingedge ofSDENB when it will3-state. Figure50. SerialInterfaceRead Timing Diagram Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Table2.RegisterMap (1) (MSB) (LSB)Name Address Default Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1Bit15 Bit0 qmc_ qmc_ qmc_ qmc_ alarm_out_ alarm_out clkdiv_sync_ invsincAB_ invsincCD_config0 0x00 0x049C offsetAB_ offsetCD_ corrAB_ corrCD_ interp(3:0) fifo_ena reserved reserved ena pol ena ena enaena ena ena ena single_ dual_ alarm_ alarm_ alarm_64cnt_iotest_ oddeven_ rev_ dacA_ dacB_ dacC_ dacD_config1 0x01 0x040E reserved reserved parity_ parity_ 2away_ 1away_ collision_ reservedena parity interface complement complement complement complementena ena ena ena ena ena dacclk dataclk collision_config2 0x02 0x7000 reserved reserved reserved reserved reserved sif4_ena mixer_ena mixer_gain nco_ena revbus reserved twos reservedgone_ena gone_ena gone_ena config3 0x03 0xF000 coarse_dac(3:0) reserved reserved sif_txenable config4 0x04 NA iotest_results(15:0) alarm_ alarm_alarm_ alarm_ alarm_ alarm_alarm_ alarm_ alarm_ alarm_dacclk_ dataclk_ output_config5 0x05 NA from_ reserved alarms_from_fifo(2:0) from_ reserved reservedfrom_pll Aparity Cparity DparityBparitygone gone gonezerochk iotest config6 0x06 NA tempdata(7:0) reserved reserved reserved config7 0x07 0xFFFF alarms_mask(15:0) config8 0x08 0x0000 reserved reserved reserved qmc_offsetA(12:0) config9 0x09 0x8000 fifo_offset(2:0) qmc_offsetB(12:0) config10 0x0A 0x0000 reserved reserved reserved qmc_offsetC(12:0) config11 0x0B 0x0000 reserved reserved reserved qmc_offsetD(12:0) config12 0x0C 0x0400 reserved reserved reserved reserved reserved qmc_gainA(10:0) config13 0x0D 0x0400 cmix(3:0) reserved qmc_gainB(10:0) config14 0x0E 0x0400 reserved reserved reserved reserved reserved qmc_gainC(10:0) config15 0x0F 0x0400 output_delayAB(1:0) output_delayCD(1:0) reserved qmc_gainD(10:0) config16 0x10 0x0000 reserved reserved reserved reserved qmc_phaseAB(11:0) config17 0x11 0x0000 reserved reserved reserved reserved qmc_phaseCD(11:0) config18 0x12 0x0000 phase_offsetAB(15:0) config19 0x13 0x0000 phase_offsetCD(15:0) config20 0x14 0x0000 phase_addAB(15:0) config21 0x15 0x0000 phase_addAB(31:16) config22 0x16 0x0000 phase_addCD(15:0) config23 0x17 0x0000 phase_addCD(31:16) pll_ config24 0x18 NA reserved pll_reset ndivsync_ pll_ena reserved pll_cp(1:0) pll_p(2:0) pll_lfvolt(2:0) ena config25 0x19 0x0440 pll_m(7:0) pll_n(3:0) pll_vcoitune(2:0) reserved bias_ tsense_ clkrecv_config26 0x1A 0x0020 pll_vco(5:0) reserved reserved pll_sleep sleepA sleepB sleepC sleepDsleep sleep sleep extref_ fuse_config27 0x1B 0x0000 reserved reserved reserved reserved reserved reserved reserved reserved reservedena sleep config28 0x1C 0x0000 reserved reserved config29 0x1D 0x0000 reserved reserved config30 0x1E 0x1111 syncsel_qmoffsetAB(3:0) syncsel_qmoffsetCD(3:0) syncsel_qmcorrAB(3:0) syncsel_qmcorrCD(3:0) (1) Unlessotherwisenoted,allreservedregistersshouldbe programmed todefaultvalues.

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Table2.RegisterMap (1)(continued) (MSB) (LSB)Name Address Default Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1Bit15 Bit0 config31 0x1F 0x1140 syncsel_mixerAB(3:0) syncsel_mixerCD(3:0) syncsel_nco(3:0) syncsel_fifo_input sif_sync reserved clkdiv_config32 0x20 0x2400 syncsel_fifoin(3:0) syncsel_fifoout(3:0) reserved sync_sel config33 0x21 0x0000 reserved config34 0x22 0x1B1B pathA_in_set(1:0) pathB_in_set(1:0) pathC_in_set(1:0) pathD_in_set(1:0) DACA_out_set(1:0) DACB_out_set(1:0) DACC_out_set(1:0) DACD_out_set(1:0) config35 0x23 0xFFFF sleep_cntl(15:0) config36 0x24 0x0000 datadly(2:0) clkdly(2:0) reserved config37 0x25 0x7A7A iotest_pattern0 config38 0x26 0xB6B6 iotest_pattern1 config39 0x27 0xEAEA iotest_pattern2 config40 0x28 0x4545 iotest_pattern3 config41 0x29 0x1A1A iotest_pattern4 config42 0x2A 0x1616 iotest_pattern5 config43 0x2B 0xAAAA iotest_pattern6 config44 0x2C 0xC6C6 iotest_pattern7 ostrtodig_config45 0x2D 0x0004 reserved ramp_ena reserved sifdac_enasel config46 0x2E 0x0000 grp_delayA(7:0) grp_delayB(7:0) config47 0x2F 0x0000 grp_delayC(7:0) grp_delayD(7:0) config48 0x30 0x0000 sifdac(15:0) version 0x7F 0x5409 reserved reserved reserved reserved deviceid(1:0) versionid(2:0) Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com REGISTER DESCRIPTIONS Registername: config0– Address: 0x00,Default:0x049C Register DefaultAddress Bit Name FunctionName Value config0 0x00 15 qmc_offsetAB_ena When set,thedigitalQuadratureModulatorCorrection(QMC) offset 0 correctionfortheAB datapathisenabled. 14 qmc_offsetCD_ena When set,thedigitalQuadratureModulatorCorrection(QMC) offset 0 correctionfortheCD datapathisenabled. 13 qmc_corrAB_ena When set,theQMC phase and gaincorrectioncircuitryfortheAB 0 datapathisenabled. 12 qmc_corrCD_ena When set,theQMC phase and gaincorrectioncircuitryfortheCD 0 datapathisenabled. 11:8 interp(3:0) These bitsdefinetheinterpolationfactor 0100 interp InterpolationFactor 0000 1x 0001 2x 0010 4x 0100 8x 1000 16x 7 fifo_ena When set,theFIFO isenabled.When theFIFO isdisabled 1 DACCCLKP/N and DATACLKP/N must be aligned(not recommended). 6 Reserved Reservedforfactoryuse. 0 5 Reserved Reservedforfactoryuse. 0 4 alarm_out_ena When set,theALARM pinbecomes an output.When cleared,the 1 ALARM pinis3-stated. 3 alarm_out_pol Thisbitchanges thepolarityoftheALARM signal. 1 MM 0:Negativelogic MM 1:Positivelogic 2 clkdiv_sync_ena When set,enablesthesyncingoftheclockdividerand theFIFO 1 outputpointerusingthesyncsourceselectedby registerconfig32. The internaldivided-downclockswillbe phase alignedaftersyncing. RefertothePower-Up Sequence sectionformore detail. 1 invsincAB_ena When set,theinversesincfilterfortheAB datapathisenabled. 0 0 invsincCD_ena When set,theinversesincfilterfortheCD datapathisenabled. 0

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Registername: config1– Address: 0x01,Default:0x040E Register DefaultAddress Bit Name FunctionName Value config1 0x01 15 iotest_ena When set,enablesthedatapatterncheckertest.The outputsare 0 deactivatedregardlessofthestateofTXENA and sif_txenable. 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12 64cnt_ena When set,enablesresettingofthealarmsafter64 good samples 0 withthegoalofremovingunnecessaryerrors.Forinstance,when checkingsetup/holdthroughthepatterncheckertest,theremay initiallybe errors.Settingthisbitremoves theneed fora SIF writeto clearthealarmregister. 11 oddeven_parity Selectsbetween odd and even paritycheck 0 MM 0:Even parity MM 1:Odd parity 10 single_parity_ena When set,enablesparitycheckingofeach inputword usingthe1 1 PARITYP/N parityinput.Itshouldmatch theoddeven_parity registersetting. 9 dual_parity_ena When set,enablesparitycheckingusingtheISTR signalto0 source 0 theparitybit.The paritybitshouldmatch theoddeven_parity registersetting. 8 rev_interface When set,thePARITY, SYNC, and ISTR inputsarerotatedtoallow 0 completereversalofthedatainterfacewhen settingthe rev_interfacebit. When rev_interface= “1”,thefollowingchanges occurs MM 1.SYNCP/N becomes ISTRP/N MM 2.PARITYP/N becomes SYNCP/N MM 3.ISTRP/N becomes PARITYP/N 7 dacA_complement When set,theDACA outputiscomplemented.Thisallowsto 0 effectivelychange the+ and – designationsoftheLVDS datalines. 6 dacB_complement When set,theDACB outputiscomplemented.Thisallowsto 0 effectivelychange the+ and – designationsoftheLVDS datalines. 5 dacC_complement When set,theDACC outputiscomplemented.Thisallowsto 0 effectivelychange the+ and – designationsoftheLVDS datalines. 4 dacD_complement When set,theDACD outputiscomplemented.Thisallowsto 0 effectivelychange the+ and – designationsoftheLVDS datalines. 3 alarm_2away_ena When set,thealarmfromtheFIFO indicatingthewriteand read 1 pointersbeing2 away isenabled. 2 alarm_1away_ena When set,thealarmfromtheFIFO indicatingthewriteand read 1 pointersbeing1 away isenabled. 1 alarm_collision_ena When set,thealarmfromtheFIFO indicatinga collisionbetween the 1 writeand readpointersisenabled. 0 Reserved Reservedforfactoryuse. 0 Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):DAC34H84

/c40 /c41EXTIO FS BIAS VI 2 coarse _ dac 1R/c61 /c180 /c180 /c43 DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Registername: config2– Address: 0x02,Default:0x7000 Register DefaultAddress Bit Name FunctionName Value config2 0x02 15 Reserved Reservedforfactoryuse. 0 14 dacclkgone_ena When set,theDACCLK-gone signalfromtheclockmonitorcircuitcan 1 be used toshutofftheDAC outputs.The correspondingalarms, alarm_dacclk_goneand alarm_output_gone,must notbe masked (i.e.Config7,bit<10> and bit<8> must setto"0"). 13 dataclkgone_ena When set,theDATACLK-gone signalfromtheclockmonitorcircuit 1 can be used toshutofftheDAC outputs.The correspondingalarms, alarm_dataclk_goneand alarm_output_gone,must notbe masked (i.e.Config7,bit<9> and bit<8> must setto"0"). 12 collisiongone_ena When set,theFIFO collisionalarmscan be used toshutofftheDAC 1 outputs.The correspondingalarms,alarm_fifo_collisionand alarm_output_gone,must notbe masked (i.e.Config7,bit<13> and bit<8> must setto"0"). 11 Reserved Reservedforfactoryuse. 0 10 Reserved Reservedforfactoryuse. 0 9 Reserved Reservedforfactoryuse. 0 8 Reserved Reservedforfactoryuse. 0 7 sif4_ena When set,theserialinterface(SIF)isa 4 bitinterface,otherwiseitis 0 a 3 bitinterface. 6 mixer_ena When set,themixerblockisenabled. 0 5 mixer_gain When set,a 6dB gainisadded tothemixeroutput. 0 4 nco_ena When set,theNCO isenabled.Thisisnotrequiredforcoarsemixing. 0 3 revbus When set,theinputbitsforthedatabus arereversed.MSB becomes 0 LSB. 2 Reserved Reservedforfactoryuse. 0 1 twos When set,theinputdataformatisexpectedtobe 2’s complement. 0 When cleared,theinputisexpectedtobe offset-binary. 0 Reserved Reservedforfactoryuse. 0 Registername: config3– Address: 0x03,Default:0xF000 Register DefaultAddress Bit Name FunctionName Value config3 0x03 15:12 coarse_dac(3:0) Scalestheoutputcurrentin16 equalsteps. 1111 11:8 Reserved Reservedforfactoryuse. 0000 7:1 Reserved Reservedforfactoryuse. 0000000 0 sif_txenable When set,theinternalvalueofTXENABLE issetto“1”. 0 To enableanalogoutputdatatransmission,setsif_txenableto“1” or pullCMOS TXENA pin(N9)tohigh.To disableanalogoutput,set sif_txenableto“0” and pullCMOS TXENA pin(N9)tolow.

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Registername: config4– Address: 0x04,Default:No RESET Value (WRITE TO CLEAR) Register DefaultAddress Bit Name FunctionName Value config4 0x04 15:0 iotest_results(15:0) Bitsiniotest_resultswithlogicvalueof“1” tellwhichbitineitherDAB[15:0] No RESET bus orDCD[15:0]bus failedduringthepatterncheckertest. Value iotest_results(15:8)correspondtothedatabitson bothDAB[15:8]and DCD[15:8]. iotest_results(7:0)correspondtothedatabitson bothDAB[7:0]and DCD[7:0]. Registername: config5– Address: 0x05,Default:Setup and Power-Up ConditionsDependent (WRITE TO CLEAR) Register Address DefaultBit Name FunctionName Value config5 0x05 15 alarm_from_zerochk Thisalarmindicatesthe8-bitFIFO writepointeraddresshas an all NA zerospatterns.Due topointeraddressbeinga shiftregister,thisis nota validaddressand willcause thewritepointertobe stuckuntil thenextsync.Thiserroristypicallycaused by timingerroror improperpower start-upsequence.Ifthisalarmisasserted, resynchronizationofFIFO isnecessary.RefertothePower-Up Sequence sectionformore detail. 14 Reserved Reservedforfactoryuse. NA 13:11 alarms_from_fifo(2:0) AlarmindicatingFIFO pointercollisionsand nearness: NA MM 000:Allfine MM 001:Pointersare2 away MM 01x:Pointersare1 away MM 1xx:FIFO pointercollision IftheFIFO pointercollisionalarmissetwhen collisiongone_enais enabled,theFIFO must be re-synchronizedand thebitsmust be clearedtoresume normaloperation. 10 alarm_dacclk_gone AlarmindicatingtheDACCLK has been stopped. NA Ifthebitissetwhen dacclkgone_enaisenabled,theDACCLK must resume and thebitmust be clearedtoresume normaloperation. 9 alarm_dataclk_gone AlarmindicatingtheDATACLK has been stopped. NA Ifthebitissetwhen dataclkgone_enaisenabled,theDATACLK must resume and thebitmust be clearedtoresume normal operation. 8 alarm_output_gone Alarmindicatingeitheralarm_dacclk_gone,alarm_dataclk_gone,or NA alarm_fifo_collisionareasserted.Itcontrolstheoutput.When highit willoutput"0x8000"foreach outputconnectedtotheDAC. Ifthebit issetwhen dacclkgone_ena,dataclkgone_ena,or collisiongone_enaareenabled,thenthecorrespondingerrorsmust be fixedand thebitsmust be clearedtoresume normaloperation. 7 alarm_from_iotest Alarmindicatingtheinputdatapatterndoes notmatch thepatternin NA theiotest_patternregisters.When datapatterncheckermode is enabled,thisalarminregisterconfig5,bit7istheonlyvalidalarm. Otheralarmsinregisterconfig5arenotvalidand can be disregarded. 6 Reserved Reservedforfactoryuse. NA 5 alarm_from_pll AlarmindicatingthePLL has lostlock.ForversionID "001", NA alarm_from_PLLmay notindicatethecorrectstatusofthePLL. Refertopll_lfvolt(2:0)inregisterconfig24forproperPLL lock indication. 4 alarm_Aparity Indualparitymode, alarmindicatinga parityerroron theA word.In NA singleparitymode, alarmon the32-bitdatacapturedon therising edge ofDATACLKP/N. 3 alarm_Bparity Indualparitymode, alarmindicatinga parityerroron theB word.In NA singleparitymode, alarmon the32-bitdatacapturedon thefalling edge ofDATACLKP/N. 2 alarm_Cparity Indualparitymode, alarmindicatinga parityerroron theC word. NA 1 alarm_Dparity Indualparitymode, alarmindicatinga parityerroron theD word. NA 0 Reserved Reservedforfactoryuse. NA Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Registername: config6– Address: 0x06,Default:No RESET Value (READ ONLY) Register DefaultAddress Bit Name FunctionName Value config6 0x06 15:8 tempdata(7:0) Thisistheoutputfromthechiptemperaturesensor.The valueofthisregisterin No two’s complement formatrepresentsthetemperatureindegreesCelsius.This RESET registermust be read witha minimum SCLK periodof1μs. Value 7:2 Reserved Reservedforfactoryuse. 000000 1 Reserved Reservedforfactoryuse. 0 0 Reserved Reservedforfactoryuse. 0 Registername: config7– Address: 0x07,Default:0xFFFF Register DefaultAddress Bit Name FunctionName Value config7 0x07 15:0 alarms_mask(15:0) These bitscontrolthemaskingofthealarms.(0=notmasked, 1= masked) 0xFFFF alarm_mask Alarm thatisMasked 15 alarm_from_zerochk 14 notused 13 alarm_fifo_collision 12 alarm_fifo_1away 11 alarm_fifo_2away 10 alarm_dacclk_gone 9 alarm_dataclk_gone 8 alarm_output_gone 7 alarm_from_iotest 6 notused 5 alarm_from_pll 4 alarm_Aparity 3 alarm_Bparity 2 alarm_Cparity 1 alarm_Dparity 0 notused Registername: config8– Address: 0x08,Default:0x0000 (CAUSES AUTO-SYNC) Register DefaultAddress Bit Name Function ValueName config8 0x08 15 Reserved Reservedforfactoryuse. 0 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12:0 qmc_offsetA(12:0) DACA offsetcorrection.The offsetismeasured inDAC LSBs. Ifenabled inconfig30 Allzeros writingtothisregistercauses an auto-synctobe generated.Thisloadsthevaluesof theQMC offsetregisters(config8-config9)intotheoffsetblockatthesame time. When updatingtheoffsetvaluesfortheAB channel config8should be writtenlast. Programming config9willnot affecttheoffsetsetting. Registername: config9– Address: 0x09,Default:0x8000 Register DefaultAddress Bit Name Function ValueName config9 0x09 15:13 fifo_offset(2:0) When thesynctotheFIFO occurs,thisisthevalueloadedintotheFIFO readpointer.With 100 thisvaluetheinitialdifferencebetween writeand readpointerscan be controlled.Thismay be helpfulinsyncingmultiplechipsorcontrollingthedelaythroughthedevice. 12:0 qmc_offsetB(12:0)DACB offsetcorrection.The offsetismeasured inDAC LSBs. Allzeros

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Registername: config10– Address: 0x0A, Default:0x0000 (CAUSES AUTO-SYNC) Register DefaultAddress Bit Name Function ValueName config10 0x0A 15 Reserved Reservedforfactoryuse. 0 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12:0 qmc_offsetC(12:0) DACC offsetcorrection.The offsetismeasured inDAC LSBs. Ifenabled inconfig30 Allzeros writingtothisregistercauses an auto-synctobe generated.Thisloadsthevaluesof theCD-channel QMC offsetregisters(config10-config11)intotheoffsetblockatthe same time.When updatingtheoffsetvaluesfortheCD-channel config10should be writtenlast.Programming config11willnot affecttheoffsetsetting. Registername: config11– Address: 0x0B, Default:0x0000 Register DefaultAddress Bit Name Function ValueName config11 0x0B 15 Reserved Reservedforfactoryuse. 0 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12:0 qmc_offsetD(12:0) DACD offsetcorrection.The offsetismeasured inDAC LSBs. Allzeros Registername: config12– Address: 0x0C, Default:0x0400 Register DefaultAddress Bit Name Function ValueName config12 0x0C 15 Reserved Reservedforfactoryuse. 0 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12 Reserved Reservedforfactoryuse. 0 11 Reserved Reservedforfactoryuse. 0 10:0 qmc_gainA(10:0) QMC gainforDACA. The full11-bitqmc_gainA(10:0)word isformattedas UNSIGNED 10000000 witha rangeof0 to1.9990.The implieddecimalpointforthemultiplicationisbetween bit 000 9 and bit10. Registername: config13– Address: 0x0D, Default:0x0400 Register DefaultAddress Bit Name Function ValueName config13 0x0D 15 cmix_mode(3:0) Setsthemixingfunctionofthecoarsemixer. 0000 MM Bit15:Fs/8mixer MM Bit14:Fs/4mixer MM Bit13:Fs/2mixer MM Bit12:-Fs/4mixer The variousmixerscan be combined togethertoobtaina ±n×Fs/8totalmixingfactor. 11 Reserved Reservedforfactoryuse. 0 10:0 qmc_gainB(10:0) QMC gainforDACB. The full11-bitqmc_gainB(10:0)word isformattedas UNSIGNED 10000000 witha rangeof0 to1.9990.The implieddecimalpointforthemultiplicationisbetween 000 bit9 and bit10. Registername: config14– Address: 0x0E,Default:0x0400 Register DefaultAddress Bit Name Function ValueName config14 0x0E 15 Reserved Reservedforfactoryuse. 0 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12 Reserved Reservedforfactoryuse. 0 11 Reserved Reservedforfactoryuse. 0 10:0 qmc_gainC(10:0) QMC gainforDACC. The full11-bitqmc_gainC(10:0)word isformattedas UNSIGNED 10000000 witha rangeof0 to1.9990.The implieddecimalpointforthemultiplicationisbetween 000 bit9 and bit10. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Registername: config15– Address: 0x0F,Default:0x0400 Register DefaultAddress Bit Name Function ValueName config15 0x0F 15:14 output_ DelaystheAB datapathoutputsfrom0 to3 DAC clockcycles. 00 delayAB(1:0) 13:12 output_ DelaystheCD datapathoutputsfrom0 to3 DAC clockcycles. 00 delayCD(1:0) 11 Reserved Reservedforfactoryuse. 0 10:0 qmc_gainD(10:0) QMC gainforDACD. The full11-bitqmc_gainD(10:0)word isformattedas UNSIGNED 10000000 witha rangeof0 to1.9990.The implieddecimalpointforthemultiplicationisbetween 000 bit9 and bit10. Registername: config16– Address: 0x10,Default:0x0000 (CAUSES AUTO-SYNC) Register DefaultAddress Bit Name Function ValueName config16 0x10 15 Reserved Reservedforfactoryuse. 0 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12 Reserved Reservedforfactoryuse. 0 11:0 qmc_phaseAB(11:0) QMC correctionphase fortheAB datapath.The 12-bitqmc_phaseAB(11:0)word is Allzeros formattedas two’s complement and scaledtooccupya rangeof-0.5to0.49975and a defaultphase correctionof0.00.To accomplishQMC phase correction,thisvalue ismultipliedby thecurrentB sample,thensummed intotheA sample.Ifenabled in config30writingtothisregistercauses an auto-synctobe generated.This loadsthevaluesoftheQMC offsetregisters(config12,config13,and config16) intotheQMC blockatthesame time.When updatingtheQMC valuesforthe AB channel config16should be writtenlast.Programming config12and config13willnot affecttheQMC settings. Registername: config17– Address: 0x11,Default:0x0000 (CAUSES AUTO-SYNC) Register DefaultAddress Bit Name Function ValueName config17 0x11 15 Reserved Reservedforfactoryuse. 0 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12 Reserved Reservedforfactoryuse. 0 11:0 qmc_phaseCD(11:0) QMC correctionphase fortheCD datapath.The 12-bitqmc_gainCD(11:0)word is Allzeros formattedas two’s complement and scaledtooccupya rangeof-0.5to0.49975 and a defaultphase correctionof0.00.To accomplishQMC phase correction,this valueismultipliedby thecurrentD sample,thensummed intotheC sample.If enabled inconfig30writingtothisregistercauses an auto-synctobe generated.ThisloadsthevaluesoftheCD-channel QMC blockregisters (config14,config15and config17)intotheQMC blockatthesame time.When updatingtheQMC valuesfortheCD-channel config17should be writtenlast. Programming config14and config15willnot affecttheQMC settings. Registername: config18– Address: 0x12,Default:0x0000 (CAUSES AUTO-SYNC) Register DefaultAddress Bit Name Function ValueName config18 0x12 15:0 phase_offsetAB(15:0)Phase offsetadded totheAB datapathNCO accumulatorbeforethegenerationof 0x0000 theSIN and COS values.The phase offsetisadded totheupper16 bitsoftheNCO accumulatorresultsand these16 bitsareused inthesin/coslookuptables.If enabled inconfig31writingtothisregistercauses an auto-synctobe generated.Thisloadsthevaluesofthefinemixer blockregisters(config18, config20,and config21)atthesame time.When updatingthemixer valuesthe config18should be writtenlast.Programming config20and config21willnot affectthemixer settings.

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Registername: config19– Address: 0x13,Default:0x0000 (CAUSES AUTO-SYNC) Register DefaultAddress Bit Name Function ValueName config19 0x13 15:0 phase_offsetCD(15:0) Phase offsetadded totheCD datapathNCO accumulatorbeforethegenerationof 0x0000 theSIN and COS values.The phase offsetisadded totheupper16 bitsoftheNCO accumulatorresultsand these16 bitsareused inthesin/coslookuptables.If enabled inconfig31writingtothisregistercauses an auto-synctobe generated.ThisloadsthevaluesoftheCD-channel finemixer blockregisters (config19,config22,and config23)atthesame time.When updatingthemixer valuesfortheCD-channel config19should be writtenlast.Programming config22and config23willnot affectthemixer settings. Registername: config20– Address: 0x14,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config20 0x14 15:0 phase_ addAB(15:0) The phase_addAB(15:0)valueisused todeterminetheNCO frequency.The two’s 0x0000 complement formattedvaluecan be positiveornegative.Each LSB represents Fs/(2^32)frequencystep. Registername: config21– Address: 0x15,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config21 0x15 15:0 phase_ addAB(31:16) See config20above. 0x0000 Registername: config22– Address: 0x16,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config22 0x16 15:0 phase_ addCD(15:0) The phase_addCD(15:0)valueisused todeterminetheNCO frequency.The two’s 0x0000 complement formattedvaluecan be positiveornegative.Each LSB represents Fs/(2^32)frequencystep. Registername: config23– Address: 0x17,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config23 0x17 15:0 phase_ addCD(31:16) See config22above. 0x0000 Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Registername: config24– Address: 0x18,Default:NA Register DefaultAddress Bit Name Function ValueName config24 0x18 15:13 Reserved Reservedforfactoryuse. 001 12 pll_reset When set,thePLL loopfilter(LPF)ispulleddown to0V.Togglefrom‘1’ to‘0’ to 0 restartthePLL ifan over-speedlock-upoccurs.Over-speedcan happen when the processisfast,thesuppliesarehigherthannominal,etc.resultinginthefeedback dividersmissinga clock. 11 pll_ndivsync_ena When set,theLVDS SYNC inputisused tosyncthePLL N dividers. 1 10 pll_ena When set,thePLL isenabled.When cleared,thePLL isbypassed. 0 9:8 Reserved Reservedforfactoryuse. 00 7:6 pll_cp(1:0) PLL pump chargeselect 00 MM 00:No chargepump MM 01:Singlepump charge MM 10:Not used MM 11:Dualpump charge 5:3 pll_p(2:0) PLL pre-scalerdividingmodule control. 001 MM 010:2 MM 011:3 MM 100:4 MM 101:5 MM 110:6 MM 111:7 MM 000:8 2:0 pll_lfvolt(2:0) PLL loopfiltervoltage.Thisthreebitread-onlyindicatorhas stepsizeof0.4125V. NA The entirerangecoversfrom0V to3.3V.The optimallockrangeofthePLL willbe Registername: config25– Address: 0x19,Default:0x0440 Register DefaultAddress Bit Name Function ValueName config25 0x19 15:8 pll_m(7:0) M portionoftheM/N dividerofthePLL. 0x04 Ifpll_m<7> = 0,theM dividervaluehas therangeofpll_m<6:0>,spanningfrom 4 to127.(i.e.0,1,2,and 3 arenotvalid.) Ifpll_m<7> = 1,theM dividervaluehas therangeof2 × pll_m<6:0>,spanning 7:4 pll_n(3:0) N portionoftheM/N dividerofthePLL. 0100 MM 0000:1 MM 0001:2 MM 0010:3 MM 0011:4 MM 0100:5 MM 0101:6 MM 0110:7 MM 0111:8 MM 1000:9 MM 1001:10 MM 1010:11 MM 1011:12 MM 1100:13 MM 1101:14 MM 1110:15 MM 1111:16 3:2 pll_vcoitune(1:0) PLL VCO biastuningbits.Setto"01"fornormalPLL operation 00 1:0 Reserved Reservedforfactoryuse. 00

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Registername: config26– Address: 0x1A, Default:0x0020 Register DefaultAddress Bit Name Function ValueName config26 0x1A 15:10 pll_vco(5:0) VCO frequencycoarsetuningbits. 000000 9 Reserved Reservedforfactoryuse. 0 8 Reserved Reservedforfactoryuse. 0 7 bias_sleep When set,thebiasamplifierisputintosleepmode. 0 6 tsense_sleep Turnsoffthetemperaturesensorwhen asserted. 0 5 pll_sleep When set,thePLL isputintosleepmode. 1 4 clkrecv_sleep When assertedtheclockinputreceivergetsputintosleepmode. Thisaffectsthe 0 OSTR receiveras well. 3 sleepA When set,theDACA isputintosleepmode. 0 2 sleepB When set,theDACB isputintosleepmode. 0 1 sleepC When set,theDACC isputintosleepmode. 0 0 sleepD When set,theDACD isputintosleepmode. 0 Registername: config27– Address: 0x1B, Default:0x0000 Register DefaultAddress Bit Name Function ValueName config27 0x1B 15 extref_ena Allowsthedevicetouse an externalreferenceortheinternalreference. 0 0:Internalreference 1:Externalreference 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12 Reserved Reservedforfactoryuse. 0 11 fuse_sleep Putthefusestosleepwhen sethigh. 0 Note:Defaultvalueis‘0’.Must be setto‘1’ forproperoperation 10 Reserved Reservedforfactoryuse. 0 9 Reserved Reservedforfactoryuse. 0 8 Reserved Reservedforfactoryuse. 0 7 Reserved Reservedforfactoryuse. 0 6 Reserved Reservedforfactoryuse. 0 5:0 atest ATEST mode allowstheusertocheckfortheinternaldievoltagestoensurethe 000000 supplyvoltagesarewithintherange.When ATEST mode isprogrammed,the internaldievoltagescan be measured attheTXENA pin.The TXENA pin(N9)must be floatingwithoutany pull-uporpull-downresistors. InATEST mode, theTXENA and sif_txenablelogicsarebypassed,and outputwill be activeatalltime. Config27,bit<5:0> Description Expected Nominal Voltage

001110 DACA AVSS 0V

001111 DACA DVDD 1.2V 010000 DACA AVDD 3.3V

010110 DACB AVSS 0V

010111 DACB DVDD 1.2V 011000 DACB AVDD 3.3V

011110 DACC AVSS 0V

011111 DACC DVDD 1.2V 100000 DACC AVDD 3.3V

100110 DACD AVSS 0V

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Registername: config28– Address: 0x1C, Default:0x0000 Register DefaultAddress Bit Name Function ValueName config28 0x1C 15:8 Reserved Reservedforfactoryuse. 0x00 7:0 Reserved Reservedforfactoryuse. 0x00 Registername: config29– Address: 0x1D, Default:0x0000 Register DefaultAddress Bit Name Function ValueName config29 0x1D 15:8 Reserved Reservedforfactoryuse. 0x00 7:0 Reserved Reservedforfactoryuse. 0x00 Registername: config30– Address: 0x1E,Default:0x1111 Register DefaultAddress Bit Name Function ValueName config30 0x1E 15:12 syncsel_qmoffsetAB(3:0)Selectsthesyncingsource(s)oftheAB datapathdoublebufferedQMC offset 0001 registers.A ‘1’ inthebitenablesthesignalas a syncsource.More thanone sync sourceispermitted. MM Bit15:sif_sync(viaconfig31) MM Bit14:SYNC MM Bit13:OSTR MM Bit12:Auto-syncfromregisterwrite 11:8 syncsel_qmoffsetCD(3:0)Selectsthesyncingsource(s)oftheCD datapathdoublebufferedQMC offset 0001 registers.A ‘1’ inthebitenablesthesignalas a syncsource.More thanone sync sourceispermitted. MM Bit11:sif_sync(viaconfig31) MM Bit10:SYNC MM Bit9:OSTR MM Bit8:Auto-syncfromregisterwrite 7:4 syncsel_qmcorrAB(3:0) Selectsthesyncingsource(s)oftheAB datapathdoublebufferedQMC offset 0001 registers.A ‘1’ inthebitenablesthesignalas a syncsource.More thanone sync sourceispermitted. MM Bit7:sif_sync(viaconfig31) MM Bit6:SYNC MM Bit5:OSTR MM Bit4:Auto-syncfromregisterwrite 3:0 syncsel_qmcorrCD(3:0) Selectsthesyncingsource(s)oftheCD datapathdoublebufferedQMC offset 0001 registers.A ‘1’ inthebitenablesthesignalas a syncsource.More thanone sync sourceispermitted. MM Bit3:sif_sync(viaconfig31) MM Bit2:SYNC MM Bit1:OSTR MM Bit0:Auto-syncfromregisterwrite

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Registername: config31– Address: 0x1F,Default:0x1140 Register DefaultAddress Bit Name Function ValueName config31 0x1F 15:12 syncsel_mixerAB(3:0) Selectsthesyncingsource(s)oftheAB datapathdoublebufferedmixer 0001 registers.A ‘1’ inthebitenablesthesignalas a syncsource.More thanone syncsourceispermitted. MM Bit15:sif_sync(viaconfig31) MM Bit14:SYNC MM Bit13:OSTR MM Bit12:Auto-syncfromregisterwrite 11:8 syncsel_mixerCD(3:0) Selectsthesyncingsource(s)oftheCD datapathdoublebufferedmixer 0001 registers.A ‘1’ inthebitenablesthesignalas a syncsource.More thanone syncsourceispermitted. MM Bit11:sif_sync(viaconfig31) MM Bit10:SYNC MM Bit9:OSTR MM Bit8:Auto-syncfromregisterwrite 7:4 syncsel_nco(3:0) Selectsthesyncingsource(s)ofthetwo NCO accumulators.A ‘1’ inthebit 0100 enablesthesignalas a syncsource.More thanone syncsourceispermitted. MM Bit7:sif_sync(viaconfig31) MM Bit6:SYNC MM Bit5:OSTR MM Bit4:ISTR 3:2 syncsel_fifo_input SelectseitherISTR orSYNC LVDS signaltobe routedtotheinternal 00 FIFO_ISTR pathifsyncsel_fifoin(3:0)issettobe ISTR (i.e.syncsel_fifoin(3:0)= “0010”).Inconjunctionwithconfig1registerbit(8),thisallowsflexibilityof externalLVDS signalroutingtotheinternalFIFO.The syncsel_fifo_input(1:0) can onlyhave one bitactiveata time. MM 00:externalLVDS ISTR signaltointernalFIFO_ISTR path MM 01:externalLVDS SYNC signaltointernalFIFO_ISTR path MM 10:externalLVDS ISTR signaltointernalFIFO_ISTR path MM 11:externalLVDS SYNC signaltointernalFIFO_ISTR path 1 sif_sync SIF createdsyncsignal.Setto‘1’ tocause a syncand thenclearto‘0’ to 0 remove it. 0 Reserved Reservedforfactoryuse. 0 Registername: config32– Address: 0x20,Default:0x2400 Register DefaultAddress Bit Name Function ValueName config32 0x20 15:12 syncsel_fifoin(3:0) Selectsthesyncingsource(s)oftheFIFO inputside.A ‘1’ inthebitenablesthe 0010 signalas a syncsource.More thanone syncsourceispermitted. MM Bit15:sif_sync(viaconfig31) MM Bit14:Alwayszero MM Bit13:ISTR MM Bit12:SYNC 11:8 syncsel_fifoout(3:0) Selectsthesyncingsource(s)oftheFIFO outputside.A ‘1’ inthebitenablesthe 0100 signalas a syncsource.More thanone syncsourceispermitted.clkdiv_sync_ena must be setto"1"fortheFIFO outputpointersynctooccur. MM Bit11:sif_sync(viaconfig31) MM Bit10:OSTR – DualSync SourcesMode MM Bit9:ISTR – SingleSync Sourcemode MM Bit8:SYNC – SingleSync Sourcemode 7:1 Reserved Reservedforfactoryuse. 0000 0 clkdiv_sync_sel Selectsthesignalsourceforclockdividersynchronization. 0 clkdiv_sync_sel Sync Source

0 OSTR

1 ISTR,SYNC, orSIF SYNC, based on syncsel_fifoin

(config32,bit<15:12>) Registername: config33– Address: 0x21,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config33 0x21 15:0 Reserved Reservedforfactoryuse. 0x0000 Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Registername: config34– Address: 0x22,Default:0x1B1B Register DefaultAddress Bit Name Function ValueName config34 0x22 15:14 pathA_in_sel(1:0) Selectstheword used fortheA channelpath. 00 13:12 pathB_in_sel(1:0) Selectstheword used fortheB channelpath. 01 11:10 pathC_in_sel(1:0) Selectstheword used fortheC channelpath. 10 9:8 pathD_in_sel(1:0) Selectstheword used fortheD channelpath. 11 7:6 DACA_out_sel(1:0) Selectstheword used fortheDACA output. 00 5:4 DACB_out_sel(1:0) Selectstheword used fortheDACB output. 01 3:2 DACC_out_sel(1:0) Selectstheword used fortheDACC output. 10 1:0 DACD_out_sel(1:0) Selectstheword used fortheDACD output. 11 Registername: config35– Address: 0x23,Default:0xFFFF Register DefaultAddress Bit Name Function ValueName config35 0x23 15:0 sleep_cntl(15:0) ControlstheroutingoftheCMOS SLEEP signal(pinN11) todifferentblocks.When a 0xFFFF bitinthisregisterisset,theSLEEP signalwillbe senttothecorrespondingblock.The blockwillonlybe disabledwhen theSLEEP islogicHIGH and thecorrespondbitisset to“1”. These bitsdo notoverrideSIF bitsinconfig26thatcontrolthesame sleepfunction. sleep_cntl(bit) Function

15 DACA sleep

14 DACB sleep

13 DACC sleep

12 DACD sleep

11 Clockreceiversleep

10 PLL sleep

9 LVDS datasleep

8 LVDS controlsleep

7 Temp sensorsleep

5 Biasamplifiersleep

Registername: config36– Address: 0x24,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config36 0x24 15:13 datadly(2:0) ControlsthedelayofthedatainputsthroughtheLVDS receivers.Each LSB adds 000 approximately50 ps 0:Minimum 12:10 clkdly(2:0) ControlsthedelayofthedataclockthroughtheLVDS receivers.Each LSB adds 000 approximately50 ps 0:Minimum 9:0 Reserved Reservedforfactoryuse. 0x000 Registername: config37– Address: 0x25,Default:0x7A7A Register DefaultAddress Bit Name Function ValueName config37 0x25 15:0 iotest_pattern0 Dataword0intheIO testpattern.Itisused withtheseven otherwords totesttheinputdata. 0x7A7A AtthestartoftheIO testpattern,thisword shouldbe alignedwithrisingedge ofISTR or SYNC signaltoindicatesample 0.

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Registername: config38– Address: 0x26,Default:0xB6B6 Register DefaultAddress Bit Name Function ValueName config38 0x26 15:0 iotest_pattern1 Dataword1intheIO testpattern.Itisused withtheseven otherwords totesttheinputdata. 0xB6B6 Registername: config39– Address: 0x27,Default:0xEAEA Register DefaultAddress Bit Name Function ValueName config39 0x27 15:0 iotest_pattern2 Dataword2intheIO testpattern.Itisused withtheseven otherwords totesttheinput 0xEAEA data. Registername: config40– Address: 0x28,Default:0x4545 Register DefaultAddress Bit Name Function ValueName config40 0x28 15:0 iotest_pattern3 Dataword3intheIO testpattern.Itisused withtheseven otherwords totesttheinputdata. 0x4545 Registername: config41– Address: 0x29,Default:0x1A1A Register DefaultAddress Bit Name Function ValueName config41 0x29 15:0 iotest_pattern4Dataword4intheIO testpattern.Itisused withtheseven otherwords totesttheinputdata. 0x1A1A Registername: config42– Address: 0x2A, Default:0x1616 Register DefaultAddress Bit Name Function ValueName config42 0x2A 15:0 iotest_pattern5 Dataword5intheIO testpattern.Itisused withtheseven otherwords totesttheinput 0x1616 data. Registername: config43– Address: 0x2B, Default:0xAAAA Register DefaultAddress Bit Name Function ValueName config43 0x2B 15:0 iotest_pattern6 Dataword6intheIO testpattern.Itisused withtheseven otherwords totesttheinput 0xAAAA data. Registername: config44– Address: 0x2C, Default:0xC6C6 Register DefaultAddress Bit Name Function ValueName config44 0x2C 15:0 iotest_pattern7 Dataword7intheIO testpattern.Itisused withtheseven otherwords totesttheinput 0xC6C6 data. Registername: config45– Address: 0x2D, Default:0x0004 Register DefaultAddress Bit Name Function ValueName config45 0x2D 15 Reserved Reservedforfactoryuse. 0 14 ostrtodig_sel When set,theOSTR signalispassed directlytothedigitalblock.Thisisthesignalthat 0 isused toclockthedividers. 13 ramp_ena When set,a ramp signalisinsertedintheinputdataattheFIFO input. 0 12:1 Reserved Reservedforfactoryuse. 0000 0000 0010 0 sifdac_ena When set,theDAC outputissettothevalueinsifdac(15:0)inregisterconfig48. 0 Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Registername: config46– Address: 0x2E,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config46 0x2E 15:8 grp_delaya(7:0) SetsthegroupdelayfunctionforDACA. The maximum delayrangesfrom30ps to 0x00 100ps and isdependenton DAC sample clock.ContactTIforspecificapplication information. 7:0 grp_delayB(7:0) SetsthegroupdelayfunctionforDACB. The maximum delayrangesfrom30ps to 0x00 100ps and isdependenton DAC sample clock.ContactTIforspecificapplication information. Registername: config47– Address: 0x2F,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config47 0x2F 15:8 grp_delayC(7:0) SetsthegroupdelayfunctionforDACC. The maximum delayrangesfrom30ps to 0x00 100ps and isdependenton DAC sample clock.ContactTIforspecificapplication information. 7:0 grp_delayD(7:0) SetsthegroupdelayfunctionforDACD. The maximum delayrangesfrom30ps to 0x00 100ps and isdependenton DAC sample clock.ContactTIforspecificapplication information. Registername: config48– Address: 0x30,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config48 0x30 15:0 sifdac(15:0) ValuesenttotheDACs when sifdac_enaisasserted.DATACLK must be runningto 0x0000 latchthisvalueintotheDACs. The formatwouldbe based on twosinregisterconfig2. Registername: version– Address: 0x7F,Default:0x5409 (READ ONLY) Register DefaultAddress Bit Name Function ValueName version 0x7F 15:10 Reserved Reservedforfactoryuse. 010101 9 Reserved Reservedforfactoryuse. 0 8:7 Reserved Reservedforfactoryuse. 00 6:5 Reserved Reservedforfactoryuse. 00 4:3 deviceid(1:0) Returns‘01’ forDAC34H84. 01 2:0 versionid(2:0) A hardwiredregisterthatcontainstheversionofthechip. 001

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DCD[15:0]P/N DAB[15:0]P/N ISTRP/N SAMPLE 0 SAMPLE 1 SAMPLE 2 SAMPLE 3 SYNCP/N T0530-01 t(ISTR_SYNC) t(ISTR_SYNC) DATACLKP/N (DDR) Sync Option #1 Sync Option #2 C [15:0] A [15:0] C [15:0] A [15:0] C [15:0] A [15:0] C [15:0] A [15:0] D [15:0] B [15:0] D [15:0] B [15:0] D [15:0] B [15:0] D [15:0] B [15:0] DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 DATA INTERFACE The DAC34H84 has a 32-bitLVDS bus thatacceptsquad,16-bitdatainword-wideformat.The quad-16-bitdata can be inputto the deviceusing a dual-bus,16-bitinterface.The bus acceptsLVDS transferratesup to 1.25GSPS which correspondsto a maximum data rateof 625MSPS per data channel.The defaultLVDS bus inputassignmentisshown inTable3. Table3.LVDS Bus InputAssignment Data Paths Pins A and B DAB[15..0] C and D DCD[15..0] Data issampled by theLVDS doubledatarate(DDR) clockDATACLK. Setup and holdrequirementsmust be met forpropersampling.A and C dataarecapturedon therisingedge ofDATACLK. B and D dataarecaptured on thefallingedge ofDATACLK. For bothinputbus modes, a sync signal,eitherISTR or SYNC, isrequiredtosync theFIFO read and/orwrite pointers. The sync signal,eitherISTR or SYNC, can be eithera pulse or a periodicsignalwhere the sync period correspondstomultiplesof8 samples.ISTR orSYNC issampled by a risingedge inDATACLK. The pulse-width t(ISTR_SYNC) needs tobe atleastequalto1/2oftheDATACLK period. DATA FORMAT The 16-bitdataforchannelsA and B isinterleavedintheform A0[15:0],B0[15:0],A1[15:0],B1[15:0],A2[15:0]… intotheDAB[15:0]P/NLVDS inputs.SimilarlydataforchannelsC and D isinterleavedintotheDCD[15:0]P/N LVDS inputs.Data intotheDAC34H84 isformattedaccordingtothediagramshown inFigure51 where index0 isthedataLSB and index15 isthedataMSB. Figure51. Data TransmissionFormat The FIFO read and writepointercan alsobe synced by SIF SYNC as the thirdsync optionifmulti-device synchronizationisnot needed. In thissync mode, the syncsel_fifoin(3:0)and syncsel_fifoout(3:0)in register config32need tobe bothsetto"1000"fortheSIF SYNC option. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLink(s):DAC34H84

DCD[15:0] DAB[15:0] FIFO A Output FIFO B Output Clock Handoff 64-Bit 64-Bit A-Data, 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit B-Data, 16-Bit C-Data, 16-Bit D-Data, 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit Write Pointer Reset Read Pointer Reset FIFO C Output FIFO D Output OSTR B0461-01 syncsel_fifoin syncsel_fifooutS M fifo_offset(2:0) ISTR/ SYNC Input Side Clocked by DATACLK 0 ... 7 Write Pointer 0 ... 7 Read Pointer S (Single Sync Sources Mode): Reset handoff from input side to output side M (Dual Sync Source Mode): OSTR resets read pointer. Allows Multi-DAC synchronization Initial Position Initial Position FIFO: 4 x 16-Bits Wide 8-Samples deep Output Side Clocked by FIFO Out Clock ( )DACCLK/Interpolation Factor Sample 0 Sample 0 Sample 0 Sample 0 Sample 0 Sample 0 Sample 0 Sample 0 DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com INPUT FIFO The DAC34H84 includesa 4-channel,16-bitswide and 8-samplesdeep inputFIFO which actsas an elastic buffer.The purposeoftheFIFO istoabsorbany timingvariationsbetween theinputdataand theinternalDAC datarateclocksuch as theones resultingfromclock-to-datavariationsfromthedatasource. Figure52 shows a simplifiedblockdiagramoftheFIFO. Figure52. DAC34H84 FIFO Block Diagram Data iswrittentothedevice32-bitsata timeon therisingand fallingedges ofDATACLK. Inordertoform a complete64-bitwide sample (16-bitA-data,16-bitB-data,16-bitC-data,and 16-bitD-data)one DATACLK periodisrequired.Each 64-bitwide sample iswrittenintotheFIFO attheaddressindicatedby thewritepointer. Similarly,datafromtheFIFO isreadby theFIFO Out Clock64-bitsata timefromtheaddressindicatedby the read pointer.The FIFO Out Clock isgeneratedinternallyfrom the DACCLK signaland itsrateisequal to DACCLK/Interpolation.Each timea FIFO writeorFIFO readisdone thecorrespondingpointermoves tothenext address. The resetpositionforthe FIFO read and writepointersissetby defaultto addresses0 and 4 as shown in Figure52. Thisoffsetgivesoptimalmargin withinthe FIFO. The defaultread pointerlocationcan be setto anothervalueusingfifo_offset(2:0)inregisterconfig3(address4 by default).Under normal conditionsdata is written-toand read-fromthe FIFO at the same rateand consequentlythe writeand read pointergap remains constant.Ifthe FIFO writeand read ratesare different,the correspondingpointerswillbe cyclingat different speeds whichcouldresultinpointercollision.Under thisconditiontheFIFO attemptstoreadand writedatafrom thesame addressatthesame timewhichwillresultinerrorsand thusmust be avoided. The writepointersync sourceisselectedby syncsel_fifoin(3:0)inregisterconfig32.Inmost applicationseither ISTR or SYNC are used to resetthe writepointer.UnlikeDATA, the sync signalislatchedonlyon the rising edges ofDATACLK. A risingedge on thesyncsignalsourcecausesthepointertoreturntoitsoriginalposition.

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Resets Write Pointer to Position 0 Resets Read Pointer to Position Set by fifo_offset (4 by Default) DATACLKP/N (DDR) ISTRP/N SYNCP/N DACCLKP/N 2x Interpolation OSTRP/N (optionally internal sync from Write Reset) D[15:0]P/N LVDS Pairs (Data Source) LVPECL Pairs (Clock Source) tS(OSTR) tH(DATA) tH(DATA) tH(DATA) tH(OSTR) tS(DATA) tS(DATA) tS(DATA) DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Similarly,thereadpointersync sourceisselectedby syncsel_fifoout(3:0).The writepointersync sourcecan be settoresetthereadpointeras well.Inthiscase,theFIFO Out clockwillrecapturethewritepointersync signal toresetthereadpointer.Thisclockdomain transfer(DATACLK toFIFO Out Clock)resultsinphase ambiguityof the sync signal.Thislimitsthe precisecontrolof the outputtimingand makes fullsynchronizationof multiple devicesdifficult. To alleviatethis,thedeviceoffersthealternativeofresettingtheFIFO read pointerindependentlyofthewrite pointerby using the OSTR signal.The OSTR signalis sampled by DACCLK and must satisfythe timing requirementsinthespecificationstable.Inordertominimizetheskew itisrecommended touse thesame clock distributiondevicesuch as Texas InstrumentsCDCE62005 toprovidetheDACCLK and OSTR signalstoallthe DAC34H84 devicesinthesystem.Swapping thepolarityoftheDACCLK outputswithrespecttotheOSTR ones establishesproperphase relationship. The FIFO pointersresetprocedurecan be done periodicallyor onlyonce duringinitializationas the pointers automaticallyreturnto the initialpositionwhen the FIFO has been filled.To resetthe FIFO periodically,itis necessaryto have the ISTR, SYNC, and OSTR signalsto repeatat multiplesof 8 FIFO samples.To disable FIFO reset,setsyncsel_fifoin(3:0)and syncsel_fifoout(3:0)to“0000”. The frequencylimitationforISTR and SYNC signalsarethefollowing: fsync = fDATACLK /(nx 8)where n = 1,2,… The frequencylimitationfortheOSTR signalisthefollowing: fOSTR = fDAC /(nx interpolationx 8)where n = 1,2,… The frequenciesabove areatmaximum when n = 1.Thisiswhen theISTR,SYNC, orOSTR have a risingedge transitionevery8 FIFO samples.The occurrencecan be made lessfrequentby settingn > 1,forexample,every n × 8 FIFO samples. Figure53. FIFO Writeand Read Descriptions FIFO MODES OF OPERATION The DAC34H84 inputFIFO can be completelybypassed throughregistersconfig0and config32. The register configurationforeach mode isdescribedinTable4. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Register ControlBits config0 fifo_ena config32 syncsel_fifoout(3:0) Table4.FIFO OperationModes config0and config32FIFO Bits FIFO Mode syncsel_fifoout fifo_ena Bit3:sif_sync Bit2:OSTR Bit1:ISTR Bit0:SYNC DualSync Sources 1 0 1 0 0 SingleSync 1 or0 Depends on thesync 1 or0 Depends on the1 0 0Source source syncsource Bypass 0 X X X X DUAL SYNC SOURCES MODE Thisisthe recommended mode of operationforthoseapplicationsthatrequireprecisecontrolof the output timing.InDual Sync Sources mode, theFIFO writeand read pointersare resetindependently.The FIFO write pointerisresetusingthe LVDS ISTR or SYNC signal,and the FIFO read pointerisresetusingthe LVPECL OSTR signal.ThisallowsLVPECL OSTR signalto controlthe phase of the outputforeithera singlechipor multiplechips.Multipledevicescan be fullysynchronizedinthismode. SINGLE SYNC SOURCE MODE In SingleSync Source mode, the FIFO writeand read pointersare resetfrom the same source,eitherLVDS ISTR orLVDS SYNC signal.Thismode has a possibilityofup to2 DAC clocksoffsetbetween themultipleDAC outputs.Applicationsrequiringexactoutputtimingcontrolwillneed Dual Sync Sources mode insteadofSingle Sync SourceMode. A singlerisingedge forFIFO and clockdividersyncisrecommended. Periodicsyncsignalis notrecommended due tothenon-deterministiclatencyofthesyncsignalthroughtheclockdomain transfer. In thismode, thereisa chance forFIFO pointers2 away alarm (orpossibly1 away alarm)to occurat initial setup/syncing.ThisistheresultofSingleSync Sourcemode having0 to3 addresslocationslip,whichiscaused by theasynchronoushandoffofthesync signaloccurringbetween theDATACLK zone and DACCLK zone.The asynchronousrelationshipbetween theclockdomains means therecouldbe a slip(fromnominal)intheREAD and Writepointersatinitialsyncing.For example,withthedefaultprogramming ofFIFO Offsetof4,theactual FIFO Offsetmay be 3,2,or insome instances,1.Pleasenotethatinthismode, thenominaladdresslocation slipis0 withthepossibilitygettinglessforeach increaseinslipamount.Also,theslipdoes notcontinuetooccur as the devicefunctions,but the READ/WRITE pointersmay not be at optimalsettings.In situationof alarm occurrence: 1. AdjusttheFIFO offsetaccordinglyand resynchronizetheFIFO, dataformatter,etcsuch thatthereare no alarmreportedoratleastonly2 away alarmisreported. 2. The FIFO collisionalarmisa warningofthesystem sincetheread and writeprocessesoccuratthesame pointer.However, the FIFO 1 away or 2 away alarms are informationalforthe system designer.The importantthingforthese two alarms is thatthe alarm should not get closerto collisionduringnormal operation.If1 away alarmand alarmcollisionstartstooccur,itisa warningtocheck forsystem errors.The systemshouldhave an interruptoralgorithmtofixtheerrorand resynchronizethealarmappropriately. BYPASS MODE InFIFO bypass mode, theFIFO blockisnotused.As a resulttheinputdataishanded offfromtheDATACLK to theDACCLK domain withoutany compensation.Inthismode therelationshipbetween DATACLK and DACCLK iscriticaland used as a synchronizingmechanism fortheinternallogic.Due tothisconstraintthismode isnot recommended .Inbypassmode thepointershave no effecton thedatapathorhandoff.

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pll_ena Clock Distribution to Digital VCO/ Dividers PLL 16-Bit DACI 16-Bit DACQ B0452-01 DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 CLOCKING MODES The DAC34H84 has a dualclocksetupinwhicha DAC clocksignalisused toclocktheDAC coresand internal digitallogicand a separateDATA clockis used to clockthe inputLVDS receiversand FIFO input.The DAC34H84 DAC clocksignalcan be sourceddirectlyor generatedthroughan on-chiplow-jitterphase-locked loop(PLL). Inthoseapplicationsrequiringextremelylow noiseitisrecommended tobypass thePLL and sourcetheDAC clockdirectlyfrom a high-qualityexternalclocktotheDACCLK input.Inmost applicationssystem clockingcan be simplifiedby using the on-chipPLL to generatethe DAC core clockwhilestillsatisfyingperformance requirements.Inthiscase theDACCLK pinsareused as thereferencefrequencyinputtothePLL. Figure54. Top LevelClock Diagram PLL BYPASS MODE InPLL bypass mode a veryhighqualityclockissourcedtotheDACCLK inputs.Thisclockisused todirectly source the DAC34H84 DAC sample rate clock.This mode gives the device best performance and is recommended forextremelydemanding applications. The bypassmode isselectedby settingthefollowing: 1. pll_enabitinregisterconfig24to“0” tobypassthePLL circuitry. 2. pll_sleepbitinregisterconfig26to“1” toputthePLL and VCO intosleepmode. PLL MODE Inthismode theclockattheDACCLKP/N inputfunctionsas a referenceclocksourcetotheon-chipPLL. The on-chipPLL willthenmultiplythisreferenceclocktosupplya higherfrequencyDAC sample rateclock.Figure55 shows theblockdiagramofthePLL circuit. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLink(s):DAC34H84

N Divider PFD and CP SYNCN DACCLKN External Loop Filter Internal Loop Filter VCO B0453-01 Prescaler M Divider DACCLK REFCLK SYNC_PLL OSTR (Internally Generated) Note: The PLL generates internal OSTR signal. In this mode external LVPECL OSTR signal is not required. If the DAC is configured with PLL enabled with Dual Sync Sources mode, then the PFD frequency has to be the pre- defined OSTR frequency. DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Figure55. PLL Block Diagram The DAC34H84 PLL mode isselectedby settingthefollowing: 1. pll_enabitinregisterconfig24to“1” toroutetothePLL clockpath. 2. pll_sleepbitinregisterconfig26to“0” toenablethePLL and VCO. The outputfrequencyof the VCO isdesignedto be the inthe range from 3.3GHz to 4.0GHz. The prescaler value,pll_p(2:0)inregisterconfig24,shouldbe chosen such thattheproductoftheprescalervalueand DAC sample rateclockiswithintheVCO range.To maintainoptimalPLL loop,thecoarsetunebits,pll_vco(5:0)in registerconfig26,can adjustthe centerfrequencyof the VCO towardsthe productof the prescalervalueand DAC sample rateclock.Figure56 shows a typicalrelationshipbetween coarse tune bitsand VCO center frequency.

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VCO Frequency (MHz) /c40 /c41VCO Frequency MHz 3253Coarse Tune Bits 11.6 /c45/c64 DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Figure56. TypicalPLL/VCO Lock Range vs Coarse Tuning Bits Common wirelessinfrastructurefrequencies(614.4MHz,737.28MHz, 983.04MHz, etc.)are generatedfrom this VCO frequencyinconjunctionwiththepre-scalersettingas shown inTable5. Table5.VCO Operation VCO Frequency (MHz) Pre-ScaleDivider DesiredDACCLK (MHz) pll_p(2:0) 3932.16 8 491.52 111 3686.4 6 614.4 110 3686.4 5 737.28 101 3932.16 4 983.04 100 The M dividerisused todeterminethephase-frequency-detector(PFD) and charge-pump(CP)frequency. Table6.PFD and CP Operation DACCLK Frequency M Divider PDF Update Rate (MHz) pll_m(7:0)(MHz) 491.52 4 122.88 00000100 491.52 8 61.44 00001000 491.52 16 30.72 00010000 491.52 32 15.36 00100000 The N dividerintheloopallowsthePFD tooperateata lowerfrequencythanthereferenceclock.Both M and N dividerscan keep thePFD frequencybelow155 MHz forpeak operation. The overalldivideratioinsidetheloopistheproductofthePre-Scaleand M dividers(P × M) and thefollowing guidelinesshouldbe followed:

The overalldivideratiorangeisfrom24 to480
When theoveralldivideratioislessthan120,theinternalloopfiltercan assurea stableloop
When theoveralldivideratioisgreaterthan120,an externalloopfilterisrequiredtoensureloopstability The singlechargepump currentoptionisselectedby settingpll_cp(1:0)inregisterconfig24to“01”.Ifan external filterisrequired,thefollowingfiltershouldbe connectedtotheLPF pin(A1): Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 49 ProductFolderLink(s):DAC34H84

R = 1 kΩ C1 = 100 nF C2 = 1 nF Clock Generator DATACLKP/N ISTRP/N FPGA DAB[15:0]P/N DCD[15:0]P/N DAB[15:0]P/N DCD[15:0]P/N DATACLKP/N ISTRP/N DACCLKP/N B0454-02 LVPECL Outputs LVDS Interface OSTRP/N LVPECL Outputs DACCLKP/N OSTRP/N PLL/ DLL DAC34H84 DAC1 Delay 1 Delay 2 Outputs are Phase Aligned DAC34H84 DAC2 Variable delays due to variations in the FPGA(s) output paths or board level wiring or temperature/voltage deltas DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Figure57. Recommended ExternalLoop Filter The PLL willgeneratean internalOSTR signaland does not requirethe externalLVPECL OSTR signal.The OSTR signalisbufferedfromtheN-divideroutputinthePLL block,and thefrequencyofthesignalisthesame as thePFD frequency.Therefore,usingPLL withDual Sync Sourcesmode would requirethePFD frequencyto be thepre-definedOSTR frequency.ThiswillallowtheFIFO tobe syncedcorrectlyby theinternalOSTR. MULTI-DEVICE SYNCHRONIZATION In variousapplications,such as multiantenna systems where the varioustransmitchannelsinformationis correlated,itisrequiredthatmultipleDAC devicesarecompletelysynchronizedsuch thattheiroutputsarephase aligned.The DAC34H84 architecturesupportsthismode ofoperation. MULTI-DEVICE SYNCHRONIZATION: PLL BYPASSED WITH DUAL SYNC SOURCES MODE For single-ormulti-devicesynchronizationitisimportantthatdelaydifferencesinthedataareabsorbedby the deviceso thatlatencythroughthedeviceremainsthesame. Furthermore,toensurethattheoutputsfromeach DAC are phase aligneditisnecessarythatdata isread from the FIFO of each devicesimultaneously.In the DAC34H84 thisisaccomplishedby operatingthemultipledevicesinDual Sync Sourcesmode. Inthismode the additionalOSTR signalisrequiredby each DAC34H84 tobe synchronized. Data intothedeviceisinputas LVDS signalsfromone ormultiplebaseband ASICs orFPGAs. Data intomultiple DAC devicescan experiencedifferentdelaysdue tovariationsinthedigitalsourceoutputpathsor board level wiring.These differentdelayscan be effectivelyabsorbedby theDAC34H84 FIFO so thatalloutputsarephase alignedcorrectly. Figure58. SynchronizationSysteminDual Sync Sources Mode withPLL Bypassed

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DACCLKP/N(2) DACCLKP/N(1) OSTRP/N(2) OSTRP/N(1) LVPECL Pairs (DAC34H84 2) LVPECL Pairs (DAC34H84 1) tS(OSTR) tS(OSTR) tSKEW ~ 0 tH(OSTR) tH(OSTR) DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 For correctoperationboth OSTR and DACCLK must be generatedfrom the same clockdomain.The OSTR signalissampled by DACCLK and must satisfythetimingrequirementsinthespecificationstable.Iftheclock generatordoes nothave theabilitytodelaytheDACCLK tomeet theOSTR timingrequirement,thepolarityof theDACCLK outputscan be swapped withrespecttotheOSTR ones tocreate180 degreephase delayofthe DACCLK. Thismay helpestablishpropersetupand holdtimerequirementoftheOSTR signal. Carefulboardlayoutplanningmust be done toensurethattheDACCLK and OSTR signalsaredistributedfrom deviceto devicewiththe lowestskew possibleas thiswillaffectthe synchronizationprocess.In orderto minimizetheskew acrossdevicesitisrecommended touse thesame clockdistributiondevicetoprovidethe DACCLK and OSTR signalstoalltheDAC devicesinthesystem. Figure59. Timing Diagram forLVPECL SynchronizationSignals The followingstepsare requiredtoensurethedevicesare fullysynchronized.The procedureassumes allthe DAC34H84 deviceshave a DACCLK and OSTR signaland must be carriedouton each device. 1. Start-upthedeviceas describedinthepower-upsequence.Set theDAC34H84 inDual Sync Sourcesmode and selectOSTR as theclockdividersyncsource(clkdiv_sync_selinregisterconfig32). 2. Sync theclockdividerand FIFO pointers. 3. Verifythereareno FIFO alarmseitherthroughregisterconfig5orthroughtheALARM pin. 4. Disableclockdividersyncby settingclkdiv_sync_enato“0” inregisterconfig0. AfterthesestepsalltheDAC34H84 outputswillbe synchronized. MULTI-DEVICE SYNCHRONIZATION: PLL ENABLED WITH DUAL SYNC SOURCES MODE The DAC34H84 allowsexactphase alignmentbetween multipledeviceseven when operatingwiththeinternal PLL clockmultiplier.InPLL clockmode, thePLL generatestheDAC clockand an internalOSTR signalfromthe referenceclockappliedtotheDACCLK inputsso thereisno need tosupplyan additionalLVPECL OSTR signal. For thismethod tooperateproperlytheSYNC signalshouldbe settoresetthePLL N dividerstoa known state by settingpll_ndivsync_enainregisterconfig24to“1”.The SYNC signalresetsthePLL N dividerswitha rising edge,and thetimingrelationshipts(SYNC_PLL) and th(SYNC_PLL) arerelativetothereferenceclockpresentedon the DACCLK pin. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 51 ProductFolderLink(s):DAC34H84

DAB[15:0]P/N DCD[15:0]P/N DAB[15:0]P/N DCD[15:0]P/N DATACLKP/N ISTRP/N DACCLKP/N B0455-02 LVDS Interface DACCLKP/N PLL/ DLL DAC34H84 DAC1 Delay 1 Delay 2 Outputs are Phase Aligned DAC34H84 DAC2 Outputs Outputs Variable delays due to variations in the FPGA(s) output paths or board level wiring or temperature/voltage deltas DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Both SYNC and DACCLK can be setas low frequencysignalstogreatlysimplifyingtracerouting(SYNC can be justa pulse as a singlerisingedge is required,ifusing a periodicsignalitis recommended to clearthe pll_ndivsync_enabitafterresettingthe PLL dividers).Besides the ts(SYNC_PLL) and th(SYNC_PLL) requirement between SYNC and DACCLK, thereisno additionalrequiredtimingrelationshipbetween theSYNC and ISTR signalsorbetween DACCLK and DATACLK. The onlyrestrictionas inthePLL disabledcase isthattheDACCLK and SYNC signalsaredistributedfromdevicetodevicewiththelowestskew possible. Figure60. SynchronizationSystem inDual Sync Sources Mode withPLL Enabled The followingstepsare requiredtoensurethedevicesare fullysynchronized.The procedureassumes allthe DAC34H84 deviceshave a DACCLK and OSTR signaland must be carriedouton each device. 1. Start-upthedeviceas describedinthepower-upsequence.Set theDAC34H84 inDual Sync Sourcesmode and enableSYNC toresetthePLL dividers(setpll_ndivsync_enainregisterconfig24to"1"). 2. ResetthePLL dividerswitha risingedge on SYNC. 3. DisablePLL dividersresetting. 4. Sync theclockdividerand FIFO pointers. 5. Verifythereareno FIFO alarmseitherthroughregisterconfig5orthroughtheALARM pin. 6. Disableclockdividersyncby settingclkdiv_sync_enato“0” inregisterconfig0. AfterthesestepsalltheDAC34H84 outputswillbe synchronized. MULTI-DEVICE OPERATION: SINGLE SYNC SOURCE MODE InSingleSync Source mode, theFIFO writeand readpointersareresetfromthesame sync source,eitherISTR or SYNC. Althoughthe FIFO inthismode can stillabsorb the data delaydifferencesdue to variationsinthe digitalsourceoutputpathsorboardlevelwiringitisimpossibletoguaranteedatawillbe readfromtheFIFO of differentdevicessimultaneouslythuspreventingexactphase alignment. InSingleSync Source mode theFIFO readpointerresetishandoffbetween thetwo clockdomains (DATACLK and FIFO OUT CLOCK) by simplyre-samplingthewritepointerreset.Sincethetwo clocksare asynchronous thereisa smallbutdistinctpossibilityofa meta-stablilityduringthepointerhandoff.Thismeta-stabilitycan cause theoutputsofthemultipledevicestoslipby up to2 DAC clockcycles. When the PLL isenabledwithSingleSync Source mode, the FIFO read pointerisnot synchronizedby the OSTR signal.Therefore,thereisno restrictionon thePLL PFD frequencyas describedintheprevioussection.

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0 to 2 DAC Clock CyclesClock Generator DATACLKP/N ISTRP/N FPGA DAB[15:0]P/N DCD[15:0]P/N DAB[15:0]P/N DCD[15:0]P/N DATACLKP/N ISTRP/N DACCLKP/N LVDS Interface DACCLKP/N PLL/ DLL DAC34H84 DAC1 Delay 1 Delay 2 Variable delays due to variations in the FPGA(s) output paths or board level wiring or temperature/voltage deltas DAC34H84 DAC2 DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Figure61. Multi-DeviceOperationinSingleSync Source Mode FIR FILTERS Figure62 throughFigure65 show the magnitude spectrum response forthe FIR0, FIR1, FIR2 and FIR3 interpolatingfilterswhere fIN istheinputdataratetotheFIR filter.Figure66 toFigure69 show thecomposite filterresponsefor2x,4x,8x and 16x interpolation.The transitionband forallinterpolationsettingsisfrom0.4to 0.6 x fDATA (theinputdata rateto the device)with< 0.001dB of pass-band rippleand > 90 dB stop-band attenuation. The DAC34H84 alsohas a 9-tapinversesincfilter(FIR4)thatrunsattheDAC updaterate(fDAC ) thatcan be used toflattenthefrequencyresponseofthesample-and-holdoutput.The DAC sample-and-holdoutputsetsthe outputcurrentand holdsitconstantforone DAC clockcycleuntilthenextsample,resultinginthewell-known sin(x)/xorsinc(x)frequencyresponse(Figure70,redline).The inversesincfilterresponse(Figure70,blueline) has theoppositefrequencyresponsefrom0 to0.4x Fdac,resultinginthecombined response(Figure70,green line).Between 0 to0.4x fDAC ,theinversesincfiltercompensates thesample-and-holdroll-offwithlessthan0.03 dB error. The inversesincfilterhas a gain> 1 atallfrequencies.Therefore,thesignalinputtoFIR4 must be reducedfrom fullscaletopreventsaturationinthefilter.The amount ofback-offrequireddepends on thesignalfrequency,and issetsuch thatatthesignalfrequenciesthecombinationoftheinputsignaland filterresponseislessthan1 (0 dB).Forexample,ifthesignalinputtoFIR4 isat0.25x fDAC ,theresponseofFIR4 is0.9dB,and thesignalmust be backed offfromfullscaleby 0.9dB toavoidsaturation.The gainfunctionintheQMC blockscan be used to reducetheamplitudeoftheinputsignal.The advantageofFIR4 havinga positivegainatallfrequenciesisthat theuseristhenabletooptimizetheback-offofthesignalbased on itsfrequency. The filtertapsforalldigitalfiltersarelistedinTable4.Note thatthelossofsignalamplitudemay resultinlower SNR due todecreaseinsignalamplitude. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 53 ProductFolderLink(s):DAC34H84

–160 –140 –120 –100 –80 –60 –40 –20 f/fIN Magnitude (dB) G048 –160 –140 –120 –100 –80 –60 –40 –20 f/fIN Magnitude (dB) G049 –160 –140 –120 –100 –80 –60 –40 –20 f/fIN Magnitude (dB) G050 –160 –140 –120 –100 –80 –60 –40 –20 f/fIN Magnitude (dB) G051 –160 –140 –120 –100 –80 –60 –40 –20 f/fDATA Magnitude (dB) G052 –160 –140 –120 –100 –80 –60 –40 –20 f/fDATA Magnitude (dB) G053 DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Figure62.Magnitude Spectrum forFIR0 Figure63.Magnitude Spectrum forFIR1 Figure64.Magnitude Spectrum forFIR2 Figure65.Magnitude Spectrum forFIR3 Figure66.2x InterpolationComposite Response Figure67.4x InterpolationComposite Response

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0 0.5 1 1.5 2 2.5 3 3.5 4 –160 –140 –120 –100 –80 –60 –40 –20 f/fDATA Magnitude (dB) G054 0 1 2 3 4 5 6 7 8 –160 –140 –120 –100 –80 –60 –40 –20 f/fDATA Magnitude (dB) G055 f/fDAC Magnitude (dB) G056 sin(x)/x Corrected FIR4 DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Figure68.8x InterpolationComposite Response Figure69.16x InterpolationComposite Response Figure70.Magnitude Spectrum forInverseSinc Filter Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 55 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Table7.FIR FilterCoefficients Non-InterpolatingInterpolatingHalf-bandFilters Inverse-SINCFilter FIR0 FIR1 FIR2 FIR3 FIR4

59 Taps 23 Taps 11 Taps 11 Taps 9 Taps

-19 -19 84 84 -214 -214 -25 -25 13 13 0 0 0 0 0 0 0 0 -50 -50 47 47 -336 -336 1209 1209 150 150 592(1) 0 0 0 0 2048(1) 256(1) -100 -100 1006 1006 0 0 0 0 192 192 -2691 -2691 0 0 0 0 -342 -342 10141 10141 0 0 16384(1) 572 572 0 0 -914 -914 0 0 1409 1409 0 0 -2119 -2119 0 0 3152 3152 0 0 -4729 -4729 0 0 7420 7420 0 0 -13334 -13334 0 0 41527 41527 65536(1) (1) CentertapsarehighlightedinBOLD

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±Fs/4 Mixer Complex Signal Multiplier (AB) Numerically Controlled Oscillator Fixed Fs/8 Oscillator I Data In (A) Q Data In (B) I Data Out (A) Q Data Out (B) CMIX<3> NCO_ENA Frequency Register

32 Accumulator32

syncsel_NCO[3:0] Phase Register

16 Look-Up

ΣΣ fDAC B0026-03 NCO _ CLK NCO 32 freq f f /c180 /c61 DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 COMPLEX SIGNAL MIXER The DAC34H84 has two pathsofcomplex signalmixerblocksthatcontaintwo fullcomplex mixer(FMIX)blocks and power savingcoarsemixer(CMIX)blocks.The signalpathisshown inFigure71. Note: ChannelCD datapathnotshown Figure71. Path ofComplex SignalMixer FULL COMPLEX MIXER The two FMIX blocksoperatewithindependentNumericallyControlledOscillators(NCOs) and enableflexible frequencyplacementwithoutimposingadditionallimitationsin the signalbandwidth.The NCOs have 32-bit frequencyregisters(phaseaddAB(31:0)and phaseaddCD(31:0))and 16-bitphase registers(phaseoffsetAB(15:0) and phaseoffsetCD(15:0))thatgeneratethe sineand cosineterms forthe complex mixing.The NCO block diagramisshown inFigure72. Figure72. NCO Block Diagram SynchronizationoftheNCOs occursby resettingtheNCO accumulatorstozero.The synchronizationsourceis selectedby syncsel_NCO(3:0)inconfig31.The frequencyword inthephaseaddAB(31:0)and phaseaddCD(31:0) registersisadded totheaccumulatorseveryclockcycle,fDAC .The outputfrequencyoftheNCO is: (1) Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 57 ProductFolderLink(s):DAC34H84

I (t)IN I (t)OUT Q (t)IN Q (t)OUT 16 16 cosine sine B0472-01 1616 DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Withthecomplex mixerenabled,thetwo channelsinthemixerpatharetreatedas complex vectorsoftheform IIN(t)+ jQ IN(t).The complexsignalmultiplier(shown inFigure73)willmultiplythecomplexchannelswiththesine and cosinetermsgeneratedby theNCO. The resultingoutput,IOUT (t)+ jQ OUT (t),ofthecomplex signalmultiplier is: IOUT (t)= (IIN(t)cos(2πfNCO t+ δ)– Q IN(t)sin(2πfNCO t+ δ))× 2(mixer_gain– 1) Q OUT (t)= (IIN(t)sin(2πfNCO t+ δ)+ Q IN(t)cos(2πfNCO t+ δ))× 2(mixer_gain– 1) where tisthetimesincethelastresettingoftheNCO accumulator,δ isthephase offsetvalueand mixer_gainis either0 or1.δ isgivenby: δ = 2π × phase_offsetAB/CD(15:0)/216 The mixer_gainoptionallowstheoutputsignalsofthemultipliertoreduceby half(6dB).See MixerGain section fordetails. Figure73. Complex SignalMultiplier COARSE COMPLEX MIXER Inadditiontothefullcomplex mixers,theDAC34H84 alsohas coarsemixerblockscapableofshiftingtheinput signalspectrumby the fixedmixingfrequencies±n×fS/8.Utilizingthe coarsemixerinsteadof the fullmixers lowerspower consumption. The outputofthefs/2,fs/4,and –fs/4mixerblockis: IOUT (t)= I(t)cos(2πfCMIX t)– Q(t)sin(2πfCMIX t) Q OUT (t)= I(t)sin(2πfCMIX t)+ Q(t)cos(2πfCMIX t) Sincethesineand thecosinetermsarea functionoffs/2,fs/4,or–fs/4mixingfrequencies,thepossibleresulting valueofthetermswillonlybe 1,-1,or0.The simplifiedmathematicsallowsthecomplex signalmultipliertobe bypassed in any one of the modes, thus mixer gain isnot available.The fs/2,fs/4,and –fs/4mixer blocks performsmixingthroughnegatingand swappingofI/Qchannelon certainsequence ofsamples.Table8 shows thealgorithmused forthosemixerblocks. Table8.Fs/2,Fs/4,and –Fs/4MixingSequence MODE MIXING SEQUENCE Iout= {+I1,+I2,+I3,+I4…} Normal (mixerbypassed) Qout = {+Q1,+Q2, +Q3, +Q4 …}

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Max output occurs when both sine and cosine are 0.707 cosine sine DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Table8.Fs/2,Fs/4,and –Fs/4MixingSequence (continued) MODE MIXING SEQUENCE Iout= {+I1,-I2,+I3,-I4…} fs/2 Qout = {+Q1,-Q2,+Q3, -Q4…} Iout= {+I1,-Q2,-I3,+Q4 …} fs/4 Qout = {+Q1,+I2,-Q3,-I4…} Iout= {+I1,+Q2, -I3,-Q4…} -fs/4 Qout = {+Q1,-I2,-Q3,+I4…} The fs/8mixercan be enabledalongwithvariouscombinationsoffs/2,fs/4,and –fs/4mixer.Sincethefs/8mixer uses thecomplexsignalmultiplierblockwithfixedfs/8sineand cosineterm,theoutputofthemultiplieris: IOUT (t)= (IIN(t)cos(2πfNCO t+ δ)– Q IN(t)sin(2πfNCO t+ δ))× 2(mixer_gain– 1) Q OUT (t)= (IIN(t)sin(2πfNCO t+ δ)+ Q IN(t)cos(2πfNCO t+ δ))× 2(mixer_gain– 1) where fCMIX isthe fixedmixingfrequencyselectedby cmix(3:0). The mixingcombinationsare describedin Table9.The mixer_gainoptionallowstheoutputsignalsofthemultipliertoreduceby half(6dB).See MixerGain sectionfordetails. Table9.Coarse MixerCombinations Fs/8Mixer Fs/4Mixer Fs/2Mixer –Fs/4Mixercmix(3:0) MixingModecmix(3) cmix(2) cmix(1) cmix(0)

0000 Disabled Disabled Disabled Disabled No mixing

0001 Disabled Disabled Disabled Enabled –Fs/4

0010 Disabled Disabled Enabled Disabled Fs/2

0100 Disabled Enabled Disabled Disabled +Fs/4

1000 Enabled Disabled Disabled Disabled +Fs/8

1010 Enabled Disabled Enabled Disabled –3Fs/8

1100 Enabled Enabled Disabled Disabled +3Fs/8

1110 Enabled Enabled Enabled Disabled –Fs/8

Allothers – – – – Not recommended MIXER GAIN The maximum outputamplitudeout of the complex signalmultiplier(i.e.,FMIX mode or CMIX mode withfs/8 mixer enabled)occurs ifIIN(t)and Q IN(t)are simultaneouslyfullscaleamplitudeand the sine and cosine argumentsareequalto2π x fMIXt+ δ (2N-1)x π/4,where N = 1,2,3,etc.... Figure74. Maximum Output oftheComplex SignalMultiplier With mixer_gain= 1 and both IIN(t)and Q IN(t)are simultaneouslyfullscaleamplitude,the maximum output possibleout of the complex signalmultiplieris0.707 + 0.707 = 1.414 (or3dB).Thisconfigurationcan cause clippingofthesignaland shouldthereforebe used withcaution. Withmixer_gain= 0 inconfig2,themaximum outputpossibleoutofthecomplex signalmultiplieris0.5x (0.707 + 0.707)= 0.707(or-3dB).Thislossinsignalpower isinmost cases undesirable,and itisrecommended that thegainfunctionoftheQMC blockbe used toincreasethesignalby 3 dB tocompensate. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 59 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com REAL CHANNEL UPCONVERSION The mixerintheDAC34H84 treatstheA, B, C, and D inputsare complex inputdataand producesa complex outputformost mixingfrequencies.The realinputdataforeach channelcan be isolatedonlywhen themixing frequencyissettonormalmode orfs/2mode. RefertoTable8 fordetails. QUADRATURE MODULATION CORRECTION (QMC) GAIN AND PHASE CORRECTION The DAC34H84 includesa QuadratureModulatorCorrection(QMC) block.The QMC blocksprovidea mean for changingthegainand phase ofthecomplex signalstocompensate forany Iand Q imbalancespresentinan analogquadraturemodulator.The blockdiagram forthe QMC blockisshown inFigure75. The QMC block contains3 programmableparameters. Registersqmc_gainA/B(10:0)and qmc_gainC/D(10:0)controlstheIand Q pathgainsand isan 11-bitunsigned valuewitha rangeof0 to1.9990and thedefaultgainis1.0000.The implieddecimalpointforthemultiplication isbetween bit9 and bit10. Registerqmc_phaseAB/CD(11:0)controlthephase imbalancebetween Iand Q and are a 12-bitvalueswitha rangeof–0.5toapproximately0.49975.The QMC phase termisnota directphase rotationbuta constantthatis multipliedby each "Q" sample thensummed intothe"I"sample path.Thisisan approximationofa truephase rotationinordertokeep theimplementationsimple. LO feed-throughcan be minimizedby adjustingtheDAC offsetfeaturedescribedbelow.

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Σ B0164-03 I Data In (C) Q Data In (D) I Data Out (C) Q Data Out (D) qmc_gainC[10:0] qmc_gainD[10:0] qmc_phaseCD[11:0] I Data In (A) Q Data In (B) I Data Out (A) Q Data Out (B) qmc_gainA[10:0] qmc_gainB[10:0] qmc_phaseAB[11:0] Σ DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Figure75. QMC Block Diagram OFFSET CORRECTION Registersqmc_offsetA(12:0),qmc_offsetB(12:0),qmc_offsetC(12:0)and qmc_offsetD(12:0)can be used to independentlyadjustthe DC offsetsof each channel.The offsetvaluesare inrepresentedin2s-complement formatwitha rangefrom–4096 to4095. The offsetvalueadds a digitaloffsetto the digitaldata beforedigital-to-analogconversion.Since the offsetis added directlytothedataitmay be necessarytoback offthesignaltopreventsaturation.Both dataand offset valuesareLSB aligned. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 61 ProductFolderLink(s):DAC34H84

qmc_offsetC qmc_offsetA qmc_offsetD qmc_offsetB B0165-03 Σ Σ Σ Σ DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Figure76. DigitalOffsetBlock Diagram GROUP DELAY CORRECTION A complex transmittersystem typicallyisconsistedofa DAC, reconstructionfilternetwork,and I/Qmodulator. Besidesthegainand phase mismatch contribution,therecouldalsobe timingmismatch contributionfrom each components.For instance,thetimingmismatch couldcome from thePCB tracelengthvariationbetween theI and Q channelsand thegroupdelayvariationfromthereconstructionfilter. Thistimingmismatch inthecomplex transmittersystem createsphase mismatch thatvarieslinearlywithrespect to frequency.To compensate forthe I/Q imbalancesdue to thismismatch,the DAC34H84 has group delay correctionblock foreach DAC channel.Each DAC channel can adjustitsdelay throughgrp_delayA(7:0) grp_delayB(7:0)grp_delayC(7:0)and grp_delayD(7:0)inregisterconfig46and config47. The maximum delay ranges from 30ps to 100ps and is dependent on DAC sample clock.Contact TI forspecificapplication information.RefertotheGroup Delayvs Step Code plotsintheTypicalCharacteristicssection.The groupdelay correction,alongwithgain/phasecorrection,can be usefulforcorrectingimbalancesinwide-bandtransmitter system. TEMPERATURE SENSOR The DAC34H84 incorporatesa temperaturesensor blockwhich monitorsthe temperatureby measuring the voltageacross2 transistors.The voltageisconvertedtoan 8-bitdigitalword usinga successive-approximation (SAR) analogtodigitalconversionprocess.The resultisscaled,limitedand formattedas a twos complement valuerepresentingthetemperatureindegreesCelsius. The samplingiscontrolledby theserialinterfacesignalsSDENB and SCLK. Ifthetemperaturesensorisenabled (tsense_sleep= “0” inregisterconfig26)a conversiontakesplaceeach timetheserialportiswrittenorread.The

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DCD[15:0]P/N DAB[15:0]P/N ISTRP/N SYNCP/N T0532-01 DATACLKP/N (DDR) Sync Option #1 Sync Option #2 Pattern 2 [15:0] Pattern 0 [15:0] Pattern 3 [15:0] Pattern 1 [15:0] Pattern 6 [15:0] Pattern 4 [15:0] Pattern 7 [15:0] Pattern 5 [15:0] Pattern 2 [15:0] Pattern 0 [15:0] Pattern 3 [15:0] Pattern 1 [15:0] Pattern 6 [15:0] Pattern 4 [15:0] Pattern 7 [15:0] Pattern 5 [15:0] Start cycle again with optional rising edge of ISTR or SYNC DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 data isonlyread and sentout by the digitalblockwhen the temperaturesensorisread intempdata(7:0)in config6.The conversionuses thefirsteightclocksoftheserialclockas thecaptureand conversionclock,the dataisvalidon thefallingeighthSCLK. The dataisthenclockedoutofthechipon therisingedge oftheninth SCLK. No otherclocksto the chip are necessary forthe temperaturesensor operation.As a resultthe temperaturesensorisenabledeven when thedeviceisinsleepmode. Inorderfortheprocessdescribedabove tooperateproperly,theserialportreadfromconfig6must be done with an SCLK periodofatleast1 μs.Ifthisisnotsatisfiedthetemperaturesensoraccuracyisgreatlyreduced. DATA PATTERN CHECKER The DAC34H84 incorporatesa simplepatterncheckertestinordertodetermineerrorsinthedatainterface.The main cause offailuresissetup/holdtimingissues.The testmode isenabledby assertingiotest_enainregister config1. In testmode the analogoutputsare deactivatedregardlessof the stateof TXENA or sif_texnablein registerconfig3. The datapatternkey used forthetestis8 words longand isspecifiedby thecontentsofiotest_pattern[0:7]in registersconfig37throughconfig44. The data patternkey can be modifiedby changingthe contentsof these registers. The firstword inthetestframe isdeterminedby a risingedge transitioninISTR or SYNC, dependingon the syncsel_fifoin(3:0)settinginconfig32.At thistransition,thepattern0word shouldbe inputtothedataDAB[15:0] pins,and pattern2shouldbe inputtothedataDCD[15:0]pins.Patterns1,4,and 5 ofDAB[15:0]bus and pattern 3, 6, and 7 of DCD[15:0]bus shouldfollowsequentiallyon each edge of DATACLK (risingand falling).The sequence shouldbe repeateduntilthepatterncheckertestisdisabledby settingiotest_enaback to“0”.Itisnot necessarytohave a risingISTR orSYNC edge alignedwitheveryfourDATACLK cycle,justthefirstone tomark thebeginningoftheseries. Figure77. IO PatternChecker Data TransmissionFormat The testmode determinesifthe allthe patternson the two 16-bitLVDS data buses (DAB[15:0]P/Nand DCD[15:0]P/N)were receivedcorrectlyby comparingthereceiveddataagainstthedatapatternkey.Ifany bitsin eitherof the two 16-bitdata buses were receivedincorrectly,the correspondingbitsiniotest_results(15:0)in registerconfig4willbe setto“1” toindicatebiterrorlocation.The usercan check thecorrespondingbitlocation on both 16-bitdata buses and implementthe fixaccordingly.Furthermore,the errorconditionwilltriggerthe alarm_from_iotestbitin registerconfig5to indicatea generalerrorin the data interface.When data pattern checkermode isenabled,thisalarm inregisterconfig5,bit7isthe onlyvalidalarm.Other alarmsinregister config5arenotvalidand can be disregarded. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 63 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com For instance,pattern0isprogrammed tothedefaultof0x7A7A. IfthereceivedPattern0 is0x7A7B, thenbit0 in iotest_results(15:0)willbe setto“1” toindicatean errorinbit0 location.The alarm_from_iotestwillalsobe setto “1” toreportthedatatransfererror.Note thatiotest_results(15:0)does notindicatewhichofthe16-bitbuses has the error.The user needs to check both 16-bitbuses and then narrow down the errorfrom the bitlocation information. The alarmscan be clearedby writing0x0000 to iotest_results(15:0)and “0” to alarm_from_iotestthroughthe serialinterface.The serialinterfacewillread back 0s ifthereare no errorsor ifthe errorsare cleared.The correspondingalarmbitwillremaina “1” iftheerrorsremain. Itisrecommended toenablethepatterncheckerand thenrun thepatternsequence for100 or more complete cyclesbeforeclearingtheiotest_results(15:0)and alarm_from_iotest. Thiswilleliminatethe possibilityof false alarmsgeneratedduringthesetupsequence.

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Pattern 0 ... 7 32-Bit 32-Bit 16-Bit 16-BitDATACLK iotest_results[15] iotest_results[0] B0462-01 alarm_from_iotest Only one edge needed ISTR or SYNC LVDS Drivers Go back to 0 after cycle or new rising edge on ISTR or SYNC Pattern 0 Bit-by-Bit Compare Pattern 1 Bit-by-Bit Compare Pattern 2 Bit-by-Bit Compare Pattern 3 Bit-by-Bit Compare Pattern 4 Bit-by-Bit Compare Pattern 5 Bit-by-Bit Compare Pattern 6 Bit-by-Bit Compare Pattern 7 Bit-by-Bit Compare 8-Bit Input 16-Bit Input 8-Bit Input Bit 15 Results Bit 0 Results

All Bits Results iotest_pattern0 iotest_pattern1 iotest_pattern2 iotest_pattern3 iotest_pattern4 iotest_pattern5 iotest_pattern6 iotest_pattern7 Data Format DAB[15:0] DCD[15:0] DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Figure78. DAC34H84 PatternCheck Block Diagram Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 65 ProductFolderLink(s):DAC34H84

alarm_Aparity alarm_Bparity B0458-02 Parity Block oddeven_parity PARITY DAB[15:0] DCD[15:0] DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com PARITY CHECK TEST The DAC34H84 has a paritycheck testthatenablescontinuousvaliditymonitoringofthedatareceivedby the DAC. Paritycheck testingincombinationwiththedatapatterncheckerofferan excellentsolutionfordetecting boardassemblyissuesdue tomissingpad connections. For theparitycheck test,an extraparitybitisadded tothedatabitstoensurethatthetotalnumber ofsetbits (bitswithvalue1)iseven orodd.Thissimplescheme isused todetectsingleorany otherodd number ofdata transfererrors.ParitytestingisimplementedintheDAC34H84 intwo ways:32-bitparityand dual16-bitparity. 32-BITPARITY Inthe32-bitmode theadditionalparitybitissourcedtotheparityinput(PARITYP/N) forthe32-bitdatatransfer intothe DAB[15:0]P/Nand DCD[15:0]P/Ninputs.Thismode isenabledby settingthe single_parity_enabitin registerconfig1.The inputparityvalueisdefinedtobe thetotalnumber oflogic1s on the33-bitdatabus – the DAB[15:0]P/Ninputs,theDCD[15:0]P/Ninputs,and thePARITYP/N input.Thisvalue,thetotalnumber oflogic 1s,must match theparitytestselectedintheoddeven_paritybitinregisterconfig1. For example,iftheoddeven_paritybitissetto“1” forodd parity,thenthenumber of1s on the33-bitdatabus shouldbe odd. The DAC willcheck the data transferthroughthe parityinput.Ifthe data receivedhas odd number of1s,thentheparityiscorrect.Ifthedatareceivedhas even number of1s,thentheparityisincorrect. The correspondingalarmforparityerrorwillbe setaccordingly. Figure79 shows the simpleXOR structureused to check word parity.Parityistestedindependentlyfordata capturedon bothrisingand fallingedges ofDATACLK (alarm_Aparityand alarm_Bparity,respectively).Testing on bothedges helpsindetermininga possiblesetup/holdissue.Both alarmsarecapturedindividuallyinregister config5. Figure79. DAC34H84 32-BitParityCheck DUAL 16-BITPARITY Inthedual16-bitmode, each 16-bitLVDS databus inputwillbe accompanied by a paritybitforerrorchecking. The DAB[15:0]P/Nand ISTRP/N are one 17-bitdatapath,and theDCD[15:0]P/Nand PARITYP/N are another path.Thismode isenabledby settingthedual_parity_enabitinregisterconfig1.The inputparityvalueisdefined tobe thetotalnumber oflogic1s on each 17-bitdatabus.Thisvalue,thetotalnumber oflogic1s,must match theparitytestselectedintheoddeven_paritybitinregisterconfig1. For example,iftheoddeven_paritybitissetto“1” forodd parity,thenthenumber of1s on each 17-bitdatabus shouldbe odd. The DAC willcheck the data transferthroughthe parityinput.Ifthe data receivedhas odd number of1s,thentheparityiscorrect.Ifthedatareceivedhas even number of1s,thentheparityisincorrect. The correspondingalarmforparityerrorwillbe setaccordingly. Figure80 shows the simpleXOR structureused to check word parity.Parityistestedindependentlyfordata capturedon both risingand fallingedges of DATACLK foreach data path (alarm_Aparity,alarm_Bparity, alarm_Cparity,and alarm_Dparity, respectively).Testingon both edges and both data buses helps in determininga possiblesetup/holdissue.Allofthealarmsarecapturedindividuallyinregisterconfig5.

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alarm_Cparity alarm_Aparity alarm_Dparity alarm_Bparity B0463-01 Parity Block Parity Block oddeven_parity oddeven_parity PARITY ISTR DCD[15:0] DAB[15:0] DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 In thismode the ISTR signalfunctionsas a paritysignaland cannot be used to sync the FIFO pointer simultaneously.Itisrecommended touse theSYNC tosynctheFIFO pointer.IfISTR has tobe used tosyncthe FIFO pointer,the ISTR sync can onlybe possibleupon start-upwhen dual16-bitparityfunctionisdisabled. Once theinitializationisfinished,disabletheFIFO pointersync throughISTR (byconfiguringsyncsel_fifoinand syncsel_fifooutinconfig32)and enablethedual16-bitparityfunctionafterwards. Figure80. DAC34H84 Dual 16-BitParityCheck DAC34H84 ALARM MONITORING The DAC34H84 includesa flexiblesetofalarmmonitoringthatcan be used toalertofa possiblemalfunction scenario.Allthealarmeventscan be accessed eitherthroughtheconfig5registeror throughtheALARM pin. Once an alarmisset,thecorrespondingalarmbitinregisterconfig5must be resetthroughtheserialinterfaceto allowfurthertesting.The setofalarmsincludesthefollowingconditions: Zerocheckalarm

Alarm_from_zerochk.Occurswhen theFIFO writepointerhas an allzerospattern.Sincethewritepointerisa shiftregister,allzeroswillcause theinputpointtobe stuckuntilthenextsync event.When thishappens a synctotheFIFO blockisrequired. FIFO alarms
alarm_from_fifo.Occurswhen thereisa collisionintheFIFO pointersora collisioneventisclose. – alarm_fifo_2away.Pointersarewithintwo addressesofeach other. – alarm_fifo_1away.Pointersarewithinone addressofeach other. – alarm_fifo_collision.Pointersareequaltoeach other. Clockalarms
clock_gone.Occurswhen eithertheDACCLK orDATACLOCK have been stopped. – alarm_dacclk_gone.Occurswhen theDACCLK has been stopped. – alarm_dataclk_gone.Occurswhen theDATACLK has been stopped. Patterncheckeralarm Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 67 ProductFolderLink(s):DAC34H84

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alarm_from_iotest.Occurswhen theinputdatapatterndoes notmatch thepatternkey. PLL alarm
alarm_from_pll.Occurswhen thePLL isoutoflock. Parityalarms
alarm_Aparity:Indualparitymode, alarmindicatinga parityerroron theA word.Insingleparitymode, alarm on the32-bitdatacapturedon therisingedge ofDATACLKP/N.
alarm_Bparity:Indualparitymode, alarmindicatinga parityerroron theB word.Insingleparitymode, alarm on the32-bitdatacapturedon thefallingedge ofDATACLKP/N.
alarm_Cparity:Indualparitymode, alarmindicatinga parityerroron theC word.
alarm_Dparity:Indualparitymode, alarmindicatinga parityerroron theD word. To preventunexpectedDAC outputsfrom propagatingintothe transmitchannelchain,the clockand alarm_ fifo_collisionalarmscan be setinconfig2to shut-offthe DAC outputautomaticallyregardlessof the stateof TXENA orsif_txenable. Alarmmonitoringisimplementedas follows:
Power up thedeviceusingtherecommended power-upsequence.
Clearallthealarmsinconfig5by settingthem tozeros.
Unmask thosealarmsthatwillgeneratea hardwareinterruptthroughtheALARM pininconfig7.
EnableautomaticDAC shut-offinregisterconfig2ifrequired.
Inthecase ofan alarmevent,theALARM pinwilltrigger.IfautomaticDAC shut-offhas been enabledthe DAC outputswillbe disabled.
Read registersconfig5todeterminewhichalarmtriggeredtheALARM pin.
Correcttheerrorconditionand re-synchronizetheFIFO.
Clearthealarmsinconfig5.
Re-readconfig5toensurethealarmeventhas been corrected.
Keep clearingand readingconfig5untilno errorisreported. POWER-UP SEQUENCE The followingstartupsequence isrecommended topower-uptheDAC34H84: 1. SetTXENA low 2. Supplyall1.2V voltages(DACVDD, DIGVDD, CLKVDD and VFUSE) and all3.3V voltages(AVDD, IOVDD, and PLLAVDD). The 1.2V and 3.3V suppliescan be powered up simultaneouslyor inany order.There are no specificrequirementson theramp rateforthesupplies. 3. ProvideallLVPECL inputs:DACCLKP/N and theoptionalOSTRP/N. These inputscan alsobe providedafter theSIF registerprogramming. 4. ToggletheRESETB pinfora minimum 25 ns activelowpulsewidth. 5. Program theSIF registers. 6. Program fuse_sleep(config27,bit<11>)toputtheinternalfusestosleep. 7. FIFO configurationneeded forsynchronization: (a) Program syncsel_fifoin(3:0)(config32,bit<15:12>)toselecttheFIFO inputpointersyncsource. (b) Program syncsel_fifoout(3:0)(config32,bit<11:8>)toselecttheFIFO outputpointersyncsource. (c) Program syncsel_fifo_input(1:0)(config31,bit<3:2>)toselecttheFIFO inputsyncsource. 8. Clockdividerconfigurationneeded forsynchronization: (a) Program clkdiv_sync_sel(config32,bit<0>)toselecttheclockdividersyncsource. (b) Program clkdiv_sync_ena(config0,bit<2>)to"1"toenableclockdividersync. (c) For multi-DACsynchronizationin PLL mode, program pll_ndivsync_ena(config24, bit<11>) to “1” to synchronizethePLL N-divider. 9. ProvideallLVDS inputs(D[15:0]P/N,DCD[15:0]P/N,DATACLKP/N, ISTRP/N, SYNCP/N and PARITYP/N) simultaneously.SynchronizetheFIFO and clockdividerby providingthepulseorperiodicsignalsneeded. (a) For SingleSync Source Mode where eitherISTRP/N or SYNCP/N isused to sync the FIFO, a single

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 risingedge forFIFO and clockdividersync isrecommended. Periodicsync signalisnotrecommended due tothenon-deterministiclatencyofthesyncsignalthroughtheclockdomain transfer. (b) ForDualSync SourcesMode, bothsinglepulseorperiodicsyncsignalscan be used. (c) For multi-DACsynchronizationin PLL mode, the LVDS SYNCP/N signalis used to sync the PLL N-dividerand can be sourcedfromeithertheFPGA/ASIC patterngeneratororclockdistributioncircuitas long as the t(SYNC_PLL) setup and hold timingrequirementismet withrespectto the referenceclock sourceatDACCLKP/N pins.The LVDS SYNCP/N signalcan be providedatthispoint. 10. FIFO and clockdividerconfigurationsafterallthesync signalshave providedtheinitialsync pulsesneeded forsynchronization: (a) For SingleSync Source Mode where theclockdividersync sourceiseitherISTRP/N orSYNCP/N, clock dividersyncingmust be disabledafterDAC34H84 initializationand beforethe data transmissionby settingclkdiv_sync_ena(config0,bit2)to“0”. (b) For Dual Sync SourcesMode, where theclockdividersync sourceisfromtheOSTR signal(eitherfrom externalOSTRP/N orinternalPLL N divideroutput),theclockdividersyncingmay be enabledatalltime. (c) Optionally,topreventaccidentalsyncingoftheFIFO when sendingtheISTRP/N or SYNCP/N pulseto otherdigitalblockssuch as NCO, QMC, etc,disableFIFO syncingby settingsyncsel_fifoin(3:0)and syncsel_fifoout(3:0)to “0000” afterthe FIFO inputand outputpointersare initialized.Ifthe FIFO and sync remain enabled afterinitialization,the ISTRP/N or SYNCP/N pulsemust occur in ways to not disturbtheFIFO operation.RefertotheINPUT FIFO sectionfordetail. (d) DisablePLL N-dividersyncingby settingpll_ndivsync_ena(config24,bit<11>)to"0". 11. Enabletransmitofdataby assertingtheTXENA pinorsetsif_txenableto“1”. 12. At any time,ifany oftheclocks(i.eDATACLK orDACCLK) islostora FIFO collisionalarmisdetected,a completeresynchronizationof the DAC isnecessary.Set TXENABLE low and repeatsteps7 through11. Program theFIFO configurationand clockdividerconfigurationpersteps7 and 8 appropriatelytoacceptthe new syncpulseorpulsesforthesynchronization. EXAMPLE START-UP ROUTINE DEVICE CONFIGURATION fDATA = 491.52MSPS Interpolation= 2x Inputdata= baseband data fOUT = 122.88MHz PLL = Enabled FullMixer= Enabled DualSync SourcesMode PLL CONFIGURATION fREFCLK = 491.52MHz attheDACCLKP/N LVPECL pins fDACCLK = fDATA x Interpolation= 983.04MHz fVCO = 4 x fDACCLK = 3932.16MHz (keepfVCO between 3.3GHz to4GHz) PFD = fOSTR = 30.72MHz N = 16,M = 32,P = 4,singlechargepump NCO CONFIGURATION fNCO = 122.88MHz fNCO_CLK = 983.04MHz Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 69 ProductFolderLink(s):DAC34H84

SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com freq= fNCO x 2^32 /983.04= 536870912 = 0x20000000 phaseaddAB (31:0)orphaseaddCD (31:0)= 0x20000000 NCO SYNC = sif_sync EXAMPLE START-UP SEQUENCE Table10.Example Start-UpSequence Description STEP READ/WRITE ADDRESS VALUE DESCRIPTION

1 N/A N/A N/A SetTXENA Low

2 N/A N/A N/A Power-upthedevice

3 N/A N/A N/A ApplyLVPECL DACCLKP/N forPLL referenceclock

4 N/A N/A N/A ToggleRESETB pin

QMC offsetand correctionenabled,2x int,FIFO enabled,Alarmenabled,5 Write 0x00 0xF19F clockdividersyncenabled,inversesincfilterenabled. 6 Write 0x01 0x040E Singleparityenabled,FIFO alarmsenabled(2away,1 away,and collision). Outputshut-offwhen DACCLK gone,DATACLK gone,and FIFO collision.7 Write 0x02 0x7052 MixerblockwithNCO enabled,twoscomplement. Outputcurrentsetto20mAFS withinternalreferenceand 1.28kohm R BIAS8 Write 0x03 0xA000 resistor. Un-mask FIFO collision,DACCLK-gone, and DATACLK-gone alarmstothe9 Write 0x07 0xD8FF Alarmoutput. Program thedesiredchannelA QMC offsetvalue.(CausesAuto-Syncfor10 Write 0x08 N/A QMC AB-ChannelsOffsetBlock) 11 Write 0x09 N/A Program thedesiredFIFO offsetvalueand channelB QMC offsetvalue. Program thedesiredchannelC QMC offsetvalue.(CausesAuto-Syncfor12 Write 0x0A N/A QMC CD-Channels OffsetBlock) 13 Write 0x0B N/A Program thedesiredchannelD QMC offsetvalue. 14 Write 0x0C N/A Program thedesiredchannelA QMC gainvalue. Coarse mixermode notused.Program thedesiredchannelB QMC gain15 Write 0x0D N/A value. 16 Write 0x0E N/A Program thedesiredchannelB QMC gainvalue. 17 Write 0x0F N/A Program thedesiredchannelC QMC gainvalue. Program thedesiredchannelAB QMC phase value.(CausesAuto-Sync18 Write 0x10 N/A QMC AB-ChannelsCorrectionBlock) Program thedesiredchannelCD QMC phase value.(CausesAuto-Syncfor19 Write 0x11 N/A theQMC CD-Channels CorrectionBlock) Program thedesiredchannelAB NCO phase offsetvalue.(Causes20 Write 0x12 N/A Auto-SyncforChannelAB NCO Mixer) Program thedesiredchannelCD NCO phase offsetvalue.(Causes21 Write 0x13 N/A Auto-SyncforChannelCD NCO Mixer)

22 Write 0x14 0x2000 Program thedesiredchannelAB NCO frequencyvalue

23 Write 0x15 0x0000 Program thedesiredchannelAB NCO frequencyvalue

24 Write 0x16 0x2000 Program thedesiredchannelCD NCO frequencyvalue

25 Write 0x17 0x0000 Program thedesiredchannelCD NCO frequencyvalue

PLL enabled,PLL N-dividerssyncenabled,singlechargepump, prescaler=26 Write 0x18 0x2C67 4.

27 Write 0x19 0x20F4 M = 32,N = 16,PLL VCO biastune= “01”

28 Write 0x1A 0xEC00 PLL VCO coarsetune= 59

29 Write 0x1B 0x0800 Internalreference

QMC offsetAB, QMC offsetCD, QMC correctionAB, and QMC correction30 Write 0x1E 0x9999 CD can be syncedby sif_syncorauto-syncfromregisterwrite MixerAB and CD valuessyncedby SYNCP/N. NCO accumulatorsyncedby31 Write 0x1F 0x4440 SYNCP/N.

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 Table10.Example Start-UpSequence Description(continued) STEP READ/WRITE ADDRESS VALUE DESCRIPTION FIFO InputPointerSync Source= ISTR FIFO OutputPointerSync Source=32 Write 0x20 0x2400 OSTR (fromPLL N-divideroutput)ClockDividerSync Source= OSTR ProvidealltheLVDS DATA and DATACLK Providerisingedge ISTRP/N

33 N/A N/A N/A and risingedge SYNCP/N tosynctheFIFO inputpointerand PLL

N-dividers. Read back pll_lfvolt(2:0).Ifthevalueisnotoptimal,adjustpll_vco(5:0)in34 Read 0x18 N/A 0x1A. 35 Write 0x05 0x0000 Clearallalarmsin0x05. Read back allalarmsin0x05.Check forPLL lock,FIFO collision, 36 Read 0x05 N/A DACCLK-gone, DATACLK-gone, etc.Fixtheerrorappropriately.Repeat step34 and 35 as necessary. Sync alltheQMC blocksusingsif_sync.These blockscan alsobe synced37 Write 0x1F 0x4442 viaauto-syncthroughappropriateregisterwrites. 38 Write 0x00 0xF19B Disableclockdividersync. 39 Write 0x1F 0x4448 Setsif_syncto“0” forthenextsif_syncevent. 40 Write 0x20 0x0000 DisableFIFO inputand outputpointersync. 41 Write 0x18 0x2467 DisablePLL N-dividerssync. 42 N/A N/A N/A SetTXENA high.Enabledatatransmission. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 71 ProductFolderLink(s):DAC34H84

250 Ω 250 Ω 2 kΩ 2 kΩ C 0.1 F AC μ C 0.1 F AC μ Differential ECL or (L V)PECL Source CLKIN CLKINC S0029-02 100 Ω R 150 T Ω R 150 T Ω DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com LVPECL INPUTS Figure81 shows an equivalentcircuitforthe DAC inputclock(DACCLKP/N) and the outputstrobeclock (OSTRP/N). Figure81. DACCLKP/N and OSTRP/N EquivalentInputCircuit Figure82 shows the preferredconfigurationfordrivingthe CLKIN/CLKINC inputclockwith a differential ECL/PECL source. Figure82. PreferredClock InputConfigurationwitha DifferentialECL/PECL Clock Source

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100 Ω LVDS Receiver DAC34H84 GND B0459-02 100 Ω VB VB VA VA 1.4 V 1 V 400 mV 0 V –400 mV V = (V + V )/2 COM A B VA, B VA, B Logical Bit Equivalent Example DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 LVDS INPUTS The DAB[15:0]P/N,DCD[15:0]P/N,DATACLKP/N, SYNCP/N, PARITYP/N, and ISTRP/N LVDS pairshave the inputconfigurationshown inFigure83.Figure84 shows thetypicalinputlevelsand common-move voltageused todrivetheseinputs. Figure83. DAB[15:0]P/N,DCD[15:0]P/N,DATACLKP/N, ISTRP/N,SYNCP/N and PARITYP/N LVDS Input Configuration Figure84. LVDS Data InputLevels Table11.Example LVDS Data InputLevels ResultingDifferential ResultingCommon-ModeAppliedVoltages LogicalBitBinaryVoltage Voltage Equivalent VA VB VA,B VCOM 1.4V 1.0V 400 mV 1 1.2V 1.0V 1.4V -400mV 0 1.2V 0.8V 400 mV 1 1.0V 0.8V 1.2V -400mV 0 Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 73 ProductFolderLink(s):DAC34H84

400 Ω 400 Ω 100 kΩ 100 kΩ GND IOVDD2 IOVDD2 SDENB RESETB Internal Digital In S0027-04 DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com CMOS DIGITAL INPUTS Figure85 shows a schematicoftheequivalentCMOS digitalinputsoftheDAC34H84. SDIO, SCLK, SLEEP and TXENA have pull-downresistorswhileSDENB and RESETB have pull-upresistorsinternaltotheDAC34H84. All theCMOS digitalinputsand outputsarereferredtotheIOVDD2 supply,whichcan varyfrom1.8V to3.3V.This facilitatesthe I/O interfaceand eliminatesthe need of leveltranslation.See the specificationtableforlogic thresholds.The pull-upand pull-downcircuitryisapproximatelyequivalentto100kΩ. Figure85. CMOS DigitalEquivalentInput REFERENCE OPERATION The DAC34H84 uses a bandgap referenceand controlamplifierforbiasingthe full-scaleoutputcurrent.The full-scaleoutputcurrentissetby applyingan externalresistorR BIAS topinBIASJ.The biascurrentIBIAS through resistorR BIAS isdefinedby the on-chipbandgap referencevoltageand controlamplifier.The defaultfull-scale outputcurrentequals64 timesthisbiascurrentand can thusbe expressedas: IOUT FS = 64 x IBIAS = 64 x (VEXTIO /R BIAS )/2 The DAC34H84 has a 4-bitcoarsegaincontrolcoarse_dac(3:0)intheconfig3register.Using gaincontrol,the IOUT FS can be expressedas: IOUT FS = (coarse_dac+ 1)/16x IBIAS x 64 = (coarse_dac+ 1)/16x (VEXTIO /RBIAS) /2 x 64 where VEXTIO isthevoltageatterminalEXTIO. The bandgap referencevoltagedeliversan accuratevoltageof 1.2V.Thisreferenceisactivewhen extref_ena= ‘0’ inconfig27.An externaldecouplingcapacitorC EXT of0.1µF shouldbe connectedexternallytoterminalEXTIO forcompensation.The bandgap referencecan additionallybe used forexternalreferenceoperation.In thatcase,an externalbufferwithhigh impedance inputshouldbe appliedin orderto limitthe bandgap load currentto a maximum of 100 nA. The internalreferencecan be disabledand overriddenby an externalreferenceby settingtheextref_enacontrolbit.CapacitorC EXT may hence be omitted.TerminalEXTIO thusservesas eitherinputoroutputnode. The full-scaleoutputcurrentcan be adjustedfrom30 mA down to10 mA by varyingresistorR BIAS,programming coarse_dac(3:0),orchangingtheexternallyappliedreferencevoltage. NOTE Withinternalreference,theminimum Rbiasresistorvalueis1.28kΩ.Resistorvaluebelow 1.28kΩ isnotrecommended siceitwillprogram thefull-scalecurrenttogo above 30mA and potentiallydamages thedevice. DAC TRANSFER FUNCTION The CMOS DACs consistofa segmented arrayofPMOS currentsources,capableofsourcinga full-scaleoutput currentup to30 mA. Differentialcurrentswitchesdirectthecurrenttoeitherone ofthecomplementaryoutput nodes IOUTP or IOUTN. Complementary outputcurrentsenable differentialoperation,thus cancelingout common mode noisesources(digitalfeed-through,on-chipand PCB noise),dc offsets,even orderdistortion components,and increasingsignaloutputpower by a factoroftwo.

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IOUTP 1:1 IOUTN AGND 50 Ω R 50 Ω LOAD 50 Ω 100 Ω S0517-01 DAC34H84 www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 The full-scaleoutputcurrentissetusingexternalresistorR BIAS incombinationwithan on-chipbandgap voltage referencesource (+1.2V) and controlamplifier.CurrentIBIAS throughresistorR BIAS ismirroredinternallyto providea maximum full-scaleoutputcurrentequalto64 timesIBIAS. The relationbetween IOUTP and IOUTN can be expressedas: IOUT FS = IOUTP + IOUTN We willdenotecurrentflowingintoa node as – currentand currentflowingoutofa node as + current.Sincethe outputstageisa currentsourcethecurrentflowsfrom theIOUTP and IOUTN pins.The outputcurrentflowin each pindrivinga resistiveloadcan be expressedas: IOUTP = IOUT FS x CODE /65536 IOUTN = IOUT FS x (65535– CODE) /65536 where CODE isthedecimalrepresentationoftheDAC datainputword For thecase where IOUTP and IOUTN driveresistorloadsR L directly,thistranslatesintosingleended voltages atIOUTP and IOUTN: VOUTP = IOUT1 x R L VOUTN = IOUT2 x R L Assuming thatthedataisfullscale(65535 inoffsetbinarynotation)and theR L is25 Ω,thedifferentialvoltage between pinsIOUTP and IOUTN can be expressedas: VOUTP = 20mA x 25 Ω = 0.5V VOUTN = 0mA x 25 Ω = 0 V VDIFF = VOUTP – VOUTN = 0.5V Note thatcareshouldbe takennottoexceed thecompliancevoltagesatnode IOUTP and IOUTN, whichwould leadtoincreasedsignaldistortion. ANALOG CURRENT OUTPUTS The DAC34H84 can be easilyconfiguredtodrivea doublyterminated50 Ω cableusinga properlyselectedRF transformer.Figure86 and Figure87 show the50 Ω doublyterminatedtransformerconfigurationwith1:1and 4:1 impedance ratio,respectively.Note thatthecentertapoftheprimaryinputofthetransformerhas tobe grounded to enable a DC currentflow.Applyinga 20 mA full-scaleoutputcurrentwould lead to a 0.5 Vpp fora 1:1 transformerand a 1 Vpp outputfora 4:1transformer.The low dc-impedancebetween IOUTP orIOUTN and the transformercentertap setsthe centerof the ac-signalto GND, so the 1 Vpp outputforthe 4:1 transformer resultsinan outputbetween –0.5V and +0.5V. Figure86. Drivinga Doubly Terminated50 Ω Cable Using a 1:1Impedance RatioTransformer Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 75 ProductFolderLink(s):DAC34H84

IOUTP 4:1 IOUTN AGND 100 Ω R 50 Ω LOAD 100 Ω S0518-01 DAC34H84 SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011 www.ti.com Figure87. Drivinga Doubly Terminated50 Ω Cable Using a 4:1Impedance RatioTransformer PACKAGE OPTION ADDENDUM ORDERABLE PACKAGE PACKAGE LEAD/BALL MSL PEAKSTATUS PINS ECO PLANDEVICE TYPE QUANTITY FINISH TEMPERATURE Green (RoHS & noDAC34H84IZAY Active NFBGA 196 800 SNAGCU MSL3 260CSb/Br) Green (RoHS & noDAC34H84IZAYR Active NFBGA 196 1000 SNAGCU MSL3 260CSb/Br)

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www.ti.com SLAS751B –MARCH 2011–REVISED SEPTEMBER 2011

REVISION HISTORY

Changes from Original(March 2011)toRevisionA Page Changes from RevisionA (June 2011)toRevisionB Page

www.ti.com 27-Jul-2011 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) DAC34H84IZAY ACTIVE NFBGA ZAY 196 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR DAC34H84IZAYR ACTIVE NFBGA ZAY 196 1000 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR PDAC34H84IZAY PREVIEW NFBGA ZAY 196 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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Product Information

DAC34H84IZAYR specifications and overview.

Summary

Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

Description

Quad-Channel, 16-Bit, 1.25 GSPS Digital-to-Analog Converter (DAC)

Source title DAC34H84IZAYR Datasheet(PDF) - Texas Instruments

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DAC34H84_1109 TI1 | Alldatasheet

Document overview

Technical content

8 Sample FIFO

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1 LSB = IOUT FS /216

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001110 DACA AVSS 0V

010110 DACB AVSS 0V

011110 DACC AVSS 0V

100110 DACD AVSS 0V

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0 OSTR

1 ISTR,SYNC, orSIF SYNC, based on syncsel_fifoin

15 DACA sleep

14 DACB sleep

13 DACC sleep

12 DACD sleep

11 Clockreceiversleep

10 PLL sleep

9 LVDS datasleep

8 LVDS controlsleep

7 Temp sensorsleep

5 Biasamplifiersleep

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59 Taps 23 Taps 11 Taps 11 Taps 9 Taps

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32 Accumulator32

16 Look-Up

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0000 Disabled Disabled Disabled Disabled No mixing

0001 Disabled Disabled Disabled Enabled –Fs/4

0010 Disabled Disabled Enabled Disabled Fs/2

0100 Disabled Enabled Disabled Disabled +Fs/4

1000 Enabled Disabled Disabled Disabled +Fs/8

1010 Enabled Disabled Enabled Disabled –3Fs/8

1100 Enabled Enabled Disabled Disabled +3Fs/8

1110 Enabled Enabled Enabled Disabled –Fs/8

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1 N/A N/A N/A SetTXENA Low

2 N/A N/A N/A Power-upthedevice

3 N/A N/A N/A ApplyLVPECL DACCLKP/N forPLL referenceclock

4 N/A N/A N/A ToggleRESETB pin

22 Write 0x14 0x2000 Program thedesiredchannelAB NCO frequencyvalue

23 Write 0x15 0x0000 Program thedesiredchannelAB NCO frequencyvalue

24 Write 0x16 0x2000 Program thedesiredchannelCD NCO frequencyvalue

25 Write 0x17 0x0000 Program thedesiredchannelCD NCO frequencyvalue

27 Write 0x19 0x20F4 M = 32,N = 16,PLL VCO biastune= “01”

28 Write 0x1A 0xEC00 PLL VCO coarsetune= 59

29 Write 0x1B 0x0800 Internalreference

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