DAC3484IZAY.A

DAC3484 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 108

Technical content

(32-bit NCO) xN xN Complex Mixer (32-bit NCO) xN xN 16-Bit LVDS Input Data Bus RF RF LVDS Interface Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community Reference Design DAC3484 SLAS749E – MARCH 2011– REVISED NOVEMBER 2015 DAC3484Quad-Channel,16-Bit,1.25GSPSDigital-to-AnalogConverter(DAC)

1 Features 3 Description

The DAC3484 is a very low power, high dynamic 1• Very Low Power: 1.27 W at 1.25 GSPS, Full range, quad-channel, 16-bit digital-to-analogOperating Conditions converter (DAC) with a sample rate as high as 1.25• Multi-DAC Synchronization GSPS.

• Selectable 2x, 4x, 8x, 16x Interpolation Filter The device includes features that simplify the design– Stop-Band Attenuation > 90 dBc of complex transmit architectures: 2x to 16x digital interpolation filters with over 90dB of stop-band• Flexible On-chip Complex Mixing attenuation simplify the data interface and– Two Independent Fine Mixers with 32-Bit reconstruction filters. Independent complex mixersNCOs allow flexible carrier placement. A high-performance– Power Saving Coarse Mixers: ± n×Fs/8 low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic• High Performance, Low Jitter Clock Multiplying range. The digital Quadrature Modulator CorrectionPLL (QMC) enables complete IQ compensation for gain,• Digital I and Q Correction offset, phase and group delay between channels in– Gain, Phase, Offset, and Group Delay direct up-conversion applications. Correction Digital data is input to the device through a 16-bit• Digital Inverse Sinc Filter LVDS data bus with on-chip termination. The device
• Flexible 16-Bit LVDS Input Data Bus includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows– 8 Sample Input FIFO full synchronization of multiple devices.– Data Pattern Checker The device is characterized for operation over the– Parity Check entire industrial temperature range of –40°C to 85°C– GC5330 Compatible and is available in a very-small 88-pin 9x9mm WQFN
• Temperature Sensor package or 196-ball 12x12mm NFBGA package.
• Differential Scalable Output: 10 mA to 30 mA Very low power, small size, superior crosstalk, high
• Multiple Package Options: 88-Pin 9x9mm WQFN dynamic range and features of the DAC3484 are an and 196-Ball 12mmx12mm NFBGA (GREEN / Pb- ideal fit for systems with multiple transmit channels. Free) Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM)2 Applications WQFN (88) 9.00 mm x 9.00 mm• Cellular Base Stations DAC3484 NFBGA (196) 12.00 mm x 12.00 mm• Diversity Transmit (1) For all available packages, see the orderable addendum at• Wideband Communications the end of the data sheet. Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SLAS749E – MARCH 2011– REVISED NOVEMBER 2015 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (September 2015) to Revision E Page Changes from Revision C (August 2012) to Revision D Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
• Added additional operation requirement for SLEEP pin if SLEEP pin is set to logic HIGH before and during device
• Added additional operation requirement for SLEEP pin if SLEEP pin is set to logic HIGH before and during device
• Changed the parameter name Single-Ended Swing Level to Single-Ended Input Level to better reflect the
• Changed the parameter name Single-Ended Swing Level to Single-Ended Input Level to better reflect the
• Changed syncsel_fifoout(3:0) description in Input FIFO section to clarify the FIFO read pointer reset capture method

2 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Product Folder Links: DAC3484

www.ti.com SLAS749E –MARCH 2011– REVISED NOVEMBER 2015

• Added the effect of bypassing the FIFO in the Bypass Mode section to clarify the operation of the FIFO, LVDS
• Changed information to Multi-Device Operation: Single Sync Source mode section to clarify the latency limitation of
• Changed the NCO setting description in the Example Start-up Sequence Section to reflect the example register writes. 64 Changes from Revision B (February) to Revision C Page Changes from Revision A (July 2011) to Revision B Page Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DAC3484

SLAS749E – MARCH 2011– REVISED NOVEMBER 2015 www.ti.com

• Changed +3.75 to –3.75 degrees in 1024 steps to +26.5 to –26.5 degrees in 4096 steps in GAIN AND PHASE Changes from Original (March 2011) to Revision A Page

4 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Product Folder Links: DAC3484

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 A33 A32 A31 A30 A29 A28 A27 A26 A25 A24 A23 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 A44 A43 A42 A41 A40 A39 A38 A37 A36 A35 A34 B40 B39 B38 B37 B36 B35 B34 B33 B32 B31 C2 C3 OSTRN OSTRP SYNCP CLKVDD DACCLKN DACCLKP VFUSE PLLAVDD LPF D15N D15P D13P DIGVDD D14N D14P IOVDD DIGVDD SYNCN D12N D12P D13N D9PD10N DATACLKP D8ND8PD9ND10PD11ND11P D7P FRAMEN D5PD6ND6PD7N FRAMEP IOVDD DATACLKN D4ND4PD5N SCLK ALARM PARITYN SDO SDIO SDENB TXENABLE RESETB BIASJ D0P D0N D2N DIGVDD D1P D1N IOVDD DIGVDD PARITYP D3P D3N D2P AVDDIOUTAP AVDDIOUTBNAVDDIOUTANDACVDDSLEEPTESTMODE IOUTCNAVDD IOUTDPAVDDIOUTDNAVDDIOUTCPDACVDDIOUTBP EXTIOAVDDDACVDD DAC3484 88-WQFN 9mm x 9mm P0133-02 DAC3484 www.ti.com SLAS749E –MARCH 2011– REVISED NOVEMBER 2015

5 Pin Configuration and Functions

NAME NO. A36, A37, A38, A40,AVDD I Analog supply voltage. (3.3 V)A41, A42, B31 CMOS output for ALARM condition. The ALARM output functionality is defined through the config7 ALARM B29 O register. Default polarity is active high, but can be changed to active low via config0 alarm_out_pol control bit. Full-scale output current bias. For 30-mA full-scale output current, connect 1.28 kΩ to ground.BIASJ A33 O Change the full-scale output current through coarse_dac(3:0) in config3, bit<15:12> Internal clock buffer supply voltage. (1.2 V)CLKVDD A4 I It is recommended to isolate this supply from DIGVDD and DACVDD. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DAC3484

SLAS749E – MARCH 2011– REVISED NOVEMBER 2015 www.ti.com Pin Functions - WQFN (continued) PIN I/O DESCRIPTION NAME NO. A7, A8, B9, LVDS positive input data bits 0 through 15. Internal 100-Ω termination resistor. Data format relative to B10, A12, DATACLKP/N clock is Double Data Rate (DDR). A13, A14, D15P is most significant data bit (MSB)A15, B17,D[15..0]P I D0P is least significant data bit (LSB)B18, B19, B20, A23, A24, B23, The order of the bus can be reversed via config2 revbus bit. B24 B7, B8, A10, A11, B11, B12, B13, B14, A19,D[15..0]N I LVDS negative input data bits 0 through 15. (See D[15:0]P description above)A20, A21, A22, B21, B22, A26, A27 DACCLKP A3 I Positive external LVPECL clock input for DAC core with a self-bias. DACCLKN B3 I Complementary external LVPECL clock input for DAC core. (see the DACCLKP description) A35, A39, DAC core supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD andDACVDD IA43 DIGVDD. LVDS positive input data clock. Internal 100 Ω termination resistor. Input data D[15:0]P/N is latchedDATACLKP A16 I on both edges of DATACLKP/N (Double Data Rate). DATACLKN B15 I LVDS negative input data clock. (See DATACLKP description) A6, A9, A25,DIGVDD I Digital supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD and DACVDD.A28 Used as external reference input when internal reference is disabled through config27 extref_ena = EXTIO A34 I/O 1b. Used as internal reference output when config27 extref_ena = 0b (default). Requires a 0.1-µF decoupling capacitor to AGND when used as reference output. LVDS frame indicator positive input. Internal 100-Ω termination resistor. The main functions of this input are to reset the FIFO pointer or to be used as a syncing source. These two functions are captured with the rising edge of DATACLKP/N. The signal captured by theFRAMEP B16 I falling edge of DATACLKP/N can be used as a block parity bit. The FRAMEP/N signal should be edge-aligned with D[15:0]P/N. Additionally it is used to indicate the beginning of the frame. FRAMEN A18 I LVDS frame indicator negative input. (See the FRAMEP description) C1, C2, C3, GND C4, Thermal I These pins are ground for all supplies. Pad IOUTAP B39 O A-Channel DAC current output. Connect directly to ground if unused. IOUTAN B38 O A-Channel DAC complementary current output. Connect directly to ground if unused. IOUTBP B36 O B-Channel DAC current output. Connect directly to ground if unused. IOUTBN B37 O B-Channel DAC complementary current output. Connect directly to ground if unused. IOUTCP B35 O C-Channel DAC current output. Connect directly to ground if unused. IOUTCN B34 O C-Channel DAC complementary current output. Connect directly to ground if unused. IOUTDP B32 O D-Channel DAC current output. Connect directly to ground if unused. IOUTDN B33 O D-Channel DAC complementary current output. Connect directly to ground if unused. IOVDD B6, A17, B25 I Supply voltage for all digital I/O. (3.3 V) LPF A1 I/O PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin can be left unconnected. LVPECL output strobe positive input. This positive/negative pair is captured with the rising edge ofOSTRP A2 I DACCLKP/N. It is used for multiple DAC synchronization. If unused it can be left unconnected. OSTRN B2 I LVPECL output strobe negative input. (See the OSTRP description) Optional LVDS positive input parity bit. The PARITYP/N LVDS pair has an internal 100 Ω terminationPARITYP B26 I resistor. If unused it can be left unconnected. PARITYN A29 I Optional LVDS negative input parity bit. PLLAVDD B1 I PLL analog supply voltage. (3.3 V)

6 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Product Folder Links: DAC3484

www.ti.com SLAS749E –MARCH 2011– REVISED NOVEMBER 2015 Pin Functions - WQFN (continued) PIN I/O DESCRIPTION NAME NO. SCLK A31 I Serial interface clock. Internal pull-down. SDENB B28 I Active low serial data enable, always an input to the DAC3484. Internal pull-up. Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional 4-pin mode. InternalSDIO A30 I/O pull-down. Uni-directional serial interface data in 4-pin mode. The SDO pin is tri-stated in 3-pin interface modeSDO B27 O (default). Active high asynchronous hardware power-down input. Internal pull-down. If SLEEP pin is set to logic SLEEP B40 I HIGH before and during device power-up and initialization, the fuse_sleep bit in register 0x1B, bit 11 must be written after register 0x23 during device initialization register setup. Optional LVDS SYNC positive input. The SYNCP/N LVDS pair has an internal 100-Ω terminationSYNCP A5 I resistor. If unused it can be left unconnected. SYNCN B5 I Optional LVDS SYNC negative input. Active low input for chip RESET, which resets all the programming registers to their default state.RESETB B30 I Internal pull-up. Transmit enable active high input. Internal pull-down. To enable analog output data transmission, set sif_txenable in register config3 to 1b or pull CMOS TXENABLE A32 I TXENABLE pin to high. To disable analog output, set sif_txenable to 0b and pull CMOS TXENABLE pin to low. The DAC output is forced to midscale. TESTMODE A44 I This pin is used for factory testing. Internal pull-down. Leave unconnected for normal operation. Digital supply voltage. This supply pin is also used for factory fuse programming. Connect toVFUSE B4 I DACVDD for normal operation. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: DAC3484

GND GND GND GND GND GND GND GND GND GND GND GND PLL AVDD LPF GND GND EXTIO BIASJ GND N/C GND ALARM SDO AVDD AVDD AVDD AVDD AVDD AVDD N/C RESET B SDENBAVDD DAC VDD DAC VDD DAC VDD DAC VDD DAC VDD DAC VDD AVDD GND TX ENABLE SCLKDAC VDD DAC VDDGND GND GND DAC VDD DAC VDD GND PLL AVDD N/C GND GND GND GND N/C SDIO GND GND GND GND GND GND GND GND GND VFUSE DIG VDDGND GND GND DIG VDD N/C GNDGND GND GND N/C N/C N/C N/C GND IO VDD DIG VDD GND GNDGND GND DIG VDD IO VDD GND N/C N/C GND IO VDD DIG VDD DIG VDD IO VDD IO VDD DIG VDD DIG VDD IO VDD GND PARITY P PARITY N N/C N/C N/C N/C D11P D10P D11N D10N N/C N/C N/C N/C D9P D8P D9N D8N N/C N/C N/C N/C N/C N/C N/C N/C D7P D6P D7N D6N N/C N/C N/C N/C D5P D4P D5N D4N D0P D0N D1P D1N D2P D2N D3P D3N DA T A CLKP DA T A CLKN FRAME P FRAME N A B C D E F G H J K L M N P DAC Output Clock Input Sync/Parity Input Data Input CMOS Pins N/C 3.3V Supply Ground P0134-02 CLK VDD 1.2V Supply (except for IOVDD2) DAC3484 SLAS749E – MARCH 2011– REVISED NOVEMBER 2015 www.ti.com 196-Pin NFBGA Top View

8 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Product Folder Links: DAC3484

www.ti.com SLAS749E –MARCH 2011– REVISED NOVEMBER 2015 Pin Functions - NFBGA PIN I/O DESCRIPTION NAME NO. D10, E11, F11, G11,AVDD I Analog supply voltage. (3.3 V)H11, J11, K11, L10 CMOS output for ALARM condition. The ALARM output functionality is defined through the ALARM N12 O config7 register. Default polarity is active low, but can be changed to active high via config0 alarm_out_pol control bit. Full-scale output current bias. For 30-mA full-scale output current, connect 1.28 kΩ to BIASJ H12 O ground. Change the full-scale output current through coarse_dac(3:0) in config3, bit<15:12> Internal clock buffer supply voltage. (1.2 V)CLKVDD C12 I It is recommended to isolate this supply from DIGVDD and DACVDD. LVDS positive input data bits 0 through 15. Internal 100-Ω termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR).N4, N3, N2, N1, M2, L2, D15P is most significant data bit (MSB)D[15..0]P K2, J2, F2, E2, D2, C2, I A1, A2, A3, A4 D0P is least significant data bit (LSB) The order of the bus can be reversed via config2 revbus bit. P4, P3, P2, P1, M1, L1, D[15..0]N K1, J1, F1, E1, D1, C1, I LVDS negative input data bits 0 through 15. (See D[15:0]P description above) B1, B2, B3, B4 DACCLKP A12 I Positive external LVPECL clock input for DAC core with a self-bias. Complementary external LVPECL clock input for DAC core. (see the DACCLKPDACCLKN A11 I description) D9, E9, E10, F10, G10, DAC core supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDDDACVDD IH10, J10, K9, K10, L9 and DIGVDD. LVDS positive input data clock. Internal 100-Ω termination resistor. Input data D[15:0]P/NDATACLKP G2 I is latched on both edges of DATACLKP/N (Double Data Rate). DATACLKN G1 I LVDS negative input data clock. (See DATACLKP description) E5, E6, E7, F5, J5, K5, Digital supply voltage. (1.2 V). It is recommended to isolate this supply from CLKVDD andDIGVDD IK6, K7 DACVDD. Used as external reference input when internal reference is disabled through config27 extref_ena = 1b. Used as internal reference output when config27 extref_ena = 0bEXTIO G12 I/O (default). Requires a 0.1-µF decoupling capacitor to AGND when used as reference output. LVDS frame indicator positive input. Internal 100-Ω termination resistor. The main functions of this input are to reset the FIFO pointer or to be used as a syncing source. These two functions are captured with the rising edge of DATACLKP/N. The signalFRAMEP H2 I captured by the falling edge of DATACLKP/N can be used as a block parity bit. The FRAMEP/N signal should be edge-aligned with D[15:0]P/N. Additionally it is used to indicate the beginning of the frame. FRAMEN H1 I LVDS frame indicator negative input. (See the FRAMEP description) A10, A13, A14, B10, B11, B12, B13, C5, C6, C7, C8, C9, C10, C13, D8, D13, D14, E8, E12, E13, F6, F7, F8, F9, F12, F13, G6, G7, G8, GND G9, G13, G14, H6, H7, I These pins are ground for all supplies. H8, H9, H13, H14, J6, J7, J8, J9, J12, J13, K8, K13, L8, L13, L14, M5, M6, M7, M8, M9, M10, M11, M12, M13, N13, P13, P14 IOUTAP B14 O A-Channel DAC current output. Connect directly to ground if unused. IOUTAN C14 O A-Channel DAC complementary current output. Connect directly to ground if unused. IOUTBP F14 O B-Channel DAC current output. Connect directly to ground if unused. IOUTBN E14 O B-Channel DAC complementary current output. Connect directly to ground if unused. IOUTCP J14 O C-Channel DAC current output. Connect directly to ground if unused. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DAC3484

SLAS749E – MARCH 2011– REVISED NOVEMBER 2015 www.ti.com Pin Functions - NFBGA (continued) PIN I/O DESCRIPTION NAME NO. IOUTCN K14 O C-Channel DAC complementary current output. Connect directly to ground if unused. IOUTDP N14 O D-Channel DAC current output. Connect directly to ground if unused. IOUTDN M14 O D-Channel DAC complementary current output. Connect directly to ground if unused. IOVDD D5, D6, G5, H5, L5, L6 I Supply voltage for all digital I/O. (3.3 V) PLL loop filter connection. If not using the clock multiplying PLL, the LPF pin can be leftLPF D12 I unconnected. LVPECL output strobe positive input. This positive/negative pair is captured with the rising OSTRP A9 I edge of DACCLKP/N. It is used for multiple DAC synchronization. If unused it can be left unconnected. OSTRN B9 I LVPECL output strobe negative input. (See the OSTRP description) Optional LVDS positive input parity bit. The PARITYP/N LVDS pair has an internal 100-ΩPARITYP N5 I termination resistor. If unused it can be left unconnected. PARITYN P5 I Optional LVDS negative input parity bit. PLLAVDD C11, D11 I PLL analog supply voltage. (3.3 V) SCLK P9 I Serial interface clock. Internal pull-down. SDENB P10 I Active low serial data enable, always an input to the DAC3484. Internal pull-up. Serial interface data. Bi-directional in 3-pin mode (default) and 4-pin mode. Internal pull-SDIO P11 I/O down. Uni-directional serial interface data in 4-pin mode. The SDO pin is three-stated in 3-pinSDO P12 O interface mode (default). Active high asynchronous hardware power-down input. Internal pull-down. If SLEEP pin is set to logic HIGH before and during device power-up and initialization, the fuse_sleep bitSLEEP B8 I in register 0x1B, bit 11 must be written after register 0x23 during device initialization register setup. Optional LVDS SYNC positive input. The SYNCP/N LVDS pair has an internal 100-ΩSYNCP A5 I termination resistor. If unused it can be left unconnected. SYNCN B5 I LVDS SYNC negative input. Active low input for chip RESET, which resets all the programming registers to their defaultRESETB N10 I state. Internal pull-up. Transmit enable active high input. Internal pull-down. To enable analog output data transmission, set sif_txenable in register config3 to 1b or TXENABLE N9 I pull CMOS TXENABLE pin to high. To disable analog output, set sif_txenable to 0b and pull CMOS TXENABLE pin to low. The DAC output is forced to midscale. This pin is used for factory testing. Internal pull-down. Leave unconnected for normalTESTMODE A8 O operation. Digital supply voltage. This supply pin is also used for factory fuse programming. ConnectVFUSE D7 I to DACVDD for normal operation.

10 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Product Folder Links: DAC3484

www.ti.com SLAS749E –MARCH 2011– REVISED NOVEMBER 2015

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT DACVDD, DIGVDD, CLKVDD –0.5 1.5 V VFUSE –0.5 1.5 VSupply voltage range(2) IOVDD –0.5 4 V AVDD, PLLAVDD –0.5 4 V D[15..0]P/N, DATACLKP/N, FRAMEP/N, PARITYP/N, SYNCP/N –0.5 IOVDD + 0.5 V DACCLKP/N, OSTRP/N –0.5 CLKVDD + 0.5 V ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TESTMODE, –0.5 IOVDD + 0.5 VTXENABLEPin voltage range(2) IOUTAP/N, IOUTBP/N, IOUTCP/N, IOUTDP/N –1.0 AVDD + 0.5 V EXTIO, BIASJ –0.5 AVDD + 0.5 V LPF 0.5 PLLAVDD+0.5V V Peak input current (any input) 20 mA Peak total input current (all inputs) –30 mA Operating free-air temperature range, TA: DAC3484 –40 85 °C Absolute maximum junction temperature, TJ 150 °C Storage temperature range –65 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions”is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Measured with respect to GND.

6.2 ESD Ratings

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22- ±500C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Recommended operating junction temperature 105 TJ °C Maximum rated operating junction temperature(1) 125 TA Recommended free-air temperature –40 25 85 °C (1) Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DAC3484

SLAS749E – MARCH 2011– REVISED NOVEMBER 2015 www.ti.com

6.4 Thermal Information

RKD ZAYTHERMAL METRIC(1) UNIT(WQFN-MR) (NFBGA)

88 PINS 196 BALLS

RθJA Junction-to-ambient thermal resistance 22.1 37.6 °C/W RθJCtop Junction-to-case (top) thermal resistance 7.1 6.8 °C/W RθJCbot Junction-to-case (bottom) thermal resistance 0.6 N/A °C/W θJB Junction-to-board thermal resistance 4.7 16.8 °C/W ψJT Junction-to-top characterization parameter 0.1 0.2 °C/W ψJB Junction-to-board characterization parameter 4.6 16.4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics – DC Specifications(1)

over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 16 Bits DC ACCURACY DNL Differential nonlinearity ±2 LSB

1 LSB = IOUTFS/216

INL Integral nonlinearity ±4 LSB ANALOG OUTPUT Coarse gain linearity ±0.04 LSB Offset error Mid code offset ±0.001 %FSR With external reference ±2 %FSR Gain error With internal reference ±2 %FSR Gain mismatch With internal reference ±2 %FSR Full scale output current 10 20 30 mA Output compliance range –0.5 0.6 V Output resistance 300 kΩ Output capacitance 5 pF REFERENCE OUTPUT VREF Reference output voltage 1.2 V Reference output current(2) 100 nA REFERENCE INPUT VEXTIO Input voltage range 0.6 1.2 1.25 V External Reference Mode Input resistance 1 MΩ Small signal bandwidth 472 kHz Input capacitance 100 pF TEMPERATURE COEFFICIENTS Offset drift ±1 ppm/°C with external reference ±15 ppm/°C Gain drift with internal reference ±30 ppm/°C Reference voltage drift ±8 ppm/°C (1) Measured differentially across IOUTP/N with 25 Ω each to GND. (2) Use an external buffer amplifier with high impedance input to drive any external load.

12 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Product Folder Links: DAC3484

www.ti.com SLAS749E –MARCH 2011– REVISED NOVEMBER 2015 Electrical Characteristics – DC Specifications(1) (continued) over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY(3) AVDD, IOVDD, PLLAVDD All Conditions 3.14 3.3 3.46 V DIGVDD All Conditions 1.14 1.2 1.32 V FDAC Sampling Rate ≤ 1.25 GSPS, PLL OFF 1.14 1.2 1.32FDAC Sampling Rate ≤ 1 GSPS, PLL ONCLKVDD, DACVDD V FDAC Sampling Rate > 1 GSPS, PLL ON 1.25 1.29 1.32 PSRR Power Supply Rejection Ratio DC tested ±0.2 %FSR/V POWER CONSUMPTION I(AVDD) Analog supply current(4) 123 135 mA MODE 1I(DIGVDD) Digital supply current 595 650 mA fDAC = 1.25 GSPS, 4x interpolation, Mixer on,I(DACVDD) DAC supply current 35 50 mAQMC on, invsinc on, PLL enabled, 20-mA FS I(CLKVDD) Clock supply current 90 100 mAoutput, IF = 200 MHz P Power dissipation 1270 1320 mW I(AVDD) Analog supply current(4) 107 mA MODE 2I(DIGVDD) Digital supply current 595 mA fDAC = 1.25 GSPS, 4x interpolation, Mixer on,I(DACVDD) DAC supply current 38 mAQMC on, invsinc on, PLL disabled, 20-mA FS I(CLKVDD) Clock supply current 71 mAoutput, IF = 200 MHz P Power dissipation 1198 mW I(AVDD) Analog supply current(4) 107 mA MODE 3I(DIGVDD) Digital supply current 282 mA fDAC = 625 MSPS, 2x interpolation, Mixer on,I(DACVDD) DAC supply current 20 mAQMC on, invsinc off, PLL disabled, 20-mA FS I(CLKVDD) Clock supply current 41 mAoutput, IF = 200 MHz P Power dissipation 765 mW I(AVDD) Analog supply current(4) 35 mA MODE 4I(DIGVDD) Digital supply current 595 mA fDAC = 1.25 GSPS, 4x interpolation, Mixer on,I(DACVDD) DAC supply current 38 mAQMC on, invsinc on, PLL enabled, Channels I(CLKVDD) Clock supply current 90 mAA/B/C/D output sleep, IF = 200 MHz, P Power dissipation 984 mW I(AVDD) Analog supply current(4) 20 mA Mode 5I(DIGVDD) Digital supply current 10 mAPower-Down mode: No clock, I(DACVDD) DAC supply current 4 mADAC on sleep mode (clock receiver sleep), Channels A/B/C/D output sleep, static dataI(CLKVDD) Clock supply current 10 mApattern P Power Dissipation 95 mW I(AVDD) Analog supply current(4) 107 mA Mode 6I(DIGVDD) Digital supply current 333 mA fDAC = 1 GSPS, 8x interpolation, Mixer off,I(DACVDD) DAC supply current 35 mAQMC on, invsinc off, PLL enabled, 20-mA FS I(CLKVDD) Clock supply current 60 mAoutput, IF = 200 MHz P Power dissipation 867 mW I(AVDD) Analog supply current(4) 123 mA Mode 7I(DIGVDD) Digital supply current 323 mA fDAC = 737.28 MSPS, 4x interpolation, Mixer on,I(DACVDD) DAC supply current 23 mAQMC on, invsinc off, PLL enabled, 20-mA FS I(CLKVDD) Clock supply current 69 mAoutput, IF = 150 MHz P Power dissipation 904 mW (3) To ensure power supply accuracy and to account for power supply filter network loss at operating conditions, the use of the ATEST function in register config27 to check the internal power supply nodes is recommended. (4) Includes AVDD, PLLAVDD, and IOVDD Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: DAC3484

SLAS749E – MARCH 2011– REVISED NOVEMBER 2015 www.ti.com

6.6 Electrical Characteristics – Digital Specifications

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVDS INPUTS: D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N, PARITYP/N(1) Logic high differential inputVA,B+ 200 mVvoltage threshold Logic low differential inputVA,B– –200 mVvoltage threshold VCOM Input Common Mode 1.0 1.2 1.6 V ZT Internal termination 85 110 135 Ω CL LVDS Input capacitance 2 pF Interleaved LVDS datafINTERL 1250 MSPStransfer rate fDATA Input data rate 312.5 MSPS CLOCK INPUT (DACCLKP/N) Differential voltage(2) |DACCLKP - DACCLKN| 0.4 0.8 V Internally biased common- 0.2 Vmode voltage Single-ended input level(3) –0.4 V OUTPUT STROBE (OSTRP/N) Differential voltage |OSTRP – OSTRN| 0.4 0.8 V Internally biased common- 0.2 Vmode voltage Single-ended input level(3) –0.4 V CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENABLE VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V IIH High-level input current -40 40 µA IIL Low-level input current -40 40 µA CI CMOS Input capacitance 2 pF IOVDD –Iload = –100 μA V0.2VOH ALARM, SDO, SDIO Iload = –2 mA 0.8 x IOVDD V Iload = 100 μA 0.2 V VOL ALARM, SDO, SDIO Iload = 2 mA 0.5 V (1) See LVDS Inputs section for terminology. (2) Standard high swing LVPECL clock signal should be applied for best performance. (3) Indicates the minimum voltage that can be applied to the DACCLK and OSTR differential pins in single-ended fashion.

14 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Product Folder Links: DAC3484

www.ti.com SLAS749E –MARCH 2011– REVISED NOVEMBER 2015

6.7 Electrical Characteristics – AC Specifications

over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT(1) fDAC Maximum DAC rate 1250 MSPS AC PERFORMANCE(2) fDAC = 1.25 GSPS, fOUT = 20 MHz 82 Spurious free dynamic rangeSFDR fDAC = 1.25 GSPS, fOUT = 50 MHz 77 dBc(0 to fDAC/2) Tone at 0 dBFS fDAC = 1.25 GSPS, fOUT = 70 MHz 72 fDAC = 1.25 MSPS, fOUT = 30 ± 0.5 MHz 81 Third-order two-tone intermodulation distortionIMD3 fDAC = 1.25 GSPS, fOUT = 50 ± 0.5 MHz 79 dBcEach tone at –12 dBFS fDAC = 1.25 GSPS, fOUT = 100 ± 0.5 MHz 77.5 fDAC = 1.25 GSPS, fOUT = 10 MHz 160Noise Spectral DensityNSD dBc/HzTone at 0dBFS fDAC = 1.25 GSPS, fOUT = 80 MHz 155 fDAC = 1.2288 GSPS, fOUT = 30.72 MHz 77 Adjacent channel leakage ratio, single carrier fDAC = 1.2288 GSPS, fOUT = 153.6 MHz 74 ACLR(3) dBc fDAC = 1.2288 GSPS, fOUT = 30.72 MHz 82 Alternate channel leakage ratio, single carrier fDAC = 1.2288 GSPS, fOUT = 153.6 MHz 80 Channel Isolation fDAC = 1.25 GSPS, fOUT = 10 MHz 84 dBc (1) Measured single ended into 50-Ω load. (2) 4:1 transformer output termination, 50 Ω doubly terminated load. (3) Single carrier, W-CDMA with 3.84-MHz BW, 5-MHz spacing, centered at IF, PAR = 12dB. TESTMODEL 1, 10 ms

6.8 Timing Requirements – Digital Specifications

CLOCK INPUT (DACCLKP/N) Duty cycle 40% 60% DACCLKP/N input frequency 1250 MHz OUTPUT STROBE (OSTRP/N) fOSTR = fDACCLK / (n x 8 x Interp) where n is any positive fDACCLK /fOSTR Frequency MHzinteger, fDACCLK is DACCLK frequency in MHz (8 x interp) Duty cycle 50% DIGITAL INPUT TIMING SPECIFICATIONS Timing LVDS inputs: D[15:0]P/N, FRAMEP/N, SYNCP/N, PARITYP/N, double edge latching Config36 Setting datadly clkdly 0 0 150 0 1 100 0 2 50 0 3 0 Setup time, 0 4 -50 FRAMEP/N reset and frame indicatorD[15:0]P/N, 0 5 -100latched on rising edge ofFRAMEP/N, DATACLKP/N.ts(DATA) SYNCP/N and 0 6 -150 PARITYP/N, valid FRAMEP/N parity bit latched on falling 0 7 -200 psto either edge of edge of DATACLKP/N. 1 0 200DATACLKP/N 2 0 250 3 0 300 4 0 350 5 0 400 6 0 450 7 0 500 Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: DAC3484

SLAS749E – MARCH 2011– REVISED NOVEMBER 2015 www.ti.com Timing Requirements – Digital Specifications (continued) MIN NOM MAX UNIT Config36 Setting datadly clkdly 0 0 350 0 1 400 0 2 450 0 3 500 Hold time, 0 4 550 FRAMEP/N reset and frame indicatorD[15:0]P/N, 0 5 600latched on rising edge ofFRAMEP/N, DATACLKP/N.th(DATA) SYNCP/N and 0 6 650 ps PARITYP/N, valid FRAMEP/N parity bit latched on falling 0 7 700after either edge of edge of DATACLKP/N. 1 0 300DATACLKP/N 2 0 250 3 0 200 4 0 150 5 0 100 6 0 50 7 0 0 t(FRAME_SYNC) FRAMEP/N and fDATACLK is DATACLK frequency in MHz 1/2fDATACLK ns SYNCP/N pulse width TIMING OUTPUT STROBE INPUT: DACCLKP/N rising edge LATCHING(1) ts(OSTR) Setup time, OSTRP/N valid to rising edge of DACCLKP/N 0 ps th(OSTR) Hold time, OSTRP/N valid after rising edge of DACCLKP/N 300 ps TIMING SYNC INPUT: DACCLKP/N rising edge LATCHING(2) ts(SYNC_PLL) Setup time, SYNCP/N valid to rising edge of DACCLKP/N 200 ps th(SYNC_PLL) Hold time, SYNCP/N valid after rising edge of DACCLKP/N 300 ps TIMING SERIAL PORT ts(SDENB) Setup time, SDENB to rising edge of SCLK 20 ns ts(SDIO) Setup time, SDIO valid to rising edge of SCLK 10 ns th(SDIO) Hold time, SDIO valid to rising edge of SCLK 5 ns Register config6 read (temperature sensor read) 1 µs t(SCLK) Period of SCLK All other registers 100 ns td(Data) Data output delay after falling edge of SCLK 10 ns tRESET Minimum RESETB pulse width 25 ns (1) OSTR is required in Dual Sync Sources mode. In order to minimize the skew it is recommended to use the same clock distribution device such as Texas Instruments CDCE62005 or LMK0480x family to provide the DACCLK and OSTR signals to all the DAC3484 devices in the system. Swap the polarity of the DACCLK outputs with respect to the OSTR ones to establish proper phase relationship. (2) SYNC is required to synchronize the PLL circuit in multiple devices. The SYNC signal must meet the timing relationship with respect to the reference clock (DACCLKP/N) of the on-chip PLL circuit.

16 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Product Folder Links: DAC3484

www.ti.com SLAS749E –MARCH 2011– REVISED NOVEMBER 2015

6.9 Switching Characteristics – AC Specifications

over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT(1) ts(DAC) Output settling time to 0.1% Transition: Code 0x0000 to 0xFFFF 10 ns DAC outputs are updated on the falling edge of DACtpd Output propagation delay 2 nsclock. Does not include Digital Latency (see below). tr(IOUT) Output rise time 10% to 220 ps 90% tf(IOUT) Output fall time 90% to 220 ps 10% No interpolation, FIFO on, Mixer off, QMC off, Inverse 128 sinc off 2x Interpolation 216 4x Interpolation 376 DAC 8x Interpolation 726Digital latency clock cycles16x Interpolation 1427 Fine mixer 24 QMC 32 Inverse sinc 36 IOUT current settling to 1% of IOUTFS from outputDAC wake-up time 2sleepPower-up µsTime IOUT current settling to less than 1% of IOUTFS inDAC sleep time 2output sleep (1) Measured single ended into 50-Ω load. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: DAC3484

6.10 Typical Characteristics

Figure 1. Integral Nonlinearity Figure 2. Differential Nonlinearity Figure 3. SFDR vs Output Frequency Over Input Scale Figure 4. Second Harmonic Distortion vs Output Frequency Figure 5. Third Harmonic Distortion vs Output Frequency Figure 6. SFDR vs Output Frequency Over Interpolation

18 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Figure 13. Single Tone Spectral Plot Figure 14. IMD3 vs Output Frequency Over Input Scale Figure 15. IMD3 vs Output Frequency Over Interpolation Figure 16. IMD3 vs Output Frequency Over fDAC Figure 17. IMD3 vs Output Frequency Over IOUTFS Figure 18. Two Tone Spectral Plot

20 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Figure 25. Single Carrier WCDMA ACLR (Adjacent) vs Figure 26. Single Carrier WCDMA ACLR (Alternate) vs Figure 27. Single Carrier W-CDMA Test Model 1 Figure 28. Single Carrier W-CDMA Test Model 1 Figure 29. Single Carrier W-CDMA Test Model 1 Figure 30. Four Carrier W-CDMA Test Model 1

22 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Figure 37. Power Consumption vs fDAC Over Interpolation Figure 38. Power Consumption vs fDAC Over Interpolation Figure 39. Power Consumption vs fDAC Over Digital Figure 40. DIGVDD Current vs fDAC Over Interpolation Figure 41. DIGVDD Current vs fDAC Over Interpolation Figure 42. DIGVDD Current vs fDAC Over Digital Processing

24 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Figure 49. IMD3 vs Output Frequency

26 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

www.ti.com SLAS749E –MARCH 2011– REVISED NOVEMBER 2015

7 Detailed Description

7.1 Overview

The DAC3484 includes a quad-channel, 16-bit digital-to-analog converter (DAC) with up to 1.25 GSPS sample rate, a 16-bit LVDS data bus with on-chip termination, FIFO, data pattern checker, and parity test. The device includes 2x to 16x digital interpolation filters with over 90dB of stop-band attenuation, reconstruction filters, independent complex mixers, a low jitter clock multiplier, and digital Quadrature Modulator Correction (QMC). Full synchronization of multiple devices is possible with the DAC3484. It is an ideal device for next generation communication systems. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: DAC3484

8 Sample FIFO

(FMIX or CMIX) AB-QMC Gain and Phase 16-b DACB 16-b DACA IOUTAP IOUTAN IOUTBP IOUTBN QMC B-offset QMC A-offset x2 x2 x2 x2 x2 x2 x2 x2 FIR1FIR0 x sin(x) x sin(x) DAC Gain FIR3FIR2 AB-Channel FIR4 2x–16x Interpolation AB 32-Bit NCO cos sin CMIX Control (±n*Fs/8) 59 taps 23 taps 11 taps 11 taps 9 taps A-Group Delay B-Group Delay Clock Distribution EXTIO BIASJ DACCLKP DACCLKN DATACLKP DATACLKN CLKVDD DIGVDD VFUSE DACVDD LVPECL 100 LVDS Programmable Delay Low Jitter PLL LPF PLLAVDD 1.2-V Reference CD 32-Bit NCO cos sin Complex Mixer (FMIX or CMIX) CD-QMC Gain and Phase 16-b DACD 16-b DACC IOUTCP IOUTCN IOUTDP IOUTDN QMC D-offset QMC C-offset x2 x2 x2 x2 x2 x2 x2 x2 FIR1FIR0 x sin(x) x sin(x) FIR3FIR2 CD-Channel FIR4 59 taps 23 taps 11 taps 11 taps 9 taps C-Group Delay D-Group Delay DAC3484 SLAS749E – MARCH 2011– REVISED NOVEMBER 2015 www.ti.com

7.2 Functional Block Diagram

28 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Product Folder Links: DAC3484

7.3 Feature Description

7.3.1 Serial Interface

with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK. detailed description of each bit. The data transfer cycle consists of two bytes. Table 1. Instruction Byte of the Serial Interface operation from DAC3484 and a low indicates a write operation to DAC3484. [A6 : A0] Identifies the address of the register to be accessed during the read or write operation. clock input to DAC3484. Serial data enable SDENB is an active low input to DAC3484. SDIO is serial data in. Input data to DAC3484 is clocked on the rising edges of SCLK. Figure 50. Serial Interface Write Timing Diagram SCLK until the rising edge of SDENB when they will 3-state.

Figure 51. Serial Interface Read Timing Diagram

7.3.2 Data Interface

bus inputs in each mode are shown in Table 2. Table 2. LVDS Bus Input Assignment For both input bus modes, a sync signal, either FRAME or SYNC, can sync the FIFO read and/or write pointers. In byte-wide mode the sync source is needed to establish the correct sample boundaries. width t(FRAME_SYNC) needs to be at least equal to 1/2 of the DATACLK period.

7.3.2.1 Word-Wide Format

index 0 is the data LSB and index 15 is the data MSB.

30 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Figure 52. Word-wide Data Transmission Format

7.3.2.2 Byte-Wide Format

Figure 53. Byte-wide Data Transmission Format

7.3.3 Input FIFO

data rate clock such as the ones resulting from clock-to-data variations from the data source.

Figure 54. DAC3484 FIFO Block Diagram Figure 54. This offset gives optimal margin within the FIFO. The default read pointer location can be set to the same address at the same time which will result in errors and thus must be avoided. edges of DATACLK. A rising edge on the sync signal source causes the pointer to return to its original position.

32 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

www.ti.com SLAS749E –MARCH 2011– REVISED NOVEMBER 2015 Similarly, the read pointer sync source is selected by syncsel_fifoout(3:0). The write pointer sync source can be set to reset the read pointer as well. In this case, FIFO Out clock will recapture the write pointer sync signal to reset the read pointer. This clock domain transfer (DATACLK to FIFO Out Clock) results in phase ambiguity of the reset signal, and will create latency variation based on the capture edge of the FIFO Out Clock. Since the reset signal also synchronizes the clock divider circuit for the FIFO Out Clock generation, the latency variation also includes the capture edge of the DACCLK cycle in the clock divider stage. Ultimately, the variation in capture edge of both the FIFO Out Clock and the DACCLK limits the precise control of the output timing latency. The full latency control of the DAC will be difficult and is not recommended in this setup. NOTE For full latency control of the DAC, refer to the Dual Sync Source mode section of the data sheet. To alleviate this, the device offers the alternative of resetting the FIFO read pointer independently of the write pointer by using the OSTR signal. The OSTR signal is sampled by DACCLK and must satisfy the timing requirements in the specifications table. In order to minimize the skew it is recommended to use the same clock distribution device such as Texas Instruments CDCE62005 or LMK0480x family to provide the DACCLK and OSTR signals to all the DAC3484 devices in the system. Swapping the polarity of the DACCLK outputs with respect to the OSTR ones establishes proper phase relationship. The FIFO pointers reset procedure can be done periodically or only once during initialization as the pointers automatically return to the initial position when the FIFO has been filled. To reset the FIFO periodically, it is necessary to have the FRAME, SYNC, and OSTR signals to repeat at multiples of 8 FIFO samples. To disable FIFO reset, set syncsel_fifoin(3:0) and syncsel_fifoout(3:0) to 0000b. The frequency limitation for FRAME and SYNC signals are the following: fsync = fDATACLK/(n x 16) where n = 1, 2, … for Word-Wide and Byte-Wide Mode The frequency limitation for the OSTR signal is the following: fOSTR = fDAC/(n x interpolation x 8) where n = 1, 2, … The frequencies above are at maximum when n = 1. This is when the FRAME, SYNC, or OSTR have a rising edge transition every 8 FIFO samples. The occurrence can be made less frequent by setting n > 1, for example, every n × 8 FIFO samples. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Links: DAC3484

Figure 55. FIFO Write and Read Descriptions

7.3.4 FIFO Modes of Operation

configuration for each mode is described in Table 3. Table 3. FIFO Operation Modes

7.3.4.1 Dual Sync Sources Mode

multiple chips. Multiple devices can be fully synchronized in this mode.

34 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

7.3.4.2 Single Sync Source Mode

the sync signal through the clock domain transfer.

7.3.4.3 Bypass Mode

• The FIFO pointers have no effect on the data path or handoff.
• The FIFO will not be able to pass the controls signals from the LVDS FRAME and LVDS SYNC to digital circuits after the FIFO. These digital circuits mainly are quadrature modulation corrections circuits, complex mixer circuits, and numerical controlled oscillator circuits.

7.3.5 Clocking Modes

DAC clock signal can be sourced directly or generated through an on-chip low-jitter phase-locked loop (PLL). requirements. In this case the DACCLK pins are used as the reference frequency input to the PLL. Figure 56. Top Level Clock Diagram

7.3.5.1 PLL Bypass Mode

for extremely demanding applications.

1. pll_ena bit in register config24 to 0b to bypass the PLL circuitry.
2. pll_sleep bit in register config26 to 1b to put the PLL and VCO into sleep mode.

7.3.5.2 PLL Mode

shows the block diagram of the PLL circuit.

external LVPECL OSTR signal is not required. Figure 57. PLL Block Diagram

1. pll_ena bit in register config24 to 1b to route to the PLL clock path.
2. pll_sleep bit in register config26 to 0b to enable the PLL and VCO.

Figure 58. Typical PLL/VCO Lock Range vs Coarse Tuning Bits

36 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

VCO frequency in conjunction with the pre-scaler setting as shown in Table 4. Table 4. VCO Operation The M divider is used to determine the phase-frequency-detector (PFD) and charge-pump (CP) frequency. Table 5. PFD and CP Operation dividers can keep the PFD frequency below 155 MHz for peak operation.

• The overall divide ratio range is from 24 to 480
• When the overall divide ratio is less than 120, the internal loop filter can guarantee a stable loop
• When the overall divide ratio is greater than 120, an external loop filter or double charge pump is required to ensure loop stability The single- and double-charge-pump current option are selected by setting pll_cp in register config24 to 01b and 11b, respectively. When using the double-charge-pump setting, an external loop filter is not required. If an external filter is required, the following filter should be connected to the LPF pin (A1 for RKD package and D12 for ZAY package):

Figure 59. Recommended External Loop Filter pre-defined OSTR frequency. This will allow the FIFO to be synced correctly by the internal OSTR.

7.3.6 FIR Filters

is that the user is then able to optimize the back-off of the signal based on its frequency. SNR due to decrease in signal amplitude. Figure 60. Magnitude Spectrum for FIR0 Figure 61. Magnitude Spectrum for FIR1

38 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Figure 68. Magnitude Spectrum for Inverse Sinc Filter

40 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Table 6. FIR Filter Coefficients

59 TAPS 23 TAPS 11 TAPS 11 TAPS 9 TAPS

32 Accumulator32

16 Look-Up

7.3.7 Complex Signal Mixer

and power saving coarse mixer (CMIX) blocks. The signal path is shown in Figure 69. Figure 69. Path of Complex Signal Mixer

7.3.7.1 Full Complex Mixer

diagram is shown in Figure 70. Figure 70. NCO Block Diagram

42 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Figure 71. Complex Signal Multiplier

7.3.7.2 Coarse Complex Mixer

the algorithm used for those mixer blocks. Table 7. Fs/2, Fs/4, and –Fs/4 Mixing Sequence

Table 7. Fs/2, Fs/4, and –Fs/4 Mixing Sequence (continued) Table 8. The mixer_gain option allows the output signals of the multiplier to reduce by half (6dB). See Mixer Gain Table 8. Coarse Mixer Combinations

0000 Disabled Disabled Disabled Disabled No mixing

0001 Disabled Disabled Disabled Enabled –Fs/4

0010 Disabled Disabled Enabled Disabled Fs/2

0100 Disabled Enabled Disabled Disabled +Fs/4

1000 Enabled Disabled Disabled Disabled +Fs/8

1010 Enabled Disabled Enabled Disabled –3Fs/8

1100 Enabled Enabled Disabled Disabled +3Fs/8

1110 Enabled Enabled Enabled Disabled –Fs/8

7.3.7.3 Mixer Gain

arguments are equal to 2π x fMIXt + δ (2N-1) x π/4, where N = 1, 2, 3, etc.... Figure 72. Maximum Output of the Complex Signal Multiplier clipping of the signal and should therefore be used with caution. the gain function of the QMC block be used to increase the signal by 3dB to compensate.

44 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

www.ti.com SLAS749E –MARCH 2011– REVISED NOVEMBER 2015

7.3.7.4 Real Channel Upconversion

The mixer in the DAC34H84 treats the A, B, C, and D inputs are complex input data and produces a complex output for most mixing frequencies. The real input data for each channel can be isolated only when the mixing frequency is set to normal mode or fs/2 mode. Refer to Table 7 for details.

7.3.8 Quadrature Modulation Correction (QMC)

7.3.8.1 Gain and Phase Correction

The DAC3484 includes a Quadrature Modulator Correction (QMC) block. The QMC blocks provide a mean for changing the gain and phase of the complex signals to compensate for any I and Q imbalances present in an analog quadrature modulator. The block diagram for the QMC block is shown in Figure 73. The QMC block contains 3 programmable parameters. Register qmc_gainA/B(10:0) and qmc_gainC/D(10:0) controls the I and Q path gains and is an 11-bit unsigned value with a range of 0 to 1.9990 and the default gain is 1.0000. The implied decimal point for the multiplication is between bit 9 and bit 10. Register qmc_phaseAB/CD(11:0) control the phase imbalance between I and Q and is a 12-bit values with a range of –0.5 to approximately 0.49975. The QMC phase term is not a direct phase rotation but a constant that is multiplied by each "Q" sample then summed into the "I" sample path. This is an approximation of a true phase rotation in order to keep the implementation simple. The corresponding phase rotation corresponds to approximately +26.5 to –26.5 degrees in 4096 steps. LO feed-through can be minimized by adjusting the DAC offset feature described below. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 45 Product Folder Links: DAC3484

Figure 73. QMC Block Diagram

7.3.8.2 Offset Correction

format with a range from -4096 to 4095.

46 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Figure 74. Digital Offset Block Diagram

7.3.8.3 Group Delay Correction

A complex transmitter system typically is consisted of DACs, reconstruction filter network, and I/Q modulator. and Q channels and the group delay variation from the reconstruction filter. specific application information.

7.3.9 Temperature Sensor

value representing the temperature in degrees Celsius.

temperature sensor is enabled even when the device is in sleep mode. an SCLK period of at least 1 μs. If this is not satisfied the temperature sensor accuracy is greatly reduced.

7.3.10 Data Pattern Checker

syncsel_fifoin(4:0) setting in config32. At this transition, the pattern0 word should be input to the data pins. Figure 75. IO Pattern Checker Data Transmission Format 7 is the only valid alarm. Other alarms in register config5 are not valid and can be disregarded. implement the fix accordingly.

48 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

www.ti.com SLAS749E –MARCH 2011– REVISED NOVEMBER 2015 The alarms can be cleared by writing 0x0000 to iotest_results(15:0) and 0b to alarm_from_iotest through the serial interface. The serial interface will read back 0s if there are no errors or if the errors are cleared. The corresponding alarm bit will remain a 1b if the errors remain. It is recommended to enable the pattern checker and then run the pattern sequence for 100 or more complete cycles before clearing the iotest_results(15:0) and alarm_from_iotest. This will eliminate the possibility of false alarms generated during the setup sequence. Based on the pattern test result, the user can adjust the data source output timing, PCB traces delay, or DAC3484 CONFIG36 LVDS Programmable delay to help optimize the setup and hold time of the transmitter system. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 49 Product Folder Links: DAC3484

• All Bits Results iotest_pattern0 iotest_pattern1 iotest_pattern2 iotest_pattern3 iotest_pattern4 iotest_pattern5 iotest_pattern6 iotest_pattern7 Data Format DAC3484 SLAS749E – MARCH 2011– REVISED NOVEMBER 2015 www.ti.com

Figure 76. DAC3484 Pattern Check Block Diagram

50 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

7.3.11 Parity Check Test

board assembly issues due to missing pad connections. transfer errors. Parity testing is implemented in the DAC3484 in two ways: word-by-word parity and block parity.

7.3.11.1 Word-by-Word Parity

parity test selected in the oddeven_parity bit in register config1. number of 1s, then the parity is correct. If the data received has even number of 1s, then the parity is incorrect. The corresponding alarm for parity error will be set accordingly. Figure 77. DAC3484 Word-by-Word Parity Check

7.3.11.2 Block Parity

The block parity method uses the FRAME signal to determine the boundaries of the data block to compute parity. This mode is enabled by setting the frame_parity_ena bit in register config1. FRAME value captured on the DATACLK falling edge right after the STOP/START point. is that there is no need for an additional parity LVDS input.

Notes: Rising edge of FRAMEP/N indicates the beginning of data block. Parity bit for the current data block is latched on falling edge of DATACLK after the start point for next data block. Figure 78. DAC3484 Block Parity Check (Example shown with Word Wide Mode)

7.3.12 DAC3484 Alarm Monitoring

scenario. All the alarm events can be accessed either through the config5 register or through the ALARM pin.

• Alarm_from_zerochk. Occurs when the FIFO write pointer has an all zeros pattern. Since the write pointer is a shift register, all zeros will cause the input pointer to be stuck until the next sync event. When this happens a sync to the FIFO block is required. FIFO alarms
• alarm_from_fifo. Occurs when there is a collision in the FIFO pointers or a collision event is close. – alarm_fifo_2away. Pointers are within two addresses of each other. – alarm_fifo_1away. Pointers are within one address of each other. – alarm_fifo_collision. Pointers are equal to each other. Clock alarms
• clock_gone. Occurs when either the DACCLK or DATACLOCK have been stopped. – alarm_dacclk_gone. Occurs when the DACCLK has been stopped. – alarm_dataclk_gone. Occurs when the DATACLK has been stopped. Pattern checker alarm
• alarm_from_iotest. Occurs when the input data pattern does not match the pattern key. PLL alarm
• alarm_from_pll. Occurs when the PLL is out of lock. Parity alarms
• alarm_rparity. Occurs when there is a parity error in the data captured by the rising edge of DATACLKP/N. The PARITYP/N input is the parity bit (word-by-word parity test).
• alarm_fparity. Occurs when there is a parity error in the data captured by the falling edge of DATACLKP/N. The PARITYP/N input is the parity bit (word-by-word parity test).
• alarm_frame_parity_err. Occurs when there is a frame parity error when using the FRAME as the parity bit (block parity test).

52 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

• Power up the device using the recommended power-up sequence.
• Clear all the alarms in config5 by setting them to 0.
• Unmask those alarms that will generate a hardware interrupt through the ALARM pin in config7.
• Enable automatic DAC shut-off in register config2 if required.
• In the case of an alarm event, the ALARM pin will trigger. If automatic DAC shut-off has been enabled the DAC outputs will be disabled.
• Read registers config5 to determine which alarm triggered the ALARM pin.
• Correct the error condition and re-synchronize the FIFO.
• Clear the alarms in config5.
• Re-read config5 to ensure the alarm event has been corrected.
• Keep clearing and reading config5 until no error is reported. For details of alarm monitoring function and behavior, refer to SLAA585.

7.3.13 LVPECL Inputs

Figure 79. DACCLKP/N and OSTRP/N Equivalent Input Circuit

NOTE: Actual RT value depends on differential clock driver output termination recommendation. It is driver type dependent. Figure 80. Preferred Clock Input Configuration with a Differential ECL/PECL Clock Source

7.3.14 LVDS Inputs

Figure 81. D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N and PARITYP/N LVDS Input Configuration Figure 82. LVDS Data Input Levels

54 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

x M Unused LVDS Ports Connected in Parallel. x Keep Positive Terminals at 1.2V. x Keep Static Differential Voltages above 100mV. Table 9. Example LVDS Data Input Levels

7.3.15 Unused LVDS Port Termination

with the unused LVDS data port with adjustments to the RSET resistor value. Characteristic – Digital Specifications Table for detail of LVDS Input requirements. Figure 83. Unused LVDS Ports Connected to Static Logic High Differential Voltage

1. Connect the positive terminals of unused LVDS ports in parallel to DIGVDD supply at 1.2 V nominal. For

instance, connect SYNC and PARITY positive pins together to DIGVDD.

1. Connect the negative terminals of unused LVDS ports in parallel to a RSET resistor to ground.
2. The REQ value is the equivalent, parallel resistance of the on-chip termination for all the unused LVDS ports.
3. With Ohm’s Law, the following equation describes the relationship between RSET and REQ.

1. With REQ of two parallel, 135 Ω ZT (or 67.5 Ω equivalent), RSET is 332 Ω with standard 1% resistor value. IEQ

is approximately 3 mA. The expected voltage at negative terminals of LVDS ports is approximately 1.0 V. The differential LVDS voltage is 200 mV.

1. With same RSET of 332 Ω, if the REQ has dropped to two parallel, 85 Ω ZT (or 42.5 Ω equivalent), IEQ is

LVDS port will register a logic HIGH value for the data.

7.3.16 CMOS Digital Inputs

TXENABLE have pull-down resistors while SDENB and RESETB have pull-up resistors internal to the DAC3484. Figure 84. CMOS Digital Equivalent Input

7.3.17 Reference Operation

be omitted. Terminal EXTIO thus serves as either input or output node. the externally applied reference voltage.

56 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

www.ti.com SLAS749E –MARCH 2011– REVISED NOVEMBER 2015 NOTE With internal reference, the minimum Rbias resistor value is 1.28 kΩ. Resistor value below 1.28 kΩ is not recommended since it will program the full-scale current to go above 30mA and potentially damages the device.

7.3.18 DAC Transfer Function

The CMOS DACs consist of a segmented array of PMOS current sources, capable of sourcing a full-scale output current up to 30 mA. Differential current switches direct the current to either one of the complementary output nodes IOUTP or IOUTN. Complementary output currents enable differential operation, thus canceling out common mode noise sources (digital feed-through, on-chip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by a factor of two. The full-scale output current is set using external resistor RBIAS in combination with an on-chip bandgap voltage reference source (+1.2 V) and control amplifier. Current IBIAS through resistor RBIAS is mirrored internally to provide a maximum full-scale output current equal to 64 times IBIAS. The relation between IOUTP and IOUTN can be expressed as: IOUTFS = IOUTP + IOUTN We will denote current flowing into a node as – current and current flowing out of a node as + current. Since the output stage is a current source the current flows from the IOUTP and IOUTN pins. The output current flow in each pin driving a resistive load can be expressed as: IOUTP = IOUTFS x CODE / 65536 IOUTN = IOUTFS x (65535 – CODE) / 65536 where CODE is the decimal representation of the DAC data input word For the case where IOUTP and IOUTN drive resistor loads RL directly, this translates into single ended voltages at IOUTP and IOUTN: VOUTP = IOUT1 x RL VOUTN = IOUT2 x RL Assuming that the data is full scale (65535 in offset binary notation) and the RL is 25 Ω, the differential voltage between pins IOUTP and IOUTN can be expressed as: VOUTP = 20mA x 25 Ω = 0.5 V VOUTN = 0mA x 25 Ω = 0 V VDIFF = VOUTP – VOUTN = 0.5V Note that care should be taken not to exceed the compliance voltages at node IOUTP and IOUTN, which would lead to increased signal distortion.

7.3.19 Analog Current Outputs

The DAC3484 can be easily configured to drive a doubly terminated 50-Ω cable using a properly selected RF transformer. Figure 85 and Figure 86 show the 50-Ω doubly terminated transformer configuration with 1:1 and 4:1 impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be grounded to enable a DC current flow. Applying a 20-mA full-scale output current would lead to a 0.5 Vpp for a 1:1 transformer and a 1 Vpp output for a 4:1 transformer. The low dc-impedance between IOUTP or IOUTN and the transformer center tap sets the center of the ac-signal to GND, so the 1 Vpp output for the 4:1 transformer results in an output between –0.5 V and 0.5 V. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 57 Product Folder Links: DAC3484

Figure 85. Driving a Doubly terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer Figure 86. Driving a Doubly Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer

7.4 Device Functional Modes

7.4.1 Multi-Device Synchronization

aligned. The DAC3484 architecture supports this mode of operation.

7.4.1.1 Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode

the additional OSTR signal is required by each DAC3484 to be synchronized.

58 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Figure 87. SynchronizationSystem in Dual Sync Sources Mode with PLL Bypassed DACCLK. This may help establish proper setup and hold time requirement of the OSTR signal. DACCLK and OSTR signals to all the DAC devices in the system.

Figure 88. Timing Diagram for LVPECL Synchronization Signals DAC3484 devices have a DACCLK and OSTR signal and must be carried out on each device.

1. Start-up the device as described in the power-up sequence. Set the DAC3484 in Dual Sync Sources mode

and select OSTR as the clock divider sync source (clkdiv_sync_sel in register config32).

1. Sync the clock divider and FIFO pointers.
2. Verify there are no FIFO alarms either through register config5 or through the ALARM pin.
3. Disable clock divider sync by setting clkdiv_sync_ena to 0b in register config0.

After these steps all the DAC3484 outputs will be synchronized.

7.4.1.2 Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode

reference clock applied to the DACCLK inputs so there is no need to supply an additional LVPECL OSTR signal. and SYNC signals are distributed from device to device with the lowest skew possible.

60 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Figure 89. Synchronization System in Dual Sync Sources Mode with PLL Enabled

1. Start-up the device as described in the power-up sequence. Set the DAC3484 in Dual Sync Sources mode

and enable SYNC to reset the PLL dividers (set pll_ndivsync_ena in register config24 to 1b).

1. Reset the PLL dividers with a rising edge on SYNC.
2. Disable PLL dividers resetting.
3. Sync the clock divider and FIFO pointers.
4. Verify there are no FIFO alarms either through register config5 or through the ALARM pin.
5. Disable clock divider sync by setting clkdiv_sync_ena to 0b in register config0.

After these steps all the DAC3484 outputs will be synchronized.

7.4.1.3 Multi-Device Operation: Single Sync Source Mode

Out clock cycles and DAC clock cycles. OSTR signal. Therefore, there is no restriction on the PLL PFD frequency as described in the previous section.

Figure 90. Multi-Device Operation in Single Sync Source Mode

7.5 Programming

7.5.1 Power-Up Sequence

1. Supply all 1.2-V voltages (DACVDD, DIGVDD, CLKVDD, and VFUSE) and all 3.3-V voltages (AVDD,

IOVDD, and PLLAVDD). The 1.2-V and 3.3-V supplies can be powered up simultaneously or in any order. There are no specific requirements on the ramp rate for the supplies.

1. Provide all LVPECL inputs: DACCLKP/N and the optional OSTRP/N. These inputs can also be provided after

the SIF register programming.

1. Toggle the RESETB pin for a minimum 25 ns active low pulse width.
2. Program the SIF registers.
3. Program fuse_sleep (config27, bit<11>) to put the internal fuses to sleep. To enable dual channel mode, set

the dual channel DAC3484 (channels B and C active). See the DAC3484 SLAS748 datasheet for details.

1. FIFO configuration needed for synchronization:

(a) Program syncsel_fifoin(3:0) (config32, bits<15:12>) to select the FIFO input pointer sync source. (b) Program syncsel_fifoout(3:0) (config32, bits<11:8>) to select the FIFO output pointer sync source. (c) Program syncsel_dataformatter(1:0) (config31, bits<3:2>) to select the FIFO Data Formatter sync source.

1. Clock divider configuration needed for synchronization:

(a) Program clkdiv_sync_sel (config32, bit<0>) to select the clock divider sync source. (b) Program clkdiv_sync_ena (config0, bit<2>) to 1b to enable clock divider sync. synchronize the PLL N-divider.

1. Provide all LVDS inputs (D[15:0]P/N, DATACLKP/N, FRAMEP/N, SYNCP/N, and PARITYP/N)

simultaneously. Synchronize the FIFO and clock divider by providing the pulse or periodic signals needed.

62 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

www.ti.com SLAS749E –MARCH 2011– REVISED NOVEMBER 2015 Programming (continued) is not recommended due to the non-deterministic latency of the sync signal through the clock domain transfer. (b) For Dual Sync Sources Mode, both single pulse or periodic sync signals can be used. (c) For multi-DAC synchronization in PLL mode, the LVDS SYNCP/N signal is used to sync the PLL N- divider and can be sourced from either the FPGA/ASIC pattern generator or clock distribution circuit as long as the t(SYNC_PLL) setup and hold timing requirement is met with respect to the reference clock source at DACCLKP/N pins. The LVDS SYNCP/N signal can be provided at this point. 10. FIFO and clock divider configurations after all the sync signals have provided the initial sync pulses needed for synchronization: (a) For Single Sync Source Mode where the clock divider sync source is either FRAMEP/N or SYNCP/N, clock divider syncing may be disabled after DAC3484 initialization and before the data transmission by setting clkdiv_sync_ena (config0, bit <2>) to 0b. This is to prevent accidental syncing of the clock divider when sending FRAMEP/N or SYNCP/N pulse to other digital blocks. (b) For Dual Sync Sources Mode, where the clock divider sync source is from the OSTR signal (either from external OSTRP/N or internal PLL N divider output), the clock divider syncing may be enabled at all time. (c) Optionally, to prevent accidental syncing of the FIFO and FIFO data formatter when sending the FRAMEP/N or SYNCP/N pulse to other digital blocks such as NCO, QMC, etc, disable FIFO syncing by setting syncsel_fifoin(3:0) and syncsel_fifoout(3:0) to 0000b after the FIFO input and output pointers are initialized. Also Disable the FIFO data formatter by setting syncsel_dataformatter(1:0) to 10b or 11b. If the FIFO and FIFO data formatter sync remain enabled after initialization, the FRAMEP/N or SYNCP/N pulse must occur in ways to not disturb the FIFO operation. Refer to the INPUT FIFO section for detail. (d) Disable PLL N-divider syncing by setting pll_ndivsync_ena (config24, bit<11>) to 0b. 11. Enable transmit of data by asserting the TXENABLE pin or set sif_txenable to 1b. 12. At any time, if any of the clocks (i.e DATACLK or DACCLK) is lost or a FIFO collision alarm is detected, a complete resynchronization of the DAC is necessary. Set TXENABLE low and repeat steps 7 through 11. Program the FIFO configuration and clock divider configuration per steps 7 and 8 appropriately to accept the new sync pulse or pulses for the synchronization.

7.5.2 Example Start-Up Routine

7.5.2.1 Device Configuration

fDATA = 307.2 MSPS Interpolation = 4x Input data = baseband data fOUT = 122.88 MHz PLL = Enabled Full Mixer = Enabled Dual Sync Sources Mode

7.5.2.2 PLL Configuration

fREFCLK = 614.4 MHz at the DACCLKP/N LVPECL pins fDACCLK = fDATA x Interpolation = 1228.8 MHz fVCO = 3 x fDACCLK = 3686.4 MHz (keep fVCO between 3.3 GHz to 4 GHz) PFD = fOSTR = 38.4 MHz N = 16, M = 32, P = 3, single charge pump pll_vco(5:0) = 100100b (36) Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 63 Product Folder Links: DAC3484

7.5.2.3 NCO Configuration

7.5.2.4 Example Start-Up Sequence

Table 10. Example Start-Up Sequence Description

1 N/A N/A N/A Set TXENABLE Low

2 N/A N/A N/A Power-up the device

3 N/A N/A N/A Apply LVPECL DACCLKP/N for PLL reference clock

4 N/A N/A N/A Toggle RESETB pin

QMC offset and correction enabled, 4x int, FIFO enabled, Alarm enabled,5 Write 0x00 0xF29F clock divider sync enabled, inverse sinc filter enabled. 6 Write 0x01 0x050E Single parity enabled, FIFO alarms enabled (2 away, 1 away, and collision). Output shut-off when DACCLK gone, DATACLK gone, and FIFO collision.7 Write 0x02 0xF052 Mixer block with NCO enabled, twos complement. Word Wide Interface. Output current set to 20mAFS with internal reference and 1.28-kΩ RBIAS8 Write 0x03 0xA000 resistor. Un-mask FIFO collision, DACCLK-gone, and DATACLK-gone alarms to the9 Write 0x07 0xD8FF Alarm output. 11 Write 0x09 N/A Program the desired FIFO offset value and channel B QMC offset value. 13 Write 0x0B N/A Program the desired channel D QMC offset value. 14 Write 0x0C N/A Program the desired channel A QMC gain value. Coarse mixer mode not used. Program the desired channel B QMC gain15 Write 0x0D N/A value. 16 Write 0x0E N/A Program the desired channel C QMC gain value. 17 Write 0x0F N/A Program the desired channel D QMC gain value.

22 Write 0x14 0x999A Program the desired channel AB NCO frequency value

23 Write 0x15 0x1999 Program the desired channel AB NCO frequency value

24 Write 0x16 0x999A Program the desired channel CD NCO frequency value

25 Write 0x17 0x1999 Program the desired channel CD NCO frequency value

PLL enabled, PLL N-dividers sync enabled, single charge pump, prescaler =26 Write 0x18 0x2C58 3.

27 Write 0x19 0x20F4 M = 32, N = 16, PLL VCO bias tune = 01b

64 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Table 10. Example Start-Up Sequence Description (continued)

28 Write 0x1A 0x9000 PLL VCO coarse tune = 36

29 Write 0x1B 0x0800 Internal reference

Mixer AB and CD values synced by SYNCP/N. NCO accumulator synced by31 Write 0x1F 0x4440 SYNCP/N.

33 N/A N/A N/A and rising edge SYNCP/N to sync the FIFO input pointer and PLL N-

Read back pll_lfvolt(2:0). If the value is not optimal, adjust pll_vco(5:0) in34 Read 0x18 N/A 0x1A. 35 Write 0x05 0x0000 Clear all alarms in 0x05. Sync all the QMC blocks using sif_sync. These blocks can also be synced37 Write 0x1F 0x4442 via auto-sync through appropriate register writes. 38 Write 0x00 0xF29B Disable clock divider sync. 39 Write 0x1F 0x4448 Set sif_sync to 0b for the next sif_sync event. 40 Write 0x20 0x0000 Disable FIFO input and output pointer sync. 41 Write 0x18 0x2458 Disable PLL N-dividers sync. 42 N/A N/A N/A Set TXENABLE high. Enable data transmission.

7.6 Register Map

Table 11. Register Map(1) (1) Unless otherwise noted, all reserved registers should be programmed to default values.

66 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Table 11. Register Map(1) (continued)

7.6.1 Register Descriptions

Table 12. Register Name: config0 – Address: 0x00, Default: 0x049C correction for the AB data path is enabled. correction for the CD data path is enabled. Sequence section for more detail.

68 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Table 13. Register Name: config1 – Address: 0x01, Default: 0x050E SLAS748 datasheet for details. effectively change the + and – designations of the LVDS data lines. effectively change the + and – designations of the LVDS data lines. effectively change the + and – designations of the LVDS data lines. effectively change the + and – designations of the LVDS data lines. pointers being 2 away is enabled. pointers being 1 away is enabled. write and read pointers is enabled.

Table 14. Register Name: config2 – Address: 0x02, Default: 0x7000 When cleared, the input interface is set to byte-wide mode. (i.e.Config7, bit <10> and bit <8> must set to 0b). (i.e.Config7, bit <9> and bit <8> must set to 0b). When cleared, the input is expected to be offset-binary. Table 15. Register Name: config3 – Address: 0x03, Default: 0xF000 Table 16. Register Name: config4 – Address: 0x04, Default: No RESET Value (Write to Clear) iotest_results(7:0) correspond to the data bits on D[7:0].

70 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Table 17. Register Name: config5 – Address: 0x05, Default: Setup and Power-Up Conditions Dependent cleared to resume normal operation. the bit must be cleared to resume normal operation. the bit must be cleared to resume normal operation. bits must be cleared to resume normal operation. enabled, this alarm in register config5, bit7 is the only valid alarm. Table 18. Register Name: config6 – Address: 0x06, Default: No RESET Value (Read Only)

Table 19. Register Name: config7 – Address: 0x07, Default: 0xFFFF Table 20. Register Name: config8 – Address: 0x08, Default: 0x0000 (Causes Auto-Sync) the QMC offset registers (config8-config9) into the offset block at the same time. When updating the offset values for AB channel config8 should be written last. Programming config9 will not affect the offset setting. Table 21. Register Name: config9 – Address: 0x09, Default: 0x8000 be helpful in syncing multiple chips or controlling the delay through the device. Table 22. Register Name: config10 – Address: 0x0A, Default: 0x0000 (Causes Auto-Sync) written last. Programming config11 will not affect the offset setting.

72 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Table 23. Register Name: config11 – Address: 0x0B, Default: 0x0000 Table 24. Register Name: config12 – Address: 0x0C, Default: 0x0400 Table 25. Register Name: config13 – Address: 0x0D, Default: 0x0400 The various mixers can be combined together to obtain a ±n×Fs/8 total mixing factor. Table 26. Register Name: config14 – Address: 0x0E, Default: 0x0400 Table 27. Register Name: config15 – Address: 0x0F, Default: 0x0400

Table 28. Register Name: config16 – Address: 0x10, Default: 0x0000 (Causes Auto-Sync) config13 will not affect the QMC settings. Table 29. Register Name: config17 – Address: 0x11, Default: 0x0000 (Causes Auto-Sync) updating the QMC values for the CD-channel config17 should be written last. Programming config14 and config15 will not affect the QMC settings. Table 30. Register Name: config18 – Address: 0x12, Default: 0x0000 (Causes Auto-Sync) Table 31. Register Name: config19 – Address: 0x13, Default: 0x0000 (Causes Auto-Sync) config22 and config23 will not affect the mixer settings.

74 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Table 32. Register Name: config20 – Address: 0x14, Default: 0x0000 Table 33. Register Name: config21 – Address: 0x15, Default: 0x0000 Table 34. Register Name: config22 – Address: 0x16, Default: 0x0000 Table 35. Register Name: config23 – Address: 0x17, Default: 0x0000 Table 36. Register Name: config24 – Address: 0x18, Default: NA from 010 to 101 (0.825 V to 2.063 V). Adjust pll_vco(5:0) for optimal lock range.

Table 37. Register Name: config25 – Address: 0x19, Default: 0x0440 Table 38. Register Name: config26 – Address: 0x1A, Default: 0x0020

76 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Table 39. Register Name: config27 – Address: 0x1B, Default: 0x0000 register 0x23 during device initialization register setup. (A32) must be floating without any pull-up or pull-down resistors. output will be active at all time.

001110 DACA AVSS 0 V

010110 DACB AVSS 0 V

011110 DACC AVSS 0 V

100110 DACD AVSS 0 V

Table 40. Register Name: config28 – Address: 0x1C, Default: 0x0000 Table 41. Register Name: config29 – Address: 0x1D, Default: 0x0000

Table 42. Register Name: config30 – Address: 0x1E, Default: 0x1111 than one sync source is permitted. than one sync source is permitted. Table 43. Register Name: config31 – Address: 0x1F, Default: 0x1140 enables the signal as a sync source. More than one sync source is permitted. 0) one sync source is allowed.

78 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Table 44. Register Name: config32 – Address: 0x20, Default: 0x2400 signal as a sync source. More than one sync source is permitted. signal as a sync source. More than one sync source is permitted.

0 OSTR

1 FRAME or SYNC, based on syncsel_fifoin source

Table 45. Register Name: config33 – Address: 0x21, Default: 0x0000 Table 46. Register Name: config34 – Address: 0x22, Default: 0x1B1B

Table 47. Register Name: config35 – Address: 0x23, Default: 0xFFFF when the SLEEP is logic HIGH and the correspond bit is set to 1b. These bits do not override SIF bits in config26 that control the same sleep function.

15 DACA sleep

14 DACB sleep

13 DACC sleep

12 DACD sleep

11 Clock receiver sleep

10 PLL sleep

9 LVDS data sleep

8 LVDS control sleep

7 Temp sensor sleep

5 Bias amplifier sleep

Table 48. Register Name: config36 – Address: 0x24, Default: 0x0000 approximately 50 ps. Refer to Digital Input Timing Specifications Table for details. approximately 50 ps. Refer to Digital Input Timing Specifications Table for details. Table 49. Register Name: config37 – Address: 0x25, Default: 0x7A7A SYNC signal to indicate sample 0. Table 50. Register Name: config38 – Address: 0x26, Default: 0xB6B6 Table 51. Register Name: config39 – Address: 0x27, Default: 0xEAEA Table 52. Register Name: config40 – Address: 0x28, Default: 0x4545

80 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Table 53. Register Name: config41 – Address: 0x29, Default: 0x1A1A Table 54. Register Name: config42 – Address: 0x2A, Default: 0x1616 Table 55. Register Name: config43 – Address: 0x2B, Default: 0xAAAA Table 56. Register Name: config44 – Address: 0x2C, Default: 0xC6C6 Table 57. Register Name: config45 – Address: 0x2D, Default: 0x0004 is used to clock the dividers. mode, sif_txena in config3 and TXENABLE inputs are ignored. Table 58. Register Name: config46 – Address: 0x2E, Default: 0x0000 Table 59. Register Name: config47 – Address: 0x2F, Default: 0x0000

Table 60. Register Name: config48 – Address: 0x30, Default: 0x0000 latch this value into the DACs. The format would be based on twos in register config2. Table 61. Register Name: Version – Address: 0x7F, Default: 0x540C (Read Only)

82 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

www.ti.com SLAS749E –MARCH 2011– REVISED NOVEMBER 2015

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DAC3484 is a quad 16-bit DAC with max input data rate of up to 312.5 MSPS per DAC and max DAC update rate of 1.25 GSPS after the final, selectable interpolation stages. With build-in interpolation filter of 2x, 4x, 8x, and 16x options, the lower input data rate can be interpolated all the way to 1.25 GSPS. This allows the DAC to update the samples at higher rate, and pushes the DAC images further away to relax anti-image filer specification due to the increased Nyquist bandwidth. With integrated coarse and fine mixers, baseband signal can be upconverted to an intermediate frequency (IF) signal between the baseband processor and post-DAC analog signal chains. The DAC can output baseband or IF when connected to post-DAC analog signals chain components such as transformers or IF amplifiers. When used in conjunction with TI RF quadrature modulator such as the TRF3705, the DAC and RF modulator can function as a set of baseband or IF upconverter. With integrated QMC circuits, the LO offset and the sideband artifacts can be properly corrected in the direct up-conversion applications. The DAC3484 provides the bandwidth, performance, small footprint, and lower power consumption needed for multi- mode 2G/3G/4G cellular base stations to migrate to more advanced technologies, such as LTE-Advanced and carrier aggregation on multiple antennas. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 83 Product Folder Links: DAC3484

8.2 Typical Applications

8.2.1 IF Based LTE Transmitter

simplify the analog filter requirements and move high order harmonics out of band (due to wider Nyquist zone). The internal PLL is used to generate the final DAC output clock from a reference clock of 491.52 MHz. Figure 91. Dual Low-IF Wideband LTE Transmitter Diagram

8.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 62 as the input parameters. Table 62. Design Parameters

84 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Data Input Rate

8.2.1.2.2 Interpolation

the data input rate and available interpolation settings. The DAC image frequency is also listed. Table 63. Interpolation

8.2.1.2.3 LO Feedthrough and Sideband Correction

meets the system requirement, then further digital cancellation of these artifacts may not be needed. perform higher order sideband suppression.

8.2.1.3 Application Curves

The ACPR performance for LTE 20 MHz TM1.1 are shown in Figure 92, Figure 93, Figure 93, and Figure 93.

86 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

8.2.2 Direct Upconversion (Zero IF) LTE Transmitter

synthesizer such as the LMK0480x family. Figure 96. Zero LTE Transmitter Diagram

8.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 64 as the input parameters. Table 64. Design Parameters

8.2.2.2 Detailed Design Procedure

8.2.2.2.1 Data Input Rate

percent of FDATA with less than 0.1dB of FIR filter roll-off. Therefore, the minimum data input rate is 228 MSPS. be 10 times of 30.72 MSPS, which is 307.2 MSPS.

8.2.2.2.2 Interpolation

based on the data input rate and available interpolation settings. The DAC image frequency is also listed. Table 65. Interpolation

8.2.2.2.3 LO Feedthrough and Sideband Correction

Refer to LO Feedthrough and Sideband Correction section of IF based LTE Transmitter design.

88 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

8.2.2.3 Application Curves

9 Power Supply Recommendations

recommended for these two rails. Figure 99. Interpolation Filters, NCOs, and QMC Blocks Powered by DIGVDD requirements for DIGVDD of the digital section of the device may be relaxed and placed at a lower priority. ATEST function in register config27 to check the internal power supply nodes is recommended. with larger bulk capacitors placed further away and near the power supply source.

90 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Table 66. Power Rails Keep Away from other noise sensitive nodes inDIGVDD 1.2 V Low Lowplacement and routing.

10 Layout

10.1 Layout Guidelines

increasing the distributed decoupling. respective ground reference planes. minimizing signal path stubs (including vias) when possible. 90° angles to minimize crosstalk. high speed serial lanes. Affordable and common FR4 varieties are adequate in most cases. very noise environment and high dynamic range applications to isolate the signal path. The following layout guidelines correspond to the layout shown in Figure 100.

1. DAC output termination resistors should be placed as close to the output pins as possible to provide a DC

path to ground and set the source impedance matching.

1. For DAC on-chip PLL clocking mode, if the external loop filter is not used, leave the loop filter pin floating
2. Route the high speed LVDS lanes as impedance-controlled, tightly-coupled, differential traces.

1. Maintain a solid ground plane under the LVDS lanes without any ground plane splits.
2. Simulation of the LVDS channel with DAC3484 IBIS model is recommended to verify good eye opening of
3. Keep the OSTR signal routing away from the DACCLK routing to reduce coupling.
4. Keep routing for RBIAS short, for instance a resistor can be placed on the board directly connecting the

RBIAS pin to the ground layer. The following layout guidelines correspond to the layouts shown in Figure 101 and Figure 102.

1. Noise power supplies should be routed away from clean supplies. Use two power plane layers, preferably

with a ground layer in between.

1. As shown in Figure 101 and Figure 102, both layers three and four are designated for power supply planes.

copied from layer three to layer four for double the copper coverage area.

1. Decoupling capacitors should be placed as close to the supply pins as possible. For instance, a capacitor

can be placed on the bottom of the board directly connecting the supply pin to a ground layer.

10.1.1 Assembly

10.2 Layout Examples

Figure 100. Top Layer of DAC3484 Layout Showing High Speed Signals such as LVDS Bus, DACCLK,

92 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Figure 101. Third Layer of DAC3484 Layout Showing Power Layers. Layout Example from DAC3484EVM

Figure 102. Fourth Layer of DAC3484 Layout Showing Power Layers. Layout Example from

94 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

www.ti.com SLAS749E –MARCH 2011– REVISED NOVEMBER 2015

11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Device Nomenclature

11.1.2.1 Definition of Specifications

Adjacent Carrier Leakage Ratio (ACLR): Defined for a 3.84Mcps 3GPP W-CDMA input signal measured in a 3.84-MHz bandwidth at a 5-MHz offset from the carrier with a 12dB peak-to-average ratio. Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR): Defined as the percentage error in the ratio of the delta IOUT and delta supply voltage normalized with respect to the ideal IOUT current. Differential Nonlinearity (DNL): Defined as the variation in analog output associated with an ideal 1 LSB change in the digital input code. Gain Drift: Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the value at ambient (25°C) to values over the full operating temperature range. Gain Error: Defined as the percentage error (in FSR%) for the ratio between the measured full-scale output current and the ideal full-scale output current. Integral Nonlinearity (INL): Defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Intermodulation Distortion (IMD3): The two-tone IMD3 is defined as the ratio (in dBc) of the 3rd-order intermodulation distortion product to either fundamental output tone. Offset Drift: Defined as the maximum change in DC offset, in terms of ppm of full-scale range (FSR) per °C, from the value at ambient (25°C) to values over the full operating temperature range. Offset Error: Defined as the percentage error (in FSR%) for the ratio between the measured mid-scale output current and the ideal mid-scale output current. Output Compliance Range: Defined as the minimum and maximum allowable voltage at the output of the current-output DAC. Exceeding this limit may result reduced reliability of the device or adversely affecting distortion performance. Reference Voltage Drift: Defined as the maximum change of the reference voltage in ppm per degree Celsius from value at ambient (25°C) to values over the full operating temperature range. Spurious Free Dynamic Range (SFDR): Defined as the difference (in dBc) between the peak amplitude of the output signal and the peak spurious signal within the first Nyquist zone. Noise Spectral Density (NSD): Defined as the difference of power (in dBc) between the output tone signal power and the noise floor of 1-Hz bandwidth within the first Nyquist zone. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 95 Product Folder Links: DAC3484

SLAS749E – MARCH 2011– REVISED NOVEMBER 2015 www.ti.com

11.2 Documentation Support

11.2.1 Related Documentation

• Design Summary Multi-row Quad Flat No-lead (MRQFN) Application Report (SZZA059)
• nFBGA Packaging Application Report (SPRAA99)
• DAC348x Device Configuration and Synchronization Application Report (SLAA584)
• Semiconductor and IC Package Thermal Metrics Application Report (SPRA953)
• Using DAC348x with Fault Detection and Auto Output Shut-off Feature Application Report (SLAA585)

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

96 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated

Product Folder Links: DAC3484

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DAC3484IRKDR Active Production WQFN-MR (RKD) | 88 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DAC3484I DAC3484IRKDR.A Active Production WQFN-MR (RKD) | 88 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DAC3484I DAC3484IRKDT Active Production WQFN-MR (RKD) | 88 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DAC3484I DAC3484IRKDT.A Active Production WQFN-MR (RKD) | 88 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DAC3484I DAC3484IRKDTG4 Active Production WQFN-MR (RKD) | 88 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DAC3484I DAC3484IRKDTG4.A Active Production WQFN-MR (RKD) | 88 250 | SMALL T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 DAC3484I DAC3484IZAY Active Production NFBGA (ZAY) | 196 160 | JEDEC TRAY (5+1) Yes SNAGCU Level-3-260C-168 HR -40 to 85 DAC3484I DAC3484IZAY.A Active Production NFBGA (ZAY) | 196 160 | JEDEC TRAY (5+1) Yes SNAGCU Level-3-260C-168 HR -40 to 85 DAC3484I DAC3484IZAYR Active Production NFBGA (ZAY) | 196 1000 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 DAC3484I DAC3484IZAYR.A Active Production NFBGA (ZAY) | 196 1000 | LARGE T&R Yes SNAGCU Level-3-260C-168 HR -40 to 85 DAC3484I (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 7-Oct-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 21-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant DAC3484IRKDR WQFN- MR DAC3484IRKDT WQFN- MR DAC3484IRKDTG4 WQFN- MR Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 21-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC3484IRKDR WQFN-MR RKD 88 2000 367.0 367.0 38.0 DAC3484IRKDT WQFN-MR RKD 88 250 367.0 367.0 38.0 DAC3484IRKDTG4 WQFN-MR RKD 88 250 367.0 367.0 38.0 DAC3484IZAYR NFBGA ZAY 196 1000 350.0 350.0 43.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 21-Jun-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) DAC3484IZAY ZAY NFBGA 196 160 8 x 20 150 315 135.9 7620 15.4 11.2 19.65 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C

1.4 MAX

TYP0.45 0.35 10.4 TYP

10.4 TYP

0.8 TYP

196X 0.55 0.45 A 12.1 11.9 B 12.1 11.9 (0.8) TYP (0.8) TYP NFBGA - 1.4 mm max heightZAY0196A PLASTIC BALL GRID ARRAY 4219823/A 09/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER SEATING PLANE BALL TYP 0.12 C

0.15 C A B

0.05 C SYMM SYMM BALL A1 CORNER P C D E F G H J K L M N 1 2 3 4 5 6 7 8 9 10 11 A B 12 13 14 SCALE 1.100

www.ti.com EXAMPLE BOARD LAYOUT 196X ( )0.4 (0.8) TYP (0.8) TYP ( ) METAL 0.4 0.05 MAX SOLDER MASK OPENING METAL UNDER SOLDER MASK ( ) SOLDER MASK OPENING 0.4

0.05 MIN

NFBGA - 1.4 mm max heightZAY0196A PLASTIC BALL GRID ARRAY 4219823/A 09/2015 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99). SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 1 2 3 4 5 6 7 8 9 10 11 B A C D E F G H J K L M N P 12 13 14 NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (0.8) TYP (0.8) TYP ( ) TYP0.4 NFBGA - 1.4 mm max heightZAY0196A PLASTIC BALL GRID ARRAY 4219823/A 09/2015 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SOLDER PASTE EXAMPLE BASED ON 0.15 mm THICK STENCIL SCALE:8X SYMM SYMM 1 2 3 4 5 6 7 8 9 10 11 B A C D E F G H J K L M N P 12 13 14

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated