DAC3482IRKDR

Texas Instruments

Dual-Channel, 16-BIT, 1.25 GSPS Digital-to-Analog Converter (DAC) JUNE2011

Manufacturer: Texas Instruments

Document: 79 Pages / 1Mb

Request Quote Download Datasheet Read online HTML view

More from Texas Instruments Browse D parts

Online Datasheet

Read DAC3482IRKDR online.

DAC3482 TI1 | Alldatasheet

Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 79

Technical content

www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Dual-Channel,16-BIT,1.25GSPSDigital-to-AnalogConverter(DAC) Check forSamples: DAC3482 1FEATURES DESCRIPTION The DAC3482 is a very low power, high dynamic• Very Low Power: 900 mW at1.25GSPS, Full range,dual-channel,16-bitdigital-to-analogconverterOperatingConditions (DAC) witha sample rateas highas 1.25GSPS.• Multi-DACSynchronization The deviceincludesfeaturesthatsimplifythedesign• Selectable2x,4x,8x,16x InterpolationFilter of complex transmitarchitectures:2x to 16x digital– Stop-Band Attenuation> 90 dBc interpolationfilterswith over 90 dB of stop-band• FlexibleOn-Chip Complex Mixing attenuation simplify the data interface and– FineMixerwith32-bitNCO reconstructionfilters.A complex mixerallowsflexible – Power Saving Coarse Mixer:± n×Fs/8 carrierplacement.A high-performancelow jitterclock multipliersimplifiesclockingof the device without• High Performance,Low JitterClock significantimpacton the dynamic range.The digitalMultiplyingPLL Quadrature Modulator Correction(QMC) enables• DigitalIand Q Correction complete IQ compensation forgain,offset,phase,– Gain,Phase, Offset,and Group Delay and group delay between channels in directCorrection up-conversionapplications.

DigitalInverseSinc Filter Digitaldata isinputto the devicethrougha flexible• FlexibleLVDS InputData Bus LVDS databus withon-chiptermination.Data can be– Word- or Byte-Wide Interface input eitherword-wide or byte-wide.The device – 8 Sample InputFIFO includesa FIFO,datapatterncheckerand paritytest toease theinputinterface.The interfacealsoallows– Data PatternChecker fullsynchronizationofmultipledevices.– ParityCheck The deviceis characterizedforoperationover the• Temperature Sensor entireindustrialtemperaturerange of–40°C to85°C• DifferentialScalableOutput:10mA to30mA and isavailableina very-small88-pin9x9mm WQFN• Space Saving Package: 88-pin9x9mm WQFN package.(GREEN /Pb-Free) The DAC3482 very low power, smallsize,superior crosstalk,high dynamic range and featuresare anAPPLICATIONS idealfitfortoday’s communicationsystems.• CellularBase Stations
DiversityTransmit
Wideband Communications These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2011,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

Pattern Test De-interleave 100 Complex Mixer(FMIX or CMIX) QMC Gain and Phase 16-b DACQ 16-b DACI Control Interface Temp Sensor Clock Distribution Frame Strobe and Optional Parity EXTIO BIASJ IOUTIP IOUTIN IOUTQP IOUTQN B0450-01 DACCLKP DACCLKN DATACLKP DATACLKN D15P D15N D0P D0N FRAMEP FRAMEN OSTRP OSTRN QMC Q-offset QMC I-offset SDO SDIO SDENB SCLK TXENABLE RESETB AVDD CLKVDD DIGVDD VFUSE DACVDD GND LVPECL LVDS LVPECL LVDS LVDS 100 LVDS

8 Sample FIFO

x sin(x) x sin(x) DAC Gain FIR3FIR2 Programmable Delay Low Jitter PLL FIR4 2x–16x Interpolation 32-Bit NCO cos sin CMIX Control (±n*Fs/8)ALARM SLEEP 100 SYNCP SYNCN LVDS 100 PARITYP PARITYN LVDS Programmable Delay TESTMODE 59 taps 23 taps 11 taps 11 taps 9 taps LPF PLLAVDD AVDDIOVDD I-Group Delay Q-Group Delay 1.2-V Reference DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM

2 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 A33 A32 A31 A30 A29 A28 A27 A26 A25 A24 A23 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 A44 A43 A42 A41 A40 A39 A38 A37 A36 A35 A34 B40 B39 B38 B37 B36 B35 B34 B33 B32 B31 C2 C3 OSTRN OSTRP SYNCP CLKVDD DACCLKN DACCLKP VFUSE PLLAVDD LPF D15N D15P D13P DIGVDD D14N D14P IOVDD DIGVDD SYNCN D12N D12P D13N D9PD10N DATACLKP D8ND8PD9ND10PD11ND11P D7P FRAMEN D5PD6ND6PD7N FRAMEP IOVDD DATACLKN D4ND4PD5N SCLK ALARM PARITYN SDO SDIO SDENB TXENABLE RESETB BIASJ D0P D0N D2N DIGVDD D1P D1N IOVDD DIGVDD PARITYP D3P D3N D2P AVDDGND AVDDIOUTINAVDDGNDDACVDDSLEEPTESTMODE IOUTQNAVDD GNDAVDDGNDAVDDIOUTQPDACVDDIOUTIP EXTIOAVDDDACVDD DAC3482 88-WQFN 9mm x 9mm (Top View) P0133-01 DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 DEVICE INFORMATION PINOUT PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. A36,A37, A38,A40,AVDD I Analogsupplyvoltage.(3.3V)A41,A42, B31 CMOS outputforALARM condition.The ALARM outputfunctionalityisdefinedthroughtheconfig7 ALARM B29 O register.Defaultpolarityisactivelow,butcan be changed toactivehighviaconfig0alarm_out_pol controlbit. Full-scaleoutputcurrentbias.For30mA full-scaleoutputcurrent,connect1.28kΩ toground.ChangeBIASJ A33 O thefull-scaleoutputcurrentthroughcoarse_dac(3:0)inconfig3,bit<15:12> Internalclockbuffersupplyvoltage.(1.2V)CLKVDD A4 I Itisrecommended toisolatethissupplyfromDIGVDD and DACVDD. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com PIN FUNCTIONS (continued) PIN I/O DESCRIPTION NAME NO. LVDS positiveinputdatabits0 through15.Internal100 Ω terminationresistor.Data formatrelativetoA7,A8,B9, DATACLKP/N clockisDoubleData Rate (DDR) and can be transferredineitherbyte-wideorB10,A12, word-widemode. Inbyte-widemode theunused pinscan be leftunconnected.A13,A14, A15,B17, D15P ismost significantdatabit(MSB) inword-widemodeD[15..0]P IB18,B19, D7P ismost significantdatabit(MSB) inbyte-widemodeB20,A23, D0P isleastsignificantdatabit(LSB)A24,B23, B24 The orderofthebus can be reversedviaconfig2revbusbit. B7,B8,A10, A11,B11, B12,B13, B14,A19,D[15..0]N I LVDS negativeinputdatabits0 through15.(See D[15:0]Pdescriptionabove)A20,A21, A22,B21, B22,A26, A27 DACCLKP A3 I PositiveexternalLVPECL clockinputforDAC corewitha self-bias. DACCLKN B3 I ComplementaryexternalLVPECL clockinputforDAC core.(seetheDACCLKP description) A35,A39, DAC coresupplyvoltage.(1.2V).Itisrecommended toisolatethissupplyfromCLKVDD andDACVDD IA43 DIGVDD. LVDS positiveinputdataclock.Internal100 Ω terminationresistor.InputdataD[15:0]P/NislatchedDATACLKP A16 I on bothedges ofDATACLKP/N (DoubleData Rate). DATACLKN B15 I LVDS negativeinputdataclock.(See DATACLKP description) A6,A9,A25,DIGVDD I Digitalsupplyvoltage.(1.2V).Itisrecommended toisolatethissupplyfromCLKVDD and DACVDD.A28 Used as externalreferenceinputwhen internalreferenceisdisabledthroughconfig27extref_ena= EXTIO A34 I/O ‘1’.Used as internalreferenceoutputwhen config27extref_ena= ‘0’ (default).Requiresa 0.1μF decouplingcapacitortoAGND when used as referenceoutput. LVDS frameindicatorpositiveinput.Internal100 Ω terminationresistor.The main functionsofthis inputaretoresettheFIFO ortobe used as a syncingsource.These two functionsarecapturedwithFRAMEP B16 I therisingedge ofDATACLKP/N. The signalcapturedby thefallingedge ofDATACLKP/N can be used as a blockparitybit.The FRAMEP/N signalshouldbe edge-alignedwithD[15:0]P/N. FRAMEN A18 I LVDS frameindicatornegativeinput.(See theFRAMEP description) C1, C2, C3, C4, B32, GND B33,B38, I These pinsaregroundforallsupplies. B39,Thermal Pad IOUTIP B36 O I-ChannelDAC currentoutput.Connectdirectlytogroundifunused. IOUTIN B37 O I-ChannelDAC complementarycurrentoutput.Connectdirectlytogroundifunused. IOUTQP B35 O Q-ChannelDAC currentoutput.Connectdirectlytogroundifunused. IOUTQN B34 O Q-ChannelDAC complementarycurrentoutput.Connectdirectlytogroundifunused. IOVDD B6,A17,B25 I SupplyvoltageforalldigitalI/O.(3.3V) LPF A1 I/O PLL loopfilterconnection.IfnotusingtheclockmultiplyingPLL,theLPF pincan be leftunconnected. LVPECL outputstrobepositiveinput.Thispositive/negativepairiscapturedwiththerisingedge of OSTRP A2 I DACCLKP/N. Itisused tosyncthedivided-downclocksand FIFO outputpointerinDualSync SourcesMode. Ifunused itcan be leftunconnected. OSTRN B2 I LVPECL outputstrobenegativeinput.(See theOSTRP description) OptionalLVDS positiveinputparitybit.The PARITYP/N LVDS pairhas an internal100 Ω terminationPARITYP B26 I resistor.Ifunused itcan be leftunconnected. PARITYN A29 I OptionalLVDS negativeinputparitybit. PLLAVDD B1 I PLL analogsupplyvoltage.(3.3V) SCLK A31 I Serialinterfaceclock.Internalpull-down. SDENB B28 I Activelowserialdataenable,alwaysan inputtotheDAC3482. Internalpull-up. Serialinterfacedata.Bi-directionalin3-pinmode (default)and uni-directionalin4-pinmode. InternalSDIO A30 I/O pull-down.

4 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 PIN FUNCTIONS (continued) PIN I/O DESCRIPTION NAME NO. Uni-directionalserialinterfacedatain4-pinmode. The SDO pinistri-statedin3-pininterfacemodeSDO B27 O (default). SLEEP B40 I Activehighasynchronoushardwarepower-down input.Internalpull-down. OptionalLVDS SYNC positiveinput.The SYNCP/N LVDS pairhas an internal100 Ω terminationSYNCP A5 I resistor.Ifunused itcan be leftunconnected. SYNCN B5 I OptionalLVDS SYNC negativeinput. ActivelowinputforchipRESET, whichresetsalltheprogrammingregisterstotheirdefaultstate.RESETB B30 I Internalpull-up. Transmitenableactivehighinput.Internalpull-down. To enableanalogoutputdatatransmission,setsif_txenableinregisterconfig3to“1” or pullCMOS TXENABLE A32 I TXENABLE pintohigh. To disableanalogoutput,setsif_txenableto“0” and pullCMOS TXENABLE pintolow.The digital logicsectionisforcedtoall0,and any inputdataisignored. TESTMODE A44 I Thispinisused forfactorytesting.Internalpull-down.Leave unconnected fornormal operation. Digitalsupplyvoltage.Thissupplypinisalsoused forfactoryfuseprogramming.Connect toVFUSE B4 I DACVDD fornormal operation. ORDERING INFORMATION (1) TA ORDER CODE PACKAGE DRAWING/TYPE (2)(3) TRANSPORT MEDIA QUANTITY DAC3482IRKDT 250 –40°C to85°C RKD /88 WQFN Quad FlatpackNo-Lead Tape and Reel DAC3482IRKDR 2000 (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orvisitthe deviceproductfolderatwww.ti.com. (2) ThermalPad Size:6.4mm x 6.4mm (3) MSL Peak Temperature:Level-3-260C-168HR ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) VALUE UNIT MIN MAX DACVDD, DIGVDD, CLKVDD –0.5 1.5 V VFUSE –0.5 1.5 VSupplyvoltage range(2) IOVDD –0.5 4 V AVDD, PLLAVDD –0.5 4 V D[15..0]P/N,DATACLKP/N, FRAMEP/N, PARITYP/N, SYNCP/N –0.5 IOVDD + 0.5 V DACCLKP/N, OSTRP/N –0.5 CLKVDD + 0.5 V ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TESTMODE, –0.5 IOVDD + 0.5 VTXENABLEPinvoltagerange(2) IOUTIP/N,IOUTQP/N –1.0 AVDD + 0.5 V EXTIO, BIASJ –0.5 AVDD + 0.5 V LPF 0.5 PLLAVDD+0.5V V Peak inputcurrent(anyinput) 20 mA Peak totalinputcurrent(allinputs) –30 mA Operatingfree-airtemperaturerange,TA:DAC3482 –40 85 °C Storagetemperaturerange –65 150 °C (1) Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings onlyand functionaloperationoftheseorany otherconditionsbeyond thoseindicatedunder“recommended operatingconditions” isnot implied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) Measured withrespecttoGND. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com THERMAL INFORMATION DAC3482 THERMAL METRIC (1) RKD PACKAGE UNITS (88)PINS TJ Maximum junctiontemperature 125 °C θJA Junction-to-ambientthermalresistance(2) 22.1 θJCtop Junction-to-case(top)thermalresistance(3) 7.1 θJCbot Junction-to-case(bottom)thermalresistance(4) 0.6 °C/W θJB Junction-to-boardthermalresistance(5) 4.7 ψJT Junction-to-topcharacterizationparameter(6) 0.1 ψJB Junction-to-boardcharacterizationparameter(7) 4.6 (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953 . (2) The junction-to-ambientthermalresistanceundernaturalconvectionisobtainedina simulationon a JEDEC-standard,high-Kboard,as specifiedinJESD51-7,inan environmentdescribedinJESD51-2a. (3) The junction-to-case(top)thermalresistanceisobtainedby simulatinga coldplateteston thepackage top.No specific JEDEC-standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. (4) The junction-to-case(bottom)thermalresistanceisobtainedby simulatinga coldplateteston theexposed (power)pad.No specific JEDEC standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. (5) The junction-to-boardthermalresistanceisobtainedby simulatinginan environmentwitha ringcoldplatefixturetocontrolthePCB temperature,as describedinJESD51-8. (6) The junction-to-topcharacterizationparameter,ψJT,estimatesthejunctiontemperatureofa deviceina realsystemand isextracted fromthesimulationdataforobtainingθJA,usinga proceduredescribedinJESD51-2a (sections6 and 7). (7) The junction-to-boardcharacterizationparameter,ψJB,estimatesthejunctiontemperatureofa deviceina realsystemand isextracted fromthesimulationdataforobtainingθJA ,usinga proceduredescribedinJESD51-2a (sections6 and 7).

6 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS (1) overrecommended operatingfree-airtemperaturerange,nominalsupplies,IOUT FS = 20mA (unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 16 Bits DC ACCURACY DNL Differentialnonlinearity ±2 LSB

1 LSB = IOUT FS /216

INL Integralnonlinearity ±4 LSB ANALOG OUTPUT Coarse gainlinearity ±0.04 LSB Offseterror Mid code offset ±0.001 %FSR Gain error Withexternalreference ±2 %FSR Withinternalreference ±2 %FSR Gain mismatch Withinternalreference ±2 %FSR Fullscaleoutputcurrent 10 20 30 mA Outputcompliancerange –0.5 0.6 V Outputresistance 300 kΩ Outputcapacitance 5 pF REFERENCE OUTPUT VREF Referenceoutputvoltage 1.2 V Referenceoutputcurrent(2) 100 nA REFERENCE INPUT VEXTIO Inputvoltagerange 0.6 1.2 1.25 V ExternalReferenceMode Inputresistance 1 M Ω Smallsignalbandwidth 472 kHz Inputcapacitance 100 pF TEMPERATURE COEFFICIENTS Offsetdrift ±1 ppm/°C Withexternalreference ±15 ppm/°C Gain drift Withinternalreference ±30 ppm/°C Referencevoltagedrift ±8 ppm/°C POWER SUPPLY AVDD, IOVDD, PLLAVDD 3.14 3.3 3.46 V CLKVDD, DACVDD, DIGVDD 1.14 1.2 1.26 V PSRR Power supplyrejectionratio DC tested ±0.2 %FSR/V POWER CONSUMPTION I(AVDD) Analogsupplycurrent(3) 80 85 mA MODE 1I(DIGVDD) Digitalsupplycurrent 390 450 mA fDAC = 1.25GSPS, 2x interpolation,Mixeron,I(DACVDD) DAC supplycurrent 30 50 mAQMC on,invsincon, I(CLKVDD) Clocksupplycurrent 95 110 mAPLL enabled,20mA FS output,IF= 200MHz P Power dissipation 882 980 mW I(AVDD) Analogsupplycurrent(3) 65 mA MODE 2I(DIGVDD) Digitalsupplycurrent 385 mA fDAC = 1.25GSPS, 2x interpolation,Mixeron,I(DACVDD) DAC supplycurrent 30 mAQMC on,invsincon, I(CLKVDD) Clocksupplycurrent 70 mAPLL disabled,20mA FS output,IF= 200MHz P Power dissipation 800 mW (1) Measured differentiallyacrossIOUTP/N with25 Ω each toGND. (2) Use an externalbufferamplifierwithhighimpedance inputtodriveany externalload. (3) IncludesAVDD, PLLAVDD, and IOVDD Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS (1)(continued) overrecommended operatingfree-airtemperaturerange,nominalsupplies,IOUT FS = 20mA (unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I(AVDD) Analogsupplycurrent(3) 65 mA MODE 3I(DIGVDD) Digitalsupplycurrent 190 mA fDAC = 625MSPS, 2x interpolation,Mixeron,I(DACVDD) DAC supplycurrent 15 mAQMC on,invsincoff, I(CLKVDD) Clocksupplycurrent 45 mAPLL disabled,20mA FS output,IF= 200MHz P Power dissipation 515 mW I(AVDD) Analogsupplycurrent(3) 35 mA MODE 4I(DIGVDD) Digitalsupplycurrent 395 mA fDAC = 1.25GSPS, 2x interpolation,Mixeron,I(DACVDD) DAC supplycurrent 30 mAQMC on,invsincon, I(CLKVDD) Clocksupplycurrent 95 mAPLL enabled,I/Qoutputsleep,IF= 200MHz, P Power dissipation 740 mW I(AVDD) Analogsupplycurrent(3) 20 mA Mode 5I(DIGVDD) Digitalsupplycurrent 10 mA Power-Down mode: No clock,I(DACVDD) DAC supplycurrent 4 mADAC on sleepmode (clockreceiversleep), I(CLKVDD) Clocksupplycurrent 10 mAI/Qoutputsleep,staticdatapattern P Power dissipation 95 mW I(AVDD) Analogsupplycurrent(3) 80 mA Mode 6I(DIGVDD) Digitalsupplycurrent 200 mA fDAC = 1GSPS, 2x interpolation,Mixeroff,I(DACVDD) DAC supplycurrent 25 mAQMC off,invsincoff,PLL enabled,20mA FS I(CLKVDD) Clocksupplycurrent 85 mAoutput,IF= 200MHz P Power dissipation 636 mW OperatingRange –40 25 85 °C

8 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVDS INPUTS: D[15:0]P/N,DATACLKP/N, FRAMEP/N, SYNCP/N, PARITYP/N (1) LogichighdifferentialVA,B+ 200 400 1000 mVinputvoltagethreshold LogiclowdifferentialVA,B– –200 mVinputvoltagethreshold VCOM Inputcommon mode 1.075 1.2 V ZT Internaltermination 110 Ω C L LVDS Inputcapacitance 2 pF InterleavedLVDS datafINTERL 1250 MSPStransferrate Word-wideinterfacemode 625 fDATA Inputdatarate MSPS Byte-wideinterfacemode 312.5 CLOCK INPUT (DACCLKP/N) Dutycycle 40% 60% Differentialvoltage(2) 0.4 1.0 V DACCLKP/N input 1250 MHzfrequency OUTPUT STROBE (OSTRP/N) fOSTR = fDACCLK /(nx 8 x Interp)where n isany positiveinteger, fDACCLK /fOSTR Frequency MHzfDACCLK isDACCLK frequencyinMHz (8x interp) Dutycycle 50% Differentialvoltage 0.4 1.0 V CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENABLE VIH High-levelinputvoltage 2 V VIL Low-levelinputvoltage 0.8 V IIH High-levelinputcurrent -40 40 µA IIL Low-levelinputcurrent -40 40 µA C I CMOS inputcapacitance 2 pF Iload= –100 μA IOVDD – 0.2 V VOH ALARM, SDO, SDIO Iload= –2 mA 0.8x IOVDD V Iload= 100 μA 0.2 V VOL ALARM, SDO, SDIO Iload= 2 mA 0.5 V (1) See LVDS INPUTS sectionforterminology. (2) Drivingtheclockinputwitha differentialvoltagelowerthan1 V may resultindegradedperformance. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT TIMING SPECIFICATIONS Timing LVDS inputs:D[15:0]P/N,FRAMEP/N, SYNCP/N, PARITYP/N, double edge latching Config36Setting datadly clkdly 0 0 150 0 1 100 0 2 50 0 3 0 0 4 -50 Setuptime,D[15:0]P/N, FRAMEP/N resetand frameindicatorlatched 0 5 -100FRAMEP/N, SYNCP/N on risingedge ofDATACLKP/N.ts(DATA) and PARITYP/N, validto 0 6 -150 psFRAMEP/N paritybitlatchedon fallingedgeeitheredge of 0 7 -200ofDATACLKP/N.DATACLKP/N 1 0 200 2 0 250 3 0 300 4 0 350 5 0 400 6 0 450 7 0 500 Config36Setting datadly clkdly 0 0 350 0 1 400 0 2 450 0 3 500 0 4 550 Holdtime,D[15:0]P/N, FRAMEP/N resetand frameindicatorlatched 0 5 600FRAMEP/N, SYNCP/N on risingedge ofDATACLKP/N.th(DATA) and PARITYP/N, valid 0 6 650 psFRAMEP/N paritybitlatchedon fallingedgeaftereitheredge of 0 7 700ofDATACLKP/N.DATACLKP/N 1 0 300 2 0 250 3 0 200 4 0 150 5 0 100 6 0 50 7 0 0 FRAMEP/N andt(FRAME_SYNC) fDATACLK isDATACLK frequencyinMHz 1/2fDATACLK nsSYNCP/N pulsewidth

10 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TIMING OUTPUT STROBE INPUT: DACCLKP/N risingedge LATCHING (3) Setuptime,OSTRP/N ts(OSTR) validtorisingedge of 0 ps DACCLKP/N Holdtime,OSTRP/N th(OSTR) validafterrisingedge of 300 ps DACCLKP/N TIMING SYNC INPUT: DACCLKP/N risingedge LATCHING (4) Setuptime,SYNCP/N ts(SYNC_PLL) validtorisingedge of 200 ps DACCLKP/N Holdtime,SYNCP/N th(SYNC_PLL) validafterrisingedge of 300 ps DACCLKP/N TIMING SERIAL PORT Setuptime,SDENB tots(SDENB) 20 nsrisingedge ofSCLK Setuptime,SDIO validtots(SDIO) 10 nsrisingedge ofSCLK Holdtime,SDIO validtoth(SDIO) 5 nsrisingedge ofSCLK Registerconfig6read(temperaturesensorread) 1 µs t(SCLK) PeriodofSCLK Allotherregisters 100 ns Data outputdelayaftertd(Data) 10 nsfallingedge ofSCLK Minimum RESETB pulsetRESET 25 nswidth (3) OSTR isrequiredinDualSync Sourcesmode. Inordertominimizetheskew itisrecommended touse thesame clockdistribution devicesuch as Texas InstrumentsCDCE62005 toprovidetheDACCLK and OSTR signalstoalltheDAC3482 devicesinthesystem. Swap thepolarityoftheDACCLK outputswithrespecttotheOSTR ones toestablishproperphase relationship. (4) SYNC isrequiredtosynchronizethePLL circuitinmultipledevices.The SYNC signalmust meet thetimingrelationshipwithrespectto thereferenceclock(DACCLKP/N) oftheon-chipPLL circuit. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS – AC SPECIFICATIONS overrecommended operatingfree-airtemperaturerange,nominalsupplies,IOUT FS = 20mA (unlessotherwisenoted) PARAMETER TEST CONDITIONS /COMMENTS MIN TYP MAX UNIT ANALOG OUTPUT (1) fDAC Maximum DAC rate 1250 MSPS ts(DAC) Outputsettlingtimeto0.1% Transition:Code 0x0000 to0xFFFF 10 ns DAC outputsareupdatedon thefallingedge ofDAC clock.Does notincludetpd Outputpropagationdelay 2 nsDigitalLatency(seebelow). tr(IOUT) Outputrisetime10% to90% 220 ps tf(IOUT) Outputfalltime90% to10% 220 ps No interpolation,FIFO enabled,Mixeroff,QMC off,Inverse 250sincoff 2x Interpolation 2128-bit interface 4x Interpolation 372 8x Interpolation 723 16x Interpolation 1440 No interpolation,FIFO enabled,Mixeroff,QMC off,Inverse 140 DACsincoffDigitallatency clock 2x Interpolation 228 cycles16-bit interface 4x Interpolation 417 8x Interpolation 817 16x Interpolation 1630 Finemixer 24 QMC 16 Inversesinc 20 Power- DAC wake-up time IOUT currentsettlingto1% ofIOUT FS fromoutputsleep 2 up μs DAC sleeptime IOUT currentsettlingtolessthan1% ofIOUT FS inoutputsleep 2Time AC PERFORMANCE (2) fDAC = 1.25GSPS, fOUT = 20 MHz 82 SpuriousfreedynamicrangeSFDR fDAC = 1.25GSPS, fOUT = 50 MHz 77 dBc(0tofDAC /2)toneat0 dBFS fDAC = 1.25GSPS, fOUT = 70 MHz 72 fDAC = 1.25MSPS, fOUT = 30 ± 0.5MHz 81Third-ordertwo-tone intermodulationdistortionIMD3 fDAC = 1.25GSPS, fOUT = 50 ± 0.5MHz 79 dBc Each toneat–12 dBFS fDAC = 1.25GSPS, fOUT = 100 ± 0.5MHz 77.5 fDAC = 1.25GSPS, fOUT = 10 MHz 160NoisespectraldensityNSD dBc/HzTone at0dBFS fDAC = 1.25GSPS, fOUT = 80 MHz 155 fDAC = 1.2288GSPS, fOUT = 30.72MHz 77Adjacentchannelleakageratio, singlecarrier fDAC = 1.2288GSPS, fOUT = 153.6MHz 74 ACLR (3) dBc fDAC = 1.2288GSPS, fOUT = 30.72MHz 82Alternatechannelleakageratio, singlecarrier fDAC = 1.2288GSPS, fOUT = 153.6MHz 80 Channelisolation fDAC = 1.25GSPS, fOUT = 10 MHz 84 dBc (1) Measured singleended into50 Ω load. (2) 4:1transformeroutputtermination,50 Ω doublyterminatedload (3) Singlecarrier,W-CDMA with3.84MHz BW, 5-MHz spacing,centeredatIF,PAR = 12dB.TESTMODEL 1,10 ms

12 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

Integral Nonlinearity Error (LSB) G001 0 10k 20k 30k 40k 50k 60k Code Differential Nonlinearity Error (LSB) G002 100 0 100 200 300 400 500 600 Output Frequency (MHz) SFDR (dBc) 0 dBFS −6 dBFS −12 dBFS G003 100 0 100 200 300 400 500 600 Output Frequency (MHz) Second Harmonic Distortion (dBc) 0 dBFS −6 dBFS −12 dBFS G004 100 0 100 200 300 400 500 600 Output Frequency (MHz) Third Harmonic Distortion (dBc) 0 dBFS −6 dBFS −12 dBFS G005 100 0 100 200 300 400 500 600 Output Frequency (MHz) SFDR (dBc) fDATA = 312.5 MSPS, 1x Interpolation fDATA = 312.5 MSPS, 2x Interpolation fDATA = 312.5 MSPS, 4x Interpolation fDATA = 156.25MSPS, 8x Interpolation fDATA = 78.125MSPS, 16x Interpolation G006 DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 TYPICAL CHARACTERISTICS Allplotsareat25°C, nominalsupplyvoltage,fDAC = 1250 MSPS, 4x interpolation,NCO enabled,MixerGain disabled,QMC enabledwithgainsetat1446 forbothI/Qchannels,0 dBFS digitalinput,20 mA full-scaleoutputcurrentwith4:1transformer (unlessotherwisenoted) Figure1.IntegralNonlinearity Figure2.DifferentialNonlinearity Figure3.SFDR vs Output Frequency Over InputScale Figure4.Second Harmonic Distortionvs Output Frequency Over InputScale Figure5.ThirdHarmonic Distortionvs Figure6.SFDR vs Output Frequency Over Interpolation Output Frequency Over InputScale Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):DAC3482

Output Frequency (MHz) SFDR (dBc) fDAC = 600 MSPS fDAC = 800 MSPS fDAC = 1000 MSPS fDAC = 1250 MSPS G007 100 0 50 100 150 200 250 300 350 400 Output Frequency (MHz) SFDR (dBc) IOUT FS = 10 mA w/ 4:1 Transformer IOUT FS = 20 mA w/ 4:1 Transformer IOUT FS = 30 mA w/ 2:1 Transformer G008 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 100 200 300 400 500 600 Frequency (MHz) Power (dBm) NCO Bypassed QMC Bypassed fDAC = 1250 MSPS fOUT = 20 MHz G009 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 100 200 300 400 500 600 Frequency (MHz) Power (dBm) NCO Bypassed QMC Bypassed fDAC = 1250 MSPS fOUT = 70 MHz G010 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 100 200 300 400 500 600 Frequency (MHz) Power (dBm) fDAC = 1250 MSPS fOUT = 150 MHz G011 −90 −80 −70 −60 −50 −40 −30 −20 −10 10 110 210 310 410 510 610 Frequency (MHz) Power (dBm) fDAC = 1250 MSPS fOUT = 200 MHz G012 DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltage,fDAC = 1250 MSPS, 4x interpolation,NCO enabled,MixerGain disabled,QMC enabledwithgainsetat1446 forbothI/Qchannels,0 dBFS digitalinput,20 mA full-scaleoutputcurrentwith4:1transformer (unlessotherwisenoted) Figure7.SFDR vs Output Frequency Over fDAC Figure8.SFDR vs Output Frequency Over IOUT FS Figure9.SingleTone SpectralPlot Figure10.SingleTone SpectralPlot Figure11.SingleTone SpectralPlot Figure12.SingleTone SpectralPlot

14 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

−90 −80 −70 −60 −50 −40 −30 −20 −10 10 110 210 310 410 510 610 Frequency (MHz) Power (dBm) PLL Enabled w/ PFD of 78.125 MHz fDAC = 1250 MSPS fOUT = 200 MHz G013 100 0 100 200 300 400 500 600 Output Frequency (MHz) IMD3 (dBc) 0 dBFS −6 dBFS −12 dBFS G014 100 0 100 200 300 400 500 600 Output Frequency (MHz) IMD3 (dBc) fDATA = 312.5 MSPS, 1x Interpolation fDATA = 312.5 MSPS, 2x Interpolation fDATA = 312.5 MSPS, 4x Interpolation fDATA = 156.25 MSPS, 8x Interpolation fDATA = 78.125 MSPS, 16x Interpolation G015 100 0 100 200 300 400 500 600 Output Frequency (MHz) IMD3 (dBc) fDAC = 600 MSPS fDAC = 800 MSPS fDAC = 1000 MSPS fDAC = 1250 MSPS G016 100 0 50 100 150 200 250 300 350 400 Output Frequency (MHz) IMD3 (dBc) IOUT FS = 10 mA w/ 4:1 Transformer IOUT FS = 20 mA w/ 4:1 Transformer IOUT FS = 30 mA w/ 2:1 Transformer G017 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 65 66 67 68 69 70 71 72 73 74 75 Frequency (MHz) Power (dBm) NCO Bypassed QMC Bypassed fDAC = 1250 MSPS fOUT = 70 MHz Tone Spacing = 1 MHzG018 DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltage,fDAC = 1250 MSPS, 4x interpolation,NCO enabled,MixerGain disabled,QMC enabledwithgainsetat1446 forbothI/Qchannels,0 dBFS digitalinput,20 mA full-scaleoutputcurrentwith4:1transformer (unlessotherwisenoted) Figure13.SingleTone SpectralPlot Figure14.IMD3 vs Output Frequency Over InputScale Figure15.IMD3 vs Output Frequency Over Interpolation Figure16.IMD3 vs Output Frequency Over fDAC Figure17.IMD3 vs Output Frequency Over IOUT FS Figure18.Two Tone SpectralPlot Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):DAC3482

−100 −90 −80 −70 −60 −50 −40 −30 −20 −10 195 196 197 198 199 200 201 202 203 204 205 Frequency (MHz) Power (dBm) fDAC = 1250 MSPS fOUT = 200 MHz Tone Spacing = 1 MHz G019 130 135 140 145 150 155 160 165 170 0 100 200 300 400 500 600 Output Frequency (MHz) NSD (dBc/Hz) 0 dBFS −6 dBFS −12 dBFS G020 130 135 140 145 150 155 160 165 170 0 100 200 300 400 500 600 Output Frequency (MHz) NSD (dBc/Hz) fDATA = 312.5 MSPS, 1x Interpolation fDATA = 312.5 MSPS, 2x Interpolation fDATA = 312.5 MSPS, 4x Interpolation fDATA = 156.25 MSPS, 8x Interpolation fDATA = 78.125 MSPS, 16x Interpolation G021 130 135 140 145 150 155 160 165 170 0 100 200 300 400 500 600 Output Frequency (MHz) NSD (dBc/Hz) fDAC = 600 MSPS fDAC = 800 MSPS fDAC = 1000 MSPS fDAC = 1250 MSPS G022 130 135 140 145 150 155 160 165 170 0 50 100 150 200 250 300 350 400 Output Frequency (MHz) NSD (dBc/Hz) IOUT FS = 10 mA w/ 4:1 Transformer IOUT FS = 20 mA w/ 4:1 Transformer IOUT FS = 30 mA w/ 2:1 Transformer G023 130 135 140 145 150 155 160 165 170 0 100 200 300 400 500 600 Output Frequency (MHz) NSD (dBc/Hz) PLL Bypassed PLL Enabled w/ PFD of 78.125 MHz G024 DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltage,fDAC = 1250 MSPS, 4x interpolation,NCO enabled,MixerGain disabled,QMC enabledwithgainsetat1446 forbothI/Qchannels,0 dBFS digitalinput,20 mA full-scaleoutputcurrentwith4:1transformer (unlessotherwisenoted) Figure19.Two Tone SpectralPlot Figure20.NSD vs Output Frequency Over InputScale Figure21.NSD vs Output Frequency Over Interpolation Figure22.NSD vs Output Frequency Over fDAC Figure23.NSD vs Output Frequency Over IOUT FS Figure24.NSD vs Output Frequency Over Clocking Options

16 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

Output Frequency (MHz) ACLR (dBc) PLL Disabled PLL Enabled G025 0 100 200 300 400 500 600 Output Frequency (MHz) ACLR (dBc) PLL Disabled PLL Enabled G026 4x Interpolation, 0 dBFS f = 1228.8 MSPS f = 70 MHz DAC OUT G027 4x Interpolation, 0 dBFS f = 1228.8 MSPS f = 120 MHz DAC OUT G028 4x Interpolation, 0 dBFS f = 1228.8 MSPS f = 200 MHz DAC OUT G029 4x Interpolation, 0 dBFS f = 1228.8 MSPS f = 70 MHz DAC OUT G030 DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltage,fDAC = 1250 MSPS, 4x interpolation,NCO enabled,MixerGain disabled,QMC enabledwithgainsetat1446 forbothI/Qchannels,0 dBFS digitalinput,20 mA full-scaleoutputcurrentwith4:1transformer (unlessotherwisenoted) Figure25.SingleCarrierWCDMA ACLR (Adjacent)vs Figure26.SingleCarrierWCDMA ACLR (Alternate)vs Output Frequency Over ClockingOptions Output Frequency Over ClockingOptions Figure27. SingleCarrierW-CDMA TestModel 1 Figure28. SingleCarrierW-CDMA TestModel 1 Figure29.SingleCarrierW-CDMA TestModel 1 Figure30.Four CarrierW-CDMA TestModel 1 Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):DAC3482

4x Interpolation, 0 dBFS f = 1228.8 MSPS f = 120 MHz DAC OUT G031 4x Interpolation, 0 dBFS f = 1228.8 MSPS f = 200 MHz DAC OUT G032 4x Interpolation, 0 dBFS f = 1228.8 MSPS f = 140 MHz DAC OUT G033 4x Interpolation, 0 dBFS f = 1228.8 MSPS f = 240 MHz DAC OUT G034 4x Interpolation, 0 dBFS f = 1228.8 MSPS f = 140 MHz DAC OUT G035 4x Interpolation, 0 dBFS f = 1228.8 MSPS f = 240 MHz DAC OUT G036 DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltage,fDAC = 1250 MSPS, 4x interpolation,NCO enabled,MixerGain disabled,QMC enabledwithgainsetat1446 forbothI/Qchannels,0 dBFS digitalinput,20 mA full-scaleoutputcurrentwith4:1transformer (unlessotherwisenoted) Figure31. Four CarrierW-CDMA TestModel 1 Figure32.Four CarrierW-CDMA TestModel 1 Figure33.10 MHz SingleCarrierLTE TestModel 3.1 Figure34.10 MHz SingleCarrierLTE TestModel 3.1 Figure35.20 MHz SingleCarrierLTE TestModel 3.1 Figure36. 20 MHz SingleCarrierLTE TestModel 3.1

18 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

0 200 400 600 800 1000 1200 fDAC (MSPS) Power Consumption (mW) 1x Interpolation 2x Interpolation 4x Interpolation 8x Interpolation 16x Interpolation Bandbase Input = 5 MHz NCO Disabled QMC Disabled CMIX Disabled G037 100 200 300 400 500 600 700 800 0 200 400 600 800 1000 1200 fDAC (MSPS) Power Consumption (mW) 1x Interpolation 2x Interpolation 4x Interpolation 8x Interpolation 16x Interpolation Bandbase Input = 0 MHz NCO Enabled w/ 5 MHz Mixing QMC Enabled G038 0 200 400 600 800 1000 1200 fDAC (MSPS) Power Consumption (mW) NCO Enabled QMC Enabled G039 100 150 200 250 300 350 400 450 500 0 200 400 600 800 1000 1200 fDAC (MSPS) DIGVDD Current (mA) 1x Interpolation 2x Interpolation 4x Interpolation 8x Interpolation 16x Interpolation Bandbase Input = 5 MHz NCO Disabled QMC Disabled CMIX Disabled G040 100 150 200 250 300 350 400 0 200 400 600 800 1000 1200 fDAC (MSPS) DIGVDD Current (mA) 1x Interpolation 2x Interpolation 4x Interpolation 8x Interpolation 16x Interpolation Bandbase Input = 0 MHz NCO Enabled w/ 5 MHz Mixing QMC Enabled G041 0 200 400 600 800 1000 1200 fDAC (MSPS) DIGVDD Current (mA) NCO Enabled QMC Enabled G042 DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltage,fDAC = 1250 MSPS, 4x interpolation,NCO enabled,MixerGain disabled,QMC enabledwithgainsetat1446 forbothI/Qchannels,0 dBFS digitalinput,20 mA full-scaleoutputcurrentwith4:1transformer (unlessotherwisenoted) Figure37.Power Consumption vs fDAC Over Interpolation Figure38.Power Consumption vs fDAC Over Interpolation Figure39.Power Consumption vs fDAC Over Digital Figure40.DIGVDD Currentvs fDAC Over Interpolation ProcessingFunctions Figure41.DIGVDD Currentvs fDAC Over Interpolation Figure42.DIGVDD Currentvs fDAC Over Digital ProcessingFunctions Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):DAC3482

0 200 400 600 800 1000 1200 fDAC (MSPS) DACVDD Current (mA) G043 100 0 200 400 600 800 1000 1200 fDAC (MSPS) CLKVDD Current (mA) G044 100 0 200 400 600 800 1000 1200 fDAC (MSPS) AVDD Current (mA) G045 100 110 120 0 50 100 150 200 250 Output Frequency (MHz) Isolation Level (dBc) G046 DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltage,fDAC = 1250 MSPS, 4x interpolation,NCO enabled,MixerGain disabled,QMC enabledwithgainsetat1446 forbothI/Qchannels,0 dBFS digitalinput,20 mA full-scaleoutputcurrentwith4:1transformer (unlessotherwisenoted) Figure43.DACVDD Currentvs fDAC Figure44.CLKVDD Currentvs fDAC Figure45.AVDD Currentvs fDAC Figure46.IsolationLevelvs Output Frequency

20 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 DEFINITION OF SPECIFICATIONS Adjacent CarrierLeakage Ratio(ACLR): Definedfora 3.84Mcps 3GPP W-CDMA inputsignalmeasured ina 3.84MHz bandwidthata 5MHz offsetfromthecarrierwitha 12dB peak-to-averageratio. Analog and DigitalPower Supply RejectionRatio(APSSR, DPSSR): Definedas thepercentageerrorinthe ratioofthedeltaIOUT and deltasupplyvoltagenormalizedwithrespecttotheidealIOUT current. DifferentialNonlinearity(DNL): Definedas the variationin analog outputassociatedwithan ideal1 LSB change inthedigitalinputcode. Gain Drift:Definedas themaximum change ingain,intermsofppm offull-scalerange(FSR) per°C, fromthe valueatambient(25°C) tovaluesoverthefulloperatingtemperaturerange. Gain Error:Definedas the percentageerror(inFSR%) forthe ratiobetween the measured full-scaleoutput currentand theidealfull-scaleoutputcurrent. IntegralNonlinearity(INL):Definedas themaximum deviationoftheactualanalogoutputfromtheidealoutput, determinedby a straightlinedrawn fromzeroscaletofullscale. IntermodulationDistortion(IMD3):The two-toneIMD3 is definedas the ratio(indBc) of the 3rd-order intermodulationdistortionproducttoeitherfundamentaloutputtone. OffsetDrift:Definedas themaximum change inDC offset,intermsofppm offull-scalerange (FSR) per °C, fromthevalueatambient(25°C) tovaluesoverthefulloperatingtemperaturerange. OffsetError:Definedas thepercentageerror(inFSR%) fortheratiobetween themeasured mid-scaleoutput currentand theidealmid-scaleoutputcurrent. Output Compliance Range: Definedas the minimum and maximum allowablevoltageat the outputof the current-outputDAC. Exceeding thislimitmay resultreduced reliabilityof the deviceor adverselyaffecting distortionperformance. Reference VoltageDrift:Definedas themaximum change ofthereferencevoltageinppm perdegreeCelsius fromvalueatambient(25°C) tovaluesoverthefulloperatingtemperaturerange. Spurious Free Dynamic Range (SFDR): Definedas thedifference(indBc) between thepeak amplitudeofthe outputsignaland thepeak spurioussignalwithinthefirstNyquistzone. Noise SpectralDensity (NSD): Definedas the differenceof power (indBc) between the outputtone signal power and thenoisefloorof1Hz bandwidthwithinthefirstNyquistzone. SERIAL INTERFACE The serialportof the DAC3482 is a flexibleserialinterfacewhich communicates with industrystandard microprocessorsand microcontrollers.The interfaceprovidesread/writeaccesstoallregistersused todefinethe operatingmodes ofDAC3482. Itiscompatiblewithmost synchronoustransferformatsand can be configuredas a 3 or 4 pininterfaceby sif4_enainregisterconfig2.Inbothconfigurations,SCLK istheserialinterfaceinput clockand SDENB isserialinterfaceenable.For 3 pinconfiguration,SDIO isa bidirectionalpinforbothdatain and dataout.For4 pinconfiguration,SDIO isdatainonlyand SDO isdataoutonly.Data isinputintothedevice withtherisingedge ofSCLK. Data isoutputfromthedeviceon thefallingedge ofSCLK. Each read/writeoperationisframedby signalSDENB (SerialData EnableBar)assertedlow.The firstframebyte isthe instructioncyclewhich identifiesthe followingdata transfercycleas read or writeas wellas the 7-bit addresstobe accessed.Table1 below indicatesthefunctionofeach bitintheinstructioncycleand isfollowed by a detaileddescriptionofeach bit.The datatransfercycleconsistsoftwo bytes. Table1.InstructionByte oftheSerialInterface MSB LSB Bit 7 6 5 4 3 2 1 0 Description R/W A6 A5 A4 A3 A2 A1 A0 Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com R/W Identifiesthefollowingdatatransfercycleas a readorwriteoperation.A highindicatesa read operationfromDAC3482 and a lowindicatesa writeoperationtoDAC3482. [A6 :A0] Identifiestheaddressoftheregistertobe accessedduringthereadorwriteoperation.

22 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

rwb A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 tS(SDENB) tH(SDIO) tS(SDIO) SDENB SCLK SDIO SDENB SCLK SDIO Instruction Cycle Data Transfer Cycle T0521-01 t(SCLK) DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Figure47 shows the serialinterfacetimingdiagram fora DAC3482 writeoperation.SCLK isthe serialinterfaceclockinputto DAC3482. Serialdata enableSDENB isan activelowinputtoDAC3482. SDIO isserialdatain.InputdatatoDAC3482 isclockedon therisingedges ofSCLK. Figure47. SerialInterfaceWriteTiming Diagram Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):DAC3482

rwb A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 td(Data) SDENB SCLK SDIO SDO SDENB SCLK Instruction Cycle Data Transfer Cycle T0522-01 SDIO SDO Data n – 1Data n DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com Figure48 shows the serialinterfacetimingdiagram fora DAC3482 read operation.SCLK isthe serialinterfaceclockinputto DAC3482. Serialdata enableSDENB isan activelow inputtoDAC3482. SDIO isserialdatainduringtheinstructioncycle.In3 pinconfiguration,SDIO isdataoutfrom the DAC3482 duringthedatatransfercycle,whileSDO isina high-impedancestate.In4 pinconfiguration,SDO isdataoutfromtheDAC3482 duringthe datatransfercycle.At theend ofthedatatransfer,SDIO and SDO willoutputlow on thefinalfallingedge ofSCLK untiltherisingedge ofSDENB when theywill3-state. Figure48. SerialInterfaceRead Timing Diagram

24 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Table2.RegisterMap (1) (MSB) (LSB)Name Address Default Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1Bit15 Bit0 qmc_offset_ qmc_corr_ alarm_out alarm_out clkdiv_sync_config0 0x00 0x049C reserved reserved interp(3:0) fifo_ena reserved reserved invsinc_ena reservedena ena _ ena pol ena word_ frame_ alarm_ alarm_ alarm_64cnt_ oddeven_ dacI_ dacQ_config1 0x01 0x050E iotest_ena reserved reserved parity_ parity_e reserved reserved reserved 2away_ 1away_ collision_ reservedparity complement complementena ena na ena ena ena dacclk dataclk collision_config2 0x02 0x7000 16bit_in resreved reserved reserved reserved sif4_ena mixer_ena mixer_gain nco_ena revbus reserved twos reservedgone_ena gone_ena gone_ena config3 0x03 0xF000 coarse_dac(3:0) reserved reserved sif_txenable config4 0x04 NA iotest_results(15:0) alarm_ alarm_alarm_ alarm_ alarm_ alarm_alarm_ alarm_ alarm_dacclk_ dataclk_ output_config5 0x05 0x0000 from_ reserved alarms_from_fifo(2:0) from_ reserved reserved reservedfrom_pll rparity frame_parityfparitygone gone gonezerochk iotest config6 0x06 NA tempdata(7:0) reserved reserved reserved config7 0x07 0xFFFF alarms_mask(15:0) config8 0x08 0x0000 reserved reserved reserved qmc_offsetI(12:0) config9 0x09 0x8000 fifo_offset(2:0) qmc_offsetQ(12:0) config10 0x0A 0x0000 reserved reserved reserved reserved config11 0x0B 0x0000 reserved reserved reserved reserved config12 0x0C 0x0400 reserved reserved reserved reserved reserved qmc_gainI(10:0) config13 0x0D 0x0400 cmix(3:0) reserved qmc_gainQ(10:0) config14 0x0E 0x0400 reserved reserved reserved reserved reserved reserved config15 0x0F 0x0400 output_delay(1:0) reserved reserved reserved config16 0x10 0x0000 reserved reserved reserved reserved qmc_phase(11:0) config17 0x11 0x0000 reserved reserved reserved reserved reserved config18 0x12 0x0000 phase_offset(15:0) config19 0x13 0x0000 reserved config20 0x14 0x0000 phase_add(15:0) config21 0x15 0x0000 phase_add(31:16) config22 0x16 0x0000 reserved config23 0x17 0x0000 reserved pll_ config24 0x18 NA reserved pll_reset ndivsync_ pll_ena reserved pll_cp(1:0) pll_p(2:0) pll_lfvolt(2:0) ena config25 0x19 0x0440 pll_m(7:0) pll_n(3:0) pll_vcoitune(2:0) reserved bias_ tsense_ clkrecv_config26 0x1A 0x0020 pll_vco(5:0) reserved reserved pll_sleep reserved reserved reserved reservedsleep sleep sleep fuse_config27 0x1B 0x0000 extref_ena reserved reserved reserved reserved reserved reserved reserved reserved reservedsleep config28 0x1C 0x0000 reserved reserved config29 0x1D 0x0000 reserved reserved config30 0x1E 0x1111 syncsel_qmoffset(3:0) reserved syncsel_qmcorr(3:0) reserved (1) Unlessotherwisenoted,allreservedregistersshouldbe programmed todefaultvalues. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com Table2.RegisterMap (1)(continued) (MSB) (LSB)Name Address Default Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1Bit15 Bit0 config31 0x1F 0x1140 syncsel_mixer(3:0) reserved syncsel_nco(3:0) syncsel_dataformatter sif_sync reserved clkdiv_config32 0x20 0x2400 syncsel_fifoin(3:0) syncsel_fifoout(3:0) reserved sync_sel config33 0x21 0x0000 reserved config34 0x22 0x1B1B reserved reserved reserved reserved reserved reserved reserved reserved config35 0x23 0xFFFF sleep_cntl(15:0) config36 0x24 0x0000 datadly(2:0) clkdly(2:0) reserved config37 0x25 0x7A7A iotest_pattern0 config38 0x26 0xB6B6 iotest_pattern1 config39 0x27 0xEAEA iotest_pattern2 config40 0x28 0x4545 iotest_pattern3 config41 0x29 0x1A1A iotest_pattern4 config42 0x2A 0x1616 iotest_pattern5 config43 0x2B 0xAAAA iotest_pattern6 config44 0x2C 0xC6C6 iotest_pattern7 ostrtodig_config45 0x2D 0x0004 reserved ramp_ena reserved sifdac_enasel config46 0x2E 0x0000 reserved grp_delayI(7:0) config47 0x2F 0x0000 grp_delayQ(7:0) reserved config48 0x30 0x0000 sifdac(15:0) version 0x7F 0x5409 reserved reserved reserved reserved deviceid(1:0) versionid(2:0)

26 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 REGISTER DESCRIPTIONS Registername: config0– Address: 0x00,Default:0x049C Register DefaultAddress Bit Name FunctionName Value config0 0x00 15 qmc_offset_ena When set,thedigitalQuadratureModulatorCorrection(QMC) offset 0 correctionisenabled. 14 Reserved Reservedforfactoryuse. 0 13 qmc_corr_ena When set,theQMC phase and gaincorrectioncircuitryisenabled. 0 12 Reserved Reservedforfactoryuse. 0 11:8 interp(3:0) These bitsdefinetheinterpolationfactor 0100 interp InterpolationFactor 0000 1x 0001 2x 0010 4x 0100 8x 1000 16x 7 fifo_ena When set,theFIFO isenabled.When theFIFO isdisabled 1 DACCCLKP/N and DATACLKP/N must be aligned(not recommended). 6 Reserved Reservedforfactoryuse. 0 5 Reserved Reservedforfactoryuse. 0 4 alarm_out_ena When set,theALARM pinbecomes an output.When cleared,the 1 ALARM pinis3-stated. 3 alarm_out_pol Thisbitchanges thepolarityoftheALARM signal. 1 MM 0:Negativelogic MM 1:Positivelogic 2 clkdiv_sync_ena When set,enablesthesyncingoftheclockdividerusingthesync 1 sourceselectedby registerconfig32.The internaldivided-down clockswillbe phase alignedaftersyncing.See thePower-Up Sequence sectionformore detail. 1 invsinc_ena When set,theinversesincfilterisenabled. 0 0 Reserved Reservedforfactoryuse. 0 Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com Registername: config1– Address: 0x01,Default:0x050E Register DefaultAddress Bit Name FunctionName Value config1 0x01 15 iotest_ena When set,enablesthedatapatterncheckertest.The outputsare 0 deactivatedregardlessofthestateofTXENABLE and sif_txenable. 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12 64cnt_ena When set,enablesresettingofthealarmsafter64 good samples 0 withthegoalofremovingunnecessaryerrors.Forinstance,when checkingsetup/holdthroughthepatterncheckertest,theremay initiallybe errors.Settingthisbitremoves theneed fora SIF writeto clearthealarmregister. 11 oddeven_parity Selectsbetween odd and even paritycheck 0 MM 0:Even parity MM 1:Odd parity 10 word_parity_ena When set,enablesparitycheckingofeach inputword usingthe 1 PARITYP/N parityinput.Itshouldmatch theoddeven_parity registersetting. 9 frame_parity_ena When set,enablesparitycheckingusingtheFRAME signalto 0 sourcetheparitybit. 8 Reserved Reservedforfactoryuse. 1 Note:Defaultvalueis‘1’.Must be setto ‘0’ forproperoperation 7 Reserved Reservedforfactoryuse. 0 6 dacI_complement When set,theDACI outputiscomplemented.Thisallowsto 0 effectivelychange the+ and – designationsoftheLVDS datalines. 5 dacQ_complement When set,theDACQ outputiscomplemented.Thisallowsto 0 effectivelychange the+ and – designationsoftheLVDS datalines. 4 Reserved Reservedforfactoryuse. 0 3 alarm_2away_ena When set,thealarmfromtheFIFO indicatingthewriteand read 1 pointersbeing2 away isenabled. 2 alarm_1away_ena When set,thealarmfromtheFIFO indicatingthewriteand read 1 pointersbeing1 away isenabled. 1 alarm_collision_ena When set,thealarmfromtheFIFO indicatinga collisionbetween the 1 writeand readpointersisenabled. 0 Reserved Reservedforfactoryuse. 0

28 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

/c40 /c41EXTIO FS BIAS VI 2 coarse _ dac 1R/c61 /c180 /c180 /c43 DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Registername: config2– Address: 0x02,Default:0x7000 Register DefaultAddress Bit Name FunctionName Value config2 0x02 15 16bit_in When set,theinputinterfaceissettoword-widemode. 0 When cleared,theinputinterfaceissettobyte-widemode. 14 dacclkgone_ena When set,theDACCLK-gone signalfromtheclockmonitorcircuitcan 1 be used toshutofftheDAC outputs.The correspondingalarms, alarm_dacclk_goneand alarm_output_gone,must notbe masked (i.e.Config7,bit<10> and bit<8> must setto"0"). 13 dataclkgone_ena When set,theDATACLK-gone signalfromtheclockmonitorcircuit 1 can be used toshutofftheDAC outputs.The correspondingalarms, alarm_dataclk_goneand alarm_output_gone,must notbe masked (i.e.Config7,bit<9> and bit<8> must setto"0"). 12 collisiongone_ena When set,theFIFO collisionalarmscan be used toshutofftheDAC 1 outputs.The correspondingalarms,alarm_fifo_collisionand alarm_output_gone,must notbe masked (i.e.Config7,bit<13> and bit<8> must setto"0"). 11 Reserved Reservedforfactoryuse. 0 10 Reserved Reservedforfactoryuse. 0 9 Reserved Reservedforfactoryuse. 0 8 Reserved Reservedforfactoryuse. 0 7 sif4_ena When set,theserialinterface(SIF)isa 4 bitinterface,otherwiseitis 0 a 3 bitinterface. 6 mixer_ena When set,themixerblockisenabled. 0 5 mixer_gain When set,a 6dB gainisadded tothemixeroutput. 0 4 nco_ena When set,theNCO isenabled.Thisisnotrequiredforcoarsemixing. 0 3 revbus When set,theinputbitsforthedatabus arereversed.MSB becomes 0 LSB. 2 Reserved Reservedforfactoryuse. 0 1 twos When set,theinputdataformatisexpectedtobe 2’s complement. 0 When cleared,theinputisexpectedtobe offset-binary. 0 Reserved Reservedforfactoryuse. 0 Registername: config3– Address: 0x03,Default:0xF000 Register DefaultAddress Bit Name FunctionName Value config3 0x03 15:12 coarse_dac(3:0) Scalestheoutputcurrentin16 equalsteps. 1111 11:8 Reserved Reservedforfactoryuse. 0000 7:1 Reserved Reservedforfactoryuse. 0000000 0 sif_txenable When set,theinternalvalueofTXENABLE issetto“1”. 0 To enableanalogoutputdatatransmission,setsif_txenableto“1” or pullCMOS TXENABLE pin(A32)tohigh.To disableanalogoutput, setsif_txenableto“0” and pullCMOS TXENABLE pin(A32)tolow. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com Registername: config4– Address: 0x04,Default:No RESET Value (WRITE TO CLEAR) Register DefaultAddress Bit Name FunctionName Value config4 0x04 15:0 iotest_results(15:0) Thisregisterisused withpatterncheckertestenabled(iotest_enainconfig1, No RESET bit<15> setto“1”).Itdoes nothave a defaultRESET value. Value The valuesofthesebitstellwhichbitintheword failedduringthepattern checkertest.iotest_results(15:8)correspondtothedatabitson D[15:8]and iotest_results(7:0)correspondtothedatabitson D[7:0]. Registername: config5– Address: 0x05,Default:Setup and Power-Up ConditionsDependent (WRITE TO CLEAR) Register Address DefaultBit Name FunctionName Value config5 0x05 15 alarm_from_zerochk Thisalarmindicatesthe8-bitFIFO writepointeraddresshas an all NA zerospatterns.Due topointeraddressbeinga shiftregister,thisis nota validaddressand willcause thewritepointertobe stuckuntil thenextsync.Thiserroristypicallycaused by timingerroror improperpower start-upsequence.Ifthisalarmisasserted, resynchronizationofFIFO isnecessary.RefertothePower-Up Sequence sectionformore detail. 14 Reserved Reservedforfactoryuse. NA 13:11 alarms_from_fifo(2:0) AlarmindicatingFIFO pointercollisionsand nearness: NA MM 000:Allfine MM 001:Pointersare2 away MM 01x:Pointersare1 away MM 1xx:FIFO pointercollision IftheFIFO pointercollisionalarmissetwhen collisiongone_enais enabled,theFIFO must be re-synchronizedand thebitsmust be clearedtoresume normaloperation. 10 alarm_dacclk_gone AlarmindicatingtheDACCLK has been stopped.Ifthebitisset NA when dacclkgone_enaisenabled,theDACCLK must resume and thebitmust be clearedtoresume normaloperation. 9 alarm_dataclk_gone AlarmindicatingtheDATACLK has been stopped. NA Ifthebitissetwhen dataclkgone_enaisenabled,theDATACLK must resume and thebitmust be clearedtoresume normal operation. 8 alarm_output_gone Alarmindicatingeitheralarm_dacclk_gone,alarm_dataclk_gone,or NA alarm_fifo_collisionareasserted.Itcontrolstheoutput.When highit willoutput"0x8000"foreach outputconnectedtotheDAC. Ifthebit issetwhen dacclkgone_ena,dataclkgone_ena,or collisiongone_enaareenabled,thenthecorrespondingerrorsmust be fixedand thebitsmust be clearedtoresume normaloperation. 7 alarm_from_iotest Alarmindicatingtheinputdatapatterndoes notmatch thepatternin NA theiotest_patternregisters.When datapatterncheckermode is enabled,thisalarminregisterconfig5,bit7istheonlyvalidalarm. Otheralarmsinregisterconfig5arenotvalidand can be disregarded. 6 Reserved Reservedforfactoryuse. NA 5 alarm_from_pll AlarmindicatingthePLL has lostlock.ForversionID "100"or NA earlier,alarm_from_PLLmay notindicatethecorrectstatusofthe PLL.Refertopll_lfvolt(2:0)inregisterconfig24forproperPLL lock indication. 4 alarm_rparity Alarmindicatinga parityerroron datacapturedon therisingedge NA ofDATACLKP/N. 3 alarm_fparity Alarmindicatinga parityerroron datacapturedon thefallingedge NA ofDATACLKP/N. 2 alarm_frame_parity Alarmindicatinga parityerrorwhen usingtheFRAME as paritybit. NA 1 Reserved Reservedforfactoryuse. NA 0 Reserved Reservedforfactoryuse. NA

30 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Registername: config6– Address: 0x06,Default:No RESET Value (READ ONLY) Register DefaultAddress Bit Name FunctionName Value config6 0x06 15:8 tempdata(7:0) Thisistheoutputfromthechiptemperaturesensor.The valueofthisregisterin No two’s complement formatrepresentsthetemperatureindegreesCelsius.This RESET registermust be read witha minimum SCLK periodof1μs. Value 7:2 Reserved Reservedforfactoryuse. 000000 1 Reserved Reservedforfactoryuse. 0 0 Reserved Reservedforfactoryuse. 0 Registername: config7– Address: 0x07,Default:0xFFFF Register DefaultAddress Bit Name FunctionName Value config7 0x07 15:0 alarms_mask(15:0) These bitscontrolthemaskingofthealarms.(0=notmasked, 1= masked) 0xFFFF alarm_mask Alarm thatisMasked 15 alarm_from_zerochk 14 notused 13 alarm_fifo_collision 12 alarm_fifo_1away 11 alarm_fifo_2away 10 alarm_dacclk_gone 9 alarm_dataclk_gone 8 alarm_output_gone 7 alarm_from_iotest 6 notused 5 alarm_from_pll 4 alarm_rparity 3 alarm_lparity 2 alarm_frame_parity 1 notused 0 notused Registername: config8– Address: 0x08,Default:0x0000 (CAUSES AUTO-SYNC) Register DefaultAddress Bit Name Function ValueName config8 0x08 15 Reserved Reservedforfactoryuse. 0 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12:0 qmc_offsetI(12:0) DACI offsetcorrection.The offsetismeasured inDAC LSBs. Ifenabled inconfig30 Allzeros writingtothisregistercauses an auto-synctobe generated.Thisloadsthevaluesof theQMC offsetregisters(config8-config9)intotheoffsetblockatthesame time. When updatingtheoffsetvaluesconfig8should be writtenlast.Programming config9willnot affecttheoffsetsetting. Registername: config9– Address: 0x09,Default:0x8000 Register DefaultAddress Bit Name Function ValueName config9 0x09 15:13 fifo_offset(2:0) When thesynctotheFIFO occurs,thisisthevalueloadedintotheFIFO readpointer.With 100 thisvaluetheinitialdifferencebetween writeand readpointerscan be controlled.Thismay be helpfulinsyncingmultiplechipsorcontrollingthedelaythroughthedevice. 12:0 qmc_offsetQ(12:0) DACQ offsetcorrection.The offsetismeasured inDAC LSBs. Allzeros Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com Registername: config10– Address: 0x0A, Default:0x0000 Register DefaultAddress Bit Name Function ValueName config10 0x0A 15 Reserved Reservedforfactoryuse. 0 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12:0 Reserved Reservedforfactoryuse. Allzeros Registername: config11– Address: 0x0B, Default:0x0000 Register DefaultAddress Bit Name Function ValueName config10 0x0A 15 Reserved Reservedforfactoryuse. 0 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12:0 Reserved Reservedforfactoryuse. Allzeros Registername: config12– Address: 0x0C, Default:0x0400 Register DefaultAddress Bit Name Function ValueName config12 0x0C 15 Reserved Reservedforfactoryuse. 0 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12 Reserved Reservedforfactoryuse. 0 11 Reserved Reservedforfactoryuse. 0 10:0 qmc_gainI(10:0) QMC gainforDACI. The full11-bitqmc_gainI(10:0)word isformattedas UNSIGNED 10000000 witha rangeof0 to1.9990.The implieddecimalpointforthemultiplicationisbetween bit 000 9 and bit10. Registername: config13– Address: 0x0D, Default:0x0400 Register DefaultAddress Bit Name Function ValueName config13 0x0D 15 cmix_mode(3:0) Setsthemixingfunctionofthecoarsemixer. 0000 MM Bit15:Fs/8mixer MM Bit14:Fs/4mixer MM Bit13:Fs/2mixer MM Bit12:-Fs/4mixer The variousmixerscan be combined togethertoobtaina ±n×Fs/8totalmixingfactor. 11 Reserved Reservedforfactoryuse. 0 10:0 qmc_gainQ(10:0) QMC gainforDACQ. The full11-bitqmc_gainb(10:0)word isformattedas UNSIGNED 10000000 witha rangeof0 to1.9990.The implieddecimalpointforthemultiplicationisbetween 000 bit9 and bit10. Registername: config14– Address: 0x0E,Default:0x0400 Register DefaultAddress Bit Name Function ValueName config14 0x0E 15 Reserved Reservedforfactoryuse. 0 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12 Reserved Reservedforfactoryuse. 0 11 Reserved Reservedforfactoryuse. 0 10:0 Reserved Reservedforfactoryuse. 10000000 000

32 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Registername: config15– Address: 0x0F,Default:0x0400 Register DefaultAddress Bit Name Function ValueName config15 0x0F 15:14 output_delay(1:0) DelaystheDAC outputsfrom0 to3 DAC clockcycles. 00 13:12 Reserved Reservedforfactoryuse. 00 11 Reserved Reservedforfactoryuse. 0 10:0 Reserved Reservedforfactoryuse. 10000000 000 Registername: config16– Address: 0x10,Default:0x0000 (CAUSES AUTO-SYNC) Register DefaultAddress Bit Name Function ValueName config16 0x10 15 Reserved Reservedforfactoryuse. 0 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse.Note:Defaultvalueis‘0’.Must be setto‘1’ forproper 0 operation 12 Reserved Reservedforfactoryuse.Note:Defaultvalueis‘0’.Must be setto‘1’ forproper 0 operation 11:0 qmc_phase(11:0) QMC correctionphase.The 12-bitqmc_phase(11:0)word isformattedas two’s Allzeros complement and scaledtooccupya rangeof-0.5to0.49975and a defaultphase correctionof0.00.To accomplishQMC phase correction,thisvalueismultipliedby thecurrentB sample,thensummed intotheA sample.Ifenabled inconfig30 writingtothisregistercauses an auto-synctobe generated.Thisloadsthe valuesoftheQMC offsetregisters(config12,config13,and config16)intothe QMC blockatthesame time.When updatingtheQMC valuesconfig16should be writtenlast.Programming config12and config13willnot affecttheQMC settings. Registername: config17– Address: 0x11,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config17 0x11 15 Reserved Reservedforfactoryuse. 0 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12 Reserved Reservedforfactoryuse. 0 11:0 Reserved Reservedforfactoryuse. Allzeros Registername: config18– Address: 0x12,Default:0x0000 (CAUSES AUTO-SYNC) Register DefaultAddress Bit Name Function ValueName config18 0x12 15:0 phase_offset(15:0) Phase offsetadded totheNCO accumulatorbeforethegenerationoftheSIN and 0x0000 COS values.The phase offsetisadded totheupper16 bitsoftheNCO accumulator resultsand these16 bitsareused inthesin/coslookuptables.Ifenabled in config31writingtothisregistercauses an auto-synctobe generated.This loadsthevaluesoftheQfinemixer blockregisters(config18,config20,and config21)atthesame time.When updatingthemixer valuestheconfig18 should be writtenlast.Programming config20and config21willnot affectthe mixer settings. Registername: config19– Address: 0x13,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config19 0x13 15:0 Reserved Reservedforfactoryuse. 0x0000 Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com Registername: config20– Address: 0x14,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config20 0x14 15:0 phase_ add(15:0) The phase_add(15:0)valueisused todeterminetheNCO frequency.The two’s 0x0000 complement formattedvaluecan be positiveornegative.Each LSB represents Fs/(2^32)frequencystep. Registername: config21– Address: 0x15,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config21 0x15 15:0 phase_ add(31:16) See config20above. 0x0000 Registername: config22– Address: 0x16,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config22 0x16 15:0 Reserved Reservedforfactoryuse. 0x0000 Registername: config23– Address: 0x17,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config23 0x17 15:0 Reserved Reservedforfactoryuse. 0x0000 Registername: config24– Address: 0x18,Default:NA Register DefaultAddress Bit Name Function ValueName config24 0x18 15:13 Reserved Reservedforfactoryuse. 001 12 pll_reset When set,thePLL loopfilter(LPF)ispulleddown to0V.Togglefrom‘1’ to‘0’ to 0 restartthePLL ifan over-speedlock-upoccurs.Over-speedcan happen when the processisfast,thesuppliesarehigherthannominal,etc.resultinginthefeedback dividersmissinga clock. 11 pll_ndivsync_ena When set,theLVDS SYNC inputisused tosyncthePLL N dividers. 1 10 pll_ena When set,thePLL isenabled.When cleared,thePLL isbypassed. 0 9:8 Reserved Reservedforfactoryuse. 00 7:6 pll_cp(1:0) PLL pump chargeselect 00 MM 00:No chargepump MM 01:Singlepump charge MM 10:Not used MM 11:Dualpump charge 5:3 pll_p(2:0) PLL pre-scalerdividingmodule control. 001 MM 010:2 MM 011:3 MM 100:4 MM 101:5 MM 110:6 MM 111:7 MM 000:8 2:0 pll_lfvolt(2:0) PLL loopfiltervoltage.Thisthreebitread-onlyindicatorhas stepsizeof0.4125V. NA The entirerangecoversfrom0V to3.3V.The optimallockrangeofthePLL willbe

34 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Registername: config25– Address: 0x19,Default:0x0440 Register DefaultAddress Bit Name Function ValueName config25 0x19 15:8 pll_m(7:0) M portionoftheM/N dividerofthePLL. 00000100 Ifpll_m<7> = 0,theM dividervaluehas therangeofpll_m<6:0>,spanningfrom 4 to127.(i.e.0,1,2,and 3 arenotvalid.) Ifpll_m<7> = 1,theM dividervaluehas therangeof2 × pll_m<6:0>,spanning 7:4 pll_n(3:0) N portionoftheM/N dividerofthePLL. 0100 MM 0000:1 MM 0001:2 MM 0010:3 MM 0011:4 MM 0100:5 MM 0101:6 MM 0110:7 MM 0111:8 MM 1000:9 MM 1001:10 MM 1010:11 MM 1011:12 MM 1100:13 MM 1101:14 MM 1110:15 MM 1111:16 3:2 pll_vcoitune(1:0) PLL VCO biastuningbits.Setto"01"fornormalPLL operation. 00 1:0 Reserved Reservedforfactoryuse. 00 Registername: config26– Address: 0x1A, Default:0x0020 Register DefaultAddress Bit Name Function ValueName config26 0x1A 15:10 pll_vco(6:0) VCO frequencycoarsetuningbits. 000000 9 Reserved Reservedforfactoryuse. 0 8 Reserved Reservedforfactoryuse. 0 7 bias_sleep When set,thebiasamplifierisputintosleepmode. 0 6 tsense_sleep Turnsoffthetemperaturesensorwhen asserted. 0 5 pll_sleep When set,thePLL isputintosleepmode. 1 4 clkrecv_sleep When assertedtheclockinputreceivergetsputintosleepmode. Thisaffectsthe 0 OSTR receiveras well. 3 Reserved Reservedforfactoryuse. 0 2 Reserved Reservedforfactoryuse. 0 1 Reserved Reservedforfactoryuse. 0 0 Reserved Reservedforfactoryuse. 0 Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com Registername: config27– Address: 0x1B, Default:0x0000 Register DefaultAddress Bit Name Function ValueName config27 0x1B 15 extref_ena Allowsthedevicetouse an externalreferenceortheinternalreference. 0 MM 0:Internalreference MM 1:Externalreference 14 Reserved Reservedforfactoryuse. 0 13 Reserved Reservedforfactoryuse. 0 12 Reserved Reservedforfactoryuse. 0 11 fuse_sleep Putsthefusestosleepwhen sethigh. 0 Note:Defaultvalueis‘0’.Must be setto‘1’ forproperoperation 10 Reserved Reservedforfactoryuse. 0 9 Reserved Reservedforfactoryuse. 0 8 Reserved Reservedforfactoryuse. 0 7 Reserved Reservedforfactoryuse. 0 6 Reserved Reservedforfactoryuse. 0 5:0 Reserved Reservedforfactoryuse. 000000 Registername: config28– Address: 0x1C, Default:0x0000 Register DefaultAddress Bit Name Function ValueName config28 0x1C 15:8 Reserved Reservedforfactoryuse. 0x00 7:0 Reserved Reservedforfactoryuse. 0x00 Registername: config29– Address: 0x1D, Default:0x0000 Register DefaultAddress Bit Name Function ValueName config29 0x1D 15:8 Reserved Reservedforfactoryuse. 0x00 7:0 Reserved Reservedforfactoryuse. 0x00 Registername: config30– Address: 0x1E,Default:0x1111 Register DefaultAddress Bit Name Function ValueName config30 0x1E 15:12 syncsel_qmoffset(3:0) Selectsthesyncingsource(s)ofthedoublebufferedQMC offsetregisters.A ‘1’ in 0001 thebitenablesthesignalas a syncsource.More thanone syncsourceis permitted. MM Bit15:sif_sync(viaconfig31) MM Bit14:SYNC MM Bit13:OSTR MM Bit12:Auto-syncfromregisterwrite 11:8 Reserved Reservedforfactoryuse. 0001 7:4 syncsel_qmcorr(3:0) Selectsthesyncingsource(s)ofthedoublebufferedQMC correctionregisters.A ‘1’ 0001 inthebitenablesthesignalas a syncsource.More thanone syncsourceis permitted. MM Bit7:sif_sync(viaconfig31) MM Bit6:SYNC MM Bit5:OSTR MM Bit4:Auto-syncfromregisterwrite 3:0 Reserved Reservedforfactoryuse. 0001

36 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Registername: config31– Address: 0x1F,Default:0x1140 Register DefaultAddress Bit Name Function ValueName config31 0x1F 15:12 syncsel_mixer(3:0) Selectsthesyncingsource(s)ofthedoublebufferedmixerregisters.A ‘1’ inthe 0001 bitenablesthesignalas a syncsource.More thanone syncsourceispermitted. MM Bit15:sif_sync(viaconfig31) MM Bit14:SYNC MM Bit13:OSTR MM Bit12:Auto-syncfromregisterwrite 11:8 Reserved Reservedforfactoryuse. 0001 7:4 syncsel_nco(3:0) Selectsthesyncingsource(s)ofthetwo NCO accumulators.A ‘1’ inthebit 0100 enablesthesignalas a syncsource.More thanone syncsourceispermitted. MM Bit7:sif_sync(viaconfig31) MM Bit6:SYNC MM Bit5:OSTR MM Bit4:FRAME 3:2 syncsel_dataformatter Selectsthesyncingsourceofthedataformatter.Unliketheothersyncsonly 00 one syncsourceisallowed. MM 00:FRAME MM 01:SYNC MM 10:No sync MM 11:No sync 1 sif_sync SIF createdsyncsignal.Setto‘1’ tocause a syncand thenclearto‘0’ to 0 remove it. 0 Reserved Reservedforfactoryuse. 0 Registername: config32– Address: 0x20,Default:0x2400 Register DefaultAddress Bit Name Function ValueName config32 0x20 15:12 syncsel_fifoin(3:0) Selectsthesyncingsource(s)oftheFIFO inputside.A ‘1’ inthebitenablesthe 0010 signalas a syncsource.More thanone syncsourceispermitted. MM Bit15:sif_sync(viaconfig31) MM Bit14:Alwayszero MM Bit13:FRAME MM Bit12:SYNC 11:8 syncsel_fifoout(3:0) Selectsthesyncingsource(s)oftheFIFO outputside.A ‘1’ inthebitenablesthe 0100 signalas a syncsource.More thanone syncsourceispermitted. MM Bit11:sif_sync(viaconfig31) MM Bit10:OSTR – DualSync SourcesMode MM Bit9:FRAME – SingleSync Sourcemode MM Bit8:SYNC – SingleSync Sourcemode 7:1 Reserved Reservedforfactoryuse. 0000 0 clkdiv_sync_sel Selectsthesignalsourceforclockdividersynchronization. 0 clkdiv_sync_sel Sync Source

0 OSTR

1 FRAME orSYNC, based on syncsel_fifoinsource

selection(config32,bit<15:12>) Registername: config33– Address: 0x21,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config33 0x21 15:0 Reserved Reservedforfactoryuse. 0x0000 Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com Registername: config34– Address: 0x22,Default:0x1B1B Register DefaultAddress Bit Name Function ValueName config34 0x22 15:14 Reserved Reservedforfactoryuse. 00 13:12 Reserved Reservedforfactoryuse. 01 11:10 Reserved Reservedforfactoryuse. 10 9:8 Reserved Reservedforfactoryuse. 11 7:6 Reserved Reservedforfactoryuse. 00 5:4 Reserved Reservedforfactoryuse. 01 3:2 Reserved Reservedforfactoryuse. 10 1:0 Reserved Reservedforfactoryuse. 11 Registername: config35– Address: 0x23,Default:0xFFFF Register DefaultAddress Bit Name Function ValueName config35 0x23 15:0 sleep_cntl(15:0) ControlstheroutingoftheCMOS SLEEP signal(pinB40) todifferentblocks.When a 0xFFFF bitisset,theSLEEP signalwillbe senttothecorrespondingblock.These bitsdo not overridetheSIF bitsinregisterconfig26. sleep_cntl(bit) Function 15 reserved

14 DACI sleep

13 DACQ sleep

11 Clockreceiversleep

10 PLL sleep

9 LVDS datasleep

8 LVDS controlsleep

7 Temp sensorsleep

5 Biasamplifiersleep

Registername: config36– Address: 0x24,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config36 0x24 15:13 datadly(2:0) ControlsthedelayofthedatainputsthroughtheLVDS receivers.Each LSB adds 000 approximately40 ps MM 0:Minimum 12:10 clkdly(2:0) ControlsthedelayofthedataclockthroughtheLVDS receivers.Each LSB adds 000 approximately40 ps MM 0:Minimum 9:0 Reserved Reservedforfactoryuse. 0x000 Registername: config37– Address: 0x25,Default:0x7A7A Register DefaultAddress Bit Name Function ValueName config37 0x25 15:0 iotest_pattern0 Dataword0intheIO testpattern.Itisused withtheseven otherwords totesttheinputdata. 0x7A7A AtthestartoftheIO testpattern,thisword shouldbe alignedwithrisingedge ofFRAME or SYNC signaltoindicatesample 0. Registername: config38– Address: 0x26,Default:0xB6B6 Register DefaultAddress Bit Name Function ValueName config38 0x26 15:0 iotest_pattern1 Dataword1intheIO testpattern.Itisused withtheseven otherwords totesttheinputdata. 0xB6B6

38 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Registername: config39– Address: 0x27,Default:0xEAEA Register DefaultAddress Bit Name Function ValueName config39 0x27 15:0 iotest_pattern2 Dataword2intheIO testpattern.Itisused withtheseven otherwords totesttheinput 0xEAEA data. Registername: config40– Address: 0x28,Default:0x4545 Register DefaultAddress Bit Name Function ValueName config40 0x28 15:0 iotest_pattern3 Dataword3intheIO testpattern.Itisused withtheseven otherwords totesttheinputdata. 0x4545 Registername: config41– Address: 0x29,Default:0x1A1A Register DefaultAddress Bit Name Function ValueName config41 0x29 15:0 iotest_pattern4Dataword4intheIO testpattern.Itisused withtheseven otherwords totesttheinputdata. 0x1A1A Registername: config42– Address: 0x2A, Default:0x1616 Register DefaultAddress Bit Name Function ValueName config42 0x2A 15:0 iotest_pattern5 Dataword5intheIO testpattern.Itisused withtheseven otherwords totesttheinput 0x1616 data. Registername: config43– Address: 0x2B, Default:0xAAAA Register DefaultAddress Bit Name Function ValueName config43 0x2B 15:0 iotest_pattern6 Dataword6intheIO testpattern.Itisused withtheseven otherwords totesttheinput 0xAAAA data. Registername: config44– Address: 0x2C, Default:0xC6C6 Register DefaultAddress Bit Name Function ValueName config44 0x2C 15:0 iotest_pattern7 Dataword7intheIO testpattern.Itisused withtheseven otherwords totesttheinput 0xC6C6 data. Registername: config45– Address: 0x2D, Default:0x0004 Register DefaultAddress Bit Name Function ValueName config45 0x2D 15 Reserved Reservedforfactoryuse. 0 14 ostrtodig_sel When set,theOSTR signalispassed directlytothedigitalblock.Thisisthesignalthat 0 isused toclockthedividers. 13 ramp_ena When set,a ramp signalisinsertedintheinputdataattheFIFO input. 0 12:1 Reserved Reservedforfactoryuse. 0000 0000 0100 0 sifdac_ena When set,theDAC outputissettothevalueinsifdac(15:0)inregisterconfig48. 0 Registername: config46– Address: 0x2E,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config46 0x2E 15:8 Reserved Reservedforfactoryuse. 0x00 7:0 grp_delayI(7:0) SetsthegroupdelayfunctionforDACI. The maximum delayrangesfrom30ps to 0x00 100ps and isdependenton DAC sample clock.ContactTIforspecificapplication information. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com Registername: config47– Address: 0x2F,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config47 0x2F 15:8 grp_delayQ(7:0) SetsthegroupdelayfunctionforDACQ. The maximum delayrangesfrom30ps to 0x00 100ps and isdependenton DAC sample clock.ContactTIforspecificapplication information. 7:0 Reserved Reservedforfactoryuse. 0x00 Registername: config48– Address: 0x30,Default:0x0000 Register DefaultAddress Bit Name Function ValueName config48 0x30 15:0 sifdac(15:0) ValuesenttotheDACs when sifdac_enaisasserted.DATACLK must be runningto 0x0000 latchthisvalueintotheDACs. The formatwouldbe based on twosinregisterconfig2. Registername: version– Address: 0x7F,Default:0x5409 (READ ONLY) Register DefaultAddress Bit Name Function ValueName version 0x7F 15:10 Reserved Reservedforfactoryuse. 010101 9 Reserved Reservedforfactoryuse. 0 8:7 Reserved Reservedforfactoryuse. 00 6:5 Reserved Reservedforfactoryuse. 00 4:3 deviceid(1:0) Returns‘01’ forDAC3482. 01 2:0 versionid(2:0) A hardwiredregisterthatcontainstheversionofthechip. 100

40 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

D[15:0]P/N FRAMEP/N SAMPLE 0 SAMPLE 1 SAMPLE 2 SAMPLE 3 SYNCP/N T0523-01 t(FRAME_SYNC) t(FRAME_SYNC) DATACLKP/N (DDR) Sync Option #1 Sync Option #2 I [15:0] 0 I [15:0] 1 I [15:0] 2 I [15:0] [15:0] 0 Q [15:0] 1 Q [15:0] 2 Q [15:0] Optional Parity Bit DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 DATA INTERFACE The DAC3482 has a 16-bitLVDS bus thataccepts16-bitIand Q dataineitherword-wideorbyte-wideformats. Inword-widemode dataissentthrougha 16-bitbus whileinbyte-widemode an 8-bitbus isused.The selection between thetwo modes isdone through16bit_inintheconfig2register.The LVDS bus inputsineach mode are shown inTable3. Table3.LVDS Bus InputAssignment InputMode Pins Word-wide D[15..0] Byte-wide(1) D[7..0] (1) The unused pinscan be leftfloating.Forword-by-wordparityand IO patterncheckerfunctionality,thepinsneed tohave known logic valuesforvalidfunctionality. Data issampled by theLVDS doubledatarate(DDR) clockDATACLK. Setup and holdrequirementsmust be met forpropersampling. For bothinputbus modes, a sync signal,eitherFRAME orSYNC, can sync theFIFO readand/orwritepointers. Inbyte-widemode thesyncsourceisneeded toestablishthecorrectsample boundaries. The sync signal,eitherFRAME or SYNC, can be eithera pulseor a periodicsignalwhere the sync period correspondsto multiplesof 8 samples.FRAME or SYNC is sampled by a risingedge in DATACLK. The pulse-width(t(FRAME_SYNC) )needs tobe atleastequalto½ oftheDATACLK period. For bothinputbus mode, thevalueinFRAME sampled by thenextfallingedge inDATACLK can be used as a blockparityvalue.Thisfeatureisenabledby settingframe_parity_enainregisterconfig1to“1”.Referto“Parity Check Test” sectionformore detail WORD-WIDE FORMAT The word-wideformatisselectedby setting16bit_into“1” intheconfig2register.Inthismode the16-bitdatafor channelsIand Q isword-wideinterleavedintheform I0,Q 0,I1,Q 1… intotheD[15:0]16-bitbus.Data intothe DAC3482 isformattedaccordingtothediagramshown inFigure49 where index0 isthedataLSB and index15 isthedataMSB. Figure49. Word-Wide Data TransmissionFormat For word-wideformatonly.The FIFO read and writepointerscan alsobe synced by SIF SYNC as the third optionifmulti-devicesynchronizationisnotneeded.Inthissync mode, syncsel_data_formatter(1:0)inregister config32can be setto"10"or"11".The syncsel_fifoin(3:0)and syncsel_fifoout(3:0)inregisterconfig32need to be bothsetto"1000"fortheSIF SYNC option. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLink(s):DAC3482

D[7:0]P/N FRAMEP/N SAMPLE 0 SAMPLE 1 SYNCP/N T0524-01 t(FRAME_SYNC) t(FRAME_SYNC) DATACLKP/N (DDR) Sync Option #1 Sync Option #2 I [15:8] 0 Q [15:8] 0 I [15:8] 1 Q [15:8] [7:0] 0 Q [7:0] 0 I [7:0] 1 Q [7:0] Optional Parity Bit DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com BYTE-WIDE FORMAT The byte-wideformatisselectedby setting16bit_into“0” intheconfig2register.Inthismode the16-bitdatafor channelsIand Q isbyte-wideinterleavedintheformI0[15:8],I0[7:0],Q 0[15:8],Q 0[7:0],I1[15:8]… intotheD[7:0] 8-bitbus.Data intotheDAC3482 isformattedaccordingtothediagramshown inFigure50 where index0 isthe dataLSB and index15 isthedataMSB. A risingedge transitionofthesync signal,eitherFRAME orSYNC, is used toestablishthecorrectsample boundaries. Figure50. Byte-Wide Data TransmissionFormat INPUT FIFO The DAC3482 includesa 2-channel,16-bitswideand 8-samplesdeep inputFIFO whichactsas an elasticbuffer. The purposeoftheFIFO istoabsorbany timingvariationsbetween theinputdataand theinternalDAC data rateclocksuch as theones resultingfromclock-to-datavariationsfromthedatasource. Figure51 shows a simplifiedblockdiagramoftheFIFO.

42 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

I-Data, 16-Bit Q-Data, 16-Bit 16-Bit 16-Bit Write Pointer Reset Read Pointer Reset FIFO Q Output OSTR B0451-01 syncsel_fifoin syncsel_fifooutS M fifo_offset(2:0) FRAME/ SYNC Input Side Clocked by DATACLK 0 ... 7 Write Pointer 0 ... 7 Read Pointer S (Single Sync Source Mode): Reset handoff from input side to output side M (Dual Sync Source Mode): OSTR resets read pointer. Allows Multi-DAC synchronization Initial Position Initial Position FIFO: 2 x 16-Bits Wide 8-Samples deep Output Side Clocked by FIFO Out Clock Word Wide Mode: DACCLK/2/Interpolation Factor Byte Wide Mode: DACCLK/Interpolation Factor Sample 0 Sample 1 Sample 2 Sample 3 Sample 4 Sample 5 Sample 6 Sample 7 DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Figure51. DAC3482 FIFO Block Diagram Data iswrittentothedeviceon therisingand fallingedges ofDATACLK. Each 32-bitwide sample (16-bitI-data and 16-bitQ-data)iswrittenintotheFIFO attheaddressindicatedby thewritepointer.Similarly,datafromthe FIFO isreadby theFIFO Out Clock32-bitsata timefromtheaddressindicatedby thereadpointer.The FIFO Out Clock is generatedinternallyfrom the DACCLK signal.Itsrateis equal to DACCLK/2/Interpolationfor word-widedatatransmission,or DACCLK/Interpolationforbyte-widedatatransmission.Each timea FIFO write orFIFO readisdone thecorrespondingpointermoves tothenextaddress. The resetpositionforthe FIFO read and writepointersissetby defaultto addresses0 and 4 as shown in Figure51. Thisoffsetgivesoptimalmargin withinthe FIFO. The defaultread pointerlocationcan be setto anothervalueusingfifo_offset(2:0)inregisterconfig3(address4 by default).Under normal conditionsdata is written-toand read-fromthe FIFO at the same rateand consequentlythe writeand read pointergap remains constant.Ifthe FIFO writeand read ratesare different,the correspondingpointerswillbe cyclingat different speeds whichcouldresultinpointercollision.Under thisconditiontheFIFO attemptstoreadand writedatafrom thesame addressatthesame timewhichwillresultinerrorsand thusmust be avoided. The writepointersync sourceisselectedby syncsel_fifoin(3:0)inregisterconfig32.Inmost applicationseither FRAME or SYNC isused toresetthewritepointer.UnlikeDATA, thesync signalislatchedonlyon therising edges ofDATACLK. A risingedge on thesyncsignalsourcecausesthepointertoreturntoitsoriginalposition. Similarly,thereadpointersync sourceisselectedby syncsel_fifoout(3:0).The writepointersync sourcecan be settoresetthereadpointeras well.Inthiscase,theFIFO Out clockwillrecapturethewritepointersync signal toresetthereadpointer.Thisclockdomain transfer(DATACLK toFIFO Out Clock)resultsinphase ambiguityof the resetsignal.Thislimitsthe precisecontrolof the outputtimingand makes fullsynchronizationof multiple devicesdifficult. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLink(s):DAC3482

Resets Write Pointer to Position 0 Resets Read Pointer to Position Set by fifo_offset (4 by Default) DATACLKP/N (DDR) FRAMEP/N SYNCP/N DACCLKP/N 1x Interpolation OSTRP/N (optionally internal sync from Write Reset) D[15:0]P/N LVDS Pairs (Data Source) LVPECL Pairs (Clock Source) tS(OSTR) tH(DATA) tH(DATA) tH(DATA) tH(OSTR) tS(DATA) tS(DATA) tS(DATA) DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com To alleviatethis,thedeviceoffersthealternativeofresettingtheFIFO read pointerindependentlyofthewrite pointerby using the OSTR signal.The OSTR signalis sampled by DACCLK and must satisfythe timing requirementsinthespecificationstable.Inordertominimizetheskew itisrecommended touse thesame clock distributiondevicesuch as Texas InstrumentsCDCE62005 toprovidetheDACCLK and OSTR signalstoallthe DAC3482 devicesinthesystem.Swapping thepolarityoftheDACCLK outputswithrespecttotheOSTR ones establishesproperphase relationship. The FIFO pointersresetprocedurecan be done periodicallyor onlyonce duringinitializationas the pointers automaticallyreturnto the initialpositionwhen the FIFO has been filled.To resetthe FIFO periodically,the signalsto sync the FIFO read and writepointercan repeatat multiplesof 8 FIFO samples when the data interfaceisbyte-wideformat.When thedatainterfaceisword-wideformat,thesignaltosync theFIFO readand writepointercan repeatatmultiplesof16 FIFO samples. The frequencylimitationforFRAME and SYNC signalsarethefollowing: fsync = fDATACLK /(nx 16)where n = 1,2,… can repeatmultiplesof8 FIFO samplesforByte-WideMode fsync = fDATACLK /(nx 16)where n = 1,2,… can repeatmultiplesof16 FIFO samplesforWord-Wide Mode The frequencylimitationfortheOSTR signalisthefollowing: fOSTR = fDAC /(nx interpolationx 8)where n = 1,2,… can repeatmultiplesof8 FIFO samples forByte-Wide Mode fOSTR = fDAC /(nx interpolationx 16) where n = 1, 2, … can repeatmultiplesof 16 FIFO samples for World-WideMode The frequenciesabove are atmaximum when n = 1.Thisiswhen theFRAME, SYNC, or OSTR have a rising edge transitionevery8 or 16 FIFO samples.The occurrencecan be made lessfrequentby settingn > 1,for example,everyn × 8 orn × 16 FIFO samples. Figure52. FIFO Writeand Read Descriptions(Example shown withWord-Wide Mode)

44 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 FIFO MODES OF OPERATION The DAC3482 inputFIFO can be completelybypassed throughregistersconfig0and config32. The register configurationforeach mode isdescribedinTable4. Register ControlBits config0 fifo_ena config32 syncsel_fifoout(3:0) Table4.FIFO OperationModes config0and config32FIFO Bits FIFO Mode syncsel_fifoout fifo_ena Bit3:sif_sync Bit2:OSTR Bit1:FRAME Bit0:SYNC DualSync Sources 1 0 1 0 0 SingleSync 1 or0 Depends on thesync 1 or0 Depends on the1 0 0Source source syncsource Bypass 0 X X X X DUAL SYNC SOURCES MODE Thisisthe recommended mode of operationforthoseapplicationsthatrequireprecisecontrolof the output timing.InDual Sync Sources mode, theFIFO writeand read pointersare resetindependently.The FIFO write pointerisresetusingtheLVDS FRAME orSYNC signal,and theFIFO readpointerisresetusingtheLVPECL OSTR signal.ThisallowsLVPECL OSTR signalto controlthe phase of the outputforeithera singlechipor multiplechips.Multipledevicescan be fullysynchronizedinthismode. SINGLE SYNC SOURCE MODE In SingleSync Source mode, the FIFO writeand read pointersare resetfrom the same source,eitherLVDS FRAME or LVDS SYNC signal.Thismode has a possibilityofup to2 DAC clocksoffsetbetween themultiple DAC outputs.Applicationsrequiringexactoutputtimingcontrolwillneed Dual Sync Sources mode insteadof SingleSync Source Mode. A singlerisingedge forFIFO and clockdividersync isrecommended. Periodicsync signalisnotrecommended due tonon-deterministiclatencyofthesyncsignalthroughtheclockdomain transfer. BYPASS MODE InFIFO bypass mode, theFIFO blockisnotused.As a resulttheinputdataishanded offfromtheDATACLK to theDACCLK domain withoutany compensation.Inthismode therelationshipbetween DATACLK and DACCLK iscriticaland used as a synchronizingmechanism fortheinternallogic.Due tothisconstraintthismode isnot recommended. Inbypassmode thepointershave no effecton thedatapathorhandoff. CLOCKING MODES The DAC3482 has a dualclocksetupinwhich a DAC clocksignalisused toclocktheDAC coresand internal digitallogicand a separateDATA clockisused toclocktheinputLVDS receiversand FIFO input.The DAC3482 DAC clocksignalcan be sourceddirectlyorgeneratedthroughan on-chiplow-jitterphase-lockedloop(PLL). Inthoseapplicationsrequiringextremelylow noiseitisrecommended tobypass thePLL and sourcetheDAC clockdirectlyfrom a high-qualityexternalclocktotheDACCLK input.Inmost applicationssystem clockingcan be simplifiedby using the on-chipPLL to generatethe DAC core clockwhilestillsatisfyingperformance requirements.Inthiscase theDACCLK pinsareused as thereferencefrequencyinputtothePLL. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLink(s):DAC3482

pll_ena Clock Distribution to Digital VCO/ Dividers PLL 16-Bit DACI 16-Bit DACQ B0452-01 SYNCP DACCLKP N Divider PFD and CP SYNCN DACCLKN External Loop Filter Internal Loop Filter VCO B0453-01 Prescaler M Divider DACCLK REFCLK SYNC_PLL OSTR (Internally Generated) Note: The PLL generates internal OSTR signal. In this mode external LVPECL OSTR signal is not required. If the DAC is configured with PLL enabled with Dual Sync Sources mode, then the PFD frequency has to be the pre- defined OSTR frequency. DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com Figure53. Top LevelClock Diagram PLL BYPASS MODE InPLL bypass mode a veryhighqualityclockissourcedtotheDACCLK inputs.Thisclockisused todirectly clocktheDAC3482 DAC sample rateclock.Thismode givesthedevicebestperformanceand isrecommended forextremelydemanding applications. The bypassmode isselectedby settingthefollowing: 1. pll_enabitinregisterconfig24to“0” tobypassthePLL circuitry. 2. pll_sleepbitinregisterconfig26to“1” toputthePLL and VCO intosleepmode. PLL MODE In thismode the clockat the DACCLK inputfunctionsas a referenceclocksourceto the on-chipPLL. The on-chipPLL willthenmultiplythisreferenceclocktosupplya higherfrequencyDAC sample rateclock.Figure54 shows theblockdiagramofthePLL circuit. Figure54. PLL Block Diagram The DAC3482 PLL mode isselectedby settingthefollowing: 1. pll_enabitinregisterconfig24to“1” toroutetothePLL clockpath. 2. pll_sleepbitinregisterconfig26to“0” toenablethePLL and VCO.

46 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

VCO Frequency (MHz) /c40 /c41VCO Frequency MHz 3253Coarse Tune Bits 11.6 /c45/c64 DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 The outputfrequencyof the VCO isdesignedto be the inthe range from 3.3GHz to 4.0GHz. The prescaler value,pll_p(2:0)inregisterconfig24,shouldbe chosen such thattheproductoftheprescalervalueand DAC sample rateclockiswithintheVCO range.To maintainoptimalPLL loop,thecoarsetunebits,pll_vco(5:0)in registerconfig26,can adjustthe centerfrequencyof the VCO towardsthe productof the prescalervalueand DAC sample rateclock.Figure55 shows a typicalrelationshipbetween coarse tune bitsand VCO center frequency. Figure55. TypicalPLL/VCO Lock Range vs Coarse Tuning Bits Common wirelessinfrastructurefrequencies(614.4MHz,737.28MHz, 1.2288GHz, etc.)are generatedfrom this VCO frequencyinconjunctionwiththepre-scalersettingas shown inTable5. Table5.VCO Operation VCO Frequency (MHz) Pre-ScaleDivider DesiredDACCLK (MHz) pll_p(2:0) 3440.64 7 491.52 111 3686.4 6 614.4 110 3686.4 5 737.28 101 3686.4 3 1228.8 011 The M dividerisused todeterminethephase-frequency-detector(PFD) and charge-pump(CP)frequency. Table6.PFD and CP Operation DACCLK Frequency M Divider PDF Update Rate (MHz) pll_m(7:0)(MHz) 491.52 4 122.88 00000100 491.52 8 61.44 00001000 491.52 16 30.72 00010000 491.52 32 15.36 00100000 The N dividerintheloopallowsthePFD tooperateata lowerfrequencythanthereferenceclock.Both M and N dividerscan keep thePFD frequencybelow155 MHz forpeak operation. The overalldivideratioinsidetheloopistheproductofthePre-Scaleand M dividers(P * M) and thefollowing guidelinesshouldbe followed:

The overalldivideratiorangeisfrom24 to480
When theoveralldivideratioislessthan120,theinternalloopfiltercan guaranteea stableloop Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLink(s):DAC3482

R = 1 kΩ C1 = 100 nF C2 = 1 nF DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com

When theoveralldivideratioisgreaterthan120,an externalloopfilterisrequiredtoensureloopstability The singlechargepump currentoptionisselectedby settingpll_cpinregisterconfig24to“01”. Ifan externalfilterisrequired,thefollowingfiltershouldbe connectedtotheLPF pin(A1): Figure56. Recommended ExternalLoop Filter The PLL willgeneratean internalOSTR signaland does not requirethe externalLVPECL OSTR signal.The OSTR signalisbufferedfromtheN-divideroutputinthePLL block,and thefrequencyofthesignalisthesame as thePFD frequency.Therefore,usingPLL withDualSync Sourcesmode requiresthePFD frequencytobe the pre-definedOSTR frequencylistedinInputFIFO section.ThiswillallowtheFIFO tobe synced correctlyby the internalOSTR. MULTI-DEVICE SYNCHRONIZATION In variousapplications,such as multiantenna systems where the varioustransmitchannelsinformationis correlated,itisrequiredthatmultipleDAC devicesarecompletelysynchronizedsuch thattheiroutputsarephase aligned.The DAC3482 architecturesupportsthismode ofoperation. MULTI-DEVICE SYNCHRONIZATION: PLL BYPASSED WITH DUAL SYNC SOURCES MODE For singleor multi-devicesynchronizationitisimportantthatdelaydifferencesinthedataare absorbedby the deviceso thatlatencythroughthe deviceremainsthe same. Furthermore,to guaranteethatthe outputsfrom each DAC are phase aligneditisnecessarythatdataisread from theFIFO ofeach devicesimultaneously.In theDAC3482 thisisaccomplishedby operatingthemultipledevicesinDual Sync Sources mode. Inthismode theadditionalOSTR signalisrequiredby each DAC3482 tobe synchronized. Data intothe deviceisinputas LVDS signalsfrom one or multiplebaseband ASICs or FPGAs. Data intothe multipleDAC devicescan experiencedifferentdelaysdue tovariationsinthedigitalsourceoutputpathsorboard levelwiring.These differentdelayscan be effectivelyabsorbed by the DAC3482 FIFO so thatalloutputsare phase alignedcorrectly.

48 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

D[15:0]P/N D[15:0]P/N DATACLKP/N FRAMEP/N DACCLKP/N B0454-01 LVPECL Outputs LVDS Interface OSTRP/N LVPECL Outputs DACCLKP/N OSTRP/N PLL/ DLL DAC3482 DAC1 Delay 1 Delay 2 Outputs are Phase Aligned DAC3482 DAC2 Variable delays due to variations in the FPGA(s) output paths or board level wiring or temperature/voltage deltas T0526-01 DACCLKP/N(2) DACCLKP/N(1) OSTRP/N(2) OSTRP/N(1) LVPECL Pairs (DAC3482 2) LVPECL Pairs (DAC3482 1) tS(OSTR) tS(OSTR) tSKEW ~ 0 tH(OSTR) tH(OSTR) DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Figure57. SynchronizationSystem inDual Sync Sources Mode withPLL Bypassed For correctoperationboth OSTR and DACCLK must be generatedfrom the same clockdomain.The OSTR signalissampled by DACCLK and must satisfythetimingrequirementsinthespecificationstable.Iftheclock generatordoes nothave theabilitytodelaytheDACCLK tomeet theOSTR timingrequirement,thepolarityof theDACCLK outputscan be swapped withrespecttotheOSTR ones tocreate180 degreephase delayofthe DACCLK. Thismay helpestablishpropersetupand holdtimerequirementoftheOSTR signal. Carefulboardlayoutplanningmust be done toensurethattheDACCLK and OSTR signalsaredistributedfrom deviceto devicewiththe lowestskew possibleas thiswillaffectthe synchronizationprocess.In orderto minimizetheskew acrossdevicesitisrecommended touse thesame clockdistributiondevicetoprovidethe DACCLK and OSTR signalstoalltheDAC devicesinthesystem. Figure58. Timing Diagram forLVPECL SynchronizationSignals Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 49 ProductFolderLink(s):DAC3482

D[15:0]P/N D[15:0]P/N DATACLKP/N FRAMEP/N DACCLKP/N B0455-01 Outputs LVDS Interface SYNCP/N Outputs DACCLKP/N SYNCP/N PLL/ DLL DAC3482 DAC1 Delay 1 Delay 2 Outputs are Phase Aligned DAC3482 DAC2 Variable delays due to variations in the FPGA(s) output paths or board level wiring or temperature/voltage deltas DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com The followingstepsare requiredtoensurethedevicesare fullysynchronized.The procedureassumes allthe DAC3482 deviceshave a DACCLK and OSTR signaland must be carriedouton each device. 1. Start-upthedeviceas describedinthepower-upsequence.Set theDAC3482 inDual Sync Sources mode and selectOSTR as theclockdividersyncsource(clkdiv_sync_selinregisterconfig32). 2. Sync theclockdividerand FIFO pointers. 3. Verifythereareno FIFO alarmseitherthroughregisterconfig5orthroughtheALARM pin. 4. Disableclockdividersyncby settingclkdiv_sync_enato“0” inregisterconfig0. AfterthesestepsalltheDAC3482 outputswillbe synchronized. MULTI-DEVICE SYNCHRONIZATION: PLL ENABLED WITH DUAL SYNC SOURCES MODE The DAC3482 allowsexactphase alignmentbetween multipledeviceseven when operatingwiththeinternalPLL clockmultiplier.In PLL clockmode, the PLL generatesthe DAC clockand an internalOSTR signalfrom the referenceclockappliedtotheDACCLK inputsso thereisno need tosupplyan additionalLVPECL OSTR signal. For thismethod tooperateproperlytheSYNC signalshouldbe settoresetthePLL N dividerstoa known state by settingpll_ndivsync_enainregisterconfig24to“1”.The SYNC signalresetsthePLL N dividerswitha rising edge,and thetimingrelationshipts(SYNC_PLL) and th(SYNC_PLL) arerelativetothereferenceclockpresentedon the DACCLK pin. Both SYNC and DACCLK can be setas low frequencysignalstogreatlysimplifyingtracerouting(SYNC can be justa pulse as a singlerisingedge is required,ifusing a periodicsignalitis recommended to clearthe pll_ndivsync_enabitafterresettingthe PLL dividers).Besidesthe t(SYNC_PLL) requirementbetween SYNC and DACCLK, thereisno additionalrequiredtimingrelationshipbetween theSYNC and FRAME signalsorbetween DACCLK and DATACLK. The onlyrestrictionas inthePLL disabledcase isthattheDACCLK and SYNC signals aredistributedfromdevicetodevicewiththelowestskew possible. Figure59. SynchronizationSystem inDual Sync Sources Mode withPLL Enabled The followingstepsare requiredtoensurethedevicesare fullysynchronized.The procedureassumes allthe DAC3482 deviceshave a DACCLK and OSTR signaland must be carriedouton each device. 1. Start-upthedeviceas describedinthepower-upsequence.Set theDAC3482 inDual Sync Sources mode and enableSYNC toresetthePLL dividers(setpll_ndivsync_enainregisterconfig24to"1"). 2. ResetthePLL dividerswitha risingedge on SYNC. 3. DisablePLL dividersresetting. 4. Sync theclockdividerand FIFO pointers.

50 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

D[15:0]P/N D[15:0]P/N DATACLKP/N FRAMEP/N DACCLKP/N B0456-01 LVPECL Outputs LVDS Interface LVPECL Outputs DACCLKP/N PLL/ DLL DAC3482 DAC1 Delay 1 Delay 2 DAC3482 DAC2 0 to 2 DAC Clock Cycles Variable delays due to variations in the FPGA(s) output paths or board level wiring or temperature/voltage deltas DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 5. Verifythereareno FIFO alarmseitherthroughregisterconfig5orthroughtheALARM pin. 6. Disableclockdividersyncby settingclkdiv_sync_enato“0” inregisterconfig0. AfterthesestepsalltheDAC3482 outputswillbe synchronized. MULTI-DEVICE OPERATION: SINGLE SYNC SOURCE MODE In SingleSync Source mode, the FIFO writeand read pointersare resetfrom the same sync source,either FRAME orSYNC. AlthoughtheFIFO inthismode can stillabsorbthedatadelaydifferencesdue tovariationsin thedigitalsourceoutputpathsorboardlevelwiringitisimpossibletoguaranteedatawillbe readfromtheFIFO ofdifferentdevicessimultaneouslythuspreventingexactphase alignment. InSingleSync Source mode theFIFO readpointerresetishandoffbetween thetwo clockdomains (DATACLK and FIFO OUT CLOCK) by simplyre-samplingthewritepointerreset.Sincethetwo clocksare asynchronous thereisa smallbut distinctpossibilityof a meta-stablesituationduringthe pointerhandoff.Thismeta-stable situationcan cause theoutputsofthemultipledevicestoslipby up to2 DAC clockcycles. When the PLL isenabledwithSingleSync Source mode, the FIFO read pointerisnot synchronizedby the OSTR signal.Therefore,thereisno restrictionon thePLL PFD frequencyas describedintheprevioussection. Figure60. Multi-DeviceOperationinSingleSync Source Mode FIR FILTERS Figure61 throughFigure64 show the magnitude spectrum response forthe FIR0, FIR1, FIR2 and FIR3 interpolatingfilterswhere fIN istheinputdataratetotheFIR filter.Figure65 toFigure68 show thecomposite filterresponsefor2x,4x,8x and 16x interpolation.The transitionband forallinterpolationsettingsisfrom0.4to 0.6 x fDATA (theinputdata rateto the device)with< 0.001dB of pass-band rippleand > 90 dB stop-band attenuation. The DAC3482 alsohas a 9-tapinversesincfilter(FIR4)thatrunsattheDAC updaterate(fDAC )thatcan be used to flattenthe frequencyresponse of the sample-and-holdoutput.The DAC sample-and-holdoutputsetsthe outputcurrentand holdsitconstantforone DAC clockcycleuntilthenextsample,resultinginthewell-known sin(x)/xorsinc(x)frequencyresponse(Figure15,redline).The inversesincfilterresponse(Figure62,blueline) has theoppositefrequencyresponsefrom0 to0.4x Fdac,resultinginthecombined response(Figure62,green line).Between 0 to0.4x fDAC ,theinversesincfiltercompensates thesample-and-holdroll-offwithlessthan0.03 dB error. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 51 ProductFolderLink(s):DAC3482

–160 –140 –120 –100 –80 –60 –40 –20 f/fIN Magnitude (dB) G048 –160 –140 –120 –100 –80 –60 –40 –20 f/fIN Magnitude (dB) G049 –160 –140 –120 –100 –80 –60 –40 –20 f/fIN Magnitude (dB) G050 –160 –140 –120 –100 –80 –60 –40 –20 f/fIN Magnitude (dB) G051 DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com The inversesincfilterhas a gain> 1 atallfrequencies.Therefore,thesignalinputtoFIR4 must be reducedfrom fullscaletopreventsaturationinthefilter.The amount ofback-offrequireddepends on thesignalfrequency,and issetsuch thatatthesignalfrequenciesthecombinationoftheinputsignaland filterresponseislessthan1 (0 dB).Forexample,ifthesignalinputtoFIR4 isat0.25x fDAC ,theresponseofFIR4 is0.9dB,and thesignalmust be backed offfromfullscaleby 0.9dB toavoidsaturation.The gainfunctionintheQMC blockscan be used to reducetheamplitudeoftheinputsignal.The advantageofFIR4 havinga positivegainatallfrequenciesisthat theuseristhenabletooptimizetheback-offofthesignalbased on itsfrequency. The filtertapsforalldigitalfiltersarelistedinTable4.Note thatthelossofsignalamplitudemay resultinlower SNR due todecreaseinsignalamplitude. SPACER Figure61.Magnitude Spectrum forFIR0 Figure62.Magnitude Spectrum forFIR1 SPACER SPACER Figure63.Magnitude Spectrum forFIR2 Figure64.Magnitude Spectrum forFIR3 SPACER SPACER

52 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

–160 –140 –120 –100 –80 –60 –40 –20 f/fDATA Magnitude (dB) G052 –160 –140 –120 –100 –80 –60 –40 –20 f/fDATA Magnitude (dB) G053 0 0.5 1 1.5 2 2.5 3 3.5 4 –160 –140 –120 –100 –80 –60 –40 –20 f/fDATA Magnitude (dB) G054 0 1 2 3 4 5 6 7 8 –160 –140 –120 –100 –80 –60 –40 –20 f/fDATA Magnitude (dB) G055 f/fDAC Magnitude (dB) G056 sin(x)/x Corrected FIR4 DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Figure65.2x InterpolationComposite Response Figure66.4x InterpolationComposite Response SPACER SPACER Figure67.8x InterpolationComposite Response Figure68.16x InterpolationComposite Response SPACER SPACER Figure69.Magnitude Spectrum forInverseSinc Filter Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 53 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com Table7.FIR FilterCoefficients Non-Interpolating2x InterpolatingHalf-bandFilters Inverse-SINCFilter FIR0 FIR1 FIR2 FIR3 FIR4

59 Taps 23 Taps 11 Taps 11 Taps 9 Taps

-19 -19 84 84 -214 -214 -25 -25 13 13 0 0 0 0 0 0 0 0 -50 -50 47 47 -336 -336 1209 1209 150 150 592(1) 0 0 0 0 2048(1) 256(1) -100 -100 1006 1006 0 0 0 0 192 192 -2691 -2691 0 0 0 0 -342 -342 10141 10141 0 0 16384(1) 572 572 0 0 -914 -914 0 0 1409 1409 0 0 -2119 -2119 0 0 3152 3152 0 0 -4729 -4729 0 0 7420 7420 0 0 -13334 -13334 0 0 41527 41527 65536(1) (1) CentertapsarehighlightedinBOLD

54 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

±Fs/4 Mixer Complex Signal Multiplier Numerically Controlled Oscillator Fixed Fs/8 Oscillator I Data In Q Data In I Data Out Q Data Out CMIX<3> NCO_ENA Frequency Register

32 Accumulator32

syncsel_NCO[3:0] Phase Register

16 Look-Up

ΣΣ fDAC B0026-03 NCO _ CLK NCO 32 freq f f /c180 /c61 DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 COMPLEX SIGNAL MIXER The DAC3482 has two pathsofcomplex signalmixerblocksthatcontaintwo fullcomplex mixer(FMIX)blocks and power savingcoarsemixer(CMIX)blocks.The signalpathisshown inFigure70. Figure70. Path ofComplex SignalMixer FULL COMPLEX MIXER The DAC3482 has a fullcomplex mixer (FMIX) blockwitha NumericallyControlledOscillators(NCO) that enablesflexiblefrequencyplacementwithoutimposingadditionallimitationsinthesignalbandwidth.The NCO has a 32-bitfrequencyregisters(phaseadd(31:0)) and a 16-bitphase register(phaseoffset(15:0)) thatgenerate thesineand cosinetermsforthecomplexmixing.The NCO blockdiagramisshown belowinFigure71. Figure71. NCO Block Diagram SynchronizationoftheNCOs occursby resettingtheNCO accumulatorstozero.The synchronizationsourceis selectedby syncsel_NCO(3:0)inconfig31.The frequencyword inthephaseadd(31:0)registerisadded tothe accumulatorseveryclockcycle,fDAC .The outputfrequencyoftheNCO is: (1) Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 55 ProductFolderLink(s):DAC3482

I (t)IN I (t)OUT Q (t)IN Q (t)OUT 16 16 cosine sine B0472-01 1616 DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com Withthecomplex mixerenabled,thetwo channelsinthemixerpatharetreatedas complex vectorsoftheform IIN(t)+ jQ IN(t).The complexsignalmultiplier(shown inFigure72)willmultiplythecomplexchannelswiththesine and cosinetermsgeneratedby theNCO. The resultingoutput,IOUT (t)+ jQ OUT (t),ofthecomplex signalmultiplier is: IOUT (t)= (IIN(t)cos(2πfNCO t+ δ)– Q IN(t)sin(2πfNCO t+ δ))× 2(mixer_gain– 1) Q OUT (t)= (IIN(t)sin(2πfNCO t+ δ)+ Q IN(t)cos(2πfNCO t+ δ))× 2(mixer_gain– 1) Figure72. Complex SignalMultiplier where tisthetimesincethelastresettingoftheNCO accumulator,δ isthephase offsetvalueand mixer_gainis either0 or1.δ isgivenby: δ = 2π × phase_offset(15:0)/216 The mixer_gainoptionallowstheoutputsignalsofthemultipliertoreduceby half(6dB).See MixerGain Section fordetail. COARSE COMPLEX MIXER Inadditiontothefullcomplex mixer,theDAC3482 alsohas a coarsemixerblockcapableofshiftingtheinput signalspectrumby thefixedmixingfrequencies±n×fS/8.Usingthecoarsemixerinsteadofthefullmixerlowers power consumption. The outputofthefs/2,fs/4,and –fs/4mixerblockis: IOUT (t)= I(t)cos(2πfCMIX t)– Q(t)sin(2πfCMIX t) Q OUT (t)= I(t)sin(2πfCMIX t)+ Q(t)cos(2πfCMIX t) Sincethesineand thecosinetermsarea functionoffs/2,fs/4,or–fs/4mixingfrequencies,thepossibleresulting valueofthetermswillonlybe 1,-1,or0.The simplifiedmathematicsallowsthecomplex signalmultipliertobe bypassed in any one of the modes, thus mixer gain isnot available.The fs/2,fs/4,and –fs/4mixer blocks performsmixingthroughnegatingand swappingofI/Qchannelon certainsequence ofsamples.Table8 shows thealgorithmused forthosemixerblocks.

56 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC3482

Max output occurs when both sine and cosine are 0.707 cosine sine DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Table8.Fs/2,Fs/4,and –Fs/4MixingSequence MODE MIXING SEQUENCE Iout= {+I1,+I2,+I3,+I4…} Normal (mixerbypassed) Qout = {+Q1,+Q2, +Q3, +Q4 …} Iout= {+I1,-I2,+I3,-I4…} fs/2 Qout = {+Q1,-Q2,+Q3, -Q4…} Iout= {+I1,-Q2,-I3,+Q4 …} fs/4 Qout = {+Q1,+I2,-Q3,-I4…} Iout= {+I1,+Q2, -I3,-Q4…} -fs/4 Qout = {+Q1,-I2,-Q3,+I4…} The fs/8mixercan be enabledalongwithvariouscombinationsoffs/2,fs/4,and –fs/4mixer.Sincethefs/8mixer uses thecomplexsignalmultiplierblockwithfixedfs/8sineand cosineterm,theoutputofthemultiplieris: IOUT (t)= (IIN(t)cos(2πfNCO t+ δ)– Q IN(t)sin(2πfNCO t+ δ))× 2(mixer_gain– 1) Q OUT (t)= (IIN(t)sin(2πfNCO t+ δ)+ Q IN(t)cos(2πfNCO t+ δ))× 2(mixer_gain– 1) where fCMIX isthe fixedmixingfrequencyselectedby cmix(3:0). The mixingcombinationsare describedin Table9.The mixer_gainoptionallowstheoutputsignalsofthemultipliertoreduceby half(6dB).See MixerGain sectionfordetail. Table9.Coarse MixerCombinations Fs/8Mixer Fs/4Mixer Fs/2Mixer –Fs/4Mixercmix(3:0) MixingModecmix(3) cmix(2) cmix(1) cmix(0)

0000 Disabled Disabled Disabled Disabled No mixing

0001 Disabled Disabled Disabled Enabled –Fs/4

0010 Disabled Disabled Enabled Disabled Fs/2

0100 Disabled Enabled Disabled Disabled +Fs/4

1000 Enabled Disabled Disabled Disabled +Fs/8

1010 Enabled Disabled Enabled Disabled –3Fs/8

1100 Enabled Enabled Disabled Disabled +3Fs/8

1110 Enabled Enabled Enabled Disabled –Fs/8

Allothers – – – – Not recommended MIXER GAIN The maximum outputamplitudeout of the complex signalmultiplier(i.e.,FMIX mode or CMIX mode withfs/8 mixer enabled)occurs ifIIN(t)and Q IN(t)are simultaneouslyfullscaleamplitudeand the sine and cosine argumentsareequalto2π x fMIXt+ δ (2N-1)x π/4,where N = 1,2,3,etc.... Figure73. Maximum Output oftheComplex SignalMultiplier With mixer_gain= 1 and both IIN(t)and Q IN(t)are simultaneouslyfullscaleamplitude,the maximum output possibleout of the complex signalmultiplieris0.707 + 0.707 = 1.414 (or3dB).Thisconfigurationcan cause clippingofthesignaland shouldthereforebe used withcaution. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 57 ProductFolderLink(s):DAC3482

qmc_gain[10:0] qmc_gain[10:0] qmc_phase[11:0] B0164-02 Σ DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com Withmixer_gain= 0 inconfig2,themaximum outputpossibleoutofthecomplex signalmultiplieris0.5x (0.707 + 0.707)= 0.707(or-3dB).Thislossinsignalpower isinmost cases undesirable,and itisrecommended that thegainfunctionoftheQMC blockbe used toincreasethesignalby 3 dB tocompensate. REAL CHANNEL UPCONVERSION The mixerintheDAC3482 treatstheIand Q inputsarecomplex inputdataand producesa complex outputfor most mixingfrequencies.The realinputdataforeach channelcan be isolatedonlywhen themixingfrequencyis settonormalmode orfs/2mode. RefertoTable8 fordetails. QUADRATURE MODULATION CORRECTION (QMC) GAIN AND PHASE CORRECTION The DAC3482 includesa QuadratureModulatorCorrection(QMC) block.The QMC blocksprovidea mean for changingthegainand phase ofthecomplex signalstocompensate forany Iand Q imbalancespresentinan analogquadraturemodulator.The blockdiagram forthe QMC blockisshown inFigure74. The QMC block contains3 programmableparameters. Registerqmc_gain(10:0)controlstheIand Q pathgainsand isan 11-bitunsignedvaluewitha range of0 to 1.9990and thedefaultgainis1.0000.The implieddecimalpointforthemultiplicationisbetween bit9 and bit10. Registerqmc_phase(11:0)controlthe phase imbalancebetween I and Q and isa 12-bitvalueswitha range of –0.5 to approximately0.49975.The QMC phase term isnot a directphase rotationbut a constantthatis multipliedby each "Q" sample thensummed intothe"I"sample path.Thisisan approximationofa truephase rotationin order to keep the implementationsimple.The correspondingphase rotationcorrespondsto approximately+3.75to–3.75degreesin1024 steps. LO feed-throughcan be minimizedby adjustingtheDAC offsetfeaturedescribedbelow. Figure74. QMC Block Diagram OFFSET CORRECTION Registersqmc_offsetI(12:0)and qmc_offsetQ(12:0)can be used toindependentlyadjusttheDC offsetsofeach channel.The offsetvaluesareinrepresentedin2s-complementformatwitha rangefrom–4096 to4095. The offsetvalueadds a digitaloffsetto the digitaldata beforedigital-to-analogconversion.Since the offsetis added directlytothedataitmay be necessarytoback offthesignaltopreventsaturation.Both dataand offset valuesareLSB aligned.

ProductFolderLink(s):DAC3482

qmc_offsetI qmc_offsetQ B0165-02 Σ Σ DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Figure75. DigitalOffsetBlock Diagram GROUP DELAY CORRECTION A complex transmittersystem typicallyisconsistedofa DAC, reconstructionfilternetwork,and I/Qmodulator. Besidesthegainand phase mismatch contribution,therecouldalsobe timingmismatch contributionfrom each components.For instance,thetimingmismatch couldcome from thePCB tracelengthvariationbetween theI and Q channelsand thegroupdelayvariationfromthereconstructionfilter. Thistimingmismatch inthecomplex transmittersystem createsphase mismatch thatvarieslinearlywithrespect to frequency.To compensate forthe I/Q imbalancesdue to thismismatch,the DAC3482 has group delay correctionblockforeach DAC channel.Each DAC channelcan adjustitsdelaythroughgrp_delayI(7:0)and grp_delayq(7:0)inregisterconfig46and config47,respectively.The maximum delayrangesfrom30ps to100ps and is dependent on DAC sample clock.ContactTI forspecificapplicationinformation.The group delay correction,alongwithgain/phasecorrection,can be usefulforcorrectingimbalancesinwide-bandtransmitter system. TEMPERATURE SENSOR The DAC3482 incorporatesa temperaturesensor blockwhich monitorsthe temperatureby measuring the voltageacross2 transistors.The voltageisconvertedtoan 8-bitdigitalword usinga successive-approximation (SAR) analogtodigitalconversionprocess.The resultisscaled,limitedand formattedas a twos complement valuerepresentingthetemperatureindegreesCelsius. The samplingiscontrolledby theserialinterfacesignalsSDENB and SCLK. Ifthetemperaturesensorisenabled (tsense_sleep= 0 inregisterconfig26)a conversiontakesplaceeach timetheserialportiswrittenorread.The data isonlyread and sentout by the digitalblockwhen the temperaturesensorisread intempdata(7:0)in config6.The conversionuses thefirsteightclocksoftheserialclockas thecaptureand conversionclock,the dataisvalidon thefallingeighthSCLK. The dataisthenclockedoutofthechipon therisingedge oftheninth SCLK. No otherclocksto the chip are necessary forthe temperaturesensor operation.As a resultthe temperaturesensorisenabledeven when thedeviceisinsleepmode. Inorderfortheprocessdescribedabove tooperateproperly,theserialportreadfromconfig6must be done with an SCLK periodofatleast1 μs.Ifthisisnotsatisfiedthetemperaturesensoraccuracyisgreatlyreduced. DATA PATTERN CHECKER The DAC3482 incorporatesa simplepatterncheckertestinordertodetermineerrorsinthedatainterface.The main cause offailuresissetup/holdtimingissues.The testmode isenabledby assertingiotest_enainregister config1.Intestmode theanalogoutputsaredeactivatedregardlessofthestateofTXENABLE orsif_texnablein registerconfig3. The datapatternkey used forthetestis8 words longand isspecifiedby thecontentsofiotest_pattern[0:7]in registersconfig37throughconfig44. The data patternkey can be modifiedby changingthe contentsof these registers. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 59 ProductFolderLink(s):DAC3482

D[15:0]P/N FRAMEP/N SYNCP/N T0528-01 DATACLKP/N (DDR) Sync Option #1 Sync Option #2 Pattern 0 [15:0] Pattern 1 [15:0] Pattern 2 [15:0] Pattern 3 [15:0] Pattern 4 [15:0] Pattern 5 [15:0] Pattern 6 [15:0] Pattern 7 [15:0] Start cycle again with optional rising edge of FRAME or SYNC DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com The firstword inthetestframeisdeterminedby a risingedge transitioninFRAME orSYNC, dependingon the syncsel_fifoin(3:0)settingin config32. At thistransition,the pattern0word shouldbe inputto the data pins. Patterns1 through7 shouldfollowsequentiallyon each edge of DATACLK (risingand falling).The sequence shouldbe repeateduntilthepatterncheckertestisdisabledby settingiotest_enaback to0.Itisnotnecessaryto have a risingFRAME orSYNC edge alignedwitheverypattern0word,justthefirstone tomark thebeginningof theseries. Figure76. IO PatternChecker Data TransmissionFormat The testmode determinesifthe 16-bitLVDS data D[15:0]P/Nof allthe patternswere receivedcorrectlyby comparingthe receiveddata againstthe data patternkey.Ifany of the 16-bitdata D[15:0]P/Nwere received incorrectly,thecorrespondingbitsiniotest_results(15:0)inregisterconfig4willbe setto“1” toindicatebiterror location.Furthermore,the errorconditionwilltriggerthe alarm_from_iotestbitinregisterconfig5to indicatea generalerrorinthedatainterface.When datapatterncheckermode isenabled,thisalarminregisterconfig5,bit 7 istheonlyvalidalarm.Otheralarmsinregisterconfig5arenotvalidand can be disregarded. For instance,pattern0isprogrammed tothedefaultof0x7A7A. IfthereceivedPattern0 is0x7A7B, thenbit0 in iotest_results(15:0)willbe setto“1” toindicatean errorinbit0 location.The alarm_from_iotestwillalsobe setto “1” to reportthe data transfererror.The user can then narrow down the errorfrom the alarm_from_iotestbit locationinformationand implementthefixaccordingly. The alarmscan be clearedby writing0x0000 to iotest_results(15:0)and “0” to alarm_from_iotestthroughthe serialinterface.The serialinterfacewillread back 0s ifthereare no errorsor ifthe errorsare cleared.The correspondingalarmbitwillremaina “1” iftheerrorsremain. Note thatunlesstheunused datapinsinbyte-wideinputformatare forcedtoa known valuethedatapattern checkerisonlyavailableforthe word-wideinputdata format.In byte-wideinputformat,the first8-bitsof the iotest_pattern[0:7]inregistersconfig37throughconfig44willeitherneed to be 0s or 1s forvaliddata pattern checking. Itisrecommended toenablethepatterncheckerand thenrun thepatternsequence for100 or more complete cyclesbeforeclearingthe iotest_results(15:0)and alarm_from_iotest. Thiswilleliminatethe possibilityof false alarmsgeneratedduringthesetupsequence.

ProductFolderLink(s):DAC3482

Pattern 0 ... 7 D[15:0] 16-Bit 16-Bit 16-Bit DATACLK iotest_results[15] iotest_results[0] B0457-01 alarm_from_iotest Only one edge needed FRAME or SYNC LVDS Drivers Go back to 0 after cycle or new rising edge on FRAME or SYNC Pattern 0 Bit-by-Bit Compare Pattern 1 Bit-by-Bit Compare Pattern 2 Bit-by-Bit Compare Pattern 3 Bit-by-Bit Compare Pattern 4 Bit-by-Bit Compare Pattern 5 Bit-by-Bit Compare Pattern 6 Bit-by-Bit Compare Pattern 7 Bit-by-Bit Compare 8-Bit Input 16-Bit Input 8-Bit Input Bit 15 Results Bit 0 Results

All Bits Results iotest_pattern0 iotest_pattern1 iotest_pattern2 iotest_pattern3 iotest_pattern4 iotest_pattern5 iotest_pattern6 iotest_pattern7 Data Format DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Figure77. DAC3482 PatternCheck Block Diagram Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 61 ProductFolderLink(s):DAC3482

D[15:0] PARITY DATACLK alarm_rparity alarm_fparity B0458-01 Parity Block oddeven_parity DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com PARITY CHECK TEST The DAC3482 has a paritycheck testthatenablescontinuousvaliditymonitoringof the data receivedby the DAC. Paritycheck testingincombinationwiththedatapatterncheckerofferan excellentsolutionfordetecting boardassemblyissuesdue tomissingpad connections. For theparitycheck test,an extraparitybitisadded tothedatabitstoensurethatthetotalnumber ofsetbits (bitswithlogicvalueof “1”) iseven or odd. Thissimplescheme isused to detectdata transfererrors.Parity testingisimplementedintheDAC3482 intwo ways:word-by-wordparityand blockparity. WORD-BY-WORD PARITY Word-by-wordparityisthe easiestmode to implement.In thismode the additionalparitybitissourcedto the parityinput(PARITYP/N) foreach dataword transferintotheD[15:0]P/Ninputs.Thismode isenabledby setting theword_parity_enabit.The inputparityvalueisdefinedtobe thetotalnumber oflogic1s on the17-bitdata bus,theD[15:0]P/Ninputsand thePARITYP/N input.Thisvalue,thetotalnumber oflogic1s,must match the paritytestselectedintheoddeven_paritybitinregisterconfig1. For example,iftheoddeven_paritybitissetto“1” forodd parity,thenthenumber of1s on the17-bitdatabus shouldbe odd. The DAC willcheck the data transferthroughthe parityinput.Ifthe data receivedhas odd number of1s,thentheparityiscorrect.Ifthedatareceivedhas even number of1s,thentheparityisincorrect. The correspondingalarmforparityerrorwillbe setaccordingly. Note thatunlesstheunused datapinsinbyte-wideinputformatare forcedtoa known valuetheword-by-word parityisonlyavailablefortheword-wideinputdataformat. Figure78 shows the simpleXOR structureused to check word parity.Parityistestedindependentlyfordata capturedon bothrisingand fallingedges ofDATACLK (alarm_rparityand alarm_fparity,respectively).Testingon both edges helpsindetermininga possiblesetup/holdissue.Both alarmsare capturedindividuallyinregister config5. Figure78. DAC3482 Word-by-Word ParityCheck BLOCK PARITY The blockparitymethod uses theFRAME signaltodeterminetheboundariesofthedatablocktocompute parity. Thismode isenabledby settingtheframe_parity_enabitinregisterconfig1. A low-to-hightransitionofFRAME capturedwiththeDATACLK risingedge determinestheend pointoftheparity blockand thebeginningofthenextone.Inthismethod theparitybitofthecompletedblockcorrespondstothe FRAME valuecapturedon theDATACLK fallingedge rightaftertheSTOP/START point. The inputparityvalueisdefinedtobe thetotalnumber oflogic1s inthedatablock.A logicHIGH capturedon thefallingedge ofDATACLK indicatesodd parityor odd number oflogic1s,whilea logicLOW indicateseven parityor even number oflogic1s.Iftheexpectedparitydoes notmatch thenumber oflogic1s inthereceived data,thenalarm_frame_parityinregisterconfig5willbe setto“1”.The main advantageoftheblockparitymode isthatthereisno need foran additionalparityLVDS input.

ProductFolderLink(s):DAC3482

D[15:0]P/N FRAMEP/N T0527-01 DATACLKP/N (DDR) I [15:0] 0 I [15:0] [15:0] 0 Q [15:0] Parity Bit for Data Block N – 1 High Low = Odd Parity = Even Parity Stop Point for Data Block N – 1 Start Point for Data Block N D[15:0]P/N FRAMEP/N DATACLKP/N (DDR) I [15:0] x I [15:0] yQ [15:0] x Q [15:0] y Parity Bit for Data Block N High Low = Odd Parity = Even Parity Stop Point for Data Block N Start Point for Data Block N + 1 Data Block N DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 SincetheFRAME signalisused forparitytestinginadditiontoFIFO syncingand frameboundaryassignment,it ismandatorytotakesome extrastepstoavoiddevicemalfunction.IfFRAME isused toresettheFIFO pointers continuously,theblocksizemust be a multipleof8 samples (eachsample correspondingto16-bitsIand 16-bits Q).InadditionsinceFRAME isused inbyte-wideinputdatamode toestablishtheframe boundary,theparity blockmust be alignedwiththedataframeboundaries. Notes: Risingedge ofFRAMEP/N indicatesthebeginningofdatablock. Paritybitforthecurrentdatablockislatchedon fallingedge ofDATACLK afterthestartpointfornextdatablock. Figure79. DAC3482 Block ParityCheck (Example shown withWord-Wide Mode) DAC3482 ALARM MONITORING The DAC3482 includesa flexiblesetof alarm monitoringthatcan be used to alertof a possiblemalfunction scenario.Allthealarmeventscan be accessed eitherthroughtheconfig5registeror throughtheALARM pin. Once an alarmisset,thecorrespondingalarmbitinregisterconfig5must be resetthroughtheserialinterfaceto allowfurthertesting.The setofalarmsincludesthefollowingconditions Zerocheckalarm

Alarm_from_zerochk.Occurswhen theFIFO writepointerhas an allzerospattern.Sincethewritepointerisa shiftregister,allzeroswillcause theinputpointtobe stuckuntilthenextsync event.When thishappens a synctotheFIFO blockisrequired. FIFO alarms
alarm_from_fifo.Occurswhen thereisa collisionintheFIFO pointersora collisioneventisclose. – alarm_fifo_2away.Pointersarewithintwo addressesofeach other. – alarm_fifo_1away.Pointersarewithinone addressofeach other. – alarm_fifo_collision.Pointersareequaltoeach other. Clockalarms
clock_gone.Occurswhen eithertheDACCLK orDATACLOCK have been stopped. – alarm_dacclk_gone.Occurswhen theDACCLK has been stopped. – alarm_dataclk_gone.Occurswhen theDATACLK has been stopped. Patterncheckeralarm
alarm_from_iotest.Occurswhen theinputdatapatterndoes notmatch thepatternkey. PLL alarm

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com Parityalarms

alarm_rparity.Occurs when thereisa parityerrorinthedatacapturedby therisingedge ofDATACLKP/N. The PARITYP/N inputistheparitybit(word-by-wordparitytest).
alarm_fparity.Occurs when thereisa parityerrorinthedatacapturedby thefallingedge ofDATACLKP/N. The PARITYP/N inputistheparitybit(word-by-wordparitytest).
alarm_frame_parity_err.Occurs when thereisa frame parityerrorwhen usingtheFRAME as theparitybit (blockparitytest). To preventunexpectedDAC outputsfrom propagatingintothe transmitchannelchain,the clockand alarm_ fifo_collisionalarmscan be setinconfig2to shut-offthe DAC outputautomaticallyregardlessof the stateof TXENABLE orsif_txenable. Alarmmonitoringisimplementedas follows:
Power up thedeviceusingtherecommended power-upsequence.
Clearallthealarmsinconfig5by settingthem to0.
Unmask thosealarmsthatwillgeneratea hardwareinterruptthroughtheALARM pininconfig7.
EnableautomaticDAC shut-offinregisterconfig2ifrequired.
Inthecase ofan alarmevent,theALARM pinwilltrigger.IfautomaticDAC shut-offhas been enabledthe DAC outputswillbe disabled.
Read registersconfig5todeterminewhichalarmtriggeredtheALARM pin.
Correcttheerrorconditionand re-synchronizetheFIFO.
Clearthealarmsinconfig5.
Re-readconfig5toensurethealarmeventhas been corrected.
Keep clearingand readingconfig5untilno errorisreported. POWER-UP SEQUENCE The followingstartupsequence isrecommended topower-uptheDAC3482: 1. SetTXENABLE low 2. Supplyall1.2V voltages(DACVDD, DIGVDD, CLKVDD and VFUSE) and all3.3V voltages(AVDD, IOVDD, and PLLAVDD). The 1.2V and 3.3V suppliescan be powered up simultaneouslyor inany order.There are no specificrequirementson theramp rateforthesupplies. 3. ProvideallLVPECL inputs:DACCLKP/N and theoptionalOSTRP/N. These inputscan alsobe providedafter theSIF registerprogramming. 4. ToggletheRESETB pinfora minimum 25 ns activelowpulsewidth. 5. Program theSIF registers. 6. Program config1,bit<8> = "0"and config16,bit<13:12> = "11". 7. Program fuse_sleep(config27,Bit<11> )toputinternalfusestosleep. 8. FIFO configurationneeded forsynchronization: (a) Program syncsel_fifoin(3:0)(config32,bit<15:12>)toselecttheFIFO inputpointersyncsource. (b) Program syncsel_fifoout(3:0)(config32,bit<11:8>)toselecttheFIFO outputpointersyncsource. (c) Program syncsel_dataformatter(1:0)(config32,bit<3:2>)toselecttheFIFO Data Formattersyncsource. 9. Clockdividerconfigurationneeded forsynchronization: (a) Program clkdiv_sync_sel(config32,bit<0>)toselecttheclockdividersyncsource. (b) Program clkdiv_sync_ena(config0,bit<2>)to"1"toenableclockdividersync. (c) For multi-DACsynchronizationin PLL mode, program pll_ndivsync_ena(config24,bit<11>) to “1” to synchronizethePLL N-divider. 10. Provide all LVDS inputs (D[15:0]P/N,DATACLKP/N, FRAMEP/N, SYNCP/N and PARITYP/N) simultaneously.SynchronizetheFIFO and clockdividerby providingthepulseorperiodicsignalsneeded. (a) For SingleSync Source Mode where eitherFRAMEP/N orSYNCP/N isused tosync theFIFO,a single risingedge forFIFO,FIFO dataformatter,and clockdividersync isrecommended. Periodicsync signal isnot recommended due to the non-deterministiclatencyof the sync signalthroughthe clockdomain transfer. (b) ForDualSync SourcesMode, bothsinglepulseorperiodicsyncsignalscan be used.

ProductFolderLink(s):DAC3482

www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 (c) For multi-DACsynchronizationin PLL mode, the LVDS SYNCP/N signalis used to sync the PLL N-dividerand can be sourcedfromeithertheFPGA/ASIC patterngeneratororclockdistributioncircuitas long as the t(SYNC_PLL) setup and hold timingrequirementismet withrespectto the referenceclock sourceatDACCLKP/N pins.The LVDS SYNCP/N signalcan be providedatthispoint. 11. FIFO and clockdividerconfigurationsafterallthesync signalshave providedtheinitialsync pulsesneeded forsynchronization: (a) For SingleSync Source Mode where theclockdividersync sourceiseitherFRAMEP/N or SYNCP/N, clockdividersyncingmay be disabledafterDAC3482 initializationand beforethedatatransmissionby settingclkdiv_sync_ena(config0,bit2)to“0”.Thisistopreventaccidentalsyncingoftheclockdivideror when sendingFRAMEP/N orSYNCP/N pulsetootherdigitalblocks. (b) For Dual Sync SourcesMode, where theclockdividersync sourceisfromtheOSTR signal(eitherfrom externalOSTRP/N orinternalPLL N divideroutput),theclockdividersyncingmay be enabledatalltime. (c) Optionally,to preventaccidentalsyncingof the FIFO and FIFO data formatterwhen sending the FRAMEP/N orSYNCP/N pulsetootherdigitalblockssuch as NCO, QMC, etc,disableFIFO syncingby settingsyncsel_fifoin(3:0)and syncsel_fifoout(3:0)to“0000” aftertheFIFO inputand outputpointersare initialized.AlsoDisabletheFIFO dataformatterby settingsyncsel_dataformatter(1:0)to“10” or “11”.If theFIFO and FIFO dataformattersync remainenabledafterinitialization,theFRAMEP/N or SYNCP/N pulsemust occurinways tonotdisturbtheFIFO operation.RefertotheINPUT FIFO sectionfordetail. (d) DisablePLL N-dividersyncingby settingpll_ndivsync_ena(config24,bit<11>)to"0". 12. Enabletransmitofdataby assertingtheTXENABLE pinorsetsif_txenableto“1”. 13. At any time,ifany oftheclocks(i.eDATACLK orDACCLK) islostora FIFO collisionalarmisdetected,a completeresynchronizationof the DAC isnecessary.Set TXENABLE low and repeatsteps8 through12. Program theFIFO configurationand clockdividerconfigurationpersteps8 and 9 appropriatelytoacceptthe new syncpulseorpulsesforthesynchronization. EXAMPLE START-UP ROUTINE DEVICE CONFIGURATION fDATA = 614.4MSPS, 16-bitword wideinterface Interpolation= 2x Inputdata= baseband data fOUT = 122.88MHz PLL = Enabled FullMixer= Enabled DualSync SourcesMode PLL CONFIGURATION fREFCLK = 614.4MHz attheDACCLKP/N LVPECL pins fDACCLK = fDATA x Interpolation= 1228.8MHz fVCO = 3 x fDACCLK = 3686.4MHz (keepfVCO between 3.3GHz to4GHz) PFD = fOSTR = 38.4MHz N = 16,M = 32,P = 3,singlechargepump NCO CONFIGURATION fNCO = 122.88MHz fNCO_CLK = 1228.8MHz Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 65 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com freq= fCNO x 2^32 /1228.8= 429496730 = 0x1999999A phaseaddAB (31:0)orphaseaddCD (31:0)= 0x1999999A NCO SYNC = sif_sync EXAMPLE START-UP SEQUENCE Table10.Example Start-UpSequence Description STEP READ/WRITE ADDRESS VALUE DESCRIPTION

1 N/A N/A N/A SetTXENABLE Low

2 N/A N/A N/A Power-upthedevice

3 N/A N/A N/A ApplyLVPECL DACCLKP/N forPLL referenceclock

4 N/A N/A N/A ToggleRESETB pin

QMC offsetand correctionenabled,2x int,FIFO enabled,Alarmenabled,5 Write 0x00 0xA19E clockdividersyncenabled,inversesincfilterenabled. Singleparityenabled,FIFO alarmsenabled(2away,1 away,and collision).6 Write 0x01 0x040E Note:bit8= ‘0’ Outputshut-offwhen DACCLK gone,DATACLK gone,and FIFO collision.7 Write 0x02 0xF052 MixerblockwithNCO enabled,twoscomplement.Word wideinterface. Outputcurrentsetto20mAFS withinternalreferenceand 1.28kohm R BIAS8 Write 0x03 0xA000 resistor. Un-mask FIFO collision,DACCLK-gone, and DATACLK-gone alarmstothe9 Write 0x07 0xD8FF Alarmoutput. Program thedesiredchannelIQMC offsetvalue.(CausesAuto-Syncfor10 Write 0x08 N/A QMC OffsetBlock) 11 Write 0x09 N/A Program thedesiredFIFO offsetvalueand channelQ QMC offsetvalue. 12 Write 0x0C N/A Program thedesiredchannelIQMC gainvalue. Coarse mixermode notused.Program thedesiredchannelQ QMC gain13 Write 0x0D N/A value. Program thedesiredchannelIQ QMC phase value.(CausesAuto-Sync14 Write 0x10 N/A QMC CorrectionBlock)Note :bit13and bit12= ‘1’ Program thedesiredchannelIQ NCO phase offsetvalue.(Causes15 Write 0x12 N/A Auto-SyncforChannelIQ NCO Mixer)

16 Write 0x14 0x999A Program thedesiredchannelIQ NCO frequencyvalue

17 Write 0x15 0x1999 Program thedesiredchannelIQ NCO frequencyvalue

PLL enabled,PLL N-dividerssyncenabled,singlechargepump, prescaler=18 Write 0x18 0x2C58 3.

19 Write 0x19 0x20F4 M = 32,N = 16,PLL VCO biastune= “01”

20 Write 0x1A 0x9000 PLL VCO coarsetune= 36

21 Write 0x1B 0x0800 Internalreference

QMC offsetIQ and QMC correctionIQ can be syncedby sif_syncor22 Write 0x1E 0x9191 auto-syncfromregisterwrite MixerIQ valuessyncedby SYNCP/N. NCO accumulatorsyncedby23 Write 0x1F 0x4140 SYNCP/N. FIFO dataformattersyncedby FRAMEP/N. FIFO InputPointerSync Source= FRAME

24 Write 0x20 0x2400 FIFO OutputPointerSync Source= OSTR (fromPLL N-divideroutput)

ClockDividerSync Source= OSTR ProvidealltheLVDS DATA and DATACLK

25 N/A N/A N/A Providerisingedge FRAMEP/N and risingedge SYNCP/N tosynctheFIFO

inputpointerand PLL N-dividers. Read back pll_lfvolt(2:0).Ifthevalueisnotoptimal,adjustpll_vco(5:0)in26 Read 0x18 N/A 0x1A. 27 Write 0x05 0x0000 Clearallalarmsin0x05. Read back allalarmsin0x05.Check forPLL lock,FIFO collision, 28 Read 0x05 N/A DACCLK-gone, DATACLK-gone, etc.Fixtheerrorappropriately.Repeat step26 and 27 as necessary.

ProductFolderLink(s):DAC3482

250 Ω 250 Ω 2 kΩ 2 kΩ DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Table10.Example Start-UpSequence Description(continued) STEP READ/WRITE ADDRESS VALUE DESCRIPTION Sync alltheQMC blocksusingsif_sync.These blockscan alsobe synced29 Write 0x1F 0x4142 viaauto-syncthroughappropriateregisterwrites. 30 Write 0x00 0xA19A Disableclockdividersync. DisableFIFO dataformattersync.Setsif_syncto“0” forthenextsif_sync31 Write 0x1F 0x4148 event. 32 Write 0x20 0x0000 DisableFIFO inputand outputpointersync. 33 Write 0x18 0x2458 DisablePLL N-dividerssync. 34 N/A N/A N/A SetTXENABLE high.Enabledatatransmission. LVPECL INPUTS Figure80 shows an equivalentcircuitforthe DAC inputclock(DACCLKP/N) and the outputstrobeclock (OSTRP/N). Figure80. DACCLKP/N and OSTRP/N EquivalentInputCircuit Figure81 shows the preferredconfigurationfordrivingthe CLKIN/CLKINC inputclockwith a differential ECL/PECL source. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 67 ProductFolderLink(s):DAC3482

C 0.1 F AC μ C 0.1 F AC μ Differential ECL or (L V)PECL Source CLKIN CLKINC S0029-02 100 Ω R 150 T Ω R 150 T Ω GND Internal Digital In IOVDD LVDS Receiver S0516-01 100 Ω LVDS Receiver DAC3482 GND B0459-01 100 Ω VB VB VA VA 1.4 V 1 V 400 mV 0 V –400 mV V = (V + V )/2 COM A B VA, B VA, B Logical Bit Equivalent Example DAC3482 SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com Figure81. PreferredClock InputConfigurationwitha DifferentialECL/PECL Clock Source LVDS INPUTS The D[15:0]P/N,DATACLKP/N, SYNCP/N, PARITYP/N and FRAMEP/N LVDS pairshave theinputconfiguration shown inFigure82. Figure83 shows the typicalinputlevelsand common-move voltageused to drivethese inputs. Figure82. D[15:0]P/N,DATACLKP/N, FRAMEP/N, SYNCP/N and PARITYP/N LVDS InputConfiguration Figure83. LVDS Data InputLevels

ProductFolderLink(s):DAC3482

400 Ω 400 Ω 100 kΩ 100 kΩ GND IOVDD IOVDD SDENB RESETB Internal Digital In S0027-03 DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Table11.Example LVDS Data InputLevels ResultingDifferential ResultingCommon-ModeAppliedVoltages LogicalBitBinaryVoltage Voltage Equivalent VA VB VA,B VCOM 1.4V 1.0V 400 mV 1.2V 1 1.0V 1.4V -400mV 0 1.2V 0.8V 400 mV 1.0V 1 0.8V 1.2V -400mV 0 CMOS DIGITAL INPUTS Figure84 shows a schematicoftheequivalentCMOS digitalinputsoftheDAC3482. SDIO, SCLK, SLEEP and TXENABLE have pull-downresistorswhileSDENB and RESETB have pull-upresistorsinternaltotheDAC3482. See thespecificationtableforlogicthresholds.The pull-upand pull-downcircuitryisapproximatelyequivalentto 100kΩ. Figure84. CMOS DigitalEquivalentInput REFERENCE OPERATION The DAC3482 uses a bandgap referenceand controlamplifierforbiasingthe full-scaleoutputcurrent.The full-scaleoutputcurrentissetby applyingan externalresistorR BIAS topinBIASJ.The biascurrentIBIAS through resistorR BIAS isdefinedby the on-chipbandgap referencevoltageand controlamplifier.The defaultfull-scale outputcurrentequals64 timesthisbiascurrentand can thusbe expressedas: IOUT FS = 64 x IBIAS = 64 x (VEXTIO /R BIAS )/2 The DAC3482 has a 4-bitcoarsegaincontrolcoarse_dac(3:0)intheconfig3register.Using gaincontrol,the IOUT FS can be expressedas: IOUT FS = (coarse_dac+ 1)/16x IBIASx 64 = (coarse_dac+ 1)/16x (VEXTIO /RBIAS) /2 x 64 where VEXTIO isthevoltageatterminalEXTIO. The bandgap referencevoltagedeliversan accuratevoltageof 1.2V.Thisreferenceisactivewhen extref_ena= ‘0’ inconfig27.An externaldecouplingcapacitorC EXT of0.1µF shouldbe connectedexternallytoterminalEXTIO forcompensation.The bandgap referencecan additionallybe used forexternalreferenceoperation.In thatcase,an externalbufferwithhigh impedance inputshouldbe appliedin orderto limitthe bandgap load currentto a maximum of 100 nA. The internalreferencecan be disabledand overriddenby an externalreferenceby settingtheextref_enacontrolbit.CapacitorC EXT may hence be omitted.TerminalEXTIO thusservesas eitherinputoroutputnode. The full-scaleoutputcurrentcan be adjustedfrom30 mA down to10 mA by varyingresistorR BIAS,programming coarse_dac(3:0),orchangingtheexternallyappliedreferencevoltage. Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 69 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com NOTE Withinternalreference,theminimum Rbiasresistorvalueis1.28kΩ.Resistorvaluebelow 1.28kΩ isnotrecommended sinceitwillprogram thefull-scalecurrenttogo above 30mA and potentiallydamages thedevice. DAC TRANSFER FUNCTION The CMOS DAC ’s consistof a segmented arrayof PMOS currentsources,capableof sourcinga full-scale outputcurrentup to30 mA. Differentialcurrentswitchesdirectthecurrenttoeitherone ofthecomplementary outputnodes IOUTP orIOUTN. Complementary outputcurrentsenabledifferentialoperation,thuscancelingout common mode noisesources(digitalfeed-through,on-chipand PCB noise),dc offsets,even orderdistortion components,and increasingsignaloutputpower by a factoroftwo. The full-scaleoutputcurrentissetusingexternalresistorR BIAS incombinationwithan on-chipbandgap voltage referencesource (+1.2V) and controlamplifier.CurrentIBIAS throughresistorR BIAS ismirroredinternallyto providea maximum full-scaleoutputcurrentequalto64 timesIBIAS. The relationbetween IOUTP and IOUTN can be expressedas: IOUT FS = IOUTP + IOUTN We willdenotecurrentflowingintoa node as – currentand currentflowingoutofa node as + current.Sincethe outputstageisa currentsourcethecurrentflowsfrom theIOUTP and IOUTN pins.The outputcurrentflowin each pindrivinga resistiveloadcan be expressedas: IOUTP = IOUT FS x CODE /65536 IOUTN = IOUT FS x (65535– CODE) /65536 where CODE isthedecimalrepresentationoftheDAC datainputword For thecase where IOUTP and IOUTN driveresistorloadsR L directly,thistranslatesintosingleended voltages atIOUTP and IOUTN: VOUTP = IOUT1 x R L VOUTN = IOUT2 x R L Assuming thatthedataisfullscale(65535 inoffsetbinarynotation)and theR L is25 Ω,thedifferentialvoltage between pinsIOUTP and IOUTN can be expressedas: VOUTP = 20mA x 25 Ω = 0.5V VOUTN = 0mA x 25 Ω = 0 V VDIFF = VOUTP – VOUTN = 0.5V Note thatcareshouldbe takennottoexceed thecompliancevoltagesatnode IOUTP and IOUTN, whichwould leadtoincreasedsignaldistortion. ANALOG CURRENT OUTPUTS The DAC3482 can be easilyconfiguredtodrivea doublyterminated50 Ω cableusinga properlyselectedRF transformer.Figure85 and Figure86 show the50 Ω doublyterminatedtransformerconfigurationwith1:1and 4:1 impedance ratio,respectively.Note thatthecentertapoftheprimaryinputofthetransformerhas tobe grounded to enable a DC currentflow.Applyinga 20 mA full-scaleoutputcurrentwould lead to a 0.5 Vpp fora 1:1 transformerand a 1 Vpp outputfora 4:1transformer.The low dc-impedancebetween IOUTP orIOUTN and the transformercentertap setsthe centerof the ac-signalto GND, so the 1 Vpp outputforthe 4:1 transformer resultsinan outputbetween –0.5V and +0.5V.

ProductFolderLink(s):DAC3482

IOUTP 1:1 IOUTN AGND 50 Ω R 50 Ω LOAD 50 Ω 100 Ω S0517-01 IOUTP 4:1 IOUTN AGND 100 Ω R 50 Ω LOAD 100 Ω S0518-01 DAC3482 www.ti.com SLAS748A –MARCH 2011–REVISED JUNE 2011 Figure85. Drivinga Doubly Terminated50 Ω Cable Using a 1:1Impedance RatioTransformer Figure86. Drivinga Doubly Terminated50 Ω Cable Using a 4:1Impedance RatioTransformer Copyright© 2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 71 ProductFolderLink(s):DAC3482

SLAS748A –MARCH 2011–REVISED JUNE 2011 www.ti.com

REVISION HISTORY

Changes from Original(March 2011)toRevisionA Page

ProductFolderLink(s):DAC3482

www.ti.com 27-Jun-2011 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) DAC3482IRKDR ACTIVE WQFN RKD 88 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR DAC3482IRKDT ACTIVE WQFN RKD 88 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR PDAC3482IRKDT PREVIEW WQFN RKD 88 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 27-Jun-2011 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC3482IRKDR WQFN RKD 88 2000 333.2 345.9 28.6 DAC3482IRKDT WQFN RKD 88 250 333.2 345.9 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jun-2011 Pack Materials-Page 2

Texas InstrumentsIncorporatedand itssubsidiaries(TI)reservetherighttomake corrections,modifications,enhancements,improvements, and otherchanges toitsproductsand servicesatany timeand todiscontinueany productorservicewithoutnotice.Customersshould obtainthelatestrelevantinformationbeforeplacingordersand shouldverifythatsuch informationiscurrentand complete.Allproductsare soldsubjecttoTI’s termsand conditionsofsalesuppliedatthetimeoforderacknowledgment. TIwarrantsperformanceofitshardwareproductstothespecificationsapplicableatthetimeofsaleinaccordancewithTI’s standard warranty.Testingand otherqualitycontroltechniquesareused totheextentTIdeems necessarytosupportthiswarranty.Exceptwhere mandated by governmentrequirements,testingofallparametersofeach productisnotnecessarilyperformed. TIassumes no liabilityforapplicationsassistanceorcustomerproductdesign.Customersareresponsiblefortheirproductsand applicationsusingTIcomponents.To minimizetherisksassociatedwithcustomerproductsand applications,customersshouldprovide adequatedesignand operatingsafeguards. TIdoes notwarrantorrepresentthatany license,eitherexpressorimplied,isgrantedunderany TIpatentright,copyright,mask work right, orotherTIintellectualpropertyrightrelatingtoany combination,machine,orprocessinwhichTIproductsorservicesareused.Information publishedby TIregardingthird-partyproductsorservicesdoes notconstitutea licensefromTItouse such productsorservicesora warrantyorendorsementthereof.Use ofsuch informationmay requirea licensefroma thirdpartyunderthepatentsorotherintellectual propertyofthethirdparty,ora licensefromTIunderthepatentsorotherintellectualpropertyofTI. ReproductionofTIinformationinTIdatabooks ordatasheetsispermissibleonlyifreproductioniswithoutalterationand isaccompanied by allassociatedwarranties,conditions,limitations,and notices.Reproductionofthisinformationwithalterationisan unfairand deceptive businesspractice.TIisnotresponsibleorliableforsuch altereddocumentation.Informationofthirdpartiesmay be subjecttoadditional restrictions. ResaleofTIproductsorserviceswithstatementsdifferentfromorbeyond theparametersstatedby TIforthatproductorservicevoidsall expressand any impliedwarrantiesfortheassociatedTIproductorserviceand isan unfairand deceptivebusinesspractice.TIisnot responsibleorliableforany such statements. TIproductsarenotauthorizedforuse insafety-criticalapplications(suchas lifesupport)where a failureoftheTIproductwouldreasonably be expectedtocause severepersonalinjuryordeath,unlessofficersofthepartieshave executedan agreementspecificallygoverning such use.Buyersrepresentthattheyhave allnecessaryexpertiseinthesafetyand regulatoryramificationsoftheirapplications,and acknowledgeand agreethattheyaresolelyresponsibleforalllegal,regulatoryand safety-relatedrequirementsconcerningtheirproducts and any use ofTIproductsinsuch safety-criticalapplications,notwithstandingany applications-relatedinformationorsupportthatmay be providedby TI.Further,Buyersmust fullyindemnifyTIand itsrepresentativesagainstany damages arisingoutoftheuse ofTIproductsin such safety-criticalapplications. TIproductsareneitherdesignednorintendedforuse inmilitary/aerospaceapplicationsorenvironmentsunlesstheTIproductsare specificallydesignatedby TIas military-gradeor"enhanced plastic."Onlyproductsdesignatedby TIas military-grademeet military specifications.Buyersacknowledgeand agreethatany such use ofTIproductswhichTIhas notdesignatedas military-gradeissolelyat theBuyer's risk,and thattheyaresolelyresponsibleforcompliancewithalllegaland regulatoryrequirementsinconnectionwithsuch use. TIproductsareneitherdesignednorintendedforuse inautomotiveapplicationsorenvironmentsunlessthespecificTIproductsare designatedby TIas compliantwithISO/TS 16949 requirements.Buyersacknowledgeand agreethat,iftheyuse any non-designated productsinautomotiveapplications,TIwillnotbe responsibleforany failuretomeet such requirements. FollowingareURLs where you can obtaininformationon otherTexas Instrumentsproductsand applicationsolutions: Products Applications Audio www.ti.com/audio Communicationsand Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP ® Products www.dlp.com Energyand Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocksand Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space,Avionicsand Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportationand www.ti.com/automotive Automotive Microcontrollers microcontroller.ti.com Videoand Imaging www.ti.com/video RFID www.ti-rfid.com Wireless www.ti.com/wireless-apps RF/IFand ZigBee® Solutions www.ti.com/lprf TIE2E Community Home Page e2e.ti.com MailingAddress:Texas Instruments,PostOfficeBox 655303,Dallas,Texas 75265 Copyright© 2011,Texas InstrumentsIncorporated

Product Information

DAC3482IRKDR specifications and overview.

Summary

Dual-Channel, 16-BIT, 1.25 GSPS Digital-to-Analog Converter (DAC) JUNE2011

Description

Dual-Channel, 16-BIT, 1.25 GSPS Digital-to-Analog Converter (DAC) JUNE2011

Source title DAC3482IRKDR Datasheet(PDF) - Texas Instruments

Related Parts

More parts from the same family.

Browse manufacturer

DAC3482IRKDR

Read DAC3482IRKDR online.

DAC3482 TI1 | Alldatasheet

Document overview

Technical content

8 Sample FIFO

2 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

4 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

6 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

1 LSB = IOUT FS /216

8 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

10 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

12 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

14 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

16 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

18 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

20 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

22 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

24 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

26 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

28 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

30 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

32 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

34 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

36 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

0 OSTR

1 FRAME orSYNC, based on syncsel_fifoinsource

14 DACI sleep

13 DACQ sleep

11 Clockreceiversleep

10 PLL sleep

9 LVDS datasleep

8 LVDS controlsleep

7 Temp sensorsleep

5 Biasamplifiersleep

38 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

40 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

42 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

44 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

46 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

48 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

50 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

52 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

59 Taps 23 Taps 11 Taps 11 Taps 9 Taps

54 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

32 Accumulator32

16 Look-Up

56 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

0000 Disabled Disabled Disabled Disabled No mixing

0001 Disabled Disabled Disabled Enabled –Fs/4

0010 Disabled Disabled Enabled Disabled Fs/2

0100 Disabled Enabled Disabled Disabled +Fs/4

1000 Enabled Disabled Disabled Disabled +Fs/8

1010 Enabled Disabled Enabled Disabled –3Fs/8

1100 Enabled Enabled Disabled Disabled +3Fs/8

1110 Enabled Enabled Enabled Disabled –Fs/8

58 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

60 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

62 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

64 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

1 N/A N/A N/A SetTXENABLE Low

2 N/A N/A N/A Power-upthedevice

3 N/A N/A N/A ApplyLVPECL DACCLKP/N forPLL referenceclock

4 N/A N/A N/A ToggleRESETB pin

16 Write 0x14 0x999A Program thedesiredchannelIQ NCO frequencyvalue

17 Write 0x15 0x1999 Program thedesiredchannelIQ NCO frequencyvalue

19 Write 0x19 0x20F4 M = 32,N = 16,PLL VCO biastune= “01”

20 Write 0x1A 0x9000 PLL VCO coarsetune= 36

21 Write 0x1B 0x0800 Internalreference

24 Write 0x20 0x2400 FIFO OutputPointerSync Source= OSTR (fromPLL N-divideroutput)

25 N/A N/A N/A Providerisingedge FRAMEP/N and risingedge SYNCP/N tosynctheFIFO

66 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

68 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

70 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

REVISION HISTORY

72 SubmitDocumentationFeedback Copyright© 2011,Texas InstrumentsIncorporated

DAC3482IRKDR specifications and overview.

More parts from the same family.