DAC3164IRGCT

DAC3154_16 TI1 | Alldatasheet

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www.ti.com SLAS960 –MAY 2013 Dual12-/10-Bit500MSPSDigital-to-AnalogConverters Check forSamples: DAC3154 ,DAC3164 1FEATURES APPLICATIONS 2• Dual Channel • Multi-Carrier,Multi-ModeCellular InfrastructureBase Stations• Resolution

• Radar– DAC3154: 10-Bit
• SignalIntelligence– DAC3164: 12-Bit
• Software-DefinedRadio• Maximum Sample Rate:500 MSPS
• Testand Measurement Instrumentation• Pin Compatible FamilywithDAC3174 and DAC3151/DAC3161/DAC3171 DESCRIPTION• InputInterface: The DAC3154/DAC3164 are dualchannel10-/12-bit,– 12-/10-BitWide LVDS Inputs pin-compatiblefamilyof 500 MSPS digital-to-analog – InternalFIFO converters(DAC).The DAC3154/DAC3164 use a 10- /12-bitwide LVDS digitalbus withan inputFIFO.• Chip toChip Synchronization FIFO inputand outputpointerscan be synchronized• Power Dissipation:460mW across multiple devices for precise signal
• SpectralPerformance at20 MHz IF synchronization.The DAC outputs are current sourcingand terminateto GND witha compliance– SNR: 62 dBFS forDAC3154, 72 dBFS for range of –0.5 to 1V. DAC3154/ DAC3164 are pinDAC3164 compatiblewiththe dual-channel,14-bit,500 MSPS– SFDR: 76 dBc forDAC3154, 77 dBc for digital-to-analogconvertersDAC3174, and thesingle-DAC3164 channel, 14-/12-10-bit,digital-to-analogconverters
• CurrentSourcing DACs DAC3171/DAC3161/DAC3151.
• Compliance Range: –0.5Vto1V The devicesare availableina QFN-64 PowerPAD ™
• Package: 64 Pin QFN (9x9mm) package is specifiedover the full industrial temperaturerange(–40°C to85°C). Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2PowerPAD isa trademarkofTexas Instruments. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

8 Sample FIFO

1.2 V Reference 100 Pattern Test DATA0P DATA0N LVDS DACA Gain Optional Input Used for multi-DAC sync DAC3154 DAC3164 SLAS960 –MAY 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. BLOCK DIAGRAMS Figure1. DAC3154

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1.2 V Reference 100 Pattern Test DATA0P DATA0N LVDS DACA Gain Optional Input Used for multi-DAC sync DAC3154 DAC3164 www.ti.com SLAS960 –MAY 2013 Figure2. DAC3164 Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DAC3154 DAC3164

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DACCLKP DACCLKN ALIGNP ALIGNN SYNCP SYNCN VFUSE (MSB) D9P D9N D8P D8N D7P D7N D6P D6N NC TXENABLE ALARM SDO IOVDD SDIO SCLK SDENB RESETB NC NC NC NC NC NC NC D5P D5N D4P D4N D3P D3N DATACLKP DATACLKN D2P D2N DIGVDD18 D1P D1N (LSB) D0P D0N GND PAD (backside) DAC3154 SLEEP IOUTAP IOUTAN VDDA33 EXTIO BIASJ IOUTBN IOUTBP CLKVDD18 DIGVDD18 VDDA18 NC NC VDDA33 VDDA33 NC NC VDDA18 DAC3154 DAC3164 SLAS960 –MAY 2013 www.ti.com PINOUT – DAC3154 PIN ASSIGNMENT TABLE – DAC3154 PIN I/O DESCRIPTION NAME NO. CONTROL/SERIAL SCLK 43 I Serialinterfaceclock.Internalpull-down. SDENB 42 I Serialinterfaceclock.Internalpull-up. SDIO 44 I/O Bi-directionalserialdatain3 pinmode (default).In4-pininterfacemode (registerXYZ),theSDIO pinin an inputonly.InternalPull-down. SDO 46 O Uni-directionalserialinterfacedatain4 pinmode (registerXYZ).The SDO pinistri-statedin3-pin interfacemode (default).InternalPulldown. RESETB 41 I Serialinterfaceresetinput.Activelow.Initializedinternalregistersduringhightolowtransition. Assynchronous.Internalpull-up. ALARM 47 O CMOS outputforALARM condition. TXENABLE 48 I Transmitenableactivehighinput.TXENABLE must be highfortheDATA totheDAC tobe enabled. When TXENABLE islow,thedigitallogicsectionisforcedtoall0,and any inputdataisignored.Internal pull-down. SLEEP 49 I Putsdeviceinsleep,activehigh.Internalpull-down.

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www.ti.com SLAS960 –MAY 2013 PIN ASSIGNMENT TABLE – DAC3154 (continued) PIN I/O DESCRIPTION NAME NO. DATA INTERFACE DATA[9:0]P/N 9/10- I LVDS inputdatabitsforbothchannels.Each positive/negativeLVDS pairhas an internal100 Ω 19/20 terminationresistor.Data formatrelativetoDATACLKP/N clockisDoubleData Rate (DDR) withtwo data transfersperDATACKP/N clockcycle.22/23 26/27- The dataformatisinterleavedwithchannelA (risingedge)and channelB fallingedge. 31/32 Inthedefaultmode (reversebus notenabled): DATA9P/N ismost significantdatabit(MSB) DATA0P/N ismost significantdatabit(LSB) DATACLKP/N 24/25 I DDR differentialinputdataclock.Edge tocenternominaltiming.Ch A risingedge,Ch B fallingedge in multiplexedoutputmode. SYNCP/N 6/7 I ResettheFIFO ortobe used as a syncingsource.These two functionsarecapturedwiththerisingedge ofDATACLKP/N. The signalcapturedby thefallingedge ofDATACLKP/N. ALIGNP/N 4/5 I LVPECL FIFO outputsyncrhonization.Thispositive/negativepairiscapturedwiththerisingedge of DACCLKP/N. Itisused toresettheclockdividersand formultipleDAC synchronization.Ifunused itcan be leftunconnected. OUTPUT/CLOCK DACCLKP/N 1/2 I LVPECL clockinputforDAC corewitha self-biasofapproximatelyCLKVDD18/2. IOUTAP/N 61/60 O A-ChannelDAC currentoutput.An offsetbinarydatapatternof0x0000 attheDAC inputresultsina full scalecurrentsourceand themost positivevoltageon theIOUTAP pin.Similarly,a 0xFFFF datainput resultsina 0 mA currentsourceand theleastpositivevoltageon theIOUTAP pin. IOUTBP/N 53/54 O B-ChannelDAC currentoutput.An offsetbinarydatapatternof0x0000 attheDAC inputresultsina full scalecurrentsourceand themost positivevoltageon theIOUTBP pin.Similarly,a 0xFFFF datainput resultsina 0 mA currentsourceand theleastpositivevoltageon theIOUTBP pin. REFERENCE EXTIO 58 I/O Used as externalreferenceinputwhen internalreferenceisdisabled.Requiresa 0.1µF decoupling capacitortoGND when used as referenceoutput. BIASJ 57 O Full-scaleoutputcurrentbias.For20 mA full-scaleoutputcurrent,connecta 960 Ω resistortoGND. POWER SUPPLY IOVDD 45 I SupplyvoltageforCMOS IO’s.1.8V– 3.3V. CLKVDD18 3 I 1.8Vclocksupply DIGVDD18 21,28 I 1.8Vdigitalsupply.AlsosuppliesLVDS receivers. VDDA18 50,64 I Analog1.8Vsupply VDDA33 55,56, I Analog3.3Vsupply VFUSE 8 I Digitalsupplyvoltage.(1.8V)Thissupplypinisalsoused forfactoryfuseprogramming.Connectto DVDD pinsfornormaloperation. NC 33-40, Not used.These pinscan be leftopen ortiedtoGROUND inactualapplicationuse. 51,52, 62,63 Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DAC3154 DAC3164

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DACCLKP DACCLKN ALIGNP ALIGNN SYNCP SYNCN VFUSE (MSB) D11P D11N D10P D10N D9P D9N D8P D8N D1P TXENABLE ALARM SDO IOVDD SDIO SCLK SDENB RESETB NC NC NC NC D0N D0P (LSB) D1N D7P D7N D6P D6N D5P D5N DATACLKP DATACLKN D4P D4N DIGVDD18 D3P D3N D2P D2N GND PAD (backside) DAC3164 SLEEP IOUTAP IOUTAN VDDA33 EXTIO BIASJ IOUTBN IOUTBP CLKVDD18 DIGVDD18 VDDA18 NC NC VDDA33 VDDA33 NC NC VDDA18 DAC3154 DAC3164 SLAS960 –MAY 2013 www.ti.com PINOUT – DAC3164 PIN ASSIGNMENT TABLE – DAC3164 PIN I/O DESCRIPTION NAME NO. CONTROL/SERIAL SCLK 43 I Serialinterfaceclock.Internalpull-down. SDENB 42 I Serialinterfaceclock.Internalpull-up. SDIO 44 I/O Bi-directionalserialdatain3 pinmode (default).In4-pininterfacemode (registerXYZ),theSDIO pin inan inputonly.InternalPull-down. SDO 46 O Uni-directionalserialinterfacedatain4 pinmode (registerXYZ).The SDO pinistri-statedin3-pin interfacemode (default).InternalPulldown. RESETB 41 I Serialinterfaceresetinput.Activelow.Initializedinternalregistersduringhightolowtransition. Assynchronous.Internalpull-up. ALARM 47 O CMOS outputforALARM condition. TXENABLE 48 I Transmitenableactivehighinput.TXENABLE must be highfortheDATA totheDAC tobe enabled. When TXENABLE islow,thedigitallogicsectionisforcedtoall0,and any inputdataisignored. Internalpull-down. SLEEP 49 I Putsdeviceinsleep,activehigh.Internalpull-down.

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www.ti.com SLAS960 –MAY 2013 PIN ASSIGNMENT TABLE – DAC3164 (continued) PIN I/O DESCRIPTION NAME NO. DATA INTERFACE DATA[11:0]P/N 9/10- I LVDS inputdatabitsforbothchannels.Each positive/negativeLVDS pairhas an internal100 Ω 19/20 terminationresistor.Data formatrelativetoDATACLKP/N clockisDoubleData Rate (DDR) withtwo datatransfersperDATACKP/N clockcycle.22/23, 26-27- The dataformatisinterleavedwithchannelA (risingedge)and channelB fallingedge.35/36 Inthedefaultmode (reversebus notenabled): DATA11P/N ismost significantdatabit(MSB) DATA0P/N ismost significantdatabit(LSB) DATACLK[:0]P/N 24/25 I DDR differentialinputdataclock.Edge tocenternominaltiming.Ch A risingedge,Ch B fallingedge inmultiplexedoutputmode. SYNCP/N 6/7 I ResettheFIFO ortobe used as a syncingsource.These two functionsarecapturedwiththerising edge ofDATACLKP/N. The signalcapturedby thefallingedge ofDATACLKP/N. ALIGNP/N 24/25 I LVPECL FIFO outputsyncrhonization.Thispositive/negativepairiscapturedwiththerisingedge of DACCLKP/N. Itisused toresettheclockdividersand formultipleDAC synchronization.Ifunused it can be leftunconnected. OUTPUT/CLOCK DACCLKP/N 1/2 I LVPECL clockinputforDAC corewitha self-biasofapproximatelyCLKVDD18/2. IOUTAP/N 61/60 O A-ChannelDAC currentoutput.An offsetbinarydatapatternof0x0000 attheDAC inputresultsina fullscalecurrentsourceand themost positivevoltageon theIOUTA1 pin.Similarly,a 0xFFFF data inputresultsina 0 mA currentsourceand theleastpositivevoltageon theIOUTA1 pin.The IOUTA2 pinisthecomplement ofIOUTA1. IOUTBP/N 53/54 O B-ChannelDAC currentoutput.An offsetbinarydatapatternof0x0000 attheDAC inputresultsina fullscalecurrentsourceand themost positivevoltageon theIOUTB1 pin.Similarly,a 0xFFFF data inputresultsina 0 mA currentsourceand theleastpositivevoltageon theIOUTB1 pin.The IOUTB2 pinisthecomplement ofIOUTB1. REFERENCE EXTIO 58 I/O Used as externalreferenceinputwhen internalreferenceisdisabled.Requiresa 0.1µF decoupling capacitortoGND when used as referenceoutput. BIASJ 57 O Full-scaleoutputcurrentbias.For20 mA full-scaleoutputcurrent,connecta 960 Ω resistortoGND. POWER SUPPLY IOVDD 45 I SupplyvoltageforCMOS IO’s.1.8V– 3.3V. CLKVDD18 3 I 1.8Vclocksupply DIGVDD18 21,28 I 1.8Vdigitalsupply.AlsosuppliesLVDS receivers. VDDA18 50,64 I Analog1.8Vsupply VDDA33 55,56, I Analog3.3Vsupply VFUSE 8 I Digitalsupplyvoltage.(1.8V)Thissupplypinisalsoused forfactoryfuseprogramming.Connectto DVDD pinsfornormaloperation. NC 37,38, Not used.These pinscan be leftopen ortiedtoGROUND inactualapplicationuse. 39,40, 51,52 62,63 PACKAGE/ORDERING INFORMATION (1) SPECIFIEDPACKAGE- PACKAGE ORDERING TRANSPORTPRODUCT TEMPERATURE ECO PLAN QUANTITYLEAD DESIGNATOR NUMBER MEDIARANGE DAC3154IRGCT 250 DAC3154 DAC3154IRGCR 2000 GREEN (RoHSQFN-64 RGC –40°C to85°C DAC3164IRGC25 Tape and Reel 25and no Sb/Br) DAC3164 DAC3164IRGCT 250 DAC3164IRGCR 2000 (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTI websiteatwww.ti.com. Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DAC3154 DAC3164

SLAS960 –MAY 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) VALUE UNIT VDDA33 toGND –0.5to4 VDDA18 toGND –0.5to2.3 Supplyvoltage CLKVDD18 toGND –0.5to2.3 V IOVDD toGND –0.5to4 DIGVDD18 toGND –0.5to2.3 CLKVDD18 toDIGVDD18 –0.5to0.5 VDDA18 toDIGVDD18 –0.5to0.5 Terminalvoltage DACCLKP, DACCLKN, ALIGNP, ALIGNN –0.5toCLKVDD18 + 0.5 Vrange TXENABLE, ALARM, SDO, SDIO, SCLK, SDENB, RESETB toGND –0.5toIOVDD + 0.5 IOUTAP, IOUTAN, IOUTBP, IOUTBN toGND –0.7to1.4 EXTIO, BIASJ toGND –0.5toVDDA33 + 0.5 Storagetemperaturerange –65 to150 °C ESD, Human Body Model 2 kV (1) Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings onlyand functionaloperationoftheseorany otherconditionsbeyond thoseindicatedunder“recommended operatingconditions”isnot implied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. THERMAL INFORMATION DAC3174 THERMAL METRIC (1) UNITS QFN (64PIN) θJA Junction-to-ambientthermalresistance 23.0 θJCtop Junction-to-case(top)thermalresistance 7.6 θJB Junction-to-boardthermalresistance 2.8 °C/W ψJT Junction-to-topcharacterizationparameter 0.1 ψJB Junction-to-boardcharacterizationparameter 2.8 θJCbot Junction-to-case(bottom)thermalresistance 0.2 (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953 .

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www.ti.com SLAS960 –MAY 2013 ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS TypicalvaluesatTA = 25°C, fulltemperaturerangeisTMIN = –40°C toTMAX = 85°C, DAC sample rate= 500MSPS, 50% clock dutycycle,VDDA33/IOVDD = 3.3V,VDDA18/CLKVDD18/DIGVDD18 = 1.8V,IOUT FS = 20mA (unlessotherwisenoted). DAC3154 DAC3164 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX Resolution 10 12 Bits DC ACCURACY DNL Differentialnonlinearity 1 LSB = IOUT FS /210 for ±0.04 ±0.2 DAC3154; 1 LSB = IOUT FS /212 LSB INL Integralnonlinearity ±0.15 ±0.5forDAC3164 ANALOG OUTPUTS Coarse gainlinearity ±0.4 ±0.4 LSB Offseterror Mid code offset 0.01 0.01 %FSR Withexternalreference ±2 ±2 Gain error %FSR Withinternalreference ±2 ±2 Gain mismatch Withinternalreference -2 2 -2 2 %FSR Minimum fullscaleoutputcurrent 2 2Nominalfull-scalecurrent, mAIOUT FS = 16xIBAIScurrentMaximum fullscaleoutputcurrent 20 20 Outputcompliancerange IOUTFS = 20 mA -0.5 -0.5 1 V Outputresistance 300 300 kΩ Outputcapacitance 5 5 pF REFERENCE OUTPUT Referenceoutputcurrent 100 100 nA REFERENCE INPUT Inputresistance 1 1 M Ω Smallsignalbandwidth 500 500 kHz Inputcapacitance 100 100 pF TEMPERATURE COEFFICIENTS ppm ofOffsetdrift ±1 ±1 FSR/°C Withexternalreference ±15 ±15 Gain drift Withinternalreference ±30 ±30 Referencevoltagedrift ±8 ±8 ppm /°C POWER SUPPLY Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DAC3154 DAC3164

SLAS960 –MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS (continued) TypicalvaluesatTA = 25°C, fulltemperaturerangeisTMIN = –40°C toTMAX = 85°C, DAC sample rate= 500MSPS, 50% clock dutycycle,VDDA33/IOVDD = 3.3V,VDDA18/CLKVDD18/DIGVDD18 = 1.8V,IOUT FS = 20mA (unlessotherwisenoted). DAC3154 DAC3164 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX POWER CONSUMPTION IVDDA33 3.3VAnalogsupplycurrent 52 59 52 59 mA ICLKVDD18 1.8VClocksupplycurrent 49 67 49 57 mAMODE 1 1.8VDigitalsupplycurrent fDAC = 491.52MSPS,IDIGVDD18 115 130 115 130 mA(DIGVDD18 and VFUSE) QMC on, Pdis Totalpower dissipation 464 530 464 530 mW IVDDA33 3.3VAnalogsupplycurrent 51 51 mA ICLKVDD18 1.8VClocksupplycurrent 38 38 mAMODE 2 1.8VDigitalsupplycurrent fDAC = 320 MSPS,IDIGVDD18 87 87 mA(DIGVDD18 and VFUSE) QMC on, IF= 20 MHzIIOVDD 1.8VIO Supplycurrent 0.002 0.002 mA Pdis Totalpower dissipation 396 396 mW IVDDA33 3.3VAnalogsupplycurrent 2.6 2.6 mA ICLKVDD18 1.8VClocksupplycurrent 43 43 mAMODE 3 1.8VDigitalsupplycurrent Sleepmode,IDIGVDD18 110 110 mA(DIGVDD18 and VFUSE) fDAC = 491.52MSPS, DAC insleepmodeIIOVDD 1.8VIO Supplycurrent 0.003 0.003 mA Pdis Totalpower dissipation 284 284 mW IVDDA33 3.3VAnalogsupplycurrent 1.6 4 1.6 4 mA ICLKVDD18 1.8VClocksupplycurrent 1.8 4 1.8 4 mAMODE 4 1.8VDigitalsupplycurrent Power-down mode,IDIGVDD18 1.7 3 mA(DIGVDD18 and VFUSE) no clock, Pdis Totalpower dissipation 10 26 10 26 mW PSRR Power supplyrejectionratio DC tested –0.4 0.4 -0.4 0.4 %/FSR/V T Operatingtemperature –40 85 -40 85 °C

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www.ti.com SLAS960 –MAY 2013 ELECTRICAL CHARACTERISTICS – AC SPECIFICATIONS TypicalvaluesatT A = 25°C, fulltemperaturerangeisT MIN = –40°C toT MAX = 85°C, DAC sample rate= 500MSPS, 50% clockdutycycle,VDDA33/IOVDD = 3.3V,VDDA18/CLKVDD18/DIGVDD18 = 1.8V,IOUT FS = 20mA (unlessotherwise noted). DAC3154 DAC3164 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX ANALOG OUTPUT fDAC Maximum sample rate 500 500 MSPS Outputsettlingtimetots(DAC) Transition:Code 0x0000 to0x3FFF 11 11 ns0.1% tPD Outputpropagationdelay Does notincludedigitallatency 2 2 ns Outputrisetime10% totr(IOUT) 200 200 ps90% Outputfalltime90% totf(IOUT) 200 200 ps10% LengthofdelayfromDAC inputpinstoDATA at DigitalLatency outputpins.Innormaloperationmode includingthe 26 26 µs latencyofFIFO. AC PERFORMANCE fDAC = 500 MSPS, fout= 10.1MHz 81 82 SpuriousfreedynamicSFDR fDAC = 500 MSPS, fout= 20.1MHz 76 77 dBcrange fDAC = 500 MSPS, fout= 70.1MHz 69 70 fDAC = 500 MSPS, fout= 10.1±0.5MHz 82 83 fDAC = 500 MSPS, fout= 20.1±0.5MHz 81 82 IMD3 Intermodulationdistortion dBc fDAC = 500 MSPS, fout= 70.1±0.5MHz 73.5 74 fDAC = 500 MSPS, fout= 150.1±0.5MHz 61 61 fDAC = 500 MSPS, fout= 10.1MHz 147 158 NSD Noisespectraldensity fDAC = 500 MSPS, fout= 20.1MHz 146 156 dBc/Hz fDAC = 500 MSPS, fout= 70.1MHz 146 153 fDAC = 491.52MSPS, fout= 30.72MHz, 69 77WCDMA TM1AdjacentchannelleakageACLR dBcratio fAC = 491.52MSPS, fout= 153.6MHz, 68 73WCDMA TM1 fDAC = 500 MSPS,Channelisolation 90 90 dBcfout= 20 MHz Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DAC3154 DAC3164

SLAS960 –MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS TypicalvaluesatT A = 25°C, fulltemperaturerangeisT MIN = –40°C toT MAX = 85°C, DAC sample rate= 500MSPS, 50% clockdutycycle,VDDA33/IOVDD = 3.3V,VDDA18/CLKVDD18/DIGVDD18 = 1.8V,IOUT FS = 20mA (unlessotherwise noted). DAC3154 DAC3164 PARAMETERS TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX CMOS DIGITAL INPUTS (RESETB, SDENB, SCLK, SDIO, TXENABLE) 0.6x 0.6xVIH High-levelinputvoltage VIOVDD IOVDD IIH High-levelinputcurrent –40 40 -40 40 μA IIL Low-levelinputcurrent –40 40 -40 40 μA DIGITAL OUTPUTS – CMOS INTERFACE (SDOUT, SDIO) 0.125× 0.125×VOL Low-leveloutputvoltage VIOVDD IOVDD SERIAL PORT TIMING Setuptime,SDENB torisingedge ofts(SENDB) 20 20 nsSCLK ts(SDIO) Setuptime,SDIO torisingedge ofSCLK 10 10 ns th(SDIO) Holdtime,SDIO fromrisingedge ofSCLK 5 5 ns t(SCLK) PeriodofSCLK 100 100 ns t(SCLKH) HightimeofSCLK 40 40 ns t(SCLKL) Low timeofSCLK 40 40 ns Data outputdelayafterfallingedge oftd(DATA) 10 10 nsSCLK TRESET Minimum RESTB pulsewidth LogichighdifferentialinputvoltageVA,B+ 175 175 mVthreshold LogiclowdifferentialinputvoltageVA,B– -175 –175 mVthreshold ZT Internaltermination 85 110 135 85 110 135 Ω C L LVDS inputcapacitance 2 2 pF

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www.ti.com SLAS960 –MAY 2013 ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued) TypicalvaluesatT A = 25°C, fulltemperaturerangeisT MIN = –40°C toT MAX = 85°C, DAC sample rate= 500MSPS, 50% clockdutycycle,VDDA33/IOVDD = 3.3V,VDDA18/CLKVDD18/DIGVDD18 = 1.8V,IOUT FS = 20mA (unlessotherwise noted). DAC3154 DAC3164 PARAMETERS TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX LVDS INPUT TIMING: SINGLE BUS SINGLE CLOCK MODE config3Setting datadly clkdly 0 0 -20 -20 0 1 -120 -120 0 2 -220 -220 0 3 -310 -310 0 4 -390 -390 0 5 -480 -480 Setup D[x..0]validtoDATACLK risingorts(DATA) 0 6 -560 -560 pstime fallingedge 0 7 -630 -630 1 0 70 70 2 0 150 150 3 0 230 230 4 0 330 330 5 0 430 430 6 0 530 530 7 0 620 620 congfig3Setting datadly clkdly 0 0 310 310 0 1 390 390 0 2 480 480 0 3 560 560 0 4 650 650 0 5 740 740 Hold D[x..0]validtoDATACLK risingorth(DATA) 0 6 850 850 pstime fallingedge 0 7 930 930 1 0 200 200 2 0 100 100 3 0 20 20 4 0 -60 -60 5 0 -140 -140 6 0 -220 -220 7 0 -290 -290 Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DAC3154 DAC3164

Output Frequency (dB) HD3 (dBc) 0dBFS −6dBFS −12dBFS G007 100 0 50 100 150 200 250 Output Frequency (MHz) SFDR (dBc) fDAC = 200 MSPS fDAC = 300 MSPS fDAC = 400 MSPS fDAC = 500 MSPS G008 100 0 50 100 150 200 250 Output Frequency (dB) SFDR (dBc) 0dBFS −6dBFS −12dBFS G005 100 0 50 100 150 200 250 Output Frequency (dB) HD2 (dBc) 0dBFS −6dBFS −12dBFS G006 −0.2 −0.15 −0.1 −0.05 0.05 0.1 0.15 0.2 0 200 400 600 800 1000 Code INL (LSB) G003 −0.05 −0.04 −0.03 −0.02 −0.01 0.01 0.02 0.03 0.04 0.05 0 200 400 600 800 1000 Code DNL (LSB) G004 DAC3154 DAC3164 SLAS960 –MAY 2013 www.ti.com TYPICAL CHARACTERISTICS Allplotsareat25°C, nominalsupplyvoltages,fDAC = 500MSPS, 50% clockdutycycle,0-dBFS inputsignaland 20mA full- scaleoutputcurrent(unlessotherwisenoted). Figure3.DAC3154 IntegralNonlinearity Figure4.DAC3154 DifferentialNonlinearity Figure5.DAC3154 SFDR vs Output Frequency Over Input Figure6.DAC3154 Second-Order Harmonic Distortionvs Scale Output Frequency Over InputScale Figure7.DAC3154 Third-OrderHarmonic Distortionvs Figure8.DAC3154 SFDR vs Output Frequency Over fDAC Output Frequency Over InputScale

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−100 −90 −80 −70 −60 −50 0 50 100 150 200 250 Output Frequency (MHz) ACLR (dBc) Adjacent channel fDAC = 500 MSPS G013 −100 −90 −80 −70 −60 −50 0 50 100 150 200 250 Output Frequency (MHz) ACLR (dBc) Alternate channel fDAC = 500 MSPS G012 100 110 120 130 140 150 160 170 0 50 100 150 200 250 Output Frequency (dB) NSD (dBc/Hz) 0dBFS −6dBFS −12dBFS G011 100 110 120 130 140 150 160 170 0 100 200 250 Output Frequency (MHz) NSD (dBc/Hz) fDAC = 200 MSPS fDAC = 300 MSPS fDAC = 400 MSPS fDAC = 500 MSPS G012 100 0 50 100 150 200 250 Output Frequency (dB) IMD3 (dBc) 0dBFS −6dBFS −12dBFS G009 100 0 50 100 150 200 250 Output Frequency (MHz) IMD3 (dBc) fDAC = 200 MSPS fDAC = 300 MSPS fDAC = 400 MSPS fDAC = 500 MSPS G010 DAC3154 DAC3164 www.ti.com SLAS960 –MAY 2013 TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltages,fDAC = 500MSPS, 50% clockdutycycle,0-dBFS inputsignaland 20mA full- scaleoutputcurrent(unlessotherwisenoted). Figure9.DAC3154 IMD3 vs Output Frequency Over Input Figure10.DAC3154 IMD3 vs Output Frequency Over fDAC Scale Figure11.DAC3154 NSD vs Output Frequency Over Input Figure12.DAC3154 NSD vs Output Frequency Over fDAC Scale Figure13.DAC3154 ACLR (AdjacentChannel)vs Output Figure14.DAC3154 ACLR (AlternateChannel)vs Output Frequency Frequency Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DAC3154 DAC3164

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V B W 3 0 0 k H z* S W T 2 s R e f - 2 0 d B m A t t 5 d B C L R W R

1 R M

C e n t e r 7 0 M H z S p a n 4 0 . 8 M H z4 . 0 8 M H z / - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 S t a n d a r d : W - C D M A 3 G P P F W D T x C h a n n e l s Ch1 -18.62 dBm( R e f ) Ch2 -18.64 dBm Ch3 -18.72 dBm Ch4 -18.70 dBm Total -12.65 dBm A d j a c e n t C h a n n e l Lower -61.24 dB Upper -61.34 dB A l t e r n a t e C h a n n e l Lower -61.11 dB Upper -61.39 dB A R e f - 1 0 d B m C e n t e r 7 0 M H z S p a n 1 5 . 5 M H z1 . 5 5 M H z / - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 T x C h a n n e l W - C D M A 3 G P P F W D B a n d w i d t h 3 . 8 4 M H z Power -10.64 dBm A d j a c e n t C h a n n e l B a n d w i d t h 3 . 8 4 M H z Lower -69.11 dB S p a c i n g 5 M H z Upper -69.15 dB −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 15 17 19 21 23 25 Frequency (MHz) Power (dBm) fDAC = 500 MSPS fout = 20 MHz Tone spacing = 1 MHz G017 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 65 67 69 71 73 75 Frequency (MHz) Power (dBm) fDAC = 500 MSPS fout = 70 MHz Tone spacing = 1 MHz G018 −90 −80 −70 −60 −50 −40 −30 −20 −10 10 50 90 130 170 210 250 Frequency (MHz) Power (dBm) fDAC = 491. 52MSPS fout = 20 MHz G011 −90 −80 −70 −60 −50 −40 −30 −20 −10 10 50 90 130 170 210 250 Frequency (MHz) Power (dBm) fDAC = 491. 52MSPS fout = 70 MHz G016 DAC3154 DAC3164 SLAS960 –MAY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltages,fDAC = 500MSPS, 50% clockdutycycle,0-dBFS inputsignaland 20mA full- scaleoutputcurrent(unlessotherwisenoted). Figure15.DAC3154 Single-ToneSpectralPlot(IF= 20MHz) Figure16.DAC3154 Single-ToneSpectralPlot(IF= 70MHz) Figure17.DAC3154 Two-Tone SpectralPlot(IF= 20MHz) Figure18.DAC3154 Two-Tone SpectralPlot(IF= 70MHz) Figure19.DAC3154 ACPR Four-Carrier Figure20.DAC3154 ACPR Single-Carrier WCDMA TestMode 1 WCDMA TestMode 1

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−0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0.1 0.2 0.3 0.4 0 500 1000 1500 2000 2500 3000 3500 4000 Code INL (LSB) G024 −0.2 −0.15 −0.1 −0.05 0.05 0.1 0.15 0.2 0 500 1000 1500 2000 2500 3000 3500 4000 Code DNL (LSB) G025 100 200 300 400 500 600 200 300 400 500 fDAC (MSPS) Power (mW) QMC on G023 A R e f - 1 0 d B m A t t 5 d B C L R W R S W T 2 s* C e n t e r 7 0 M H z S p a n 2 9 . 2 8 2 7 4 1 9 M H z2 . 9 2 8 2 7 4 1 9 M H z / - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 T x C h a n n e l E - U T R A / L T E S q u a r e B a n d w i d t h 9 . 0 1 5 M H z Power -12.33 dBm A d j a c e n t C h a n n e l B a n d w i d t h 9 . 0 1 5 M H z Lower -64.00 dB S p a c i n g 1 0 M H z Upper -64.09 dB A R e f - 1 0 d B m C e n t e r 7 0 M H z S p a n 5 8 . 5 5 0 3 4 5 3 8 M H z5 . 8 5 5 0 3 4 5 3 8 M H z / - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 T x C h a n n e l E - U T R A / L T E S q u a r e B a n d w i d t h 1 8 . 0 1 5 M H z Power -11.14 dBm A d j a c e n t C h a n n e l B a n d w i d t h 1 8 . 0 1 5 M H z Lower -61.93 dB S p a c i n g 2 0 M H z Upper -62.21 dB DAC3154 DAC3164 www.ti.com SLAS960 –MAY 2013 TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltages,fDAC = 500MSPS, 50% clockdutycycle,0-dBFS inputsignaland 20mA full- scaleoutputcurrent(unlessotherwisenoted). Figure21.DAC3154 ACPR LTE 10-MHz FDD E-TM 1.1 Figure22.DAC3154 ACPR LTE 20-MHz FDD E-TM 1.1 Figure23.DAC3154 Power Consumption vs fDAC Figure24.DAC3164 IntegralNonlinearity Figure25.DAC3164 DifferentialNonlinearity Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DAC3154 DAC3164

Output Frequency (dB) IMD3 (dBc) 0dBFS −6dBFS −12dBFS G030 100 0 50 100 150 200 250 Output Frequency (MHz) IMD3 (dBc) fDAC = 200 MSPS fDAC = 300 MSPS fDAC = 400 MSPS fDAC = 500 MSPS G031 100 0 50 100 150 200 250 Output Frequency (dB) HD3 (dBc) 0dBFS −6dBFS −12dBFS G028 100 0 50 100 150 200 250 Output Frequency (MHz) SFDR (dBc) fDAC = 200 MSPS fDAC = 300 MSPS fDAC = 400 MSPS fDAC = 500 MSPS G029 100 0 50 100 150 200 250 Output Frequency (dB) SFDR (dBc) 0dBFS −6dBFS −12dBFS G026 100 0 50 100 150 200 250 Output Frequency (dB) HD2 (dBc) 0dBFS −6dBFS −12dBFS G027 DAC3154 DAC3164 SLAS960 –MAY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltages,fDAC = 500MSPS, 50% clockdutycycle,0-dBFS inputsignaland 20mA full- scaleoutputcurrent(unlessotherwisenoted). Figure26.DAC3164 SFDR vs Output Frequency Over Input Figure27.DAC3164 Second-Order Harmonic Distortionvs Scale Output Frequency Over InputScale Figure28.DAC3164 Third-OrderHarmonic Distortionvs Figure29.DAC3164 SFDR vs Output Frequency Over fDAC Output Frequency Over InputScale Figure30.DAC3164 IMD3 vs Output Frequency Over Input Figure31.DAC3164 IMD3 vs Output Frequency Over fDAC Scale

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−90 −80 −70 −60 −50 −40 −30 −20 −10 10 50 90 130 170 210 250 Frequency (MHz) Power (dBm) fDAC = 491. 52MSPS fout = 20 MHz G036 −90 −80 −70 −60 −50 −40 −30 −20 −10 10 50 90 130 170 210 250 Frequency (MHz) Power (dBm) fDAC = 491. 52MSPS fout = 70 MHz G037 −100 −90 −80 −70 −60 −50 0 50 100 150 200 250 Output Frequency (MHz) ACLR (dBc) Adjacent channel fDAC = 500 MSPS G034 −100 −90 −80 −70 −60 −50 0 50 100 150 200 250 Output Frequency (MHz) ACLR (dBc) Alternate channel fDAC = 500 MSPS G035 110 120 130 140 150 160 170 180 0 50 100 150 200 250 Output Frequency (dB) NSD (dBc/Hz) 0dBFS −6dBFS −12dBFS G032 110 120 130 140 150 160 170 180 0 100 200 250 Output Frequency (MHz) NSD (dBc/Hz) fDAC = 200 MSPS fDAC = 300 MSPS fDAC = 400 MSPS fDAC = 500 MSPS G033 DAC3154 DAC3164 www.ti.com SLAS960 –MAY 2013 TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltages,fDAC = 500MSPS, 50% clockdutycycle,0-dBFS inputsignaland 20mA full- scaleoutputcurrent(unlessotherwisenoted). Figure32.DAC3164 NSD vs Output Frequency Over Input Figure33.DAC3164 NSD vs Output Frequency Over fDAC Scale Figure34.DAC3164 ACLR (AdjacentChannel)vs Output Figure35.DAC3164 ACLR (AlternateChannel)vs Output Frequency Frequency Figure36.DAC3164 Single-ToneSpectralPlot(IF= 20MHz) Figure37.DAC3164 Single-ToneSpectralPlot(IF= 70MHz) Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:DAC3154 DAC3164

A R e f - 2 0 d B m C e n t e r 7 0 M H z S p a n 2 9 . 2 8 2 7 4 1 9 M H z2 . 9 2 8 2 7 4 1 9 M H z / - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 T x C h a n n e l E - U T R A / L T E S q u a r e B a n d w i d t h 9 . 0 1 5 M H z Power -12.37 dBm A d j a c e n t C h a n n e l B a n d w i d t h 9 . 0 1 5 M H z Lower -73.67 dB S p a c i n g 1 0 M H z Upper -73.46 dB A S W T 2 sR e f - 2 0 d B m A t t 5 d B C L R W R C e n t e r 7 0 M H z S p a n 5 8 . 5 5 0 3 4 5 3 8 M H z5 . 8 5 5 0 3 4 5 3 8 M H z / - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 T x C h a n n e l E - U T R A / L T E S q u a r e B a n d w i d t h 1 8 . 0 1 5 M H z Power -11.20 dBm A d j a c e n t C h a n n e l B a n d w i d t h 1 8 . 0 1 5 M H z Lower -70.91 dB S p a c i n g 2 0 M H z Upper -70.66 dB A R e f - 1 0 d B m V B W 3 0 0 k H z* S W T 2 sA t t 5 d B C L R W R C e n t e r 7 0 M H z S p a n 4 0 . 8 M H z4 . 0 8 M H z / - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 S t a n d a r d : W - C D M A 3 G P P F W D T x C h a n n e l s Ch1 -18.70 dBm( R e f ) Ch2 -18.69 dBm Ch3 -18.77 dBm Ch4 -18.75 dBm Total -12.71 dBm A d j a c e n t C h a n n e l Lower -70.74 dB Upper -70.87 dB A l t e r n a t e C h a n n e l Lower -70.86 dB Upper -70.84 dB A S W T 2 sR e f - 1 0 d B m A t t 5 d B C L R W R C e n t e r 7 0 M H z S p a n 1 5 . 5 M H z1 . 5 5 M H z / - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 T x C h a n n e l W - C D M A 3 G P P F W D B a n d w i d t h 3 . 8 4 M H z Power -10.70 dBm A d j a c e n t C h a n n e l B a n d w i d t h 3 . 8 4 M H z Lower -77.84 dB S p a c i n g 5 M H z Upper -77.14 dB −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 15 17 19 21 23 25 Frequency (MHz) Power (dBm) fDAC = 500 MSPS fout = 20 MHz Tone spacing = 1 MHz G038 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 65 67 69 71 73 75 Frequency (MHz) Power (dBm) fDAC = 500 MSPS fout = 70 MHz Tone spacing = 1 MHz G039 DAC3154 DAC3164 SLAS960 –MAY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltages,fDAC = 500MSPS, 50% clockdutycycle,0-dBFS inputsignaland 20mA full- scaleoutputcurrent(unlessotherwisenoted). Figure38.DAC3164 Two-Tone SpectralPlot(IF= 20MHz) Figure39.DAC3164 Two-Tone SpectralPlot(IF= 70MHz) Figure40.DAC3164 ACPR Four-Carrier Figure41.DAC3164 ACPR Single-Carrier WCDMA TestMode 1 WCDMA TestMode 1 Figure42.DAC3164 ACPR LTE 10-MHz FDD E-TM 1.1 Figure43.DAC3164 ACPR LTE 20-MHz FDD E-TM 1.1

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fDAC (MSPS) Power (mW) QMC on G044 DAC3154 DAC3164 www.ti.com SLAS960 –MAY 2013 TYPICAL CHARACTERISTICS (continued) Allplotsareat25°C, nominalsupplyvoltages,fDAC = 500MSPS, 50% clockdutycycle,0-dBFS inputsignaland 20mA full- scaleoutputcurrent(unlessotherwisenoted). Figure44.DAC3164 Power Consumption vs fDAC Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:DAC3154 DAC3164

(DDR) SYNCP/N Resets write pointer to position 0 ts(DATA) th(DATA) ts(DATA) th(DATA) ts(DATA) th(DATA) DAC3154 DAC3164 SLAS960 –MAY 2013 www.ti.com DEFINITION OF SPECIFICATIONS Adjacent CarrierLeakage Ratio(ACLR): Definedas theratioindeciblerelativetothecarrier(dBc)between themeasured power withinthechanneland thatofitsadjacentchannel. Analog and DigitalPower Supply RejectionRatio(APSSR, DPSSR): Definedas thepercentageerrorinthe ratioofthedeltaIOUT and deltasupplyvoltagenormalizedwithrespecttotheidealIOUT current. DifferentialNonlinearity(DNL): Definedas the variationin analog outputassociatedwithan ideal1 LSB change inthedigitalinputcode. Gain Drift:Definedas themaximum change ingain,intermsofppm offull-scalerange(FSR) per°C, fromthe valueatambient(25°C) tovaluesoverthefulloperatingtemperaturerange. Gain Error:Definedas the percentageerror(inFSR%) forthe ratiobetween the measured full-scaleoutput currentand theidealfull-scaleoutputcurrent. IntegralNonlinearity(INL):Definedas themaximum deviationoftheactualanalogoutputfromtheidealoutput, determinedby a straightlinedrawn fromzeroscaletofullscale. IntermodulationDistortion(IMD3):The two-toneIMD3 is definedas the ratio(indBc) of the 3rd-order intermodulationdistortionproducttoeitherfundamentaloutputtone. OffsetDrift:Definedas themaximum change inDC offset,intermsofppm offull-scalerange (FSR) per °C, fromthevalueatambient(25°C) tovaluesoverthefulloperatingtemperaturerange. OffsetError:Definedas thepercentageerror(inFSR%) fortheratiobetween themeasured mid-scaleoutput currentand theidealmid-scaleoutputcurrent. Output Compliance Range: Definedas the minimum and maximum allowablevoltageat the outputof the current-outputDAC. Exceeding thislimitmay resultreduced reliabilityof the deviceor adverselyaffecting distortionperformance. Reference VoltageDrift:Definedas themaximum change ofthereferencevoltageinppm perdegreeCelsius fromvalueatambient(25°C) tovaluesoverthefulloperatingtemperaturerange. Spurious Free Dynamic Range (SFDR): Definedas thedifference(indBc) between thepeak amplitudeofthe outputsignaland thepeak spurioussignal. Signalto Noise Ratio (SNR): Definedas the ratioof the RMS valueof the fundamentaloutputsignalto the RMS sum ofallotherspectralcomponents below theNyquistfrequency,includingnoise,butexcludingthefirst sixharmonicsand dc. TIMING DIAGRAMS Figure45. DAC3154 InputTiming Diagram forDual Channel DDR Mode

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(SDR) SYNCP/N Resets write pointer to position 0 ts(DATA) th(DATA) ts(DATA) th(DATA) DATACLKP/N (DDR) SYNCP/N Resets write pointer to position 0 ts(DATA) th(DATA) ts(DATA) th(DATA) ts(DATA) th(DATA) DATACLKP/N (SDR) SYNCP/N Resets write pointer to position 0 ts(DATA) th(DATA) ts(DATA) th(DATA) DAC3154 DAC3164 www.ti.com SLAS960 –MAY 2013 Figure46. DAC3154 InputTiming Diagram forSingleChannel SDR Mode Figure47. DAC3164 InputTiming Diagram forDual Channel DDR Mode Figure48. DAC3164 InputTiming Diagram forSingleChannel SDR Mode Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:DAC3154 DAC3164

SLAS960 –MAY 2013 www.ti.com DATA INPUT FORMATS Table1.DAC3154 Dual Channel DDR Mode BITS DIFFERENTIAL PAIR (P/N) DATACLK RISING EDGE DATACLK FALLING EDGE D9 A9 B9 D8 A8 B8 D7 A7 B7 D6 A6 B6 D5 A5 B5 D4 A4 B4 D3 A3 B3 D2 A2 B2 D1 A1 B1 D0 A0 B0 SYNC FIFO WriteReset – Table2. DAC3154 SingleChannel SDR Mode BITS DIFFERENTIAL PAIR (P/N) DATACLK RISING EDGE DATACLK FALLING EDGE D9 A9 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 SYNC FIFO WriteReset – Table3.DAC3164 Dual Channel DDR Mode BITS DIFFERENTIAL PAIR (P/N) DATACLK RISING EDGE DATACLK FALLING EDGE D11 A11 B11 D10 A10 B10 D9 A9 B9 D8 A8 B8 D7 A7 B7 D6 A6 B6 D5 A5 B5 D4 A4 B4 D3 A3 B3 D2 A2 B2 D1 A1 B1 D0 A0 B0 SYNC FIFO WriteReset –

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www.ti.com SLAS960 –MAY 2013 Table4.DAC3164 SingleChannel DDR Mode BITS DIFFERENTIAL PAIR (P/N) DATACLK RISING EDGE DATACLK FALLING EDGE D11 A11 D10 A10 D9 A9 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 SYNC FIFO WriteReset – Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:DAC3154 DAC3164

rwb A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Instruction Cycle Data Transfer Cycle tS (SDENB) tS(SDIO) tH(SDIO) tSCLK SDENB SCLK SDIO SDENB SCLK SDIO DAC3154 DAC3164 SLAS960 –MAY 2013 www.ti.com SERIAL INTERFACE DESCRIPTION The serialportoftheDAC3154/DAC3164 isa flexibleserialinterfacewhichcommunicateswithindustrystandard microprocessorsand microcontrollers.The interfaceprovidesread/writeaccesstoallregistersused todefinethe operatingmodes of DAC3154/DAC3164. Itiscompatiblewithmost synchronoustransferformatsand can be configuredas a 3 or4 pininterfaceby sif4_enainregisterconfig0,bit9.Inbothconfigurations,SCLK istheserial interfaceinputclockand SDENB isserialinterfaceenable.For 3 pinconfiguration,SDIO isa bidirectionalpinfor bothdatainand dataout.For 4 pinconfiguration,SDIO isdatainonlyand SDO isdataoutonly.Data isinput intothedevicewiththerisingedge ofSCLK. Data isoutputfromthedeviceon thefallingedge ofSCLK. Each read/writeoperationisframedby signalSDENB (SerialData EnableBar)assertedlow.The firstframebyte isthe instructioncyclewhich identifiesthe followingdata transfercycleas read or writeas wellas the 7-bit addresstobe accessed.Table5 indicatesthefunctionofeach bitintheinstructioncycleand isfollowedby a detaileddescriptionofeach bit.The datatransfercycleconsistsoftwo bytes. Table5.InstructionbyteoftheSerialinterface MSB LSB Bit 7 6 5 4 3 2 1 0 Description R/W A6 A5 A4 A3 A2 A1 A0 R/W Identifiesthefollowingdatatransfercycleas a readorwriteoperation.A highindicatesa read operationfromDAC3154/DAC3164 and a lowindicatesa writeoperationtoDAC3154/DAC3164. [A6:A0] Identifiestheaddressoftheregistertobe accessedduringthereadorwriteoperation. Figure49 shows theserialinterfacetimingdiagramfora DAC3154/DAC3164 writeoperation.SCLK istheserial interfaceclock input to DAC3154/DAC3164. Serialdata enable SDENB is an activelow input to DAC3154/DAC3164. SDIO isserialdatain.InputdatatoDAC3154/DAC3164 isclockedon therisingedges of SCLK. Figure49. SerialInterfaceWriteTiming Diagram Figure50 shows theserialinterfacetimingdiagramfora DAC3154/DAC3164 readoperation.SCLK istheserial interfaceclock input to DAC3154/DAC3164. Serialdata enable SDENB is an activelow input to DAC3154/DAC3164. SDIO isserialdatainduringtheinstructioncycle.In3 pinconfiguration,SDIO isdataout from the DAC3154/DAC3164 duringthe data transfercycle,whileSDO isina high-impedancestate.In 4 pin configuration,bothSDIO and SDO are dataoutfrom theDAC3154/DAC3164 duringthedatatransfercycle.At theend ofthedatatransfer,SDIO and SDO willoutputlow on thefinalfallingedge ofSCLK untiltherisingedge ofSDENB when theywill3-state.

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rwb A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Instruction Cycle Data Transfer Cycle td(Data) SDENB SCLK SDIO SDENB SCLK SDIO SDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0SDO Data n Data n-1 DAC3154 DAC3164 www.ti.com SLAS960 –MAY 2013 Figure50. SerialInterfaceRead Timing Diagram REGISTER DESCRIPTIONS IntheSIF interfacetherearefourtypesofregisters: NORMAL: The NORMAL registertypeallowsdatatobe writtenand readfrom.All16-bitsofthedataare registeredatthesame time.Thereisno synchronizingwithan internalclockthusallregister writesareasynchronouswithrespecttointernalclocks.TherearethreesubtypesofNORMAL: AUTOSYNC: A NORMAL registerthatcausesa synctobe generatedafterthewriteis finished.These aremost commonly used inthingslikeoffsetsand phaseadd where thereisa word orblocksetupthatextendsacrossmultipleregisters and alloftheregistersneed tobe programmed beforeany takeeffecton the circuit.Forexample,thephaseadd istwo registerslong.Itwouldn’tservethe usertohave thefirstwrite16 ofthe32 bitscause a change inthefrequency, so thedesignallowsalltheregisterstobe writtenand thenwhen thatlast one forthisblockisfinished,an autosyncisgeneratedforthemixertellingit tograballthenew SIF values.Thiswilloccuron a mixerclockcycleso that no meta-stabilityerrorsoccur. No RESET Value: These areNORMAL registers,butforone reasonoranotherresetvaluecan notbe guaranteed.Thiscouldbe because theregisterhas some read_only bitsorsome internallogicpartiallycontrolsthebitvalues.An example isthe SIF_CONFIG6 register.The bitscome fromthetemperaturesensorand the fuses.Dependingon whichfusesareblownand what thedietemp isthe resetvaluewillbe different. FUSE controlled:Whilethisisn’ta typeofregister,you may see thisdescriptioninthearea describingthedefaultvaluefortheregister.What ismeans isthatfuseswill change thedefaultvalueand thevalueshown inthedocument isforwhen no fusesareblown. READ_ONLY: RegistersthatareinternalwiresANDed withtheaddressbus thenconnectedtotheSIF outputdatabus. WRITE_TO_CLEAR: These registersarejustlikeNORMAL registerswithone exception.They can be written and read,however,when theinternallogicasynchronouslysetsa bithighinone of theseregisters,thatbitstayshighuntilitiswrittento‘0’.Thisway interruptswillbe capturedand stayconstantuntilclearedby theuser. Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:DAC3154 DAC3164

SLAS960 –MAY 2013 www.ti.com Table6.RegisterMap (MSB) (LSB)Name Address Default Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1Bit15 Bit0 config0 0x00 0x44FC qmc_ dual_ena chipwidth(1:0) reserved twos sif4_ena reserve fifo_ena alarm_ alarm_ alignrx_en syncrx_en lvdsdataclk_ reserved synconly_en offset_ena d out_ena out_pol a a ena a config1 0x01 0x600E iotest_ena bsideclk_e fullword_i64cnt_ena dacclkgon dataclkgone collision_enareserve daca_ dacb_ sif_sync sif_ alarm_ alarm_1awa alarm_coll reserved na nterface_ e_ ena _ena d compliment complime sync_ena 2away_en y_ena ision_ena ena nt a config2 0x02 0x3FFF reserved lvdsdata_ena(13:0) config3 0x03 0x0000 datadlya(2:0) clkdlya(2:0) datadlyb(2:0) clkdlyb(2:0) extref_ena reserved dual_ena config4 0x04 0x0000 reserved iotest_results(13:0) config5 0x05 0x0000 alarm_fro alarm_fro alarms_from_fifoa(2:0) alarms_from_fifob(2:0) alarm_dacclk alarm_dat clock_gon alarm_fro alarm_fro reserved m_ m_ _ gone aclk_ e m_ iotesta m_ iotestb zerochka zerochkb gone config6 0x06 0x0084(D tempdata(7:0) fuse_cntl(5:0) reserved AC3164) 0x0088(D AC3154) config7 0x07 0xFFFF alarms_mask(15:0) config8 0x08 0x4000 reserved qmc_offseta(12:0) config9 0x09 0x8000 fifo_offset(2:0) qmc_offsetb(12:0) config10 0x0A 0xF080 coarse_dac(3:0) fuse_ reserved reserved tsense_ clkrecv_ena sleepa sleepb reserved sleep sleep config11 0x0B 0x1111 reserved reserved reserved reserved config12 0x0C 0x3A7A reserved iotest_pattern0(13:0) config13 0x0D 0x36B6 reserved iotest_pattern1(13:0) config14 0x0E 0x2AEA reserved iotest_pattern2(13:0) config15 0x0F 0x0545 reserved iotest_pattern3(13:0) config16 0x10 0x1A1A reserved iotest_pattern4(13:0) config17 0x11 0x1616 reserved iotest_pattern5(13:0) config18 0x12 0x2AAA reserved iotest_pattern6(13:0) config19 0x13 0x06C6 reserved iotest_pattern7(13:0) config20 0x14 0x0000 sifdac_ reserved sifdac(13:0) ena config21 0x15 0xFFFF sleepcntl(15:0) config22 0x16 0x0000 fa002_data(15:0) config23 0x17 0x0000 fa002_data(31:16) config24 0x18 0x0000 fa002_data(47:32) config25 0x19 0x0000 fa002_data(63:48) config127 0x7F 0x0044 reserved reserved reserved reserved reserved titest_voh titest_vol vendorid(1:0) versionid(2:0)

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www.ti.com SLAS960 –MAY 2013 Registername: config0– Address: 0x00,Default:0x44FC Register Addr Bit Name Function DefaultValueName (Hex) config0 0x00 15 qmc_offset_ena Enabletheoffsetfunctionwhen asserted. 0 14 dual_ena UtilizesbothDACs when asserted. 1 FUSE controlled 13:12 chipwidth Programmable bitsforsettingtheinputinterfacewidth. 00 00:all14 bitsareused.NOTE: not applicableto DAC3154/DAC3164. 01:upper12 bitsareused 10:upper10 bitsareused 11:upper10 bitsareused 11 reserved reserved 0 10 twos When asserted,thisbittellsthechiptopresume 2’s 1 complement dataisarrivingattheinput.Otherwiseoffset binaryispresumed. 9 sif4_ena When assertedtheSIF interfacebecomes a 4 pininterface. 0 Thisbithas a lowerprioritythanthedieid_enabit. 8 reserved reserved 0 7 fifo_ena When asserted,theFIFO isabsorbingthedifferencebetween 1 INPUT clockand DAC clock.Ifitisnotassertedthenthe FIFO bufferingisbypassedbutthereversingofbitsand handlingofoffsetbinaryinputisstillavailable.NOTE: When theFIFO isbypassed theDACCCLK and DATACLK must be alignedor theremay be timingerrors;and,itisnot recommended foractualapplicationuse. 6 alarm_out_ena When assertedthepinalarmbecomes an outputinsteadofa 1 tri-statedpin. 5 alarm_out_pol Thisbitchanges thepolarityoftheALARM signal. 1 (0=negativelogic,1=positivelogic) 4 alignrx_ena When assertedtheALIGN pinreceiverispowered up.NOTE: 1 Itisrecommended toclearthisbitwhen ALIGNP/N are not used. 3 syncrx_ena When assertedtheSYNC pinreceiverispowered up.NOTE: 1 Itisrecommended toclearthisbitwhen SYNCP/N are not used. 2 lvdsdataclk_ena When assertedtheDATACLK pinreceiverispowered up. 1 1 reserved reserved 0 0 synconly_ena When assertedthechipisputintotheSYNC ONLY mode 0 where theSYNC pinisused as thesyncinputforboththe frontand back oftheFIFO. Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:DAC3154 DAC3164

SLAS960 –MAY 2013 www.ti.com Registername: config1– Address: 0x01,Default:0x600E Register Addr DefaultBit Name FunctionName (Hex) Value config1 0x01 15 iotest_ena Turnson theio-testingcircuitrywhen asserted.Thisisthecircuitry0 thatwillcompare a 8 sample inputpatterntoSIF programmed registerstomake surethedatacoming intothechipmeets setup/holdrequirements.Ifthisbitisa ‘0’thentheclocktothis circuitryisturnedoffforpower savings.NOTE: Sample 0 should be alignedwiththerisingedge ofSYNC. 14 bsideclk_ena When assertedtheinputclockfortheB sidedatapathisenabled. 1 OtherwisetheIO TEST and theFIFO on theB sideofthedesign willnotgeta clock. 13 reserved reserved. 1 12 64cnt_ena Thisenablestheresettingofthealarmsafter64 good sampleswith 0 thegoalofremovingunnecessaryerrors.Forinstanceon a lab board,when checkingthesetup/holdthroughIO TEST, theremay initiallybe errors,butonce thetestisup and runningeverything works.Settingthisbitremoves theneed fora SIF writetoclearthe alarmregister. 11 dacclkgone_ena ThisallowstheDACCLK gone signalfromtheclockmonitortobe 0 used toshuttheoutputoff. 10 dataclkgone_end ThisallowstheDATACLK gone signalfromtheclockmonitortobe 0 used toshuttheoutputoff. 9 collision_ena ThisallowsthecollisionalarmfromtheFIFO toshuttheoutputoff 0 8 reserved reserved. 0 7 daca_compliment When assertedtheoutputtotheDACA iscomplimented.This 0 allowstheuserofthechiptoeffectivelychange the+ and – designationsoftheDAC outputpins. 6 dacb_compliment When assertedtheoutputtotheDACB iscomplimented.This 0 allowstheuserofthechiptoeffectivelychange the+ and – designationsoftheDAC outputpins. 5 sif_sync ThisistheSIF_SYNC signal.Whateverisprogrammed intothisbit 0 willbe used as thechipsyncwhen SIF_SYNC mode isenabled. Designissensitivetorisingedges so programmingfrom0->1 is when thesyncpulseisgenerated.1->0 has no effect. 4 sif_sync_ena When assertedenableSIF_SYNC mode. 0 3 alarm_2away_ena When assertedalarmsfromtheFIFO thatrepresentthepointers 1 being2 away areenabled 2 alarm_1away_ena When assertedalarmsfromtheFIFO thatrepresentthepointers 1 being1 away areenabled 1 alarm_collision_ena When assertedthecollisionofFIFO pointerscausesan alarmtobe 1 generated 0 reserved reserved 0 Registername: config2– Address: 0x02,Default:0x3FFF Register Addr Bit Name Function DefaultValueName (Hex) config2 0x02 15 reserved reserved 0 14 reserved reserved 0 13:0 lvdsdata_ena These 14 bitsareindividualenablesforthe14 inputpinreceivers. 0x3FFF NOTE: Itisrecommended toclearbit(1:0)forthe12-bit DAC3164, and clearbit(3:0)forthe10-bitDAC3154.

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www.ti.com SLAS960 –MAY 2013 Registername: config3– Address: 0x03,Default:0x0000 Register Addr Bit Name Function DefaultValueName (Hex) config3 0x03 15:13 datadlya ControlsthedelayoftheA datainputsthroughtheLVDS receivers.000 0= no additionaldelayand each LSB adds a nominal80ps. 12:10 clkdlya ControlsthedelayoftheA dataclockinputthroughtheLVDS 000 receivers.0= no additionaldelayand each LSB adds a nominal 80ps. 9:7 datadlyb ControlsthedelayoftheB datainputsthroughtheLVDS receivers.000 0= no additionaldelayand each LSB adds a nominal80ps. 6:4 clkdlyb ControlsthedelayoftheB dataclockinputthroughtheLVDS 000 receivers.0= no additionaldelayand each LSB adds a nominal 80ps. 3 extref_ena EnableexternalreferencefortheDAC when set. 0 2:1 reserved reserved 00 0 dual_clock_ena When assertedittellstheLVDS inputcircuitthattherearetwo 0 individualdataclocks.NOTE: must be inSIF_SYNC mode, and not applicabletoDAC3154/DAC3164. Registername: config4– Address: 0x04,Default:0x0000 Register Addr DefaultBit Name FunctionName (Hex) Value config4 0x04 15:14 reserved reserved 00 WRITE TO 13:0 iotest_results The valuesofthesebitstellwhichbitintheinputword failedduringthe 0x0000CLEAR/ io-testpatterncomparison.Bit13 correspondstotheMSB input.No RESET value Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:DAC3154 DAC3164

SLAS960 –MAY 2013 www.ti.com Registername: config5– Address: 0x05,Default:0x0000 Register Addr DefaultBit Name FunctionName (Hex) Value config5 0x05 15 alarm_from_zerochka When thisbitisassertedtheFIFO A writepointerhas an allzeros 0 WRITE TO patterninit.Sincethispointerisa shiftregister,allzeroswillcause CLEAR theinputpointtobe stuckuntilthenextsync.The resultcouldbe a repeated8T patternattheoutputifthemixerisoffand no syncs occur.Check forthiserrorwilltelltheuserthatanothersyncis necessarytorestarttheFIFO writepointer. 14 alarm_from_zerochkb When thisbitisassertedtheFIFO B writepointerhas an allzeros 0 patterninit.Sincethispointerisa shiftregister,allzeroswillcause theinputpointtobe stuckuntilthenextsync.The resultcouldbe a repeated8T patternattheoutputifthemixerisoffand no syncs occur.Check forthiserrorwilltelltheuserthatanothersyncis necessarytorestarttheFIFO writepointer. 13:11 alarms_from_fifoa These bitsreporttheFIFO A pointerstatus. 000 000:Allfine 001:Pointersare2 away 01X:Pointersare1 away 1XX: FIFO Pointercollision 10:8 alarms_from_fifob These bitsreporttheFIFO B pointerstatus. 0 000:Allfine 001:Pointersare2 away 01X:Pointersare1 away 1XX: FIFO Pointercollision 7 alarm_dacclk_gone Bitgetsassertedwhen theDACCLK has been stoppedlongfor 0 enough cyclestobe caught.The number ofcyclesvarieswith interpolation. 6 alarm_dataclk_gone Bitgetsassertedwhen theDATACLK has been stoppedlongfor 0 enough cyclestobe caught.The number ofcyclesvarieswith interpolation. 5 clock_gone Thisbitgetssetwhen eitheralarm_dacclk_goneor 0 alarm_dataclk_goneareasserted.Itcontrolstheoutputofthe CDRV_SER block.When high,theCDRV_SER blockwilloutput “0x8000”foreach outputconnectedtoa DAC. The bitmust be writtento‘0’forCDRV_SER outputstoresume normaloperation. 4 alarm_from_iotesta Thisisassertedwhen theinputdatapatterndoes notmatch the 0 patternintheiotest_patternregisters. 3 alarm_from_iotestb Thisisassertedwhen theinputdatapatterndoes notmatch the 0 patternintheiotest_patternregisters. 2 reserved reserved 0 1 reserved reserved 0 0 reserved reserved 0

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www.ti.com SLAS960 –MAY 2013 Registername: config6– Address: 0x06,Default:0x0084 (DAC3164);0x0088 (DAC3154) Register Addr DefaultBit Name FunctionName (Hex) Value config6 0x06 15:8 tempdata Thistheoutputfromthechiptemperaturesensor. 0x00 No RESET NOTE: when readingthesebitstheSIF interfacemust be exteremly Value slow,1MHz range. 7:2 fuse_cntl These arethevaluesoftheblownfusesand areused todeterminethe 0x21 for availablefunctionalityinthechip. DAC3164; 0x22 forNOTE: These bitsareREAD_ONLY and allowtheuser tocheck DAC3154what featureshave been disabledinthedevice. bit5= 1:Forcefullword interface. bit4= 1:reserved bit3= 1:reserved bit2= 1:ForcesSingleDAC Mode. Note:Thisdoes not forcethe channel B insleepmode. Inordertodo so,user needs toprogram thesleepbSPI bit(config10,bit5)to"1". bit1:0:Forcesa differentbitssize. “00”14bit. “01”12bit “10”10bit “11”10bit 1 reserved reserved 0 0 reserved reserved 0 Registername: config7– Address: 0x07,Default:0xFFFF Register Addr DefaultBit Name FunctionName (Hex) Value config7 0x07 15:0 alarms_mask Each bitisused tomask an alarm.Assertionmasks thealarm:bit15= 0xFFFF alarm_mask_zerochka bit14= alarm_mask_zerochkb bit13= alarm_mask_fifoa_collision bit12= alarm_mask_fifoa_1away bit11= alarm_mask_fifoa_2away bit10= alarm_mask_fifob_collision bit9= alarm_mask_fifob_1away bit8= alarm_mask_fifob_2away bit7= alarm_mask_dacclk_gone bit6= alarm_mask_dataclk_gone bit5= Masks thesignalwhichturnsofftheDAC outputwhen a clockor collisionoccurs.Thisbithas no effecton thePAD_ALARM output. bit4= alarm_mask_iotesta bit3= alarm_mask_iotestb bit2= bit1= bit0= Registername: config8– Address: 0x08,Default:0x4000 Register Addr DefaultBit Name FunctionName (Hex) Value config8 0x08 15:13 reserved reserved 010 12:0 qmc_ offseta The DAC A offsetcorrection.The offsetismeasured inDAC LSBs. 0x0000 Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:DAC3154 DAC3164

/c40 /c41VrefIO mem_coarse_daca + 1 Rbias /c180 DAC3154 DAC3164 SLAS960 –MAY 2013 www.ti.com Registername: config9– Address: 0x09,Default:0x8000 Register Addr DefaultBit Name FunctionName (Hex) Value config9 0x09 15:13 fifo_offset ThisisthestartingpointfortheREAD_POINTER intheFIFO block. 100 The READ_POINTER issettothislocationwhen a syncoccurson theAUTO DACCLK sideoftheFIFO.SYNC 12:0 qmc_ offsetb The DAC B offsetcorrection.The offsetismeasured inDAC LSBs. 0x0000 NOTE: Writingthisregistercauses an autosync tobe generatedin theQMOFFSET block. Registername: config10– Address: 0x0A, Default:0xF080 Register Addr DefaultBit Name FunctionName (Hex) Value Config10 0x0A 15:12 coarse_dac Scalestheoutputcurrentis16 equalsteps. 1111 11 fuse_sleep Putthefusestosleepwhen sethigh. 0 10 reserved reserved 0 9 reserved reserved 0 8 tsense_sleep When assertedthetemperaturesensorisputtosleep. 0 7 clkrecv_ena Turnon theDAC CLOCK receiverblockwhen asserted. 1 6 sleepa When assertedDACA isputtosleep. 0 5 sleepb When assertedDACB isputtosleep.Note:Thisbitneeds tobe 0 programmed to"1"forsingleDAC mode. 4:0 reserved reserved 00000 Registername: config11– Address: 0x0B, Default:0x1111 Register Addr Bit Name Function DefaultValueName (Hex) config11 0x0B 15:12 reserved reserved 0001 11:8 reserved reserved 0001 7:4 reserved reserved 0001 3:0 reserved reserved 0001 Registername: config12– Address: 0x0C, Default:0x3A7A Register Addr Bit Name Function DefaultValueName (Hex) config12 0x0C 15:14 reserved reserved 00 13:0 iotest_pattern0 Thisisdataword0intheIO testpattern.Itisused withtheseven 0x3A7A otherwords totesttheinputdata.NOTE: Thisword should be alignedwiththerisingedge ofSYNC when testingtheIO interface. Registername: config13– Address: 0x0D, Default:0x36B6 Register Addr Bit Name Function DefaultValueName (Hex) config13 0x0D 15:14 reserved reserved 00 13:0 iotest_pattern1 Thisisdataword1intheIO testpattern.Itisused withtheseven 0x36B6 otherwords totesttheinputdata.

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www.ti.com SLAS960 –MAY 2013 Registername: config14– Address: 0x0E,Default:0x2AEA Register Addr Bit Name Function DefaultValueName (Hex) config14 0x0E 15:14 reserved reserved 00 13:0 iotest_pattern2 Thisisdataword2intheIO testpattern.Itisused withtheseven 0x2AEA otherwords totesttheinputdata. Registername: config15– Address: 0x0F,Default:0x0545 Register Addr Bit Name Function DefaultValueName (Hex) config15 0x0F 15:14 reserved reserved 00 13:0 iotest_pattern3 Thisisdataword3intheIO testpattern.Itisused withtheseven 0x0545 otherwords totesttheinputdata. Registername: config16– Address: 0x10,Default:0x1A1A Register Addr Bit Name Function DefaultValueName (Hex) config16 0x10 15:14 reserved reserved 00 13:0 iotest_pattern4 Thisisdataword4intheIO testpattern.Itisused withtheseven 0x1A1A otherwords totesttheinputdata. Registername: config17– Address: 0x11,Default:0x1616 Register Addr Bit Name Function DefaultValueName (Hex) config17 0x11 15:14 reserved reserved 00 13:0 iotest_pattern5 Thisisdataword5intheIO testpattern.Itisused withtheseven 0x1616 otherwords totesttheinputdata. Registername: config18– Address: 0x12,Default:0x2AAA Register Addr Bit Name Function DefaultValueName (Hex) config18 0x12 15:14 reserved reserved 00 13:0 iotest_pattern5 Thisisdatawor6intheIO testpattern.Itisused withtheseven 0x2AAA otherwords totesttheinputdata. Registername: config19– Address: 0x13,Default:0x06C6 Register Addr Bit Name Function DefaultValueName (Hex) config19 0x13 15:14 reserved reserved 00 13:0 iotest_pattern7 Thisisdataword7intheIO testpattern.Itisused withtheseven 0x06C6 otherwords totesttheinputdata. Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:DAC3154 DAC3164

SLAS960 –MAY 2013 www.ti.com Registername: config20– Address: 0x14,Default:0x0000 Register Addr Bit Name Function DefaultValueName (Hex) config20 0x14 15 sifdac_ena When assertedtheDAC outputissettothevalueinsifdac.This 0 can be used fortrimsettingand otherstatictests. 14 reserved reserved 0 13:0 sifdac ThisisthevaluethatissenttotheDACs when sifdac_enais 0x0000 asserted. Registername: config21– Address: 0x15,Default:0xFFFF Register Addr Bit Name Function DefaultValueName (Hex) config21 0x15 15:0 sleepcntl Thiscontrolswhat blocksgetsenta SLEEP signalwhen the 0xFFFF PAD_SLEEP pinisasserted.Programming a ‘1’ina bitwillpass theSLEEP signaltotheappropriateblock. bit15= DAC A bit14= DAC B bit13= FUSE Sleep bit12= TemperatureSensor bit11= ClockReceiver bit10= LVDS DATA Receivers bit9= LVDS SYNC Receiver bit8= PECL ALIGN Receiver bit7= LVDS DATACLK Receiver bit6= bit5= bit4= bit3= bit2= bit1= bit0= Registername: config22– Address: 0x16 Register Addr Bit Name Function DefaultValueName (Hex) config22 0x16 15:0 fa002_data(15:0) Lower 16bitsoftheDIE ID word READ ONLY Registername: config23– Address: 0x17 Register Addr Bit Name Function DefaultValueName (Hex) config23 0x17 15:0 fa002_data(31:16) Lower middle16bitsoftheDIE ID word READ ONLY Registername: config24– Address: 0x18,Default Register Addr Bit Name Function DefaultValueName (Hex) config24 0x18 15:0 fa002_data(47:32) Upper middle16bitsoftheDIE ID word READ ONLY

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www.ti.com SLAS960 –MAY 2013 Registername: config25– Address: 0x19 Register Addr Bit Name Function DefaultValueName (Hex) config25 0x19 15:0 fa002_data(63:48) Upper 16bitsoftheDIE ID word READ ONLY Registername: config127– Address: 0x7F,Default:0x0045 Register Addr DefaultBit Name FunctionName (Hex) Value config127 0x7F 15:14 reserved reserved 00 READ 13:12 reserved reserved 00ONLY/No 11:10 reserved reserved 00RESET Value 9:8 reserved reserved 00 7 reserved reserved 0 6 titest_voh A fixed‘1’thatcan be used totesttheVoh attheSIF output. 1 5 titest_vol A fixed‘0’thatcan be used totesttheVolattheSIF output. 0 4:3 vendorid Fixedto"01". 01 2:0 versionid Chipversion. 001 SynchronizationModes Therearethreemodes ofsyncingincludedintheDAC3154/DAC3164.

• NORMAL Dual Sync – The SYNC pinisused toaligntheinputsideoftheFIFO (writepointers)withtheA(0) sample.The ALIGN pin isused to resetthe outputsideof the FIFO (readpointers)to the offsetvalue. Multiplechipalignmentcan be accomplishedwiththiskindofsyncing.
• SYNC ONLY – Inthismode onlytheSYNC pinisused tosync boththereadand writepointersoftheFIFO. Thereisan asynchornizedhandoffbetween theDATACLK and DACCLK when usingthismode, thereforeitis impossibletoaccuratelyalignmultiplechipscloserthan2 or3T.
• SIF_SYNC – When neitherSYNC nor ALIGN are used,a programmable SYNC pulsecan be used tosync thedesign.However, thesame issuesas SYNC ONLY apply.There isan asynchornizedhandoffbetween theserialclockdomain and thetwo sidesoftheFIFO.Because oftheasynchronousnatureoftheSIF_SYNC itisimpossibletoalignthesyncup withany sample attheinput. Note:When ALIGNP/N are not used, itisrecommended to clearthe alignrx_enaregister(config1,bit4), and tieALIGNP to DIGVDD18 and ALIGNN to GROUND. When SYNCP/N are not used, itisrecommended to clearregistersyncrx_ena (config0,bit3),and the unused SYNCP/N pins can be leftopen or tiedto GROUND. Copyright© 2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:DAC3154 DAC3164

SLAS960 –MAY 2013 www.ti.com Alarm Monitoring DAC3154/DAC3164 includesflexiblealarmmonitoringthatcan be used toalerta possiblemalfunctionscenario. Allalarmeventscan be accessedeitherthroughtheSIP registersand/orthroughtheALARM pin.Once an alarm isset,thecorrespondingalarmbitinregisterconfig5must be resetthroughtheserialinterfacetoallowfurther testing.The setofalarmsincludesthefollowingconditions: Zerocheckalarm

• Alarm_from_zerochk.Occurswhen theFIFO writepointerhas an allzerospattern.Sincethewritepointerisa shiftregister,allzeroswillcause theinputpointtobe stuckuntilthenextsync event.When thishappens a synctotheFIFO blockisrequired. FIFO alarms
• alarm_from_fifo.Occurswhen thereisa collisionintheFIFO pointersora collisioneventisclose.
• alarm_fifo_2away.Pointersarewithintwo addressesofeach other.
• alarm_fifo_1away.Pointersarewithinone addressofeach other.
• alarm_fifo_collision.Pointersareequaltoeach other. Clockalarms
• clock_gone.Occurswhen eithertheDACCLK orDATACLOCK have been stopped.
• alarm_dacclk_gone.Occurswhen theDACCLK has been stopped.
• alarm_dataclk_gone.Occurswhen theDATACLK has been stopped. Patterncheckeralarm
• alarm_from_iotest.Occurswhen theinputdatapatterndoes notmatch thepatternkey. To preventunexpectedDAC outputsfrom propagatingintothe transmitchannelchain,DAC3154, DAC3164 includesa featurethatdisablestheoutputswhen a catastrophicalarmoccurs.The catastrophicalarmsinclude FIFO pointercollision,thelossDACCLK orthelossofDATACLK. When any ofthesealarmsoccurtheinternal TXenable signalisdrivenlow,causinga zeroingofthedatagoingtotheDAC in<10T. One caveatisifboth clocksstop,thecircuitcannotdetermineclocklossso no alarmsaregenerated;therefore,no zeroingofoutput dataoccurs.

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www.ti.com 7-Apr-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DAC3154IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 DAC3154I DAC3154IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 DAC3154I DAC3164IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 DAC3164I DAC3164IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 DAC3164I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

www.ti.com 7-Apr-2016 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC3154IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 DAC3154IRGCT VQFN RGC 64 250 336.6 336.6 28.6 DAC3164IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 DAC3164IRGCT VQFN RGC 64 250 336.6 336.6 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2016 Pack Materials-Page 2

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