DAC1220E TI | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 26

Technical content

2nd−Order ΔΣ Modulator Instruction Register Command Register Data Register Offset Register Full−Scale Register Microcontroller 1st−Order Switched Capacitor Filter 2nd−Order Continuous Time Post Filter Modulator Control AV DD AGNDXIN XOUT VREF CS DV DD DGND C 1 C 2 SDIO VOUT SCLK DAC1220 20-Bit,Low-Power Digital-to-AnalogConverter Check forSamples: DAC1220 1FEATURES DESCRIPTION 2• 20-BitMonotonicityEnsured Over –40°C to The DAC1220 is a 20-bitdigital-to-analog(D/A) +85°C converteroffering20-bitmonotonicperformanceover the specified temperature range. It utilizes• Low Power: 2.5mW delta-sigmatechnologyto achieveinherentlylinear• VoltageOutput performanceina smallpackage at verylow power.

  • SettlingTime: 2ms to0.012% The resolutionof the devicecan be programmed to 20 bitsforFull-Scale,settlingto0.003% within15ms• Maximum LinearityError:±0.0015% typical,or 16 bitsforFull-Scale,settlingto 0.012%• On-Chip Calibration within2ms max. The outputrange istwo timesthe external reference voltage. On-chip calibrationAPPLICATIONS circuitrydramaticallyreduces low offsetand gain
  • Process Control errors.
  • ATE Pin Electronics The DAC1220 features a synchronous serial• Closed-Loop Servo Control interface;in single-converterapplications,the serial
  • Smart Transmitters interfacecan be accomplishedwithjusttwo wires, allowinglow-costisolation.For multipleconverters,a• PortableInstruments CS signalallowsforselectionoftheappropriateD/A converter. The DAC1220 has been designed forclosed-loop controlapplicationsin the industrialprocesscontrol market and high-resolutionapplicationsin the test and measurement market.Itisalsoidealforremote applications,battery-powered instruments,and isolatedsystems.The DAC1220 is availablein an SSOP-16 package. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1998–2009,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. PACKAGE/ORDERING INFORMATION For the most currentpackage and orderinginformationsee the Package OptionAddendum at the end of this document,orsee theTIweb siteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operatingfree-airtemperaturerange(unlessotherwisenoted). DAC1220 UNIT AV DD toDV DD ±0.3 V AV DD toAGND –0.3to+6 V DV DD toDGND –0.3to+6 V AGND toDGND ±0.3 V VREF voltagetoAGND +2.0to+3.0 V DigitalinputvoltagetoDGND –0.3toDV DD + 0.3 V DigitaloutputvoltagetoDGND –0.3toDV DD + 0.3 V Package power dissipation (TJmax – TA)/θ JA W Maximum junctiontemperature(TJmax) +150 °C Thermalresistance,θ JA SSOP-16 200 °C/W Lead temperature(soldering,10s) +300 °C (1) Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedundertheElectricalCharacteristics isnotimplied.Exposuretoabsolutemaximum ratedconditionsforextendedperiodsmay affectdevicereliability.

2 SubmitDocumentationFeedback Copyright© 1998–2009,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC1220

ELECTRICAL CHARACTERISTICS

AllspecificationsatTMIN toTMAX ,AV DD = DV DD = +5V, fXIN = 2.5MHz,VREF = +2.5V,and 16-bitmode, unlessotherwisenoted. DAC1220E PARAMETER CONDITIONS MIN TYP MAX UNIT ACCURACY Monotonicity 16 Bits Monotonicity 20-bitmode 20 Bits Linearityerror ±15(1) ppm ofFSR Unipolaroffseterrorand gainerror(2) ±60 ppm ofFSR Unipolaroffseterrordrift(3) 1 ppm/°C Bipolarzerooffseterror(2) VOUT = VREF ±15 ppm ofFSR Bipolarzerooffsetdrift(3) 1 ppm/°C Gain error(2) ±150 ppm ofFSR Gain errordrift(3) 2 ppm/°C Power-supplyrejectionratio(PSRR) atDC, dB = –20log(ΔVOUT /ΔVDD ) 60 dB ANALOG OUTPUT Outputvoltage(4) 0 2 × VREF V Outputcurrent 0.5 mA Capacitiveload 500 pF Short-circuitcurrent ±20 mA Short-circuitduration GND orVDD Indefinite DYNAMIC PERFORMANCE Settlingtime(5) To ±0.012% 1.8 2 ms 20-bitmode, to±0.003% 15 ms Outputnoisevoltage 0.1Hzto10Hz 1 μVRMS REFERENCE INPUT Inputvoltage 2.25 2.5 2.75 V Inputimpedance 100 kΩ DIGITAL INPUT/OUTPUT Logicfamily TTL-compatibleCMOS Logiclevels(allexceptXIN) VIH 2.0 DV DD + 0.3 V VIL –0.3 0.8 V VOH IOH = –0.8mA 3.6 V VOL IOL = 1.6mA 0.4 V Input-leakagecurrent ±10 μA XIN frequencyrange(fXIN) 0.5 2.5 MHz Offsetbinarytwo's complementData format User-programmable orstraightbinary POWER-SUPPLY REQUIREMENTS Power-supplyvoltage 4.75 5.25 V Supplycurrent Analogcurrent 360 μA Digitalcurrent 140 μA Analogcurrent 20-bitmode 460 μA (1) ValidfromAGND + 20mV toAV DD – 20mV. (2) Appliesaftercalibration. (3) Recalibrationcan remove theseerrors. (4) Idealoutputvoltage;does nottakeintoaccountgainand offseterror. (5) ValidfromAGND + 20mV toAV DD – 20mV. Outsideofthisrange,settlingtimecan be twicethevalueindicated. For16-bitmode, C 1 = 2.2nF,C 2 = 0.22nF;for20-bitmode, C 1 = 10nF,C 2 = 3.3nF. Copyright© 1998–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):DAC1220

ELECTRICAL CHARACTERISTICS (continued) AllspecificationsatTMIN toTMAX ,AV DD = DV DD = +5V, fXIN = 2.5MHz,VREF = +2.5V,and 16-bitmode, unlessotherwisenoted. DAC1220E PARAMETER CONDITIONS MIN TYP MAX UNIT POWER-SUPPLY REQUIREMENTS, continued Digitalcurrent 20-bitmode 140 μA Power dissipation 2.5 3.5 mW 20-bitmode 3.0 mW Sleepmode 0.45 mW TEMPERATURE RANGE Specifiedperformance –40 +85 °C DEVICE INFORMATION PIN DESCRIPTIONS PIN NAME DESCRIPTION

1 DV DD Digitalsupply,+5V nominal

2 XOUT System clockoutput(forcrystal)

3 XIN System clockinput

4 DGND Digitalground

5 AV DD Analogsupply,+5V nominal

6 DNC Do notconnect

7 DNC Do notconnect

8 DNC Do notconnect

9 C 1 Filtercapacitor(seetext)

10 C 2 Filtercapacitor(seetext)

11 VOUT Analogoutputvoltage

12 VREF Referenceinput

13 AGND Analogground

14 CS Chip-selectinput

15 SDIO Serialdatainput/output

16 SCLK Clockinputforserialdatatransfer

4 SubmitDocumentationFeedback Copyright© 1998–2009,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC1220

Frequency (Hz) 10 100 1k 10k PSRR (dB) 400mV PP Ripple Mid− Range Output Time (ms) 0 1 2 3 4 (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Code 0 10k 20k 30k 40k 50k 60k 70k Linearity Error (ppm) −40°C +25°C +85°C Frequency (Hz) 10 100 1k 10k 100k 1M Noise (nV/√Hz) 10k 100 DAC1220 TYPICAL CHARACTERISTICS AtTA = +25°C, AV DD = DV DD = +5.0V,fXIN = 2.5MHz,VREF = 2.5V,C 1 = 2.2nF,and calibratedmode, unlessotherwise specified. POWER-SUPPLY REJECTION RATIO vs FREQUENCY LARGE-SIGNAL SETTLING TIME Figure1. Figure2. OUTPUT NOISE VOLTAGE LINEARITY ERROR vs vs FREQUENCY CODE Figure3. Figure4. Copyright© 1998–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):DAC1220

12pF(1) 12pF(1) 4.7µF Ceramic 2.5MHz +2.5V from Voltage Reference VOUT SPI CLOCK SPI DATA From Chip Select or Ground +5V C 2 (2) C 1 (2)4.7µF Ceramic +5V NOTES: (1) Depends on crystal and board layout. (2) See text for recommended values. DAC1220 THEORY OF OPERATION Self-CalibrationSystemThe DAC1220 isa monolithic20-bitdelta-sigma(ΔΣ) digital-to-analogconverter (DAC) designed for The self-calibrationsystem of the DAC1220 applicationsrequiringextremelyhigh precision.The measures theDAC outputand calculatesappropriate delta-sigmatopologyused inthe DAC1220 ensures gain and offsetcalibrationconstants.The output 20-bitmonotonicityover the industrialtemperature changes during calibration,but can optionallybe range.The DAC1220 can alsobe operatedin16-bit disconnectedduringtheprocedure. mode, which gives a fastersettlingtime at the Offsetcalibrationis performedby settingthe DACexpense ofhighernoise. outputvoltagetomid-scaleand repeatedlycomparing The coreoftheDAC1220 consistsofan interpolation the DAC output to the VREF voltage using an filterand a second-orderdelta-sigmamodulator.The auto-zeroedcomparator,which is re-zeroedafter outputof the modulatoris passed to a first-order every comparison. The comparator resultsare switched-capacitorfilterinserieswitha second-order recordedand averaged,two’s complement adjusted, continuous-timefilter,which generates the output and placedintheOffsetCalibrationRegister. voltage. Gain calibrationisperformedina similarway, except To increasesettlingtime,theDAC1220 can adjustits that the correction is done against an filtercutofffrequencywhen itdetectsa voltageoutput internally-generatedreferencevoltage,and the final step of greaterthan approximately40mV. This registervalueiscalculateddifferently.The Full-Scale behaviorcan be disabled. CalibrationRegisterresultrepresentsthe gain code and isnottwo’s complement adjusted.Changing theAn onboard self-calibrationfacilitycompensates for Gain Register value can change the range ofinternaloffsetand gainerrors.Calibrationvaluesmay voltagesthatare outputforthe same digitalcodes,be storedand loadedexternallyifdesired. centeredon VREF . The DAC1220 can be putintoa sleepmode, inwhich power consumption is cut by about 1/6 to BASIC CONNECTIONS approximately0.45mW. Insleepmode, theoutputis A schematic showing basic connectionsto thedisconnected. DAC1220 isgiveninFigure5. The DAC1220 is controlledusing a synchronous serialinterface,usingeithertwo or threewires.The interfacemay be operated bidirectionallyor unidirectionally;readbackisoptional. Figure5. DAC1220 Schematic

6 SubmitDocumentationFeedback Copyright© 1998–2009,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC1220

The outputvoltagerangeisnominally0V to2 × VREF . The digitallines,exceptforthecrystaloscillatorlines, Itdoes notgo below ground.The outputamplifieris operateat TTL-compatibleCMOS logiclevels.They notdesignedforheavy loads;itcan drivea maximum can be drivenfrom3.3Vlogicsources. of 0.5mA. At power-on and duringsleepmode, the In noise-sensitiveapplications,itmay be helpfultoamplifieris disconnected,so the output is high keep the leveltransitionrateson the digitallinesimpedance. slow.Fast transitionscan couplethroughthe device The outputisnot fullylinearto the rails;maximum to the output,causingnoise.Rate limitingcan be linearityisspecifiedfrom(AGND + 20mV) to(AVDD – done withresistanceoreven an RC filter. 20mV). For linearityfrom 0–5V, AV DD can be increasedto 5.02V or more, and AGND can be Clock Oscillator decreasedto–20mV orless.As longas thespecified The DAC1220 has a built-incrystaloscillatoratpinsoperatinglimitsare observed,thiswillnot damage XIN and XOUT . To use it,connecta crystaland loadthedevice. capacitorsas shown inFigure5. FilterCapacitors 12pF loadcapacitorsareshown intheschematic,but significantportionofthecrystalloadcapacitance.Table1.FilterCapacitorValues When the crystaloscillatorisoperating,a sinusoidalCAPACITOR 16-BITMODE 20-BITMODE signalofrelativelylow amplitudewillbe observedatC 1 2.2nF 10nF boththeXIN and XOUT pins. C 2 0.22nF 3.3nF The typicalfrequencyto use withthe DAC1220 is The capacitorsshouldbe stableand highgrade.Film 2.5MHz. Deviatingtoo farfrom thismay alternoise types,or other capacitorsdesigned for precision and settlingtime,as wellas timingcharacteristics. filtering,are stronglyrecommended. Low-quality capacitorswilldegradeperformancesignificantly. Connecting an ExternalClock The C 1 and C 2 pinsare verysensitive.Itiscriticalto An externalclocksignalcan be connectedat XIN. A surroundthem with a guard ringat the reference CMOS orTTL logicsignalcan be used.Ifan external voltageforbestnoiseperformance.See the Layout clocksignalisused,XOUT shouldbe leftunconnected. sectionformore information. In some cases,an RC filteron the clocklinemay reducenoise.VoltageReference The voltagereferenceinputisdesignedfor+2.5V.At thisvoltage,the outputwillrange from ground to approximately5V,as notedabove. Copyright© 1998–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):DAC1220

Figure 6. The diode ensures that DV DD willnotthatthelinewillnotbe floating. chip-selectlinemust be controlled;otherwise,itcan The DAC1220 does not have a brownout detector. supplyconnections.Both are intendedto operateat Supply Decoupling+5V. thepinsas possiblebeingdecoupled.

8 SubmitDocumentationFeedback Copyright© 1998–2009,Texas InstrumentsIncorporated

The serialinterfaceissynchronousand controlledby theSCLK input.The DAC1220 latchesincomingbitson the fallingedge of SCLK, and shiftsoutgoingbitson the risingedge of SCLK. An externalinterfaceshouldshift outgoingbitson the risingedge of SCLK, and latchincomingbitson the fallingedge of SCLK. The relevant waveforms are illustratedin the timingdiagrams (see Figure7 to Figure11).Timing numbers are givenin Table2 throughTable4. Figure7. XIN Clock Timing Table2.XIN Timing Characteristics SYMBOL DESCRIPTION MIN NOM MAX UNITS fXIN XIN clockfrequency 1 2.5 MHz tXIN XIN clockperiod 400 1000 ns t1 XIN clockhigh 0.4× tXIN ns t2 XIN clocklow 0.4× tXIN ns Figure8. SerialInput/OutputTiming Table3.SerialI/OTiming Characteristics SYMBOL DESCRIPTION MIN NOM MAX UNITS t3 SCLK high 5 × tXIN ns t4 SCLK low 5 × tXIN ns t5 Data invalidtoSCLK fallingedge (setup) 40 ns t6 SCLK fallingedge todatainnotvalid(hold) 20 ns t7 Data outvalidtorisingedge ofSCLK (hold) 0 ns t8 SCLK risingedge tonew dataoutvalid(delay) 50 ns Copyright© 1998–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):DAC1220

SDIO IN7OUT0OUT1IN0IN1IN7 OUTM Read Register Data OUT MSB OUT0 t12 t10 SDIO is an input SDIO is an output IN7 t13 t11 IN0 CS SCLK SDIO DAC1220 Figure9. SerialInterfaceTiming (CS Low) Figure10. SerialInterfaceTiming (UsingCS) Figure11. SDIO InputtoOutput TransitionTiming Table4.SerialInterfaceTiming Characteristics SYMBOL DESCRIPTION MIN NOM MAX UNITS Fallingedge oflastSCLK forcommand tot9 13 × tXIN nsrisingedge offirstSCLK forregisterdata t10 Fallingedge ofCS torisingedge ofSCLK 11 × tXIN ns Fallingedge oflastSCLK forcommand toSDIO ast11 8 × tXIN 10 × tXIN nsoutput SDIO as outputtorisingedge offirstSCLKt12 4 × tXIN nsforregisterdata Fallingedge oflastSCLK forregisterdatatoSDIOt13 4 × tXIN 6 × tXIN nstri-state Fallingedge oflastSCLK forregisterdatato t14 risingedge offirstSCLK ofnextcommand (CS tied 41 × tXIN ns low) t15 Risingedge ofCS tofallingedge ofCS (usingCS) 22 × tXIN ns

10 SubmitDocumentationFeedback Copyright© 1998–2009,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC1220

The chip-selectpin CS is activelow.When CS is SCLK Reset Pattern high,activityon SCLK isignored.There are certain The DAC1220 does not have a dedicatedresetpin.timing limitsand delays which apply to the Instead,itcontainsa circuitwhich waitsfora specialmanipulationof CS, as shown in Figure10. These patterntoappear on SCLK, and triggerstheinternalmust be observed,ortheDAC1220 may malfunction. hardware reset linewhen it detectsthe special IfCS isnotused,itshouldbe tiedlow.When CS is pattern. tiedlow,differenttiminglimitsand delaysmust be Thispattern,calledtheSCLK resetpattern,isshownobserved,as shown inFigure9.Iftheseareviolated, inFigure12,withtiminginformationgiveninTable5.theDAC1220 may malfunction. The patternisverydifferentfrom the usualclocking The serialinterfaceis byte-oriented.All data is patternswhichappearon SCLK, and isunlikelytobe transferredingroupsofeightbits. detectedby accidentduringnormaloperation. The SCLK resetpatterncan onlybe triggeredwhenI/ORecovery CS islow.When CS ishigh,theSCLK lineisignored, and theSCLK resetpatternisnotdetected.The DAC1220 has a timeouton theserialinterface.If fCLK is2.5MHz, the timeoutisapproximately100ms. At 2.5MHz, ifa command is interrupted,and no activityoccurson the SCLK or CS linesfor100ms, the DAC1220 willcancel the command. If the command was a writecommand, no registersare affected. The timeoutperiodscaleswiththefrequencyoffCLK . Figure12. ResettingtheDAC1220 Table5.Reset Timing Characteristics SYMBOL DESCRIPTION MIN NOM MAX UNITS t16 Firsthighperiod 512 × tXIN 800 × tXIN ns t17 Low period 10 × tXIN ns t18 Second highperiod 1024 × tXIN 1800 × tXIN ns t19 Thirdhighperiod 2048 × tXIN 2400 × tXIN ns Copyright© 1998–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):DAC1220

CommunicationwiththeDAC1220 consistsentirelyof Registers The formatofthecommand byteisshown inTable6, Modes and the bitsare describedin Table 7. DAC1220 The DAC1220 has threeoperatingmodes: Sleep,commands access theregistermap, which isshown Normal,and SelfCalibration.inTable11.A DAC1220 command can readorwrite one byte,or two or three adjacentbytes,in the In Sleep mode, the DAC1220 outputis off(high registermap. impedance),and much of the internalcircuitryis switchedoff.In thismode the DAC1220 draws little Bitand Byte Order power. The oscillatorcontinuesto run, however. Sleepisthemode enteredafterreset.The orderofthebitsofdatabytesina command is configurable.The DAC1220 can be programmed to InNormal mode, theDAC1220 isfullyactive,and the output data bytes MSB firstor LSB first.The outputison. affectthecommand byte;thisalwayscomes first. Table6.Command Byte Format 7 6 5 4 3 2 1 0 R/W MB 0 ADR Table7.Command Byte Bits BIT(S) NAME VALUE DESCRIPTION

7 R/W 0 Writetoregistermap

1 Read fromregistermap

6–5 MB Number ofbytestoreadorwrite 00b 1 byte 01b 2 bytes 10b 3 bytes 11b Reserved;do notuse 3–0 ADR 0–15 Startaddressinregistermap

12 SubmitDocumentationFeedback Copyright© 1998–2009,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC1220

StartupSequence Since the calibrationfunctionsare linear,calibration resultscan be averaged forgreaterprecision.ForAt startup,the followingprocedureshouldgenerally example, itmay be beneficialto perform severalbe followedtoproperlyinitializetheDAC1220: self-calibrationsin succession,recordthe resultof 1. Ifthe DAC1220 isbeingclockedfrom a crystal, each,averagethem together,and storetheaverages wait for the oscillatorto start— at least intheOCR and FCR. 25ms — beforeattemptingtocommunicate withit. Tryingtocommunicate withtheDAC1220 before Self-CalibrationProcedurethe crystaloscillatorhas reached its final To performa self-calibration,placetheDAC1220 intofrequency will usually result in corrupt SelfCalibrationmode by settingthe MD1 bitto '0'communication. power-up ensures thatthe DAC1220 is reset IftheCALPIN bitintheCommand Registeris'1',the properly,and notlingeringinan unknown statein output remains connected during calibration.The case of POR failure, brownout, etc. DAC voltage willchange during the calibration Aftera successfulreset,the DAC1220 enters process.Thiscan be importantifthe DAC outputis Normal mode. loaded significantly;disconnectingthe outputduring calibrationplaces a high load impedance on the3. Set up the Command Registeras desired.This outputamplifier,which may be differentfrom normalmay includechanging the mode from Sleep to operation.SelfCalibrationorNormal. 4. Calibratethe DAC1220. Although thisstep is IftheCALPIN bitintheCommand Registeris'0',the optional,the DAC1220 shouldalmostalways be outputwillbe disconnectedduringcalibration.Ifthis calibrated.It is permissibleto run calibration isthe case,when calibrationbegins,the DAC1220 every time,or to use values from a previous brieflychargestheC 2 capacitortothecurrentoutput calibration.See theCalibrationsectionfordetails. voltage.If the output is buffered,C 2 effectively becomes a sample-and-holdcapacitor,so thattheAftercalibration,the DAC1220 returnsto Normal finaloutputvoltageremainsduringcalibration.mode. The DAC1220 isreadytoacceptdataonce it isinNormal mode, butcalibrationortheuse ofsaved When the calibrationis complete,the DAC1220 calibrationvaluesishighlyrecommended. switches to Normal mode. If the output was disconnected,itisreconnectedatthattime.The end Calibration of the calibrationprocedure can be detectedby pollingtheMD1 and MD0 bits.When theybecome 0,Calibrationisgoverned by two registers.The Offset thecalibrationiscomplete.CalibrationRegister (OCR) stores a value determiningthe offsetcalibration,and the Full-Scale Ifreadback is not being performed,simplywaitat CalibrationRegister(FCR) storesa valuedetermining least500ms beforesendingfurthercommands tothe thegaincalibration. device,assumingthattheclockfrequencyis2.5MHz. The valueintheOCR isscaledand additive.Ithas a Once calibrationis complete,the OCR and FCR linearrelationshipto the generatedoffsetcalibration containthe resultsof the calibration,and the new voltage.The value in the FCR is scaled and constantsareeffectiveimmediately. multiplicative.It has a linearrelationshipto the generatedgaincalibrationmultiplier. Copyright© 1998–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):DAC1220

SettingtheOutput Voltage The code may be givenin eitherstraightbinaryor For reference,severalidealoutputvoltagesforgivenThe DAC1220 operatesineither16- or 20-bitmode. inputcodes areshown inTable9.The DIR is24 bitswide,and thecode storedinitis leftjustified,withthe leastsignificantbitsignored. Note thatthe DIR code can also be consideredaTherefore,in16-bitmode, onlythe upper 16 bitsof 24-bitnumber.Thismay be convenientinsoftware.IntheDIR are significant,and in20-bitmode, onlythe thiscase the transferfunctionsfor16- and 20-bitupper20 bitsoftheDIR aresignificant. modes are thesame, exceptthatin16-bitmode the code istruncatedby eightbits,and in20-bitmode theIn 20-bitmode, allthreebytesof the DIR must be code istruncatedby fourbits.writtentoinordertocompletelyupdatethecode.In 16-bitmode, itisonlynecessaryto writeto the two upperbytes;a writetothelowerbytehas no effecton theoutput. Table8.TransferFunctions DATA FORMAT 20-BITMODE 16-BITMODE Offsettwo'scomplement Straightbinary Table9.Example Output Voltages APPROXIMATE OUTPUT VOLTAGE RESOLUTION DATA FORMAT CODE DIR CONTENT (1) Two'scomplement 8000h 8000xxh 16-bit Straightbinary 0000h 0000xxh Two'scomplement 8000h 80000xh 20-bit Straightbinary 0000h 00000xh Two'scomplement 0000h 0000xxh 16-bit Straightbinary 8000h 8000xxh 2.5V Two'scomplement 0000h 00000xh 20-bit Straightbinary 8000h 80000xh Two'scomplement 7FFFh 7FFFxxh 16-bit Straightbinary FFFFh FFFFxxh Two'scomplement 7FFFFh 7FFFFxh 20-bit Straightbinary FFFFFh FFFFFxh (1) x = Do notcare

14 SubmitDocumentationFeedback Copyright© 1998–2009,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC1220

To speed up settling,the DAC1220 can change the REGISTERS cutofffrequencyofitsoutputfilter.Raisingthecutoff The registermap isshown inTable11.frequencycauses theDAC1220 tosettlefaster,butat the expense of highernoise.The adaptivefiltering Table11.RegisterMemory Mapmode providesa good compromise by increasingthe ADDRESS CONTENTfilterfrequencyonly whilethe DAC is changing its outputby more thanapproximately40mV. When the 0 DIR byte2 (MSB) outputhas settled,the filterfrequencyis reduced 1 DIR byte1 again. 2 DIR byte0 (LSB) Adaptivefilteringiscontrolledby theADPT and DISF 3 Reserved bitsin the Command Register.The actionof these 4 CMR byte1 (MSB) bitstogetherisdescribedinTable10. 5 CMR byte0 (LSB) 6 ReservedTable10.FastSettlingModes

7 ReservedADPT DISF

8 OCR byte2 (MSB)(CMR bit15) (CMR bit4) FAST SETTLING MODE

9 OCR byte10 0 Fastsettlingonlyduring> 40mV

step 10 OCR byte0 (LSB) 0 1 Disabled 11 Reserved 1 0 Fastsettlingalwayson (filtercutoff 12 FCR byte2 (MSB)increased)

13 FCR byte11 1 Disabled

14 FCR byte0 (LSB)

Command Register(CMR) The command registercontainstheconfigurationbitsoftheDAC1220. Itisshown inTable12.The bitsinthe command registerareshown inTable13. Writesto the CMR takeeffectat the negativeedge of SCLK duringthe lastbitof the lastbyteof the write command. blank Table12.Command Register 15 14 13 12 11 10 9 8 ADPT CALPIN Reserved Reserved Reserved Reserved CRST Reserved R/W-0 R/W-0 R-1(1) R-0 R-1 R-0 R/W-0 R-0 (1)InearlyversionsoftheDAC1220, thisbitwas rw-0.See theCalibrationsectionfordetails. 7 6 5 4 3 2 1 0 RES CLR DF DISF BD MSB MD R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-10b LEGEND: R = Read, W = Write Copyright© 1998–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):DAC1220

Table13.Command RegisterBits BIT(S) NAME VALUE DESCRIPTION 15 ADPT Controlsadaptivefiltering.ifDISF isset,thisbithas no effect. 0 Adaptivefilteringenabled(default). 1 Adaptivefilteringdisabled. 14 CALPIN 0 Outputisdisconnected(highimpedance)duringcalibration(default). 1 Outputisconnectedduringcalibration. 13 Reserved Write'1'tothisbit.On earlyversionsofthedevice,thisbitiswritableand defaultstozero,butstillshouldbe setto'1'.On currentdevicesthisbitisread- onlyand alwaysreads'1'.See theCalibrationsectionfordetails. 12 Reserved Read-only.Always'0'. 11 Reserved Read-only.Always'0'. 10 Reserved Read-only.Always'0'.

9 CRST InNormal mode, writing'1'tothisbitresetsthecalibrationregisters,setting

OCR to000000h and FCR to800000h.InNormal mode, thisbitalwaysreads '0'. InSleepmode, thisbitisread/write,and has no effect. Writing'1'tothisbitand switchingtoNormal mode atthesame timewillreset thecalibrationregisters. 0 Do notclearcalibrationregisters. 1 Clearcalibrationregisters. 8 Reserved Read-only.Always'0'. 7 RES Selectsresolution. 0 16-bitresolution(default). 1 20-bitresolution. 6 CLR InNormal mode, writing'1'tothisbitwrites0 tothedataregister. InSleepmode, thisbitisread/write,and has no effect. Writing'1'tothisbitand switchingtoNormal mode atthesame timewillreset thedataregister. The actualvoltagethattheDAC1220 willoutputon settingthisbitdepends on thedataformatselectedby DF. IfDF is1,zerogives0V;ifDF is0,zerogives VREF (mid-scale). 0 Do notclearcalibrationregisters. 1 Clearcalibrationregisters. 5 DF Selectsbinarynumber formatofthedataregister. 0 Offsettwo'scomplement (default). 1 Straightbinary. 4 DISF Can be used toinhibitfastsettlingand/oradaptivefiltering.See textfordetails. 0 Fastsettlingand/oradaptivefilteringenabled(default). 1 Fastsettlingdisabled;filteralwaysatdefaultcutoff.

3 BD Selectsaddressincrementordecrementwhen readingorwritingmultiplebytes,

exceptwhen writingtothecommand register.The command registerisalways writtentoinincrementmode (mostsignificantbytefirst).Reads fromthe command registerareaccordingtothisbit. 0 Addressisincrementedaftereach byte(default). 1 Addressisdecrementedaftereach byte.

16 SubmitDocumentationFeedback Copyright© 1998–2009,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC1220

Table13.Command RegisterBits(continued) BIT(S) NAME VALUE DESCRIPTION

2 MSB Selectstheorderinwhichbitsareshiftedinand outoftheDAC1220, except

when writingtothecommand register.The command registerisalwayswritten toMSB first.Reads fromthecommand registerareaccordingtothisbit. 0 Data isshiftedMSB first(default). 1 Data isshiftedLSB first. 1-0 MD Operatingmode. 00b Normal mode (default). 01b Selfcalibrationmode. (No otherbitsshouldbe changed intheCommand Registerwhen settingthismode.) 10b Sleepmode. 11b Reserved. Data InputRegister(DIR) The Data Input Registerdetermines the output After reset,the OCR contains zero. See the voltageinNormal mode. CalibrationsectionforfurtherdetailsabouttheOCR. In Sleep mode, writingto thisregisterhas no effect Full-ScaleCalibrationRegister(FCR)on the output,but the valueisstored.The valuein theDIR becomes effectiveimmediatelyupon entering The Full-ScaleCalibrationRegisterstoresthe gain Normal mode. calibrationconstant.The content of the DIR is adjusted multiplicativelyby this value beforeAfterreset,theDIR containszero. conversionby theDAC. See thesection,SettingtheOutputVoltageforfurther In Sleep mode, writingto thisregisterhas no effectdetailsabouttheData InputRegister. on the output,but the valueisstored.The valuein the FCR becomes effectiveimmediately uponOffsetCalibrationRegister(OCR) enteringNormal mode. The OffsetCalibrationRegistercontainsa 24-bit Afterreset,theFCR contains800000h.two'scomplement value.Thisvalueisadded to the valueintheDIR beforeconversionby theDAC. See the Calibrationsectionforfurtherdetailsabout theFCR.In Sleep mode, writingto thisregisterhas no effect on the output,but the valueisstored.The valuein the OCR becomes effectiveimmediately upon enteringNormal mode. Copyright© 1998–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):DAC1220

APPLICATION INFORMATION

Note thatthedelaysareslightlydifferentifchip-selectLayout Recommendations (CS) isnotbeingused. The DAC1220 isa high-precisionanalogcomponent Timing delays from the beginningof an SPI byteincorporatingdigitalelements. Achieving good transmission are a common problem inprecisionis not difficult,but achievingexcellent microcontrollerfirmwarethatuses an SPI peripheral.precisionmay requireseveralattempts. Be sure thatany delayroutinebeginsonce a byte has completed transmission,or add the byteItiscriticaltosupplya guard ring,or fill,around the transmissiontimetothedelaytime.C 1 and C 2 pins.The guard ringshouldbe connected to the voltagereference.These nodes are very Some programmers may findthatbit-banging, orsensitive,and are good placesfornoise to couple directmanipulationofmicrocontrollerI/Opins,isthethroughto the output.A ground fillon the opposite easiestway to communicate with the DAC1220,sideoftheboard,or a ground plane,isalsoa good because of the delays and directionchangesidea. required. The capacitorsthemselvesshouldbe placedas near thepinsas possible.Inparticular,thetracesleading Write-OnlyInterfacing fromC 1 and C 2 shouldbe keptveryshort.The traces In some situations,such as isolatedinterfacing,itisleadingtoVOUT and VREF can be longer. inconvenientto use the DAC1220 bidirectionally, Itisalsoveryimportantto routedigitaltracesaway sincethe SDIO pin changes directionforreadback. from analog traces,so thattheirassociatedreturn The DAC1220 can be used write-only.The following currentswillnotcoupleintotheanalogside. considerationsapply:

  • When used write-only,itisnot possibleto verifyIfa crystalisused,do notroutethetracesconnecting thatthe DAC1220 is operatingusing itsserialthe crystalto the devicethroughvias,ifpossible, interfacealone.The operationof the DAC isbecause thiswillincreasethe traceinductanceand open-loop.may affectstartupand reliability.Keep the traces
  • Itmay be helpfulto waitat least150ms-200msshort,and placethecrystalclosetothedevice.Keep afterstartup.Thisensuresthat,incase theresetin mind thatextraground planesand tracelengths was a resultof firmware problems and notincreaseparasiticcapacitance,and thisshould be power-up,any previouscommunicationwiththedeductedfromtheloadcapacitorvalues. DAC has been cancelledby the I/O recovery timeout.SoftwareConsiderations
  • When applyingtheSCLK resetpattern,whichcanA key to communicating successfullywith the be done inplaceoftheabove steps,allowtimeforDAC1220 is observingthe delays in the interface the oscillatorto startbeforeapplyingthe pattern.timingdiagrams.A violationofthesedelays,atbest, The patternisdetectedbased on oscillatorcycles,resultsinlackofcorrectoutput;atworse,violatingthe so itwillnotbe detectediftheoscillatorisnotyetdelayscan corruptcommunicationsentirely. running.

18 SubmitDocumentationFeedback Copyright© 1998–2009,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC1220

P1.1 P1.0 8051 Opto Coupler Opto Coupler Isolated Power C 2 C 1 = DGND = AGND = Isolated DAC1220 Isolation Full-ScaleRange (FSR)— This isthe magnitude of isolatedconnectionis shown in Figure 13. Here, Gain Error— This errorrepresentsthe differencein chip-selectis unused and thereforegrounded,and the slope between the actualand idealtransfer theDAC1220 isbeingoperatedunidirectionally. functions. LinearityError— The deviationoftheactualtransferDAC1220 Revisions functionfrom an idealstraightlinebetween thedata end points.As of thiswriting,there have been two released revisionsof the DAC1220. The only difference Least SignificantBit (LSB) Weight— This is thebetween the two versionsisbit13 of the Command ideal change in voltage that the analog outputRegister.In the firstrevision,thisbitwas writable, changes witha change in the digitalinputcode ofand defaultedto'0'.Inthecurrentrevision,whichwas 1LSB.releasedin 1999, thisbitisfixedat '1',and isnot writable. Monotonicity— Monotonicityassuresthattheanalog outputwillincreaseor staythe same forincreasingFor firstrevisionchips,always writea '1'to thisbit. digitalinputcodes.Althoughthe bitis not critical,performanceis not optimalunlessthisbitisset. OffsetError— The differencebetween the expected and actualoutput,when theoutputiszero.The valueThis does no harm in currentrevisionchips,and iscalculatedfrommeasurements made when VOUT =ensuresthatfirstrevisionchipsperformoptimally. 20mV. SettlingTime— The timeittakestheoutputtosettleDefinitionofTerms to a new value afterthe digitalcode has beenDifferentialNonlinearity Error— The difference changed.between an actualstepwidthand the idealvalueof fXIN — The frequency of the crystaloscillatoror1LSB. If the step width is exactly1LSB, the CMOS-compatible inputsignalattheXIN inputofthedifferentialnonlinearityerroris zero.A differential DAC1220.nonlinearityspecificationof lessthan 1LSB ensures monotonicity. Drift— The change ina parameterovertemperature. Figure13. IsolationforTwo-Wire Interface Copyright© 1998–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):DAC1220

REVISION HISTORY

20 SubmitDocumentationFeedback Copyright© 1998–2009,Texas InstrumentsIncorporated

ProductFolderLink(s):DAC1220

www.ti.com 16-Aug-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) DAC1220E ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC1220E/2K5 ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC1220E/2K5G4 ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR DAC1220EG4 ACTIVE SSOP DBQ 16 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC1220E/2K5 SSOP DBQ 16 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 Pack Materials-Page 2

Texas InstrumentsIncorporatedand itssubsidiaries(TI)reservetherighttomake corrections,enhancements,improvementsand other changes toitssemiconductorproductsand servicesperJESD46C and todiscontinueany productorserviceperJESD48B. Buyersshould obtainthelatestrelevantinformationbeforeplacingordersand shouldverifythatsuch informationiscurrentand complete.All semiconductorproducts(alsoreferredtohereinas “components”)aresoldsubjecttoTI’s termsand conditionsofsalesuppliedatthetime oforderacknowledgment. TIwarrantsperformanceofitscomponents tothespecificationsapplicableatthetimeofsale,inaccordancewiththewarrantyinTI’s terms and conditionsofsaleofsemiconductorproducts.Testingand otherqualitycontroltechniquesareused totheextentTIdeems necessary tosupportthiswarranty.Exceptwhere mandated by applicablelaw,testingofallparametersofeach component isnotnecessarily performed. TIassumes no liabilityforapplicationsassistanceorthedesignofBuyers’products.Buyersareresponsiblefortheirproductsand applicationsusingTIcomponents.To minimizetherisksassociatedwithBuyers’productsand applications,Buyersshouldprovide adequatedesignand operatingsafeguards. TIdoes notwarrantorrepresentthatany license,eitherexpressorimplied,isgrantedunderany patentright,copyright,mask work right,or otherintellectualpropertyrightrelatingtoany combination,machine,orprocessinwhichTIcomponents orservicesareused.Information publishedby TIregardingthird-partyproductsorservicesdoes notconstitutea licensetouse such productsorservicesora warrantyor endorsementthereof.Use ofsuch informationmay requirea licensefroma thirdpartyunderthepatentsorotherintellectualpropertyofthe thirdparty,ora licensefromTIunderthepatentsorotherintellectualpropertyofTI. ReproductionofsignificantportionsofTIinformationinTIdatabooks ordatasheetsispermissibleonlyifreproductioniswithoutalteration and isaccompaniedby allassociatedwarranties,conditions,limitations,and notices.TIisnotresponsibleorliableforsuch altered documentation.Informationofthirdpartiesmay be subjecttoadditionalrestrictions. ResaleofTIcomponents orserviceswithstatementsdifferentfromorbeyond theparametersstatedby TIforthatcomponent orservice voidsallexpressand any impliedwarrantiesfortheassociatedTIcomponent orserviceand isan unfairand deceptivebusinesspractice. TIisnotresponsibleorliableforany such statements. Buyeracknowledgesand agreesthatitissolelyresponsibleforcompliancewithalllegal,regulatoryand safety-relatedrequirements concerningitsproducts,and any use ofTIcomponents initsapplications,notwithstandingany applications-relatedinformationorsupport thatmay be providedby TI.Buyerrepresentsand agreesthatithas allthenecessaryexpertisetocreateand implementsafeguardswhich anticipatedangerousconsequencesoffailures,monitorfailuresand theirconsequences,lessenthelikelihoodoffailuresthatmightcause harm and takeappropriateremedialactions.BuyerwillfullyindemnifyTIand itsrepresentativesagainstany damages arisingoutoftheuse ofany TIcomponents insafety-criticalapplications. Insome cases,TIcomponents may be promotedspecificallytofacilitatesafety-relatedapplications.Withsuch components,TI’s goalisto helpenablecustomerstodesignand createtheirown end-productsolutionsthatmeet applicablefunctionalsafetystandardsand requirements.Nonetheless,such components aresubjecttotheseterms. No TIcomponents areauthorizedforuse inFDA ClassIII(orsimilarlife-criticalmedicalequipment)unlessauthorizedofficersoftheparties have executeda specialagreementspecificallygoverningsuch use. OnlythoseTIcomponents whichTIhas specificallydesignatedas militarygradeor“enhanced plastic”aredesignedand intendedforuse in military/aerospaceapplicationsorenvironments.Buyeracknowledgesand agreesthatany militaryoraerospaceuse ofTIcomponents whichhave not been so designatedissolelyattheBuyer's risk,and thatBuyerissolelyresponsibleforcompliancewithalllegaland regulatoryrequirementsinconnectionwithsuch use. TIhas specificallydesignatedcertaincomponents whichmeet ISO/TS16949 requirements,mainlyforautomotiveuse.Components which have notbeen so designatedareneitherdesignednorintendedforautomotiveuse;and TIwillnotbe responsibleforany failureofsuch components tomeet such requirements. Products Applications Audio www.ti.com/audio Automotiveand Transportationwww.ti.com/automotive Amplifiers amplifier.ti.com Communicationsand Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP ® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energyand Lighting www.ti.com/energy Clocksand Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space,Avionicsand Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Videoand Imaging www.ti.com/video RFID www.ti-rfid.com OMAP MobileProcessors www.ti.com/omap TIE2E Community e2e.ti.com WirelessConnectivity www.ti.com/wirelessconnectivity MailingAddress:Texas Instruments,PostOfficeBox 655303,Dallas,Texas 75265 Copyright© 2012,Texas InstrumentsIncorporated