DAC2932 TI | Alldatasheet
Document overview
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Technical content
SBAS279D − AUGUST 2003 − REVISED JULY 2005 /C0068/C0117/C0097/C0108/C0044 /C0049/C0050/C0262/C0066/C0105/C0116/C0044 /C0052/C0048/C0077/C0083/C0080/C0083 /C0068/C0105/C0103/C0105/C0116/C0097/C0108/C0262/C0116/C0111/C0262/C0065/C0110/C0097/C0108/C0111/C0103/C0032/C0067/C0111/C0110/C0118/C0101/C0114/C0116/C0101/C0114 /C0068/C0065/C0067/C0050/C0057/C0051/C0050
FEATURES
/C0068Dual, 12-Bit, 40MSPS Current Output DAC /C0068Four 12-Bit Voltage Output DACs—for Transmit Control /C0068Single +3V Operation /C0068Very Low Power: 29mW /C0068High SFDR: 75dB at fOUT = 5MHz /C0068Low-Current Standby or Full Power-Down Modes /C0068Internal Reference /C0068Optional External Reference /C0068Adjustable Full-Scale Range: 0.5mA to 2mA
APPLICATIONS
/C0068Transmit Channels − I and Q − PC Card Modems: GPRS, CDMA − Wireless Network Cards (NICs) /C0068Signal Synthesis (DDS) /C0068Portable Medical Instumentation /C0068Arbitrary Waveform Generation (AWG)
DESCRIPTION
The DAC2932 is a dual 12-bit, current-output digital-to-analog converter (DAC) designed to combine the features of high dynamic range and very low power consumption. The DAC2932 converter supports update rates of up to 40MSPS. In addition, the DAC2932 features four 12-bit voltage output DACs, which can be used to perform system control functions. The advanced segmentation architecture of the DAC2932 is optimized to provide a high spurious-free dynamic range (SFDR). The DAC2932 has a high impedance (> 200kΩ) differential current output with a nominal range of 2mA and a compliance voltage of up to 0.8V. The differential outputs allow for either a differential or single-ended analog signal interface. The close matching of the current outputs ensures superior dynamic performance in the differential configuration, which can be implemented with a transformer. Using a small geometry CMOS process, the monolithic DAC2932 is designed to operate within a single-supply range of 2.7V to 3.3V. Low power consumption makes it ideal for portable and battery-operated systems. Further optimization by lowering the output current can be realized with the adjustable full-scale option. The full-scale output current can be adjusted over a span of 0.5mA to 2mA. For noncontinuous operation of the DAC2932, a full power-down mode can reduce the power dissipation to as little as 25μW. The DAC2932 is designed to operate with a single parallel data port. While it alternates the loading of the input data into separate input latches for both current output DACs (I-DACs), the updating of the analog output signal occurs simultaneously. The DAC2932 integrates a temperature compensated 1.22V bandgap reference. The DAC2932 also allows for additional flexibility of using an external ref- erence. The DAC2932 is available in a TQFP-48 package. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 www.ti.com Copyright © 2003−2005, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
/C0068/C0065/C0067/C0050/C0057/C0051/C0050 SBAS279D − AUGUST 2003 − REVISED JULY 2005 www.ti.com
ORDERING INFORMATION
PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY DAC2932 TQFP 48 PFB 40°C to 85 °C DAC2932 DAC2932PFBT Tape and Reel, 250 DAC2932 TQFP-48 PFB −40°C to +85°C DAC2932 DAC2932PFBR Tape and Reel, 2000 (1) For the most current specification and package information, refer to our web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted DAC2932 UNIT +VA to AGND −0.3 to +4 V +VD to DGND −0.3 to +4 V AGND to DGND −0.2 to +0.2 V +VA to +VD −0.7 to +0.7 V CLK, PD, STBY, CS to DGND −0.3 to VD + 0.3 V D0−D1 1 to DGND −0.3 to VD + 0.3 V IOUT, IOUT to AGND −0.5 to VA + 0.3 V REFV to AGNDV −0.3 to VAV + 0.3 V GSET , REFIN, FSA to AGND −0.3 to VA + 0.3 V VOUTx to AGNDV −0.3 to VAV + 0.3 V DIN to DGNDV −0.3 to VDV + 0.3 V Junction temperature +150 °C Case temperature +100 °C Storage temperature range −40 to +150 °C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FUNCTIONAL BLOCK DIAGRAM STBY CS DIN SCLK SYNC PD CLK Parallel Data Input, 12 −Bit Data, Interleaved DAC2932 REFIN +VD+VAGSET FSA1 FSA2 AGND DGND IOUT1 IOUT1 IOUT2 IOUT2 VOUT1 VOUT2 VOUT3 VOUT4 +1.22V Reference Latch Serial−to−Parallel Shift Register Input Latch and De−Multiplexer Reference Control Amp 12−Bit 40MSPS I−DAC1 DAC Latch 1 12−Bit 40MSPS I−DAC2 12−Bit String−DAC1 Latch 12−Bit String−DAC2 Latch 12−Bit String−DAC3 Latch 12−Bit String−DAC4 DAC Latch 2 Data2 CLK2 Clock I−DAC Section A0 A A A A Dx12 REFV +VDV +VAV AGNDVDGNDVPDV V−DAC Section Data1 CLK1 [D11:D0]
/C0068/C0065/C0067/C0050/C0057/C0051/C0050 SBAS279D − AUGUST 2003 − REVISED JULY 2005 www.ti.com ELECTRICAL CHARACTERISTICS: I-DAC At TA = TMIN to TMAX (typical values are at TA = 25°C), +VA = +3V, +VD = +3V, Update Rate = 40MSPS, IOUTFS = 2mA, RL = 250Ω, CL ≤ 10pF, GSET = H, and internal reference, unless otherwise noted. DAC2932 PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Resolution 12 Bits Output update rate (fCLOCK) 40 MSPS Specified temperature range, operating Ambient, TA −40 +85 °C Static Accuracy(1)(2) Differential nonlinearity (DNL) −3.5 ±0.5 +3.5 LSB Integral nonlinearity (INL) −8 ±1.5 +8 LSB Dynamic Performance(3) Spurious-free dynamic range (SFDR) To Nyquist, 0dBFS fOUT = 0.2MHz, fCLOCK = 20MSPS 68 dBc fOUT = 0.55MHz, fCLOCK = 40MSPS 71 dBc fOUT = 1MHz, fCLOCK = 25MSPS(4) 58 70 dBc fOUT = 2.2MHz, fCLOCK = 40MSPS 72 dBc fOUT = 5MHz, fCLOCK = 40MSPS 75 dBc fOUT = 10MHz, fCLOCK = 40MSPS 69 dBc fOUT = 20MHz, fCLOCK = 40MSPS 57 dBc Spurious-free dynamic range within a window fOUT = 2.2MHz, fCLOCK = 40MSPS 1MHz span 76 dBc fOUT = 10MHz, fCLOCK = 40MSPS 2MHz span 74 dBc Total harmonic distortion (THD) fOUT = 0.55MHz, fCLOCK = 40MSPS −70 dBc fOUT = 1MHz, fCLOCK = 25MSPS(4) −58 −69 dBc fOUT = 2.2MHz, fCLOCK = 40MSPS −70 dBc Signal-to-noise and distortion (SINAD) fOUT = 1MHz, fCLOCK = 25MSPS(4) 52 61 dBc Output settling time(1) to 0.1% 20 ns Output rise time(1) 10% to 90% 7.7 ns Output fall time(1) 10% to 90% 7.4 ns DC Accuracy Full-scale output range(5)(6) (FSR) All bits high, IOUT1, IOUT2 0.5 2 mA Output compliance range(7), VCO −0.5 +0.5 +0.8 V Gain error (Full-Scale) −2 ±0.5 +2 %FSR Gain error drift 70 ppmFSR/°C Gain matching −2.5 +0.6 +2.5 %FSR Offset error ±0.001 %FSR Power-supply rejection, +VA +3V, ±10%, at 25°C −0.9 +0.5 +0.9 %FSR/V Power-supply rejection, +VD +3V, ±10%, at 25°C −0.12 +0.03 +0.12 %FSR/V Output resistance 200 kΩ Output capacitance IOUT, IOUT to Ground 5 pF (1) At output IOUT1, IOUT2, while driving a 250Ω load, transition from 000h to FFFh. (2) Measured at fCLOCK = 25MSPS and fOUT = 1.0MHz. (3) Differential, transformer (n = 4:1) coupled output, RL = 400Ω. (4) Differential outputs with a 250Ω load. (5) Nominal full−scale output current is IOUTFS /C004332 /C0032IREF /C004332 /C0032 VREF RSET ; with VREF /C00431.22V (typ) and RSET /C004319.6k/C0087(1%) (6) Ensured by design and characterization; not production tested. (7) Gain error to remain ≤10% FSR over the full compliance range. (8) Combined power dissipation of I-DAC and V-DAC.
/C0068/C0065/C0067/C0050/C0057/C0051/C0050 SBAS279D − AUGUST 2003 − REVISED JULY 2005 www.ti.com ELECTRICAL CHARACTERISTICS: I-DAC (continued) At TA = TMIN to TMAX (typical values are at TA = 25°C), +VA = +3V, +VD = +3V, Update Rate = 40MSPS, IOUTFS = 2mA, RL = 250Ω, CL ≤ 10pF, GSET = H, and internal reference, unless otherwise noted. DAC2932 PARAMETER UNITSMAXTYPMINTEST CONDITIONS Reference Voltage, VREF +1.14 +1.22 +1.26 V Tolerance ±30 mV Voltage drift −40 ppm/°C Output current 10 μA Input resistance 1 MΩ Input compliance range External VREF +1.22 V Small-signal bandwidth 0.1 MHz Digital Inputs(6) Logic coding Straight binary Logic high voltage, VIH +2 +3 V Logic low voltage, VIL 0 +0.8 V Logic high current ±1 μA Logic low current ±1 μA Input capacitance 5 pF Power Supply Analog supply voltage, +VA, +VAV 2.7 3 3.3 V Digital supply voltage, +VD, +VDV 2.7 3 3.3 V Analog supply current, IVA fCLOCK = 25MSPS, digital inputs at 0 4.7 mA IVA fCLOCK = 40MSPS, fOUT = 2.2MHz 5.4 mA IVA Standby mode 0.4 mA Digital supply current, IVD fCLOCK = 25MSPS, digital inputs at 0 2 mA lVD fCLOCK = 40MSPS, fOUT = 2.2MHz 4.3 mA IVD Standby mode, clock off 0.02 mA IVD Standby mode, CS = 0, fCLOCK = 25MSPS 1.3 mA Power dissipation, PD(8) fCLOCK = 25MSPS, digital inputs at 0 20 25 mW PD fCLOCK = 40MSPS, fOUT = 2.2MHz 29 mW PD Standby mode, fCLOCK = 25MSPS 5.5 7 mW PD Power-down mode, clock off, digital inputs at 0 25 μW Thermal resistance TQFP-48 θJA 97.5 °C/WQ θJC 20 °C/W (1) At output IOUT1, IOUT2, while driving a 250Ω load, transition from 000h to FFFh. (2) Measured at fCLOCK = 25MSPS and fOUT = 1.0MHz. (3) Differential, transformer (n = 4:1) coupled output, RL = 400Ω. (4) Differential outputs with a 250Ω load. (5) Nominal full−scale output current is IOUTFS /C004332 /C0032IREF /C004332 /C0032 VREF RSET ; with VREF /C00431.22V (typ) and RSET /C004319.6k/C0087(1%) (6) Ensured by design and characterization; not production tested. (7) Gain error to remain ≤10% FSR over the full compliance range. (8) Combined power dissipation of I-DAC and V-DAC.
/C0068/C0065/C0067/C0050/C0057/C0051/C0050 SBAS279D − AUGUST 2003 − REVISED JULY 2005 www.ti.com ELECTRICAL CHARACTERISTICS: V-DAC At TA = TMIN to TMAX (typical values are at TA = 25°C), +VAV = +3V, +VDV = +3V, RL = 2kΩ to GND, and CL = 40pF, unless otherwise noted. DAC2932 PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Static Performance(1) Resolution 12 Bits Relative accuracy At 25°C −16 ±8 +16 LSB Differential nonlinearity, DNL Tested; monotonic by design −1 ±0.2 +1 LSB Zero code error(2) All 0s loaded to DAC register 0.2 +0.8 %FSR Full-scale error(2) All 1s loaded to DAC register −10 −3 +2 %FSR Zero code error drift 5 μV/°C Full-scale error drift −15 ppmFSR/°C Output Characteristics(3) Reference voltage setting, REFV 0 +VAV V Output voltage settling time 1/4 scale to 3/4 scale change (400h to C00h) 3 μs CL = 470pF 5 μs Slew rate 1 V/μs Capacitive load stability RL = 2kΩ 470 pF Code change glitch impulse 1LSB change around major carry 11 nV-s Digital feedthrough 0.5 nV-s DC output impedance 4 Ω Short-circuit current 20 mA Power-up time Coming out of power-down mode 8 μs Logic Inputs(3) Input current ±1 μA Input low voltage, VIL 0 0.8 V Input high voltage, VIH 2 3 V Input capacitance 5 pF (1) Linearity calculated using a reduced code range of 48 to 3976. (2) Full-scale range (FSR) based on reference REFV = +VAV = +3.0V. (3) Ensured by design and characterization; not production tested.
Figure 1. Timing Diagram of I-DAC (1) Based on design simulation and characterization; not production tested. (2) All input signals are specified with tr = tf ≤ 2ns (10% to 90% of +VDV) and timed from a voltage level of (VIL + VIH)/2. (3) Output delay time measured from 50% of rising clock edge to 50% point of full-scale transition.
Figure 2. Serial Write Operation of V-DAC (1) All input signals are specified with tr = tf ≤ 2ns (10% to 90% of +VDV) and timed from a voltage level of (VIL + VIH)/2. (2) Based on design simulation and characterization; not production tested. (3) Maximum SCLK frequency is 20MHz at +VAV = +VDV = +2.7V to 3.3V. is set high, the selected V-DACs are updated with the same data word simultaneously.
/C0068/C0065/C0067/C0050/C0057/C0051/C0050 SBAS279D − AUGUST 2003 − REVISED JULY 2005 www.ti.com PIN ASSIGNMENTS 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 DAC2932 (V−DAC Section) NC +VAV IOUT2 IOUT2 AGND A IOUT1 IOUT1 REFIN DGNDV SYNC SCLK DIN PDV REFV +VDV AGNDV VOUT4 VOUT3 VOUT2 VOUT1 DGND +VD CLK PD STBY CS GSET DGND AGND FSA2 FSA1 +VA AGND AGND AGND D11 (MSB) D10 D0 (LSB) Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION D11:D0 1:12 I Parallel data input port for the dual I-DACs; MSB = D11, LSB = D0; interleaved operation. DGND 13 Digital ground of I-DAC +VD 14 Digital supply of I-DAC; 2.7V to 3.3V CLK 15 I Clock input of I-DAC PD 16 I Power-down pin; active high; a logic high initiates power-down mode. STBY 17 I Standby pin of I-DAC; active low; a logic low initiates Standby mode with PD = Low. A logic high configures the I-DAC for normal operation; pin will resume a high state if left open. CS 18 I Chip select; active low; enables the parallel data port of the I−DACs; if used as chip select in applications using multiple DAC2932 devices, the parallel port data must be scrambled for proper functionality. Pin will resume a low state if left open. GSET 19 I Gain-setting mode. A logic high enables the use of two separate full-scale adjust resistors on pins FSA1 and FSA2. A logic low allows the use of a common full-scale adjust resistor connected to FSA1. The function of the FSA2 pin is disabled, and any remaining resistor has no effect. The value for the RSET resistor remains the same for a given full-scale range, regardless of the selected GSET mode. Pin will resume a low state if left open. DGND 20 Digital ground of I-DAC AGND 21 Analog ground of I-DAC AGND 22 Analog ground of I-DAC FSA2 23 I Full-scale adjust of I-DAC2; connect external gain setting resistor RSET2 = 19.6kΩ. FSA1 24 I Full-scale adjust of I-DAC1; connect external gain setting resistor RSET1 = 19.6kΩ.
/C0068/C0065/C0067/C0050/C0057/C0051/C0050 SBAS279D − AUGUST 2003 − REVISED JULY 2005 www.ti.com Terminal Functions (continued) TERMINAL NAME DESCRIPTIONI/ONO. REFIN 25 I External reference voltage input; internal reference voltage output; bypass with 0.1μF to AGND for internal reference operation. IOUT1 26 O Complementary current ouput of I-DAC1 IOUT1 27 O Current output of I-DAC1 AGND 28 Analog ground of I-DAC +VA 29 Analog supply of I-DAC; 2.7V to 3.3V +VA 30 Analog supply of I-DAC; 2.7V to 3.3V AGND 31 Analog ground of I-DAC AGND 32 Analog ground of I-DAC IOUT2 33 O Current output of I-DAC2 IOUT2 34 O Complementary current ouput of I-DAC2 +VAV 35 Analog supply of V-DAC; 2.7V to 3.3V NC 36 No internal connection VOUT1 37 O Voltage output of V-DAC1 VOUT2 38 O Voltage output of V-DAC2 VOUT3 39 O Voltage output of V-DAC3 VOUT4 40 O Voltage output of V-DAC4 AGNDV 41 Analog ground of V-DAC REFV 42 I Reference voltage input for V-DACs; typically connected to supply (+VAV) +VDV 43 Digital supply of V-DAC; 2.7V to 3.3V PDV 44 I Power-down of V-DACs; active high; a logic high initiates the power-down mode DIN 45 I Serial digital input for V−DAC; see timing and application sections for details SCLK 46 I Clock input of V-DAC SYNC 47 I Frame synchronization signal for the serial data at DIN. Refer to timing section for details. DGNDV 48 Digital ground of V-DAC.
external setting resistor, RSET. IOUT and I/C0079/C0085/C0084 should be limited to +0.5V or less. of the DAC2932. Table 1 lists all pins and possible modes. V-DAC in a normal operating mode (fully functional). and will consume some power if the clock remains applied. being clocked, even with the clock signal applied. Table 1. Power-Down Modes
1 X X X I-DAC disabled Full power-down; STBY and CS have no effect High-Z
0 X X 0 V-DAC enabled V-DAC normal operation
Figure 29. Equivalent Analog Output exceed the compliance range. particularly the case with high output frequencies. OUT1 and IOUT2, as shown in Table 2. Table 2. Input Coding vs Analog Output Current of the converter yields the best dynamic performance. I-to-V or op-amp configuration may be considered. performance over a wide range of frequencies. isolated by the transformer.
the 16th falling edge of the clock (SCLK). occurs, as shown in Figure 40. close as physically possible to those device leads. multilayer PCB with separate power and ground planes. routing of the different supply currents and signal traces. prevent noise coupling onto the analog signal path. Figure 40. SYNC Interrupt Facility
/C0068/C0065/C0067/C0050/C0057/C0051/C0050 SBAS279D − AUGUST 2003 − REVISED JULY 2005 www.ti.com
Revision History
DATE REV PAGE SECTION DESCRIPTION
6 Timing Requirements Changed tS1, tS2, tH1, tH2 min values, CS hold time (pulse width) min value,
and CS to clock rising or falling edge setup time typ value.
8 Pin Assignments Changed pin names for pins 1 − 12
8 Terminal Functions Changed CS description. JUL 05 D 15 Power−Down Modes In Table 1, changed column 1 row 7 from X to 0.
16 Chip Select Operation Added Chip Select Operation section with figure
17 Differential With
Transformer Changed ratio and load in first paragraph. Changed ratio and load in Figure 30. AUG 03 * — — Original version NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DAC2932PFBR Active Production TQFP (PFB) | 48 2000 | LARGE T&R Yes NIPDAU Level-2A-260C-4 WKS -40 to 85 DAC2932PFB DAC2932PFBR.B Active Production TQFP (PFB) | 48 2000 | LARGE T&R Yes NIPDAU Level-2A-260C-4 WKS -40 to 85 DAC2932PFB DAC2932PFBRG4.B Active Production TQFP (PFB) | 48 2000 | LARGE T&R Yes NIPDAU Level-2A-260C-4 WKS -40 to 85 DAC2932PFB DAC2932PFBT Active Production TQFP (PFB) | 48 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC2932PFB DAC2932PFBT.B Active Production TQFP (PFB) | 48 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC2932PFB (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) DAC2932PFBR PFB TQFP 48 2000 10 x 25 150 315 135.9 7620 12.2 11.1 11.25 DAC2932PFBT PFB TQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25 Pack Materials-Page 1
www.ti.com PACKAGE OUTLINE C 48X 0.27 0.1744X 0.5 PIN 1 ID (0.13) TYP
0.05 MIN0 -7
4X 5.5 9.2
8.8 TYP
0.75 0.45 B7.2 6.8 NOTE 3 A 7.2 6.8 NOTE 3 0.25 GAGE PLANE
1.2 MAX
(1) PLASTIC QUAD FLATPACK TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MS-026. 13 24 3748
0.08 C A B
0.08 A 16 DETAIL A TYPICAL SCALE 1.900
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
(8.5) (8.5) 44X (0.5) 48X (1.35) 48X (0.25) (R0.05) TYP TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM SYMM 48 37 13 24 SEE DETAILS METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN 44X (0.5) 48X (1.35) 48X (0.25) (R0.05) TYP (8.5) (8.5) TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE SCALE:8X SYMM SYMM 48 37 13 24
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