DAC2904Y/1K

DAC2904 TI | Alldatasheet

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Dual,14-Bit,125MSPS DIGITAL-TO-ANALOGCONVERTER Check forSamples: DAC2904 1FEATURES APPLICATIONS

• COMMUNICATIONS:2• 125MSPS UPDATE RATE – Base Stations,WLL, WLAN• SINGLE SUPPLY: +3.3V or +5V – Baseband I/QModulation• HIGH SFDR: 78dB atfOUT = 10MHz
• MEDICAL/TEST INSTRUMENTATION• LOW GLITCH: 2pV-s
• ARBITRARY WAVEFORM GENERATORS• LOW POWER: 310mW (ARB)
• INTERNAL REFERENCE • DIRECT DIGITAL SYNTHESIS (DDS)
• POWER-DOWN MODE: 23mW space space The DAC2904 combines high dynamic performance with a high update rateto createa cost-effectiveDESCRIPTION solutionfor a wide varietyof waveform-synthesisThe DAC2904 isa monolithic,14-bit,dual-channel, applications:high-speedDigital-to-AnalogConverter(DAC),and is • Pincompatibilitybetween familymembersoptimizedtoprovidehighdynamic performancewhile provides10-bit(DAC2900),12-bit(DAC2902),dissipatingonly310mW. and 14-bit(DAC2904) resolution. Operatingwithhighupdateratesofup to125MSPS, • PincompatibletotheAD9767 dualDAC.
• Alldigitalinputsare+3.3V and +5V logicEach DAC has a high-impedancedifferential-current compatible.The DAC2904 has an internaloutput, suitablefor single-endedor differential referencecircuit,and allowsuse ina multiplyinganalog-outputconfigurations. configuration. The DAC2904 is availablein a TQFP-48 package, and is specifiedover the extended industrial temperaturerangeof–40°C to+85°C. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2001–2009,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. PACKAGE/ORDERING INFORMATION (1) SPECIFIED TRANSPORT PACKAGE- PACKAGE TEMPERATURE PACKAGE ORDERING MEDIA, PRODUCT LEAD DESIGNATOR RANGE MARKING NUMBER (2) QUANTITY DAC2904Y/250 Tape and Reel,250 DAC2904Y TQFP-48 PFB –40°C to+85°C DAC2904Y DAC2904Y/1K Tape and Reel,1k DAC2904IPFB Tray,250 (1) Forthemost currentpackage and orderinginformationsee thePackage OptionAddendum attheend ofthisdocument,orsee theTI websiteatwww.ti.com. (2) Models witha slash(/)areavailableonlyintapeand reelmedia inthequantitiesindicated(forexample,/1K indicates1000 devicesper reel).Ordering1000 piecesofDAC2904Y/1K willgeta single1000-piecetapeand reel. ABSOLUTE MAXIMUM RATINGS (1) DAC2904 UNIT +VA toAGND –0.3to+6 V +VD toDGND –0.3to+6 V AGND toDGND –0.3to+0.3 V +VA to+VD –6 to+6 V CLK, PD toDGND –0.3toVD +0.3 V D0 –D9 toDGND –0.3toVD +0.3 V IOUT ,IOUT toAGND –1 toVA + 0.3 V BW, BYP toAGND –0.3toVA + 0.3 V REF IN,FSA toAGND –0.3toVA + 0.3 V INT/EXT toAGND –0.3toVA + 0.3 V JunctionTemperature +150 °C Case Temperature +100 °C StorageTemperature +125 °C (1) Stressesabove thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.Exposuretoabsolute maximum conditionsforextendedperiodsmay affectdevicereliability.

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ELECTRICAL CHARACTERISTICS

TMIN toTMAX ,+VA = +5V, +VD = +3.3V,differentialtransformercoupledoutput,and 50Ω doubly-terminated,unlessotherwise noted.IndependentGain Mode. DAC2904 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION Resolution 14 Bits OutputUpdate Rate (fCLOCK ) 125 MSPS STATIC ACCURACY (1) DifferentialNonlinearity(DNL) TA = +25°C ±4.0 LSB IntegralNonlinearity(INL) TA = +25°C ±5.0 LSB DYNAMIC PERFORMANCE Spurious-FreeDynamic Range (SFDR) To Nyquist 0dBFS Output 71 82 dBc fOUT = 1MHz, fCLOCK = 50MSPS –6dBFS Output 77 dBc –12dBFS Output 72 dBc fOUT = 1MHz, fCLOCK = 26MSPS 82 dBc fOUT = 2.18MHz,fCLOCK = 52MSPS 81 dBc fOUT = 5.24MHz,fCLOCK = 52MSPS 81 dBc fOUT = 10.4MHz,fCLOCK = 78MSPS 78 dBc fOUT = 15.7MHz,fCLOCK = 78MSPS 72 dBc fOUT = 5.04MHz,fCLOCK = 100MSPS 80 dBc fOUT = 20.2MHz,fCLOCK = 100MSPS 69 dBc fOUT = 20.1MHz,fCLOCK = 125MSPS 69 dBc fOUT = 40.2MHz,fCLOCK = 125MSPS 64 dBc Spurious-FreeDynamic Range withina Window fOUT = 1MHz, fCLOCK = 50MSPS 2MHz span 80 90 dBc fOUT = 5.24MHz,fCLOCK = 52MSPS 10MHz span 88 dBc fOUT = 5.26MHz,fCLOCK = 78MSPS 10MHz span 88 dBc fOUT = 5.04MHz,fCLOCK = 125MSPS 10MHz span 88 dBc TotalHarmonicDistortion(THD) dBc fOUT = 1MHz, fCLOCK = 50MSPS –79 –70 dBc fOUT = 5.24MHz,fCLOCK = 52MSPS –77 dBc fOUT = 5.26MHz,fCLOCK = 78MSPS –76 dBc fOUT = 5.04MHz,fCLOCK = 125MSPS –75 dBc MultitonePower Ratio Eighttonewith110kHz spacing fOUT = 2.0MHz to2.99MHz,fCLOCK = 0dBFS output 80 dBc65MSPS Signal-to-NoiseRatio(SNR) fOUT = 5.02MHz,fCLOCK = 50MHz 0dBFS output 68 dBc Signal-to-Noiseand Distortion(SINAD) fOUT = 5.02MHz,fCLOCK = 50MHz 0dBFS output 67 dBc ChannelIsolation fOUT = 1MHz, fCLOCK = 52MSPS 85 dBc fOUT = 20MHz, fCLOCK = 125MSPS 77 dBc (1) AtoutputlOUT ,whiledrivinga virtualground. Copyright© 2001–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):DAC2904

ELECTRICAL CHARACTERISTICS (continued) TMIN toTMAX ,+VA = +5V, +VD = +3.3V,differentialtransformercoupledoutput,and 50Ω doubly-terminated,unlessotherwise noted.IndependentGain Mode. DAC2904 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE, continued OutputSettlingTime(2) To 0.1% 30 ns OutputRiseTime(2) 10% to90% 2 ns OutputFallTime(2) 10% to90% 2 ns GlitchImpulse 2 pV-s DC ACCURACY Full-ScaleOutputRange (3)(FSR) AllBitsHIGH, IOUT 2 20 mA OutputComplianceRange Withinternalreference –1.0 +1.25 V Gain Error— Full-Scale Withinternalreference –5 ±1 +5 %FSR Gain Error Withinternalreference –2.5 ±1 +2.5 %FSR Gain Matching Withinternalreference –2.0 0.5 +2.0 %FSR ppmFSR/ °Gain Drift Withinternalreference ±50 C OffsetError Withinternalreference –0.02 +0.02 %FSR ppmFSR/ °OffsetDrift Withinternalreference ±0.2 C Power-SupplyRejection,+VA +5V, ±10% –0.2 +0.2 %FSR/V Power-SupplyRejection,+VD +3.3V,±10% –0.025 +0.025 %FSR/V OutputNoise IOUT = 20mA, R LOAD = 50Ω 50 pA/√Hz IOUT = 2mA 30 pA/√Hz OutputResistance 200 kΩ OutputCapacitance IOUT ,IOUT toground 6 pF REFERENCE/CONTROL AMP ReferenceVoltage +1.18 +1.25 +1.31 V ppmFSR/ °ReferenceVoltageDrift ±50 C ReferenceOutputCurrent 100 nA ReferenceMultiplyingBandwidth 0.3 MHz InputComplianceRange +0.5 +1.25 V DIGITAL INPUTS LogicCoding StraightBinary LogicHighVoltage,VIH +VD = 5V 3.5 5 V LogicLow Voltage,VIL +VD = 5V 0 1.2 V LogicHighVoltage,VIH +VD = 3.3V 2 3 V LogicLow Voltage,VIL +VD = 3.3V 0 0.8 V LogicHighCurrent,IIH LogicLow Current +VD = 3.3V ±10 μA InputCapacitance 5 pF (2) Measured single-endedinto50Ω load. (3) Nominalfull-scaleoutputcurrentis32 ×IREF ;see Applicationxxsectionfordetails. (4) Typically45μA forthePD pin,whichhas an internalpull-downresistor.

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ELECTRICAL CHARACTERISTICS (continued) TMIN toTMAX ,+VA = +5V, +VD = +3.3V,differentialtransformercoupledoutput,and 50Ω doubly-terminated,unlessotherwise noted.IndependentGain Mode. DAC2904 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY SupplyVoltages +VA +3.0 +5 +5.5 V SupplyCurrent IVA (5) +VA = +5V, lOUT = 20mA 58 65 mA IVA (5) Power-Down mode 1.7 3 mA IVD (5) 4.2 7 mA IVD (6) 17 19.5 mA Power Dissipation(5) +VA = +5V, +VD = 3.3V,lOUT = 20mA 310 350 mW Power Dissipation(6) +VA = +5V, +VD = 3.3V,lOUT = 20mA 348 390 mW Power Dissipation(5) +VA = +5V, +VD = 3.3V,lOUT = 2mA 130 mW Power Dissipation Power-Down mode 23 38 mW ThermalResistance,TQFP-48 θJA 60 °C/W θJC 13 °C/W TEMPERATURE RANGE Specified Ambient –40 +85 °C Operating Ambient –40 +85 °C (5) Measured atfCLOCK = 25MSPS and fOUT = 1MHz. (6) Measured atfCLOCK = 100MSPS and fOUT = 40MHz. Copyright© 2001–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):DAC2904

48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 DAC2904 D0-2 D1-2 D2_2 D3_2 D4_2 D5_2 D6_2 D7_2 D8_2 D9_2 D10_2 D11_2 NC D1-1D0-1 DGND DGNDWRT1CLK1CLK2WRT2 D13_1□(MSB) D12_1 D11_1 D10_1 D9_1 D8_1 D7_1 D6_1 D5_1 D4_1 D3_1 D2_1 l 1OUT FSA2REF IN FSA1 GSET PDl 2OUTIOUT IOUT A AGND D D D13_2□(MSB) D12_2 DAC2904 DEVICE INFORMATION PFB PACKAGE TQFP-48 (TOP VIEW) TERMINAL FUNCTIONS TERMINAL NAME NO. DESCRIPTION D[13:0]_1 1–14 Data portDAC1, databit13 (MSB) tobit0 (LSB) DGND 15,21 Digitalground +VD 16,22 Digitalsupply,+3.0V to+5.5V WRT1 17 DAC1 inputlatcheswritesignal CLK1 18 ClockinputDAC1 CLK2 19 ClockinputDAC2 WRT2 20 DAC2 inputlatcheswritesignal D[13:0]_2 23–36 Data portDAC2, databit13 (MSB) tobit0 (LSB). PD 37 Power-down functioncontrolinput.H = DAC inpower-down mode; L = DAC innormaloperation(internalpull-downfordefaultL). AGND 38 Analogground IOUT 2 39 CurrentoutputDAC2. Full-scalewithallbitsofdataport2 high. IOUT 2 40 ComplementarycurrentoutputDAC2. Full-scalewithallbitsofdataport2 low. FSA2 41 Full-scaleadjust,DAC2. ConnectexternalR SET resistor. GSET 42 Gain-settingmode (H = one resistor,L = two resistors) REF IN 43 Internalreferencevoltageoutput;externalreferencevoltageinput.Bypass with0.1μF capacitortoAGND forinternalreferenceoperation. FSA1 44 Full-scaleadjust,DAC1. ConnectexternalR SET resistor. IOUT 1 45 ComplementarycurrentoutputDAC1. Full-scalewithallbitsofdataport1 low. IOUT 1 46 CurrentoutputDAC1. Full-scalewithallbitsofdataport1 high. +VA 47 Analogsupply,+3.0V to+5.5V NC 48 No connection

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IOUT(n) IOUT(n + 1)50% DATA□IN WRT1 WRT2 CLK1 CLK2 I 1OUT I 2OUT DAC2904 TIMING REQUIREMENTS PARAMETER MIN TYP MAX UNIT tS Inputsetuptime 2 ns tH Inputholdtime 1.5 ns tLPW ,tCPW Latch/Clockpulsewidth 3.5 4 ns tCW DelayrisingCLK edge torisingWRT edge 0 tPW – 2 ns tPD Propagationdelay 1 ns tSET Settlingtime(0.1%) 30 ns DIGITAL INPUTS AND TIMING The data inputportsof the DAC2904 accepta standardpositivecodingwithdata bitD13 being the most significantbit(MSB). The converteroutputssupporta clockrateofup to125MSPS. The bestperformancewill typicallybe achievedwitha symmetricdutycycleforwriteand clock;however,thedutycyclemay varyas long as thetimingspecificationsaremet.Also,theset-upand holdtimesmay be chosen withintheirspecifiedlimits. Alldigitalinputsof the DAC2904 are CMOS compatible.The logicthresholdsdepend on the applieddigital supplyvoltages,such thattheyare settoapproximatelyhalfthesupplyvoltage;Vth = +VD /2(±20% tolerance). The DAC2904 isdesignedtooperatewitha digitalsupply(+VD )of+3.0V to+5.5V. The two converterchannelswithinthe DAC2904 consistof two independent,14-bit,paralleldata ports.Each DAC channeliscontrolledby itsown setofwrite(WRT1, WRT2) and clock(CLK1,CLK2) inputs.Here,theWRT linescontrolthechannelinputlatchesand theCLK linescontroltheDAC latches.The dataisfirstloadedintothe inputlatchby a risingedge oftheWRT line.ThisdataispresentedtotheDAC latchon thefollowingfallingedge oftheWRT signal.On thenextrisingedge oftheCLK line,theDAC isupdatedwiththenew dataand theanalog outputsignalwillchange accordingly.The double latcharchitectureof the DAC2904 resultsin a defined sequence fortheWRT and CLK signals,expressedby parametertCW .A correcttimingisobservedwhen the risingedge ofCLK occursatthesame time,or before,therisingedge oftheWRT signal.Thisconditioncan simplybe met by connectingtheWRT and CLK linestogether.Note thatallspecificationswere measured with theWRT and CLK linesconnectedtogether. Copyright© 2001–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):DAC2904

DNL□(LBS) 0 2k 4k 6k 8k 10k 12k 14k 16k Code /c45 /c45 /c45 /c45 INL□(LBS) 0 2k 4k 6k 8k 10k 12k 14k 16k Code /c45 /c45 /c45 /c45 SFDR□(dBc) 42 6 8 10 120 0dBFS/c456dBFS /c4512dBFS f (MHz)OUT SFDR□(dBc) 105 15 20 250 0dBFS/c456dBFS /c4512dBFS f (MHz)OUT SFDR□(dBc) 105 15 20 25 30 350 0dBFS /c456dBFS /c4512dBFS f (MHz)OUT 105 15 20 25 30 35 40 450 /c456dBFS /c4512dBFS 0dBFSSFDR□(dBc) f (MHz)OUT DAC2904 TYPICAL CHARACTERISTICS AtTA = +25°C, +VD = +3.3V,+VA = +5V, differentialtransformercoupled,IOUT = 20mA, 50Ω doubleterminatedload,and SFDR up toNyquist,unlessotherwisenoted. TYPICAL DNL TYPICAL INL Figure1. Figure2. SFDR vs fOUT AT 26MSPS SFDR vs fOUT AT 52MSPS Figure3. Figure4. SFDR vs fOUT AT 78MSPS SFDR vs fOUT AT 100MSPS Figure5. Figure6.

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/c456dBFS /c4512dBFS 0dBFSSFDR□(dBc) f (MHz)OUT 0 5 10 15 20 25 20mA 5mA 10mA SFDR□(dBc) f (MHz)OUT 0dBFs T emperature□( C)/c176 Gain□Error□(%□FS) Offset□Error□(%□FS) 0/c45 20 20 40 60 80 85/c45 40 Offset□Error Gain□Error 0.8 0.6 0.4 0.2 0.2 0.4 0.6 0.8 /c45 /c45 /c45 /c45 0.004 0.003 0.002 0.001 0.001 0.002 0.003 0.004 /c45 /c45 /c45 /c45 T emperature□( C)/c176 SFDR□(dBc) 0/c45 20 20 40 60 80 100/c45 40 2MHz 40MHz 10MHz 20MHz 125MSPS 100MSPS 78MSPS 52MSPS 26MSPS I (mA)VD Ratio□(f /fOUT CLK ) 105 15 20 250 I (mA)VA I (mA)OUTFS DAC2904 TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, +VD = +3.3V,+VA = +5V, differentialtransformercoupled,IOUT = 20mA, 50Ω doubleterminatedload,and SFDR up toNyquist,unlessotherwisenoted. SFDR vs fOUT AT 125MHz SFDR vs IOUTFS AND fOUT AT 78MSPS Figure7. Figure8. SFDR AT 125MSPS vs TEMPERATURE GAIN AND OFFSET DRIFT Figure9. Figure10. IVD vs RATIO AT +VD = +3.3V IVA vs IOUTFS Figure11. Figure12. Copyright© 2001–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):DAC2904

Frequency□(MHz) 5.2 10.4 15.6 20.8 260 90/c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 Magnitude□(dBm) f =□52MSPS f =□5.23MHz Amplitude□=□0dBFS CLOCK OUT Frequency□(MHz) 10 20 30 40 500 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 Magnitude□(dBm) f =□100MSPS f =□20.2MHz Amplitude□=□0dBFS CLOCK OUT Frequency□(MHz) 7.8 15.6 23.4 31.2 390 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 Magnitude□(dBm) f =□78MSPS f =□9.44MHz Amplitude□=□0dBFS CLOCK OUT1 f 2□=□10.44MHzOUT Frequency□(MHz) 5 10 15 20 250 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 Magnitude□(dBm) f =□50MSPS f =□6.25MHz Amplitude□=□0dBFS CLOCK OUT1 f 2□=□6.75MHzOUT f 3□=□7.25MHz f 4□=□7.75MHz OUT OUT /c45 /c45 /c45 /c45 /c45 /c45 90/c45 /c45 /c45 /c45 /c45 100 110 120 130 Magnitude□(dBm) Center:□15.36MHz;□Span:□14MHz f =□61.44MSPS P = 13dBm CLOCK CHANNEL /c45 ACPR□= 69.2dB/c45 DAC2904 TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, +VD = +3.3V,+VA = +5V, differentialtransformercoupled,IOUT = 20mA, 50Ω doubleterminatedload,and SFDR up toNyquist,unlessotherwisenoted. SINGLE-TONE SFDR SINGLE-TONE SFDR Figure13. Figure14. DUAL-TONE SFDR FOUR-TONE SFDR Figure15. Figure16. WCDMA — ACPR Figure17.

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I =□I +□IOUTFS OUT OUT I =□IOUT OUTFS /c180Code 16,384 IOUT =□I (16,383 ) /c45OUTFS /c180 Code 16,384 I =□32 I =□32OUTFS REF /c180 /c180 V R REF SET V =□I ROUT OUT LOAD/c180 = IOUTVOUT /c180RLOAD V =□V = /c45OUTDIFF OUT /c180 /c180 I ROUTFS LOAD (2 Code 16,383) 16,384 /c45/c180VOUT DAC2904

APPLICATION INFORMATION

THEORY OF OPERATION DAC TRANSFER FUNCTION The architectureof the DAC2904 uses the current Each of the DACs in the DAC2904 has a set of steeringtechniquetoenablefastswitchingand a high complementarycurrentoutput,IOUT and I OUT . The update rate.The core elementwithinthe monolithic full-scaleoutputcurrent,IOUTFS , isthe summation of DAC isan arrayof segmented currentsourcesthat thetwo complementaryoutputcurrents: are designedto delivera full-scaleoutputcurrentof (1)up to 20mA, as shown in Figure18. An internal decoder addresses the differentialcurrentswitches The individualoutputcurrentsdepend on the DAC each timethe DAC isupdated and a corresponding code and can be expressedas: outputcurrentisformed by steeringallcurrentsto eitheroutputsumming node, IOUT or I OUT . The (2)complementary outputsdelivera differentialoutput signal,which improves the dynamic performance through reduction of even-order harmonics, (3) common-mode signals (noise),and double the where Code isthedecimalrepresentationoftheDACpeak-to-peakoutputsignalswing by a factorof two, data inputword.Additionally,IOUTFS isa functionofcompared tosingle-endedoperation. thereferencecurrentIREF ,whichisdeterminedby theThe segmented architectureresultsin a significant referencevoltageand the externalsettingresistor,reductionoftheglitchenergy,improvesthedynamic R SET .performance(SFDR), and DNL. The currentoutputs maintaina very high outputimpedance of greater than200kΩ. (4) The full-scaleoutputcurrentis determinedby the In most cases the complementaryoutputswilldrive ratiooftheinternalreferencevoltage(1.25V)and an resistiveloadsor a terminatedtransformer.A signal externalresistor,R SET .The resultingIREF isinternally voltagewilldevelopateach outputaccordingto: multipliedby a factorof 32 to produce an effective (5)DAC outputcurrentthatcan range from 2mA to (6)20mA, dependingon thevalueofR SET . The value of the load resistanceis limitedby theThe DAC2904 is splitintoa digitaland an analog outputcompliancespecificationof the DAC2904. Toportion,each of which is powered throughitsown maintainspecifiedlinearityperformance,the voltagesupplypin.The digitalsectionincludesedge-triggered forIOUT and I OUT shouldnot exceed the maximuminputlatchesand thedecoderlogic,whiletheanalog allowablecompliancerange.sectioncomprisesthe currentsource arraywithits associatedswitches,and thereferencecircuitry. The two single-endedoutput voltages can be combined tofindthetotaldifferentialoutputswing: (7) Copyright© 2001–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):DAC2904

Latch□1 WRT1 CLK1 CLK2 WRT2 Data□Input Port□2 D[13:0]_2 Data□Input Port□1 D[13:0]_1 l 1OUT Input Latch□1 Reference Control□Amplifier FSA2 REFIN FSA1 GSET PD DAC2904 l 2OUT +VA+VD+VD DAC Latch□2 Input Latch□2 AGNDDGNDDGND IOUT2 IOUT1 DAC1 Segmented□Switches Current□Sources DAC2 Segmented□Switches Current□Sources IOUT DAC2904 RL RL +VA IOUT DAC2904 Figure18. Block Diagram oftheDAC2904 given by the breakdown voltage of the CMOS process, and exceeding it willcompromise theANALOG OUTPUTS Best distortionperformanceistypicallyachievedwith the maximum full-scaleoutput signallimitedto approximately0.5VPP . This is the case fora 50Ω doublyterminatedloadand a 20mA full-scaleoutput current.A varietyof loads can be adapted to the output of the DAC2904 by selectinga suitable transformerwhilemaintainingoptimum voltagelevels atIOUT and IOUT .Furthermore,usingthedifferential outputconfigurationincombinationwitha transformer willbe instrumentalforachievingexcellentdistortion performance. Common-mode errors, such as even-orderharmonicsor noise,can be substantially reduced.Thisisparticularlythecase withhighoutput frequencies. For those applicationsrequiringthe optimum distortionand noiseperformance,itisrecommendedFigure19. EquivalentAnalog Output to selecta full-scaleoutput of 20mA. A lower full-scalerange down to2mA may be consideredfor applicationsthatrequirea low power consumption,The signalvoltageswingthatmay developatthetwo butcan toleratea slightlyreducedperformancelevel.outputs,IOUT and IOUT ,islimitedby a negativeand positivecompliance.The negativelimitof –1V is

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(Mini-Circuits) 1:1 DAC2904 OUTPUT CONFIGURATIONS DIFFERENTIAL WITH TRANSFORMER The currentoutputsof the DAC2904 allow for a Using an RF transformerprovidesa convenientway varietyofconfigurations,some ofwhichareillustrated of convertingthe differentialoutput signalintoa in Table 1. As mentioned previously,utilizingthe single-ended signal while achieving excellent converterdifferentialoutputs willyieldthe best dynamic performance (see Figure 20). The dynamic performance.Such a differentialoutput appropriatetransformershouldbe carefullyselected circuitmay consistof an RF transformeror a based on the output frequency spectrum and differentialamplifierconfiguration.The transformer impedance requirements.The differentialtransformer configurationis idealformost applicationswithac configurationhas thebenefitofsignificantlyreducing coupling,while op amps willbe suitablefor a common-mode signals,thus improvingthe dynamic dc-coupledconfiguration. performance over a wide range of frequencies. Furthermore,by selectinga suitableimpedance ratio Table1.InputCoding vs Analog Output Current (windingratio),the transformercan be used to provide optimum impedance matching whileINPUT CODE (D13 -D0) IOUT IOUT controllingthe compliancevoltageforthe converter11 1111 1111 1111 20mA 0mA outputs. The model shown, ADTT1-1 (by 10 0000 0000 0000 10mA 10mA Mini-Circuits),has a 1:1 ratioand may be used to 00 0000 0000 0000 0mA 20mA interfacetheDAC2904 toa 50Ω load.Thisresultsin a 25Ω loadforeach of the outputs,IOUT and IOUT . The single-endedconfigurationmay be considered The outputsignalsare ac-coupledand inherently forapplicationsrequiringa unipolaroutputvoltage. isolatedbecause ofitsmagneticcoupling. space only be used ifallcomponents are closeto each other,and iftheVSWR isnotimportant.A completespace power transferfrom the DAC outputto the loadcan space be realized,but the outputcompliancerange should be observed.Alternatively,ifthe centertap is notspace connected,thesignalswingwillbe centeredat(RL × IOUTFS /2).However, in this case, the two loadspace resistors,R L,must be used toenablethenecessary dc-currentflowforbothoutputs. Figure20. DifferentialOutput ConfigurationUsing an RF Transformer Copyright© 2001–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):DAC2904

26.1/c87 RL 28.7/c87 402/c87 200/c87 402/c87 200/c87 OPA690 COPT +5V VOUT /c45 5V IOUT DAC2904 /c45 V =□I ROUT OUT F1 /c183 RF1 RF2 CF1 CF2 CD1 CD2 IOUT 50/c87 50/c87 /c45 5V +5V IOUT IOUT/c45 VOUT = RF2/c183 OP A2690 OP A2690 DAC2904 DIFFERENTIAL CONFIGURATION USING AN slew-limitationsor intoan overloadcondition;both OP AMP would cause excessive distortion.The difference amplifiercan easilybe modifiedtoadd a levelshiftforIfthe applicationrequiresa dc-coupledoutput,a applicationsrequiringthesingle-endedoutputvoltagedifferenceamplifiermay be considered,as shown in tobe unipolar;thatis,swingbetween 0V and +2V.Figure 21. Four externalresistorsare needed to configurethevoltage-feedbackop amp OPA690 as a DUAL TRANSIMPEDANCE OUTPUTdifferenceamplifierperformingthe differentialto CONFIGURATIONsingle-endedconversion.Under the configuration shown, the DAC2904 generatesa differentialoutput The circuitexample of Figure22 shows the signal signalof0.5VPP attheloadresistors,R L.The resistor outputcurrentsconnectedintothesumming junctions valuesshown were selectedtoresultina symmetric ofthedualvoltage-feedbackop amp OPA2690 thatis 25Ω loadingforeach ofthecurrentoutputssincethe setup as a transimpedancestage,or-to-Vconverter. inputimpedance of the differenceamplifieris in With thiscircuit,the DAC outputwillbe kept at a paralleltoresistorsR L,and shouldbe considered. virtualground, minimizingthe effectsof output impedance variations,which resultsin the best dc linearity(INL).As mentionedpreviously,care should be taken not to drivethe amplifierintoslew-rate limitations,and produceunwanted distortion. Figure21. DifferenceAmplifierProvides DifferentialtoSingle-EndedConversion and DC-Coupling The OPA690 is configuredfor a gain of two. Therefore,operatingthe DAC2904 with a 20mA full-scaleoutputwillproducea voltageoutputof±1V. This requiresthe amplifierto operateoffof a dual power supply(±5V). The toleranceof the resistors typicallysets the limit for the achievable common-mode rejection.An improvement can be obtainedby fine-tuningresistorR 4. Thisconfigurationtypicallydeliversa lowerlevelofac Figure22. Dual,Voltage-FeedbackAmplifier OPA2690 Forms DifferentialTransimpedanceperformance than the previously discussed Amplifiertransformersolutionbecause theamplifierintroduces another source of distortion.Suitableamplifiers introducea realpole to createa low-passfilterin orderto slew-limitthe DAC fastoutputsignalsteps, which otherwise could drive the amplifierinto

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2 R C/c112F F

= GBP

4 R C/c112F D

2 R C/c112 F D

f =/c45 3dB I 1OUT DAC2904 I 1OUT V 1OUT VDC IOUT 1 IOUT 1 VOUT 1 IOUT DAC2904 25/c87 50/c87 50/c87 I =OUTFS 20mA V =□0V□to□+0.5VOUT IOUT DAC2904 C F isadded acrossR F to compensate forthisnoise INTERFACING ANALOG QUADRATURE gain peaking.To achieve a flattransimpedance MODULATORS frequency response, the pole in each feedback One of the main applicationsforthe dual-channelnetworkshouldbe setto: DAC isbaseband I-and Q-channeltransmissionfor digitalcommunications.Inthisapplication,theDAC is followed by an analog quadrature modulator,(8) modulatingan IF carrierwiththe baseband data,as withGBP = Gain BandwidthProductoftheOPA shown inFigure25.Often,theinputstagesofthese quadratemodulatorsconsistof npn-typetransistorswhich will give a corner frequency f–3dB of thatrequirea dc bias (base)voltagegreaterthanapproximately: 0.8V.The wide outputcompliancerange (–10V to +1.25V)allowsfora directdc-couplingbetween the DAC2904 and thequadraturemodulator.(9) toconverttoa single-endedsignal. SINGLE-ENDED CONFIGURATION Using a singleloadresistorconnectedtoone ofthe DAC outputs,a simplecurrent-to-voltageconversion can be accomplished.The circuitinFigure23 shows a 50Ω resistorconnected to IOUT , providingthe terminationof the furtherconnected 50Ω cable. Therefore,witha nominaloutputcurrentof20mA, the DAC producesa totalsignalswingof0V to0.5V into the25Ω load. Figure24. DC-Coupled InterfacetoQuadrature ModulatorApplyingLevelShifting Figure23. Drivinga Doubly-Terminated50Ω Cable Directly Differentloadresistorvaluesmay be selectedas long as the outputcompliancerange is not exceeded. Additionally,the outputcurrent,IOUTFS , and the load resistormay be mutuallyadjustedto providethe desiredoutputsignalswingand performance. Copyright© 2001–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):DAC2904

Quadrature□Modulator V ~□0V to□1.20VOUT P P V ~□0.6V to□1.8VIN P P RF IIN IREF DAC2904 /c83 IOUT2 IOUT1 Signal Conditioning I 1OUT DAC2904 I 1OUT V 1OUT

0.01 F/c109

I =□32 I =□32OUTFS REF /c180 /c180 V R REF SET DAC2904 +1.25V□Ref. RSET 2k/c87

0.1 F/c109

+5V +VA REFIN I =REF VREF RSET Current Sources Ref Control Amp DAC2904 Signalconditioning(level-shifting)may be requiredtoensurecorrectdc common-mode levelsattheinputofthequadraturemodulator. Figure25. GenericInterfacetoa QuadratureModulator INTERNAL REFERENCE OPERATION The DAC2904 has an on-chipreferencecircuitwhich consistsof a 1.25V bandgap referenceand two controlamplifiers,one foreach DAC. The full-scale outputcurrent,IOUTFS ,oftheDAC2904 isdetermined by the referencevoltage,VREF , and the value of resistorR SET .IOUTFS can be calculatedby: (10) Figure26. AC-Coupled InterfacetoQuadratureAs shown in Figure27, the externalresistorR SET ModulatorApplyingLevelShiftingconnects to the FSA pin (Full-ScaleAdjust).The referencecontrolamplifieroperates as a V-to-I converterproducinga referencecurrent,IREF , which is determinedby the ratioof VREF and R SET (see Equation10).The full-scaleoutputcurrent,IOUTFS , resultsfrommultiplyingIREF by a fixedfactorof32. Using the internalreference,a 2kΩ resistorvalue resultsina full-scaleoutputof approximately20mA. Resistorswitha toleranceof1% or bettershouldbe considered.Selectinghigher values, the output currentcan be adjustedfrom 20mA down to 2mA. Operatingthe DAC2904 at lowerthan 20mA output currentsmay be desirableforreasonsofreducingthe totalpower consumption,improvingthe distortion performance,or observingthe output compliance voltagelimitationsfora givenloadcondition. Itisrecommended to bypass the REF IN pin witha ceramicchipcapacitorof0.1μF or more. The control amplifieris internallycompensated, and its small-signalbandwidthisapproximately0.3MHz. Figure27. InternalReferenceConfiguration

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+1.25V□Ref. FSA +5V +VA REFIN I =REF VREF RSET Current Sources Ref Control AmpExternal Reference DAC2904 GAIN SETTING OPTIONS The full-scaleoutputcurrenton theDAC2904 can be set two ways: eitherfor each of the two DAC channels independently or for both channels simultaneously.For the independentgainsetmode, theGSET pin(pin42)must be low(thatis,connected to AGND). In thismode, two externalresistorsare required— one R SET connectedto the FSA1 pin(pin 44) and the otherto the FSA2 pin (pin41).In this configuration,the user has the flexibilityto set and adjustthe full-scaleoutputcurrentfor each DAC independently,allowingfor the compensation of possible gain mismatches elsewhere within the transmitsignalpath. Figure28. ExternalReferenceConfiguration Alternatively,bringingthe GSET pin high (thatis, connectedto+VA),theDAC2904 willswitchintothe GROUNDING, DECOUPLING AND LAYOUTsimultaneousgain set mode. Now the full-scale INFORMATIONoutputcurrentofbothDAC channelsisdeterminedby The DAC2904 uses separatepinsforitsanalogandEXTERNAL REFERENCE OPERATION ofthesecapacitorslargelydepends on theproximityWhilea 0.1μF capacitorisrecommended tobe used to the individualsupplyand ground pins.Therefore,with the internalreference,itis optionalfor the they should be located as close as physicallyexternalreferenceoperation.The referenceinput, possibleto those deviceleads.Whenever possible,REF IN, has a highinputimpedance (1MΩ) and can the capacitorsshouldbe locatedimmediatelyundereasilybe drivenby varioussources.Note thatthe each pairofsupply/groundpinson thereversesideofvoltagerange of the externalreferenceshouldstay the PCB. This layoutapproach willminimize thewithinthecompliancerangeofthereferenceinput. parasiticinductanceof component leads and PCB runs.POWER-DOWN MODE Further supply decoupling with surface-mountThe DAC2904 featuresa power-down functionwhich tantalumcapacitors(1μF to4.7μF) may be added ascan be used toreducethetotalsupplycurrenttoless needed inproximityoftheconverter.than6mA overthespecifiedsupplyrange of3.0V to 5.5V.Applyinga logichightothePD pinwillinitiate Low noise is requiredfor allsupply and ground the power-down mode, whilea logiclow enables connectionsto the DAC2904. Itisrecommended to normaloperation.When leftunconnected,an internal use a multilayerPCB utilizingseparatepower and active pulldown circuitwill enable the normal ground planes. Mixed signal designs require operationoftheconverter. particularattentionto the routingof the different supplycurrentsand signaltraces.Generally,analog supplyand ground planes should only extend into analogsignalareas,such as the DAC outputsignal and the referencesignal.Digitalsupplyand ground Copyright© 2001–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):DAC2904

planes must be confinedto areas coveringdigital connected togetherat the supplyconnectorof the circuitry,includingthedigitalinputlinesconnectingto PCB. In the case of onlyone supplyvoltagebeing theconverter,as wellas theclocksignal.The analog availabletopower theDAC, ferritebeads alongwith and digitalgroundplanesshouldbe joinedtogetherat bypass capacitorsmay be used tocreatean LC filter. one pointunderneaththeDAC. Thiscan be realized Thiswillgeneratea low-noiseanalogsupplyvoltage, witha shorttrackofapproximately1/8inch(3,0mm). whichcan thenbe connectedtothe+VA supplypinof theDAC2904.The power to the DAC2904 should be provided throughthe use of wide PCB runs or planes.Wide Whiledesigningthelayout,itisimportanttokeep the runs willpresenta lower traceimpedance, further analogsignaltracesseparatedfrom any digitalline, optimizingthe supply decoupling.The analog and in orderto preventnoise couplingonto the analog digitalsuppliesfor the convertershould only be signalpath.

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REVISION HISTORY

NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Copyright© 2001–2009,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):DAC2904

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DAC2904IPFB Active Production TQFP (PFB) | 48 250 | JEDEC TRAY (10+1) Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC2904Y DAC2904IPFB.B Active Production TQFP (PFB) | 48 250 | JEDEC TRAY (10+1) Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC2904Y DAC2904Y/1K Active Production TQFP (PFB) | 48 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC2904Y DAC2904Y/1K.B Active Production TQFP (PFB) | 48 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC2904Y DAC2904Y/250 Active Production TQFP (PFB) | 48 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC2904Y DAC2904Y/250.B Active Production TQFP (PFB) | 48 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC2904Y DAC2904Y/2501G4.B Active Production TQFP (PFB) | 48 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC2904Y (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 23-May-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC2904Y/1K TQFP PFB 48 1000 367.0 367.0 38.0 DAC2904Y/250 TQFP PFB 48 250 367.0 367.0 38.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) DAC2904IPFB PFB TQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.5 11.25 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 48X 0.27 0.1744X 0.5 PIN 1 ID (0.13) TYP

0.05 MIN0 -7

4X 5.5 9.2

8.8 TYP

0.75 0.45 B7.2 6.8 NOTE 3 A 7.2 6.8 NOTE 3 0.25 GAGE PLANE

1.2 MAX

(1) PLASTIC QUAD FLATPACK TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MS-026. 13 24 3748

0.08 C A B

0.08 A 16 DETAIL A TYPICAL SCALE 1.900

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

(8.5) (8.5) 44X (0.5) 48X (1.35) 48X (0.25) (R0.05) TYP TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM SYMM 48 37 13 24 SEE DETAILS METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 44X (0.5) 48X (1.35) 48X (0.25) (R0.05) TYP (8.5) (8.5) TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE SCALE:8X SYMM SYMM 48 37 13 24

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