DAC2904

DAC2904 BURR-BROWN | Alldatasheet

Document overview

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Technical content

Dual, 14-Bit, 125MSPS DIGITAL-TO-ANALOG CONVERTER

FEATURES

GGGGG SINGLE SUPPLY: +3.3V or +5V GGGGG HIGH SFDR: 78dB at fOUT = 10MHz GGGGG LOW GLITCH: 2pVs GGGGG LOW POWER: 310mW GGGGG INTERNAL REFERENCE GGGGG POWER-DOWN MODE: 23mW

APPLICATIONS

GGGGG COMMUNICATIONS: Base Stations, WLL, WLAN Baseband I/Q Modulation GGGGG MEDICAL/TEST INSTRUMENTATION GGGGG ARBITRARY WAVEFORM GENERATORS (ARB) GGGGG DIRECT DIGITAL SYNTHESIS (DDS)

DESCRIPTION

The DAC2904 is a monolithic, 14-bit, dual-channel, high-speed Digital-to-Analog Converter (DAC), and is opti- mized to provide high dynamic performance while dissipating only 310mW. Operating with high update rates of up to 125MSPS, the DAC2904 offers exceptional dynamic performance, and enables the generation of very-high output frequencies suit- able for “Direct IF” applications. The DAC2904 has been optimized for communications applications in which sepa- rate I and Q data are processed while maintaining tight-gain and offset matching. Each DAC has a high-impedance differential-current output, suitable for single-ended or differential analog-output con- figurations. The DAC2904 combines high dynamic performance with a high update rate to create a cost-effective solution for a wide variety of waveform-synthesis applications:  Pin compatibility between family members provides 10-bit (DAC2900), 12-bit (DAC2902), and 14-bit (DAC2904) resolution.  Pin compatible to the AD9767 dual DAC.  Gain matching is typically 0.5% of full-scale, and offset matching is specified at 0.02% max.  The DAC2904 utilizes an advanced CMOS process; the segmented architecture minimizes output-glitch energy, and maximizes the dynamic performance.  All digital inputs are +3.3V and +5V logic compatible. The DAC2904 has an internal reference circuit, and allows use in a multiplying configuration.  The DAC2904 is available in a TQFP-48 package, and is specified over the extended industrial temperature range of –40°C to +85°C. DAC2904 DAC2904 SBAS198B – NOVEMBER 2003 www.ti.com Copyright © 2002-2003, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 14 Bits Output Update Rate (fCLOCK ) 125 MSPS STATIC ACCURACY (1) Differential Nonlinearity (DNL) T A = +25°C ±4.0 LSB Integral Nonlinearity (INL) T A = +25°C ±5.0 LSB DYNAMIC PERFORMANCE Spurious-Free Dynamic Range (SFDR) To Nyquist fOUT = 1MHz, fCLOCK = 50MSPS 0dBFS Output 71 82 dBc –6dBFS Output 77 dBc –12dBFS Output 72 dBc fOUT = 1MHz, fCLOCK = 26MSPS 82 dBc fOUT = 2.18MHz, fCLOCK = 52MSPS 81 dBc fOUT = 5.24MHz, fCLOCK = 52MSPS 81 dBc fOUT = 10.4MHz, fCLOCK = 78MSPS 78 dBc fOUT = 15.7MHz, fCLOCK = 78MSPS 72 dBc fOUT = 5.04MHz, fCLOCK = 100MSPS 80 dBc fOUT = 20.2MHz, fCLOCK = 100MSPS 69 dBc fOUT = 20.1MHz, fCLOCK = 125MSPS 69 dBc fOUT = 40.2MHz, fCLOCK = 125MSPS 64 dBc Spurious-Free Dynamic Range within a Window fOUT = 1.0MHz, fCLOCK = 50MSPS 2MHz Span 80 90 dBc fOUT = 5.24MHz, fCLOCK = 52MSPS 10MHz Span 88 dBc fOUT = 5.26MHz, fCLOCK = 78MSPS 10MHz Span 88 dBc fOUT = 5.04MHz, fCLOCK = 125MSPS 10MHz Span 88 dBc Total Harmonic Distortion (THD) fOUT = 1MHz, fCLOCK = 50MSPS –79 –70 dBc fOUT = 5.24MHz, fCLOCK = 52MSPS –77 dBc fOUT = 5.26MHz, fCLOCK = 78MSPS –76 dBc fOUT = 5.04MHz, fCLOCK = 125MSPS –75 dBc Multitone Power Ratio 8 Tone with 110kHz Spacing fOUT = 2.0MHz to 2.99MHz, fCLOCK = 65MSPS 0dBFS Output 80 dBc Signal-to-Noise Ratio (SNR) fOUT = 5.02MHz, fCLOCK = 50MHz 0dBFS Output 68 dBc Signal-to-Noise and Distortion (SINAD) fOUT = 5.02MHz, fCLOCK = 50MHz 0dBFS Output 67 dBc TMIN to TMAX , +VA = +5V, +VD = +3.3V, differential transformer coupled output, 50ý doubly-terminated, unless otherwise noted. Independant Gain Mode. PACKAGE SPECIFIED DRAWING PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER DESIGNATOR RANGE MARKING NUMBER (1) MEDIA DAC2904Y TQFP-48 355 PFB –40°C to +85°C DAC2904Y DAC2904Y/250 Tape and Reel "" " """ DAC2904Y/1K Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC2904Y/1K” will get a single 1000-piece Tape and Reel. PACKAGE/ORDERING INFORMATION PRODUCT EVM ORDERING NUMBER COMMENT DAC2904 DAC2904-EVM Fully populated evaluation board. See user manual for details.

ELECTRICAL CHARACTERISTICS (Cont.) TMIN to TMAX , +VA = +5V, +VD = +3.3V, differential transformer coupled output, 50ý doubly terminated, unless otherwise noted. Independant Gain Mode. DYNAMIC PERFORMANCE (Cont.) Channel Isolation fOUT = 1MHz, fCLOCK = 52MSPS 85 dBc fOUT = 20MHz, fCLOCK = 125MSPS 77 dBc Output Settling Time(2) to 0.1% 30 ns Output Rise Time(2) 10% to 90% 2 ns Output Fall Time(2) 10% to 90% 2 ns Glitch Impulse 2 pV-s DC ACCURACY Full-Scale Output Range(3)(FSR) All Bits HIGH, I OUT 22 0 m A Output Compliance Range –1.0 +1.25 V Gain Error—Full-Scale With Internal Reference –5 ±1 +5 %FSR Gain Error With External Reference –2.5 ±1 +2.5 %FSR Gain Matching With Internal Reference –2.0 0.5 +2.0 %FSR Gain Drift With Internal Reference ±50 ppmFSR/°C Offset Error With Internal Reference –0.02 +0.02 %FSR Offset Drift With Internal Reference ±0.2 ppmFS R/°C Power-Supply Rejection, +V Power-Supply Rejection, +VD +3.3V, ±10% –0.025 +0.025 %FSR/V Output Noise I OUT = 20mA, RLOAD = 50Ω 50 pA/ Hz IOUT = 2mA 30 pA/šHz Output Resistance 200 k Ω Output Capacitance I OUT , IOUT to Ground 6 pF REFERENCE/CONTROL AMP Reference Voltage +1.18 +1.25 +1.31 V Reference Voltage Drift ±50 ppmFSR/°C Reference Output Current 100 nA Reference Multiplying Bandwidth 0.3 MHz Input Compliance Range +0.5 +1.25 V DIGITAL INPUTS Logic Coding Straight Binary Logic High Voltage, VIH +V D = +5V 3.5 5 V Logic Low Voltage, VIL +V D = +5V 0 1.2 V Logic High Voltage, VIH +V D = 3.3V 2 3 V Logic Low Voltage, VIL +V D = 3.3V 0 0.8 V Logic High Current, IIH(4) +V D = 3.3V ±10 µA Logic Low Current +V D = 3.3V ±10 µA Input Capacitance 5p F POWER SUPPLY Supply Voltages Supply Current IVA (5) +V A = +5V, lOUT = 20mA 58 65 mA IVA (5) Power-Down Mode 1.7 3 mA IVD (5) 4.2 7 mA IVD (6) 17 19.5 mA Power Dissipation(5) +V A = +5V, +VD = 3.3V, lOUT = 20mA 310 350 mW Power Dissipation(6) +V A = +5V, +VD = 3.3V, lOUT = 20mA 348 390 mW Power Dissipation(5) +V A = +5V, +VD = 3.3V, lOUT = 2mA 130 mW Power Dissipation Power-Down Mode 23 38 mW Thermal Resistance, TQFP-48 θJA 60 °C/W θJC 13 °C/W TEMPERATURE RANGE Specified Ambient –40 +85 °C Operating Ambient –40 +85 °C NOTES: (1) At output l OUT , while driving a virtual ground. (2) Measured single-ended into 50ý load. (3) Nominal full-scale output current is 32  IREF ; see Application section for details. (4) Typically 45µA for the PD pin, which has an internal pull-down resistor. (5) Measured at fCLOCK = 25MSPS and fOUT = 1MHz. (6) Measured at fCLOCK = 100MSPS and fOUT = 40MHz. DAC2904Y PARAMETER CONDITIONS MIN TYP MAX UNITS

PIN DESIGNATOR DESCRIPTION 1-14 D[13:0]_1 Data Port DAC1, Data Bit 13 (MSB) to Bit 0 (LSB).

15 DGND Digital Ground

D Digital Supply, +3.0V to +5.5V

17 WRT1 DAC1 Input Latches Write Signal

18 CLK1 Clock Input DAC1

19 CLK2 Clock Input DAC2

20 WRT2 DAC2 Input Latches Write Signal

21 DGND Digital Ground

D Digital Supply, +3.0V to +5.5V 23-36 D[13:0]_2 Data Port DAC2, Data Bit 13 (MSB) to Bit 0 (LSB). 37 PD Power-Down Function Control Input; “H” = DAC in power-down mode; “L” = DAC in normal operation (Internal pull-down for default “L”).

38 AGND Analog Ground

39 I OUT 2 Current Output DAC2. Full-scale with all bits of data port 2 high. 40 I OUT 2 Complementary Current Output DAC2. Full-scale with all bits of data port 2 low. 41 FSA2 Full-Scale Adjust, DAC2. Connect External R SET Resistor

42 GSET Gain-Setting Mode (H = 1 Resistor, L = 2 Resistors)

43 REF IN Internal Reference Voltage output; External Reference Voltage input. Bypass with 0.1µF to AGND for internal reference operation. 44 FSA1 Full-Scale Adjust, DAC1. Connect External R SET Resistor 45 I OUT 1 Complementary Current Output DAC1. Full-scale with all bits of data port 1 low. 46 I OUT 1 Current Output DAC1. Full-scale with all bits of data port 1 high. 47 +V A Analog Supply, +3.0V to +5.5V

48 NC No Connection

48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 DAC2904 D0-2 D1-2 D2_2 D3_2 D4_2 D5_2 D6_2 D7_2 D8_2 D9_2 D10_2 D11_2 NC A IOUT 1 IOUT 1 FSA1 REF IN GSET FSA2 I OUT 2 IOUT 2 AGND PD D1-1 D0-1 DGND D WRT1 CLK1 CLK2 WRT2 DGND D D13_2 (MSB) D12_2 D13_1 (MSB) D12_1 D11_1 D10_1 D9_1 D8_1 D7_1 D6_1 D5_1 D4_1 D3_1 D2_1

IOUT (n) IOUT (n + 1)50% DATA IN WRT1 WRT2 CLK1 CLK2 IOUT 1 IOUT 2 TIMING DIAGRAM SYMBOL DESCRIPTION MIN TYP MAX UNITS tS Input Setup Time 2 ns tH Input Hold Time 1.5 ns tLPW, tCPW Latch/Clock Pulsewidth 3.5 4 ns tCW Delay Rising CLK Edge to 0 t PW – 2 ns Rising WRT Edge tPD Propagation Delay 1 ns tSET Settling Time (0.1%) 30 ns DIGITAL INPUTS AND TIMING The data input ports of the DAC2904 accepts a standard positive coding with data bit D13 being the most significant bit (MSB). The converter outputs support a clock rate of up to 125MSPS. The best performance will typically be achieved with a symmetric duty cycle for write and clock; however, the duty cycle may vary as long as the timing specifications are met. Also, the set-up and hold times may be chosen within their specified limits. All digital inputs of the DAC2904 are CMOS compatible. The logic thresholds depend on the applied digital supply voltages, such that they are set to approximately half the supply voltage; V th = +VD /2 (±20% tolerance). The DAC2904 is designed to operate with a digital supply (+VD ) of +3.0V to +5.5V. The two converter channels within the DAC2904 consist of two independent, 14-bit, parallel data ports. Each DAC- channel is controlled by its own set of write (WRT1, WRT2) and clock (CLK1, CLK2) inputs. Here, the WRT lines control the channel input latches and the CLK lines control the DAC latches. The data is first loaded into the input latch by a rising edge of the WRT line. This data is presented to the DAC latch on the following falling edge of the WRT signal. On the next rising edge of the CLK line, the DAC is updated with the new data and the analog output signal will change accordingly. The double latch architecture of the DAC2904 results in a defined sequence for the WRT and CLK signals, expressed by parameter ‘t CW ’. A correct tim- ing is observed when the rising edge of CLK occurs at the same time, or before, the rising edge of the WRT signal. This condition can simply be met by connecting the WRT and CLK lines together. Note that all specifications were mea- sured with the WRT and CLK lines connected together.

TA = 25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50ý double terminated load, SFDR up to Nyquist, unless otherwise noted. SFDR vs fOUT AT 26MSPS fOUT (MHz) SFDR (dBc) 90/i13 85/i3 80/i3 75/i3 70/i3 65/i3 426 8 1 0 1 20 0dBFS–6dBFS –12dBFS SFDR vs fOUT AT 52MSPS fOUT (MHz) SFDR (dBc) 90/i3 85/i3 80/i3 75/i3 70/i3 65/i3 1051 5 2 0 2 50 0dBFS–6dBFS –12dBFS SFDR vs fOUT AT 78MSPS fOUT (MHz) SFDR (dBc) 85/i3 80/i3 75/i3 70/i3 65/i3 60/i3 105 1 52 02 53 03 50 0dBFS –6dBFS –12dBFS 6/i3 5/i3 4/i3 3/i3 2/i3 1/i3 0/i3 –1/i3 –2/i3 –3/i3 INL (LBS) 0 2k 4k 6k 8k 10k 12k 14k 16k Code TYPICAL INL SFDR vs fOUT AT 100MSPS fOUT (MHz) SFDR (dBc) 85/i3 80/i3 75/i3 70/i3 65/i3 60/i3 55/i3 105 1 52 02 53 03 54 04 50 –6dBFS –12dBFS 0dBFS DNL (LBS) 0 2k 4k 6k 8k 10k 12k 14k 16k Code TYPICAL DNL

TYPICAL CHARACTERISTICS (Cont.) TA = 25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50ý double terminated load, SFDR up to Nyquist, unless otherwise noted. SFDR vs fOUT AT 125MHz fOUT (MHz) SFDR (dBc) 85/i3 80/i3 75/i3 70/i3 65/i3 60/i3 55/i3 2010 30 40 50 600 –6dBFS –12dBFS 0dBFS SFDR AT 125MSPS vs TEMPERATURE Temperature (°C) SFDR (dBc) 90/i3 85/i3 80/i3 75/i3 70/i3 65/i3 60/i3 55/i3 0–20 20 40 60 80 100–40 2MHz 40MHz 10MHz 20MHz GAIN AND OFFSET DRIFT Temperature (°C) Gain Error (% FS) 0.8/i13 0.6/i13 0.4/i13 0.2/i13 0/i13 –0.2/i13 –0.4/i13 –0.6/i13 –0.8 Offset Error (% FS) 0.004/i3 0.003/i3 0.002/i3 0.001/i3 0/i3 –0.001/i13 –0.002/i13 –0.003/i13 –0.004 0–20 20 40 60 80 85–40 Offset Error Gain Error IVD vs RATIO AT +VD = +3.3V Ratio (FOUT /FCLK ) IVD (mA) 25/i3 20/i3 15/i3 10/i3 5/i3 125MSPS 100MSPS 78MSPS 52MSPS 26MSPS SFDR (dBc) 0 5 10 15 20 25 fOUT (MHz) 20mA 5mA 10mA SFDR vs IOUT FS and fOUT at 78MSPS, 0dBFS IVA vs IOUT FS IOUT FS (mA) IVA (mA) 60/i3 55/i3 50/i3 45/i3 40/i3 35/i3 30/i3 25/i3 20/i3 15/i3 1051 5 2 0 2 50

TYPICAL CHARACTERISTICS (Cont.) TA = 25°C, +VD = +3.3V, +VA = +5V, differential transformer coupled, IOUT = 20mA, 50ý double terminated load, SFDR up to Nyquist, unless otherwise noted. Frequency (MHz) Magnitude (dBm) 10/i3 0/i3 –10/i13 –20/i13 –30/i13 –40/i13 –50/i13 –60/i13 –70/i13 –80/i13 –90 5.2 10.4 15.6 20.8 260 fCLOCK = 52MSPS/i13 fOUT = 5.23MHz/i13 Amplitude = 0dBFS SINGLE-TONE SFDR Frequency (MHz) Magnitude (dBm) 10/i3 0/i3 –10/i13 –20/i13 –30/i13 –40/i13 –50/i13 –60/i13 –70/i13 –80/i13 –90 10 20 30 40 500 SINGLE-TONE SFDR fCLOCK = 100MSPS/i13 fOUT = 20.2MHz/i13 Amplitude = 0dBFS Frequency (MHz) Magnitude (dBm) 10/i3 0/i3 –10/i13 –20/i13 –30/i13 –40/i13 –50/i13 –60/i13 –70/i13 –80/i13 –90 51 0 1 5 2 0 2 50 FOUR-TONE SFDR fCLOCK = 50MSPS/i13 fOUT 1 = 6.25MHz/i13 fOUT 2 = 6.75MHz/i13 fOUT 3 = 7.25MHz/i13 fOUT 4 = 7.75MHz/i13 Amplitude = 0dBFS Magnitude (dBm) –30/i13 –40/i13 –50/i13 –60/i13 –70/i13 –80/i13 –90/i13 –100/i13 –110/i13 –120/i13 –130 WCDMA-ACPR Center 15.36MHz; Span 14MHz fCLOCK = 61.44MSPS/i13 PCHANNEL = –13dBm/i13 ACPR = –69.2dB Frequency (MHz) Magnitude (dBm) 10/i3 0/i3 –10/i13 –20/i13 –30/i13 –40/i13 –50/i13 –60/i13 –70/i13 –80/i13 –90 7.8 15.6 23.4 31.2 390 DUAL-TONE SFDR fCLOCK = 78MSPS/i13 fOUT 1 = 9.44MHz/i13 fOUT 2 = 10.44MHz/i13 Amplitude = 0dBFS

FIGURE 1. Block Diagram of the DAC2904.

APPLICATION INFORMATION

The architecture of the DAC2904 uses the current steering technique to enable fast switching and a high update rate. The core element within the monolithic DAC is an array of segmented current sources that are designed to deliver a full- scale output current of up to 20mA, as shown in Figure 1. An internal decoder addresses the differential current switches each time the DAC is updated and a corresponding output current is formed by steering all currents to either output summing node, I OUT or IOUT . The complementary outputs deliver a differential output signal, which improves the dynamic performance through reduction of even-order har- monics, common-mode signals (noise), and double the peak- to-peak output signal swing by a factor of two, compared to single-ended operation. The segmented architecture results in a significant reduction of the glitch energy, improves the dynamic performance (SFDR), and DNL. The current outputs maintain a very high output impedance of greater than 200ký. The full-scale output current is determined by the ratio of the internal reference voltage (1.25V) and an external resistor, R SET . The resulting IREF is internally multiplied by a factor of 32 to produce an effective DAC output current that can range from 2mA to 20mA, depending on the value of R SET . The DAC2904 is split into a digital and an analog portion, each of which is powered through its own supply pin. The digital section includes edge-triggered input latches and the decoder logic, while the analog section comprises the cur- rent source array with its associated switches, and the reference circuitry. DAC TRANSFER FUNCTION Each of the DACs in the DAC2904 has a set of complemen- tary current output, I OUT 1 and IOUT 2. The full-scale output current, IOUTFS , is the summation of the two complementary output currents: IOUTFS = IOUT + IOUT (1) The individual output currents depend on the DAC code and can be expressed as: IOUT = IOUTFS  (Code/16384) (2) IOUT = IOUTFS  (16383 - Code/16384) (3) where ‘Code’ is the decimal representation of the DAC data input word. Additionally, IOUTFS is a function of the refer- ence current IREF , which is determined by the reference voltage and the external setting resistor, RSET . IOUTFS = 32  IREF = 32  VREF /RSET (4) In most cases the complementary outputs will drive resistive loads or a terminated transformer. A signal voltage will develop at each output according to: V OUT = IOUT  RLOAD (5) V OUT = IOUT  RLOAD (6) DAC /i13 Latch 1 WRT1 CLK1 CLK2 WRT2 Data Input/i13 Port 2/i13 D[13:0]_2 Data Input/i13 Port 1/i13 D[13:0]_1 l OUT 1 lOUT 1 Input/i13 Latch 1 Reference/i13 Control Amplifier FSA2 REF IN FSA1 GSET PD DAC1 /i13 Segmented Switches/i13 Current Sources DAC2904 lOUT 2 lOUT 2 +VA+V D+V D DAC /i13 Latch 2 Input/i13 Latch 2 DAC2 /i13 Segmented Switches/i13 Current Sources AGNDDGNDDGND

the case with high output frequencies. the output current into a ground-referenced voltage signal. while achieving excellent dynamic performance (see Figure 3). on the output frequency spectrum and impedance requirements. the dynamic performance over a wide range of frequencies. and inherently isolated because of its magnetic coupling. FIGURE 2. Equivalent Analog Output. TABLE I. Input Coding versus Analog Output Current.

gain mismatches elsewhere within the transmit signal path. ability of dynamic gain control. enable the normal operation of the converter. FIGURE 11. External Reference Configuration.

GROUNDING, DECOUPLING AND LAYOUT INFORMATION Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for high-frequency designs. Multilayer PCBs are recommended for best perfor- mance since they offer distinct advantages such as minimiza- tion of ground impedance, separation of signal layers by ground layers, etc. The DAC2904 uses separate pins for its analog and digital supply and ground connections. The placement of the decou- pling capacitor should be such that the analog supply (+V A ) is bypassed to the analog ground (AGND), and the digital supply bypassed to the digital ground (DGND). In most cases 0.1µF ceramic chip capacitors at each supply pin are adequate to provide a low impedance decoupling path. Keep in mind that their effectiveness largely depends on the proximity to the individual supply and ground pins. There- fore they should be located as close as physically possible to those device leads. Whenever possible, the capacitors should be located immediately under each pair of supply/ground pins on the reverse side of the pc board. This layout ap- proach will minimize the parasitic inductance of component leads and PCB runs. Further supply decoupling with surface-mount tantalum ca- pacitors (1µF to 4.7µF) may be added as needed in proxim- ity of the converter. Low noise is required for all supply and ground connections to the DAC2904. It is recommended to use a multilayer PCB utilizing separate power and ground planes. Mixed signal designs require particular attention to the routing of the different supply currents and signal traces. Generally, analog supply and ground planes should only extend into analog signal areas, such as the DAC output signal and the refer- ence signal. Digital supply and ground planes must be confined to areas covering digital circuitry, including the digital input lines connecting to the converter, as well as the clock signal. The analog and digital ground planes should be joined together at one point underneath the DAC. This can be realized with a short track of approximately 1/8 inch (3mm). The power to the DAC2904 should be provided through the use of wide pcb runs or planes. Wide runs will present a lower trace impedance, further optimizing the supply decou- pling. The analog and digital supplies for the converter should only be connected together at the supply connector of the pc board. In the case of only one supply voltage being available to power the DAC, ferrite beads along with bypass capacitors may be used to create an LC filter. This will generate a low-noise analog supply voltage, which can then be connected to the +V A supply pin of the DAC2904. While designing the layout, it is important to keep the analog signal traces separated from any digital line, in order to prevent noise coupling onto the analog signal path.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) DAC2904Y/1K ACTIVE TQFP PFB 48 1000 None Call TI Call TI DAC2904Y/250 ACTIVE TQFP PFB 48 250 None Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Feb-2005 Addendum-Page 1

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 4073176/B 10/96 Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 0,17 0,27 SQ 7,20 6,80 5,50 TYP SQ8,80 9,20 1,05 0,95 1,20 MAX 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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