DAC2813 BURR-BROWN | Alldatasheet
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Technical content
© 1992 Burr-Brown Corporation PDS-1147C Printed in U.S.A. October, 1993 DAC2813 DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER (12-bit port interface)
FEATURES
l COMPLETE WITH REFERENCE AND OUTPUT AMPLIFIERS l 12-BIT PORT INTERFACE l ANALOG OUTPUT RANGE: ±10V l MONOTONICITY GUARANTEED OVER TEMPERATURE l INTEGRAL LINEARITY ERROR: ±1/2LSB max l ±12V to ±15V SUPPLIES l 28-PIN PLASTIC DIP PACKAGE
DESCRIPTION
DAC2813 is a complete dual 12-bit digital-to-analog converter with bus interface logic. Each package in- cludes a precision +10V voltage reference, double- buffered bus interface including a RESET function and 12-bit D/A converters with voltage-output opera- tional amplifiers. The double-buffered interface consists of a 12-bit input latch and a D/A latch for each D/A converter. A RESET control allows the D/A outputs to be asyn- chronously reset to bipolar zero, a feature useful for power-up reset, system initialization and recalibration. DAC2813 output range resistors are internally con- nected for 20V full scale range. A 0 to 10V range can be connected using the bipolar offset resistor. Gain and bipolar offset of each D/A are adjustable with external trim potentiometers. DAC2813 is available in one performance grade with a integral linearity error of 1/2LSB and 12-bit mono- tonicity guaranteed over temperature. It is packaged in 28-pin 0.6in. wide plastic DIP package and specified over –40oC to +85oC. 10V Reference VREF OUT VREF IN 1 BPO 1 VOUT 1 D/A 1 VREF IN 2 BPO 2 VOUT 2 D/A 2 DB0 DB11 LSB MSB DAC2813 12-bit Latches International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
At TA = +25oC, +VCC = +12V or +15V, –VCC = –12V or –15V, unless otherwise noted. DAC2813AP PARAMETER CONDITIONS MIN TYP MAX UNITS INPUTS DIGITAL INPUTS Over Temperature Input Code (1) Range Bipolar Offset Binary Logic Levels (2) VIH +2 +5.5 (3) V VIL 0 +0.8 V Logic Input Currents DB0-DB11, WR, LDAC, RESET,EN X IIH VI = +2.7V ±20 µA IIL VI = +0.4V ±20 µA TRANSFER CHARACTERISTICS ACCURACY Linearity Error ±1/4 ±1/2 LSB Differential Linearity Error ±1/2 ±1 LSB Gain Error (5,6) ±0.05 ±0.2 % Bipolar Zero Error (5,7) ±0.05 ±0.2 %FSR (4) Power Supply Sensitivity Of Full Scale +VCC ±5 ±20 ppmFSR/%+V CC –VCC ±1 ±10 ppmFSR/%–V CC DRIFT Over Specification Temperature Range Gain ±5 ±30 ppm/ °C Bipolar Zero Drift ±5 ±15 ppmFSR/ °C Linearity Error over Temperature ±1/2 ±3/4 LSB Monotonicity Guaranteed DYNAMIC CHARACTERISTICS SETTLING TIME (8) To within ±0.012%FSR of Final Value 5kΩ || 500pF Load Full Scale Range Change 20V Range 4.5 6 µs 1LSB Output Step (9) At Major Carry 2 µs Slew Rate 10 V/ µs Crosstalk (10) 5kΩ Loads 0.1 LSB OUTPUT Output Voltage Range ±VCC ≥ ±11.4V ±10 V Output Current ±5m A Output Impedance 0.2 Ω Short Circuit to ACOM Duration Indefinite REFERENCE VOLTAGE Voltage +9.95 +10.00 +10.05 V Source Current Available for External Loads 2 mA Impedance 0.2 Ω Temperature Coefficient ±5 ±25 ppm/ °C Short Circuit to Common Duration Indefinite POWER SUPPLY REQUIREMENTS Voltage:+VCC +11.4 +15 +16.5 V Current: No Load ±VCC = ±15V +VCC 24 30 mA –VCC 12 14 mA Power Dissipation 540 660 mW Potential at DCOM with Respect to ACOM (11) –3 +3 V TEMPERATURE RANGES Specification –40 +85 °C Storage –60 +100 °C Thermal Resistance, θJA,Plastic DIP 30 °C/W NOTES: (1) For Two’s Complement Input Coding invert the MSB with an external logic inverter. (2) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (3) Open DATA input lines will be pulled above +5.5V. See discussion under LOGIC INPUT COMPATIBILITY section. (4) FSR means Full Scale Range. For example, for ±10V output, FSR = 20V. (5) Adjustable to zero with external trim potentiometer. (6) Specified with 500Ω connected between VREF OUT and VREF IN. (7) Error at input code 800HEX . DAC2813 specified with 100Ω connected betweenVREF OUT and VREF IN; and with 500Ω connected between VREF OUT and BPO. (8) Maximum represents the 3σ limit. Not 100% tested for this parameter. (9) For the worst-case code change: 7FFHEX to 800HEX and 800HEX to 7FFHEX . (10) Crosstalk is defined as the change in any output as a result of any other output being driven from –10V to +10V at rated output current. (11) The maximum voltage at which ACOM and DCOM may be separated without affecting accuracy specifications.
ABSOLUTE MAXIMUM RATINGS (1) NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE DRAWING TEMPERATURE PRODUCT PACKAGE NUMBER (1) RANGE DAC2813AP 28-Pin DBL Wide DIP 215 –40 °C to +85°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. PACKAGE/ORDERING INFORMATION ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from per- formance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. BLOCK DIAGRAM LSB DB0 25kΩ 24.9kΩ BPO 1 VREF IN 1 12-Bit D/A Converter 12-Bit D/A Latch 123456789 1 0 1 1 1 2 MSB DB11 49.5kΩ +10V Reference 22 19 20 –VCC +VCCACOMVREF OUT WR 14 EN 1 16 17LDAC 12-Bit Input Latch VOUT 1 0–800µA 25kΩ 24.9kΩ BPO 2 VREF IN 2 12-Bit D/A Converter 12-Bit D/A Latch 49.5kΩ 15 12-Bit Input Latch VOUT 2 0–800µA DCOM EN 2 RESET NOTE: RESET does not reset input latches.
1 DB11 DATA, MSB, positive true.
2 DB10 DATA
3 DB9 DATA
4 DB8 DATA
5 DB7 DATA
6 DB6 DATA
7 DB5 DATA
8 DB4 DATA
9 DB3 DATA
10 DB2 DATA
11 DB1 DATA
12 DB0 DATA, LSB. 13 RESET Resets output of all D/As to bipolar-zero. The D/A remains in this state until overwritten an LDAC-WR command. RESET does not reset the input latch. After power–up and reset, input latches will be in an indeterminant state. 14 WR Write strobe. Must be low for data transfer to any latch (except RESET). 15 EN2 Enable for 12-bit input data latch of D/A 2. NOTE: This logic path is slower than the WR\\ path. 16 EN1 Enable for 12-bit input data latch of D/A 1. NOTE: This logic path is slower than the WR\\ path. 17 LDAC Load DAC enable. Must be low with WR for data transfer to the D/A latch and simultaneous update of both D/A converters. 18 DCOM Digital common, logic currents return. 19 –V CC Analog supply input, nominally –12V or –15V referred to ACOM. 20 +V CC Analog supply input, nominally +12V or +15V referred to ACOM. 21 V REF OUT +10V reference output. 22 ACOM Analog common, +V CC , –VCC supply return. 23 BPO2 Bipolar offset. Connect to pin 21 (V REF OUT ) through a 100Ω resistor or through a 200 potentiometer for Bipolar Offset Adjust for D/A 2. 24 BPO1 Bipolar offset. Connect to pin 21 (V REF OUT ) through a 100Ω resistor or through a 200 potentiometer for Bipolar Offset Adjust or D/A 1. 25 V REF IN 2 Connect to VREF OUT through 500Ω fixed resistor or through a 1kΩ gain adjustment potentiometer for D/A 2. 26 V REF IN 1 Connect to VREF OUT through 500Ω fixed resistor or through a 1kΩ gain adjustment potentiometer for D/A 1. 27 V OUT 2 D/A 2 analog output. 28 V OUT 1 D/A 1 analog output. PIN DESCRIPTIONS TRUTH TABLE WR EN1 EN2 LDAC RESET OPERATION XXXX 0 Reset both D/A Latches. Does not reset input latches.
1 X X X 1 No Operation
0101 1 Load Data into First Rank for D/A 2 0011 1 Load Data into First Rank for D/A 1 0110 1 Load Second Rank from First Rank, both D/As 0000 1 All Latches Transparent “X” = Don’t Care > 5ns > 50ns > 50ns (Load first rank from Data Bus: LDAC = 1) DB11–DB0 WR > 50ns WRITE CYCLE #1 EN X ±1/2LSB Reset > 50ns+10V –10V tSETTLING VOUT RESET COMMAND (Bipolar Mode) EN X, LDAC, WR = Don’t Care tSETTLING ±1/2LSB LDAC WR > 50ns > 50ns V OUT WRITE CYCLE #2 (Load second rank from first rank: ENX = 1) The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = ±15V, unless otherwise noted. Frequency (Hz) [Change in FSR]/[Change in Supply Voltage] 10 100 1k 10k 100k 1M POWER SUPPLY REJECTION vs POWER SUPPLY RIPPLE FREQUENCY (ppm of FSR/ %) 100 0.1 +VCC –VCC 12.0 9.6 7.2 4.8 2.4 –2.4 –4.8 –7.2 –9.6 –12.0 Input Current (µA) – 2 02468 Input Voltage (V) DIGITAL INPUT CURRENTvs INPUT VOLTAGE DB 0-DB11 RESET, LDAC EN X WR 0.5 –0.5 –60 –20 20 60 100 140 Temperature (°C) CHANGE OF GAIN AND OFFSET ERROR vs TEMPERATURE 0.8 0.4 –0.4 –0.8 Gain Error Bipolar Offset Unipolar Offset Bipolar/Unipolar Offset (%) (For 10V FSR; Double for 20V FSR) Δ Gain Error (%)Δ 0.5 –0.5 000 Input Code (Hexidecimal) INTEGRAL LINEARITY ERROR Linearity Error (LSB) 400 800 C00 FFF –10 –15 0 5 10 15 20 25 Time (µs) ± FULL SCALE OUTPUT SWING V (V)OUT WR VOUT WR (V) MAJOR CARRY GLITCH Time (µs) VOUT (mV) 250 200 150 100 – 2 02468 1 0 1 2 1 4 +10 WR (V)Data = 7FFH Data = 800H Data = 7FFH
Settling Time is the total time (including slew time) for the output to settle to within an error band around its final value after a change in input. Settling times are specified to ±0.01% of Full Scale Range (FSR) for two conditions: one for a FSR output change of 20V (25kΩ feedback) and one for a 1LSB change. The 1LSB change is measured at the Major Carry (7FFHEX to 800HEX , and 800HEX to 7FFHEX ), the input code transition at which worst-case settling time oc- curs. OPERATION INTERFACE LOGIC The bus interface logic of the DAC2813 consists of two independently addressable latches in two ranks for each D/A converter. The first rank consists of one 12-bit input latch which can be loaded directly from a 12- or 16-bit microprocessor/microcontroller bus. The input latch holds data temporarily before it is loaded into the second latch, the D/A latch. This double buffered organization permits simul- taneous update of all D/As. All latches are level-triggered. Data present when the con- trol signals are logic “0” will enter the latch. When the control signals return to logic “1”, the data is latched. CAUTION: DAC2813 was designed to use WR as the fast strobe. WR/ has a much faster logic path than ENX (or LDAC). Therefore, if one permanently wires WR to DCOM and uses only ENX to strobe data into the latches, the DATA TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VCC = ±15V, unless otherwise noted. DISCUSSION OF SPECIFICATIONS LINEARITY ERROR Linearity error is defined as the deviation of the analog output from a straight line drawn between the end points (digital inputs all “1s” and all “0s”). DAC2813 linearity error is ±1/2LSB max at +25oC. DIFFERENTIAL LINEARITY ERROR Differential Linearity Error (DLE) is the deviation from a 1LSB output change from one adjacent state to the next. A DLE specification of 1/2LSB means that the output step size can range from 1/2LSB to 3/2LSB when the digital input code changes from one code word to the adjacent code word If the DLE is more positive than –1LSB, the D/A is said to be monotonic. MONOTONICITY A D/A converter is monotonic if the output either increases or remains the same for increasing digital input values. DAC2813 is monotonic over their specification temperature range –40oC to +85oC. DRIFT Gain Drift is a measure of the change in the Full Scale Range (FSR) output over the specification temperature range. Gain Drift is expressed in parts per million per degree Celsius (ppm/oC). Bipolar Zero Drift is measured with a data input of 800HEX . The D/A is configured for bipolar output. Bipolar Zero Drift is expressed in parts per million of Full Scale Range per degree Celsius (ppm of FSR/oC). –10 –20 VOUT Δ Around –10V (mV) Time (µs) SETTLING TIME, +10V TO –10V 0 2 4 6 8 10 12 WR (V) 1LSB = 4.88mVVOUT WR VOUT –10 –20 –40 VOUT Δ Around +10V (mV) Time (µs) SETTLING TIME, –10V TO +10V WR (V) 02468 1 0 1 2 1 4 VOUT WR VOUT 1LSB = 4.88mV
FIGURE 4. DAC2813 Output Amplifier Range Connnections.