DAC102S085CIMM/NO.A

DAC102S085 TI | Alldatasheet

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Technical content

2.5k 100k 2.5k 100k

10 BIT DAC

Copyright © 2016, Texas Instruments Incorporated Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC102S085 SNAS364F –MAY 2006–REVISED APRIL 2016 DAC102S08510-BitMicroPowerDUALDigital-to-AnalogConverterWithRail-to-Rail Output

1 Features

1• Ensured Monotonicity

• Low Power Operation
• Rail-to-Rail Voltage Output
• Power-On Reset to 0 V
• Simultaneous Output Updating
• Wide Power Supply Range (2.7 V to 5.5 V)
• Industry's Smallest Package
• Power Down Modes
• Key Specifications – Resolution: 10 Bits – INL: ±2 LSB (Maximum) – DNL: +0.35 or –0.25 LSB (Maximum) – Settling Time: 6 µs (Maximum) – Zero Code Error: 15 mV (Maximum) – Full-Scale Error: –0.75% FS (Maximum) – Supply Power – Normal: 0.6 mW at 3 V, 1.6 mW at 5 V (Typical) – Power Down: 0.3 µW at 3 V, 0.8 µW at 5 V (Typical)

2 Applications

• Battery-Powered Instruments
• Digital Gain and Offset Adjustment
• Programmable Voltage and Current Sources
• Programmable Attenuators

3 Description

The DAC102S085 is a full-featured, general-purpose DUAL 10-bit voltage-output digital-to-analog converter (DAC) that can operate from a single 2.7-V to 5.5-V supply and consumes 0.6 mW at 3 V and 1.6 mW at 5 V. The DAC102S085 is packaged in 10-pin WSON and VSSOP packages. The 10-pin WSON package makes the DAC102S085 the smallest DUAL DAC in its class. The on-chip output amplifier allows rail-to- rail output swing and the three wire serial interface operates at clock rates up to 40 MHz over the entire supply voltage range. Competitive devices are limited to 25-MHz clock rates at supply voltages in the 2.7-V to 3.6-V range. The serial interface is compatible with standard SPI™ , QSPI, MICROWIRE and DSP interfaces. The reference for the DAC102S085 serves both channels and can vary in voltage between 1 V and VA, providing the widest possible output dynamic range. The DAC102S085 has a 16-bit input shift register that controls the outputs to be updated, the mode of operation, the power-down condition, and the binary input data. Both outputs can be updated simultaneously or individually depending on the setting of the two mode of operation bits. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DAC102S085 VSSOP (10) 3.00 mm × 3.00 mm WSON (10) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Block Diagram

SNAS364F –MAY 2006–REVISED APRIL 2016 www.ti.com Product Folder Links: DAC102S085 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Table of Contents

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (March 2013) to Revision F Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision D (March 2013) to Revision E Page

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5 Description (continued)

A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt with three different termination options. The low power consumption and small packages of the DAC102S085 make it an excellent choice for use in battery-operated equipment. The DAC102S085 is one of a family of pin compatible DACs, including the 8-bit DAC084S085 and the 12-bit DAC122S085. The DAC102S085 operates over the extended industrial temperature range of −40°C to 105°C.

6 Pin Configuration and Functions

(1) PAD is only applicable for the WSON package. Pin Functions PIN TYPE DESCRIPTION NO. NAME 1 VA Supply Power supply input. Must be decoupled to GND. 2 VOUTA Analog Output Channel A Analog Output Voltage. 3 VOUTB Analog Output Channel B Analog Output Voltage. 4, 5 NC — Not Connected 6 GND Ground Ground reference for all on-chip circuitry. 7 VREFIN Analog Input Unbuffered reference voltage shared by all channels. Must be decoupled to GND. 8 DIN Digital Input Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC.

9 SYNC Digital Input

Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 10 SCLK Digital Input Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin. 11 PAD(1) Ground Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package self-alignment during reflow.

SNAS364F –MAY 2006–REVISED APRIL 2016 www.ti.com Product Folder Links: DAC102S085 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. (3) All voltages are measured with respect to GND = 0 V, unless otherwise specified. (4) When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin should be limited to 10 mA. The 20-mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. (5) The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (RθJA), and the ambient temperature (TA), and can be calculated using the formula PDmax = (TJmax - TA) / RθJA.

7 Specifications

7.1 Absolute Maximum Ratings

See (1)(2)(3) MIN MAX UNIT Supply voltage VA 6.5 V Voltage DIN, SCLK, SYNC, VREFIN −0.3 6.5 V Input current(4) 10 mA Package input current(4) 20 mA Power consumption at TA = 25°C See(5) Junction temperature, TJ 150 °C Storage temperature, Tstg −65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250 (1) All voltages are measured with respect to GND = 0 V, unless otherwise specified. (2) The inputs are protected. Input voltage magnitudes up to 5.5 V, regardless of VA, do not cause errors in the conversion result. For example, if VA is 3 V, the digital input pins can be driven with a 5-V logic device.

7.3 Recommended Operating Conditions

See (1) MIN MAX UNIT Operating temperature –40 105 °C VA Supply voltage 2.7 5.5 V VREFIN Reference voltage 1 VA V Digital input voltage(2) 0 5.5 V Output load 0 1500 pF SCLK frequency 40 MHz (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.4 Thermal Information

THERMAL METRIC(1) DAC102S085 UNITDGS (VSSOP) DSC (WSON)

10 PINS 10 PINS

RθJA Junction-to-ambient thermal resistance 240 250 °C/W

www.ti.com SNAS364F –MAY 2006–REVISED APRIL 2016 Product Folder Links: DAC102S085 Submit Documentation FeedbackCopyright © 2006–2016, Texas Instruments Incorporated (1) To ensure accuracy, it is required that VA and VREFIN be well bypassed.

7.5 Electrical Characteristics

The following specifications apply for VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011. Minimum and Maximum limits apply for TA = –40°C to 105°C, Typical values apply for TA = 25°C, unless otherwise specified. Test limist are specified to AOQL (Average Outgoing Quality Level).(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE Resolution 10 Bits Monotonicity 10 Bits INL Integral non-linearity ±0.7 ±2 LSB DNL Differential non-linearity VA = 2.7 V to 5.5 V TA = 25°C –0.03 0.08 LSB TA = –40°C to 105°C –0.25 0.35 ZE Zero code error IOUT = 0 5 15 mV FSE Full-scale error IOUT = 0 −0.1 −0.75 %FSR GE Gain error All ones loaded to DAC register −0.2 −1 %FSR ZCED Zero code error drift −20 µV/°C TC GE Gain error tempco VA = 3 V −0.7 ppm/°C VA = 5 V −1 OUTPUT CHARACTERISTICS Output voltage range 0 VREFIN V IOZ High-impedance output leakage current ±1 µA ZCO Zero code output VA = 3 V, IOUT = 200 µA 1.3 mV VA = 3 V, IOUT = 1 mA 6 VA = 5 V, IOUT = 200 µA 7 VA = 5 V, IOUT = 1 mA 10 FSO Full scale output VA = 3 V, IOUT = 200 µA 2.984 V VA = 3 V, IOUT = 1 mA 2.934 VA = 5 V, IOUT = 200 µA 4.989 VA = 5 V, IOUT = 1 mA 4.958 IOS Output short-circuit current (source) VA = 3 V, VOUT = 0 V, Input Code = 3FFh –56 mA VA = 5 V, VOUT = 0 V, Input Code = 3FFh –69 IOS Output short-circuit current (sink) VA = 3 V, VOUT = 3 V, Input Code = 000h 52 mA VA = 5 V, VOUT = 5 V, Input Code = 000h 75 IO Continuous output current Available on each DAC output 11 mA CL Maximum load capacitance RL = ∞ 1500 pF RL = 2 kΩ 1500 ZOUT DC output impedance 7.5 Ω REFERENCE INPUT CHARACTERISTICS VREFIN Input range minimum 0.2 1 V Input range maximum VA ZIN Input impedance 60 kΩ LOGIC INPUT CHARACTERISTICS IIN Input current ±1 µA VIL Input low voltage VA = 3 V 0.9 0.6 V VA = 5 V 1.5 0.8 VIH Input high voltage VA = 3 V 1.4 2.1 V VA = 5 V 2.1 2.4 CIN Input capacitance 3 pF POWER REQUIREMENTS IN Normal supply current (output unloaded) fSCLK = 30 MHz VA = 2.7 V to 3.6 V 210 270 µA VA = 4.5 V to 5.5 V 320 410 fSCLK = 0 MHz VA = 2.7 V to 3.6 V 190 VA = 4.5 V to 5.5 V 290

SNAS364F –MAY 2006–REVISED APRIL 2016 www.ti.com Product Folder Links: DAC102S085 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated Electrical Characteristics (continued) The following specifications apply for VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011. Minimum and Maximum limits apply for TA = –40°C to 105°C, Typical values apply for TA = 25°C, unless otherwise specified. Test limist are specified to AOQL (Average Outgoing Quality Level).(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IPD Power-down supply current (output unloaded, SYNC = DIN = 0 V after PD mode loaded) All PD Modes VA = 2.7 V to 3.6 V 0.1 1 µA VA = 4.5 V to 5.5 V 0.15 1 PN Normal supply power (output unloaded) fSCLK = 30 MHz VA = 2.7 V to 3.6 V 0.6 1 mW VA = 4.5 V to 5.5 V 1.6 2.3 fSCLK = 0 MHz VA = 2.7 V to 3.6 V 0.6 VA = 4.5 V to 5.5 V 1.5 PPD Power down supply current (output unloaded, SYNC = DIN = 0 V after PD mode loaded) All PD Modes VA = 2.7 V to 3.6 V 0.3 3.6 µW VA = 4.5 V to 5.5 V 0.8 5.5

7.6 AC and Timing Requirements

Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011. Minimum and Maximum limits apply for TA = –40°C to 105°C, Typical values apply for TA = 25°C, unless otherwise specified. Test limist are specified to AOQL (Average Outgoing Quality Level). MIN TYP MAX UNIT fSCLK SCLK frequency 40 30 MHz ts Output voltage settling time 100h to 300h code change RL = 2 kΩ, CL = 200 pF 4.5 6 µs SR Output slew rate 1 V/µs Glitch impulse Code change from 200h to 1FFh 12 nV-sec Digital feedthrough 0.5 nV-sec Digital crosstalk 1 nV-sec DAC-to-DAC crosstalk 3 nV-sec Multiplying bandwidth VREFIN = 2.5 V ± 0.1 VPP 160 kHz Total harmonic distortion VREFIN = 2.5 V ± 1.0 VPP input frequency = 10 kHz 70 dB tWU Wake-up time VA = 3 V 6 µs VA = 5 V 39 1/fSCLK SCLK cycle time 33 25 ns tCH SCLK high time 10 7 ns tCL SCLK low time 10 7 ns tSS SYNC setup time prior to SCLK falling edge 10 4 ns tDS Data setup time prior to SCLK falling edge 3.5 1.5 ns tDH Data hold time after SCLK falling edge 3.5 1.5 ns tCFSR SCLK fall prior to rise of SYNC 3 0 ns tSYNC SYNC high time 10 6 ns

7.7 Typical Characteristics

Figure 3. INL at VA = 3 V Figure 4. INL at VA = 5 V Figure 5. DNL at VA = 3 V Figure 6. DNL at VA = 5 V Figure 7. INL and DNL vs VREFIN at VA = 3 V Figure 8. INL and DNL vs VREFIN at VA = 5 V

2.5k 100k 2.5k 100k Copyright © 2016, Texas Instruments Incorporated DAC102S085 www.ti.com SNAS364F –MAY 2006–REVISED APRIL 2016 Product Folder Links: DAC102S085 Submit Documentation FeedbackCopyright © 2006–2016, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The DAC102S085 is a full-featured, general-purpose DUAL 10-bit voltage-output digital-to-analog converter The on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock rates up to 40 MHz over the entire supply voltage range. The serial interface is compatible with standard SPI, QSPI, MICROWIRE, and DSP interfaces. The reference for the DAC102S085 serves both channels and can vary in voltage between 1 V and VA, providing the widest possible output dynamic range. The DAC102S085 has a 16-bit input shift register that controls the outputs to be updated, the mode of operation, the power-down condition, and the binary input data. Both outputs can be updated simultaneously or individually depending on the setting of the two mode-of-operation bits. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a micro-watt with three different termination options.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 DAC Section

The DAC102S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor strings that are followed by an output buffer. The reference voltage is externally applied at VREFIN and is shared by both DACs.

binary with an ideal output voltage calculated by Equation 1.

• D is the decimal equivalent of the binary code that is loaded into the DAC register. (D can take on any value between 0 and 1023. This configuration ensures that the DAC is monotonic.) (1)

Figure 31. DAC Resistor String

8.3.2 Output Amplifiers

amplifier are described in Electrical Characteristics. code and full-scale outputs for given load currents are available in Electrical Characteristics.

8.3.3 Reference Voltage

8.3.4 Power-On Reset

valid write sequence is made to the DAC.

8.4 Device Functional Modes

8.4.1 Power-Down Modes

2.5 kΩ or 100 kΩ to ground respectively (see Table 1). Table 1. Power-Down Modes Time) is typically tWU µs as stated in AC and Timing Requirements.

8.5 Programming

8.5.1 Serial Interface

at clock rates up to 40 MHz. See AC and Timing Requirements for information on a write sequence. sequences to minimize power consumption.

8.5.2 Input Shift Register

updating their outputs, or powering down both outputs). The final twelve bits of the shift register are the data bits. the DAC register on the sixteenth falling edge of SCLK. See Figure 2.

0 0 Write to specified register but do not update outputs. 0 1 Write to specified register and update outputs. 1 0 Write to all registers and update outputs. Figure 32. Input Register Contents there is no change in the mode of operation or in the DAC output voltages.

8.5.3 DSP and Microprocessor Interfacing

to hasten the design process.

8.5.3.1 ADSP-2101 and ADSP-2103 Interfacing

Length. Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled. Figure 33. ADSP-2101 and ADSP-2103 Interface Figure 34. 80C51 and 80L51 Interface

line of the DAC102S085 is driven from a port line (PC7 in the figure), similar to the 80C51 and 80L51. second byte of data to the DAC, after which PC7 should be raised to end the write sequence. Figure 35. 68HC11 Interface

8.5.3.4 Microwire Interface

driving the SCLK of the DAC102S085. Figure 36. Microwire Interface

0.1 PF+

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Bipolar Operation

output may be obtained with the circuit shown in Figure 37. This circuit provides an output voltage range of ±5 V. A rail-to-rail amplifier should be used if the amplifier supplies are limited to ±5 V. Figure 37. Bipolar Operation The output voltage of this circuit for any code is found using Equation 2.

• D is the input code in decimal form
• VA = 5 V
• R1 = R2 (3) A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2.

Table 2. Some Rail-to-Rail Amplifiers

9.2 Typical Application

Figure 38. Driving an ADC Reference

9.2.1 Design Requirements

9.2.2 Detailed Design Procedure

The output of the sensor is amplified by a fixed gain amplifier stage with a differential gain of 1 + 2 × (RF / RI). voltage from 1 V to 5 V, providing the widest dynamic range possible. cause the output of the amplifiers to clip.

9.2.3 Application Curve

Figure 39. I/O Transfer Characteristic

10 Power Supply Recommendations

10.1 Using References as Power Supplies

10.1.1 LM4130

reduce output noise. The LM4130 comes in a space-saving 5-pin SOT-23 package.

Figure 40. The LM4130 as a Power Supply

10.1.2 LM4050

DAC102S085. It is available in 4.096-V and 5-V versions and comes in a space-saving 3-pin SOT-23 package. Figure 41. The LM4050 as a Power Supply DAC102S085 draws its maximum current. Equation 4 and Equation 5 summarize these conditions.

• VZ(min) and VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over temperature

• IZ(max) is the maximum allowable current through the LM4050
• IZ(min) is the minimum current required by the LM4050 for proper regulation
• IDAC(max) is the maximum DAC102S085 supply current (5)

10.1.3 LP3985

LP3985 comes in a space-saving 5-pin SOT-23 and 5-bump DSBGA packages. Figure 42. Using the LP3985 Regulator the capacitor specification is required to ensure correct device operation.

10.1.4 LP2980

grade. It is available in 3-V, 3.3-V and 5-V versions, among others. Figure 43. Using the LP2980 Regulator

11 Layout

11.1 Layout Guidelines

separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes. single ground plane design uses a fencing technique to prevent the mixing of analog and digital ground current. continuous return path below their traces. should only be used for analog circuits. board. The clock and data lines should have controlled impedances.

11.2 Layout Example

Figure 44. DAC102S085 Layout Diagram

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Device Nomenclature

12.1.1.1 Specification Definitions

DIFFERENTIAL NON-LINEARITY (DNL) The measure of the maximum deviation from the ideal step size of 1 LSB, which is VREF / 1024 = VA / 1024. DAC-to-DAC CROSSTALK The glitch impulse transferred to a DAC output in response to a full-scale change in the output of another DAC. DIGITAL CROSSTALK The glitch impulse transferred to a DAC output at mid-scale in response to a full-scale change in the input register of another DAC. DIGITAL FEEDTHROUGH A measure of the energy injected into the analog output of the DAC from the digital inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus. FULL-SCALE ERROR The difference between the actual output voltage with a full scale code (3FFh) loaded into the DAC and the value of VA × 1023 / 1024. GAIN ERROR The deviation from the ideal slope of the transfer function. It can be calculated from Zero and Full- Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error. GLITCH IMPULSE The energy injected into the analog output when the input code to the DAC register changes. It is specified as the area of the glitch in nanovolt-seconds. INTEGRAL NON-LINEARITY (INL) A measure of the deviation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point method is used. INL for this product is specified over a limited range, per the Electrical Tables. LEAST SIGNIFICANT BIT (LSB) The bit that has the smallest value or weight of all bits in a word. LSB = VREF / 2n where

• VREF is the supply voltage for this product
• n is the DAC resolution in bits, which is 10 for the DAC102S085 (6) MAXIMUM LOAD CAPACITANCE The maximum capacitance that can be driven by the DAC with output stability maintained. MONOTONICITY The condition of being monotonic, where the DAC has an output that never decreases when the input code increases. MOST SIGNIFICANT BIT (MSB) The bit that has the largest value or weight of all bits in a word. Its value is 1/2 of VA. MULTIPLYING BANDWIDTH The frequency at which the output amplitude falls 3 dB below the input sine wave on VREFIN with a full-scale code loaded into the DAC. POWER EFFICIENCY The ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output currents is the power consumed by the device without a load. SETTLING TIME The time for the output to settle to within 1/2 LSB of the final value after the input code is updated. TOTAL HARMONIC DISTORTION (THD) The measure of the harmonics present at the output of the DACs with an ideal sine wave applied to VREFIN. THD is measured in dB.

www.ti.com SNAS364F –MAY 2006–REVISED APRIL 2016 Product Folder Links: DAC102S085 Submit Documentation FeedbackCopyright © 2006–2016, Texas Instruments Incorporated Device Support (continued) WAKE-UP TIME The time for the output to exit power-down mode. This is the time from the falling edge of the 16th SCLK pulse to when the output voltage deviates from the power-down voltage of 0 V. ZERO CODE ERROR The output error, or voltage, present at the DAC output after a code of 000h has been entered.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation, see the following: LP2980-N Micropower 50 mA Ultra Low-Dropout Regulator In SOT-23 Package (SNOS733)

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments. SPI is a trademark of Motorola, Inc.. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DAC102S085CIMM/NO.A Active Production VSSOP (DGS) | 10 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 105 X74C DAC102S085CIMM/NOPB Active Production VSSOP (DGS) | 10 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 105 X74C DAC102S085CIMMX/NO.A Active Production VSSOP (DGS) | 10 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 105 X74C DAC102S085CIMMX/NOPB Active Production VSSOP (DGS) | 10 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 105 X74C DAC102S085CISD/NO.A Active Production WSON (DSC) | 10 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 105 X75C DAC102S085CISD/NOPB Active Production WSON (DSC) | 10 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 105 X75C DAC102S085CISDX/NO.A Active Production WSON (DSC) | 10 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 105 X75C DAC102S085CISDX/NOPB Active Production WSON (DSC) | 10 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 105 X75C (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 23-May-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant DAC102S085CIMMX/ NOPB DAC102S085CISDX/ NOPB Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC102S085CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 DAC102S085CIMMX/ NOPB VSSOP DGS 10 3500 367.0 367.0 35.0 DAC102S085CISD/NOPB WSON DSC 10 1000 210.0 185.0 35.0 DAC102S085CISDX/ NOPB WSON DSC 10 4500 367.0 367.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C TYP5.05 4.75

1.1 MAX

8X 0.5 10X 0.27 0.17 0.15 0.05 TYP0.23 0.13 0 - 8 0.25 GAGE PLANE 0.7 0.4 A NOTE 3 3.1 2.9 B NOTE 4 3.1 2.9 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187, variation BA.

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 3.200

www.ti.com EXAMPLE BOARD LAYOUT (4.4)

0.05 MAX

0.05 MIN

10X (1.45) 10X (0.3) 8X (0.5) (R ) TYP 0.05 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 5 6 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (4.4) 8X (0.5) 10X (0.3) 10X (1.45) (R ) TYP0.05 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 5 6 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

www.ti.com SDA10A (Rev A)

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