DAC102S085

DAC102S085 NSC | Alldatasheet

Document overview

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Technical content

Features

n Rail-to-Rail Voltage Output n Power-on Reset to 0V n Simultaneous Output Updating n Wide power supply range (+2.7V to +5.5V) n Power Down Modes Key Specifications n Resolution 10 bits n INL ±2 LSB (max) n DNL +0.35 / −0.25 LSB (max) n Settling Time 6 µs (max) n Zero Code Error +15 mV (max) n Full-Scale Error −0.75 %FS (max) n Supply Current — Normal 270 µA (3.6V) / 410 µA (5.5V) max — Pwr Down 20 nA (3.6V) / 30 nA (5.5V) typ

Applications

n Battery-Powered Instruments n Digital Gain and Offset Adjustment n Programmable Voltage & Current Sources n Programmable Attenuators Pin Configuration 20195502 SPI™ is a trademark of Motorola, Inc. June 2006 DAC102S085 10-Bit Micro Power DUAL Digital-to-Analog Converter with Rail-to-Rail Output © 2006 National Semiconductor Corporation DS201955 www.national.com

Ordering Information

Order Numbers Temperature Range Package Top Mark DAC102S085CIMM −40˚C ≤ TA ≤ +105˚C MSOP X74C DAC102S085CIMMX −40˚C ≤ TA ≤ +105˚C MSOP Tape-and-Reel X74C DAC102S085EVAL Evaluation Board (MSOP) Block Diagram 20195503 DAC102S085 www.national.com 2

Pin No. Symbol Type Description 1V A Supply Power supply input. Must be decoupled to GND. 2V OUTA Analog Output Channel A Analog Output Voltage. 3V OUTB Analog Output Channel B Analog Output Voltage.

4 NC Not Connected

5 NC Not Connected

6 GND Ground Ground reference for all on-chip circuitry. REFIN Analog Input Unbuffered reference voltage shared by all channels. Must be decoupled to GND. 8D IN Digital Input Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC.

9 SYNC Digital Input

Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. 10 SCLK Digital Input Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin. DAC102S085 www.national.com3

(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, V A 6.5V Voltage on any Input Pin −0.3V to 6.5V Input Current at Any Pin (Note 3) 10 mA Package Input Current (Note 3) 20 mA Power Consumption at T A = 25˚C See (Note 4) ESD Susceptibility (Note 5) Human Body Model Machine Model 2500V 250V Soldering Temperature, Infrared,

10 Seconds (Note 6) 235˚C

Storage Temperature −65˚C to +150˚C Operating Ratings (Notes 1, 2) Operating Temperature Range −40˚C ≤ TA ≤ +105˚C Supply Voltage, VA +2.7V to 5.5V Reference Voltage, VREFIN +1.0V to VA Digital Input Voltage (Note 7) 0.0V to 5.5V Output Load 0 to 1500 pF SCLK Frequency Up to 40 MHz Package Thermal Resistances Package θJA 10-Lead MSOP 240˚C/W

Electrical Characteristics

Values shown in this table are design targets and are subject to change before product release. The following specifica- tions apply for V A = +2.7V to +5.5V, V REFIN =V A,C L = 200 pF to GND, f SCLK = 30 MHz, input code range 12 to 1011. Bold- face limits apply for T MIN ≤ TA ≤ TMAX and all other limits are at T A = 25˚C, unless otherwise specified. Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) STATIC PERFORMANCE Resolution 10 Bits (min) Monotonicity 10 Bits (min) INL Integral Non-Linearity ±0.7 ±2 LSB (max) DNL Differential Non-Linearity V A = 2.7V to 5.5V +0.08 +0.35 LSB (max) −0.03 −0.25 LSB (min) ZE Zero Code Error I OUT =0 + 5 +15 mV (max) FSE Full-Scale Error I OUT = 0 −0.1 −0.75 %FSR (max) GE Gain Error All ones Loaded to DAC register −0.2 −1.0 %FSR ZCED Zero Code Error Drift −20 µV/˚C TC GE Gain Error Tempco VA = 3V −0.7 ppm/˚C VA = 5V −1.0 ppm/˚C OUTPUT CHARACTERISTICS Output Voltage Range (Note 10) 0 VREFIN V (min) V (max) IOZ High-Impedance Output Leakage Current (Note 10) ±1 µA (max) ZCO Zero Code Output VA = 3V, IOUT = 200 µA 1.3 mV VA = 3V, IOUT = 1 mA 6.0 mV VA = 5V, IOUT = 200 µA 7.0 mV VA = 5V, IOUT = 1 mA 10.0 mV FSO Full Scale Output VA = 3V, IOUT = 200 µA 2.984 V VA = 3V, IOUT = 1 mA 2.934 V VA = 5V, IOUT = 200 µA 4.989 V VA = 5V, IOUT = 1 mA 4.958 V DAC102S085 www.national.com 4

Electrical Characteristics (Continued) Values shown in this table are design targets and are subject to change before product release. The following specifica- tions apply for V A = +2.7V to +5.5V, V REFIN =V A,C L = 200 pF to GND, f SCLK = 30 MHz, input code range 12 to 1011. Bold- face limits apply for T MIN ≤ TA ≤ TMAX and all other limits are at T A = 25˚C, unless otherwise specified. Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) IOS Output Short Circuit Current VA = 3V, VOUT = 0V, Input Code = 3FFh -56 mA VA = 5V, VOUT = 0V, Input Code = 3FFh -69 mA VA = 3V, VOUT = 5V, Input Code = 000h 52 mA VA = 5V, VOUT = 5V, Input Code = 000h 75 mA IO Continuous Output Current (Note 10) Available on each DAC output 11 mA (max) CL Maximum Load Capacitance RL = ∞ 1500 pF RL =2 kΩ 1500 pF ZOUT DC Output Impedance 7.5 Ω REFERENCE INPUT CHARACTERISTICS VREFIN Input Range Minimum 0.2 1.0 V (min) Input Range Maximum VA V (max) Input Impedance 60 k Ω LOGIC INPUT CHARACTERISTICS IIN Input Current (Note 10) ±1 µA (max) VIL Input Low Voltage (Note 10) VA = 3V 0.9 0.6 V (max) VA = 5V 1.5 0.8 V (max) VIH Input High Voltage (Note 10) VA = 3V 1.4 2.1 V (min) VA = 5V 2.1 2.4 V (min) CIN Input Capacitance (Note 10) 3 pF (max) POWER REQUIREMENTS VA Supply Voltage Minimum 2.7 V (min) Supply Voltage Maximum 5.5 V (max) IN Normal Supply Current (output unloaded) fSCLK =3 0M H z VA = 2.7V to 3.6V 210 270 µA (max) VA = 4.5V to 5.5V 320 410 µA (max) fSCLK =0 VA = 2.7V to 3.6V 190 µA (max) VA = 4.5V to 5.5V 290 µA (max) IPD Power Down Supply Current (output unloaded, SYNC = 0V after PD mode loaded) All PD Modes, f SCLK =3 0M H z VA = 2.7V to 3.6V 0.02 µA (max) VA = 4.5V to 5.5V 0.03 µA (max) All PD Modes, fSCLK = 0 (Note 10) VA = 2.7V to 3.6V 0.015 1.0 µA (max) VA = 4.5V to 5.5V 0.025 1.0 µA (max) DAC102S085 www.national.com5

A.C. and Timing Characteristics Values shown in this table are design targets and are subject to change before product release. The following specifica- tions apply for V A = +2.7V to +5.5V, V REFIN =V A,R L =2 kΩ to GND, CL = 200 pF to GND, f SCLK = 30 MHz, input code range 12 to 1011. Boldface limits apply for T MIN ≤ TA ≤ TMAX and all other limits are at T A = 25˚C, unless otherwise specified. Symbol Parameter Conductions Typical (Note 9) Limits (Note 9) Units (Limits) fSCLK SCLK Frequency 40 30 MHz (max) ts Output Voltage Settling Time (Note 10) 100h to 300h code change 4.5 6 µs (max) SR Output Slew Rate 1 V/µs Glitch Impulse Code change from 200h to 1FFh 12 nV-sec Digital Feedthrough 0.5 nV-sec Digital Crosstalk 1 nV-sec DAC-to-DAC Crosstalk 3 nV-sec Multiplying Bandwidth V REFIN = 2.5V ± 0.1Vpp 160 kHz Total Harmonic Distortion VREFIN = 2.5V ± 1.0Vpp input frequency = 10kHz 70 dB tWU Wake-Up Time VA = 3V 0.8 µsec VA = 5V 0.5 µsec 1/fSCLK SCLK Cycle Time 25 33 ns (min) tCH SCLK High time 7 10 ns (min) tCL SCLK Low Time 7 10 ns (min) tSS SYNC Set-up Time prior to SCLK Falling Edge 4 10 ns (min) tDS Data Set-Up Time prior to SCLK Falling Edge 1.5 3.5 ns (min) tDH Data Hold Time after SCLK Falling Edge 1.5 3.5 ns (min) tCFSR SCLK fall prior to rise of SYNC 0 3 ns (min) tSYNC SYNC High Time 6 10 ns (min) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characterist ics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the lis ted test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified Note 3: When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. Note 4: The absolute maximum junction temperature (T Jmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by T Jmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula P DMAX = (TJmax − TA)/ θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven be yond the operating ratings, or the power supply polarity is reversed). Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k Ω resistor. Machine model is 220 pF discharged through ZERO Ohms. Note 6: See the section entitled "Surface Mount" found in any post 1986 National Semiconductor Linear Data Book for methods of soldering surface mount devices. Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of VA, will not cause errors in the conversion result. For example, if VA is 3V, the digital input pins can be driven with a 5V logic device. 20195504 Note 8: To guarantee accuracy, it is required that V A and VREFIN be well bypassed. Note 9: Typical figures are at T J = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 10: This parameter is guaranteed by design and/or characterization and is not tested in production. DAC102S085 www.national.com 6

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB, which is V REF /1 0 2 4=V A / 1024. DAC-to-DAC CROSSTALK is the glitch impulse transferred to a DAC output in response to a full-scale change in the output of another DAC. DIGITAL CROSSTALK is the glitch impulse transferred to a DAC output at mid-scale in response to a full-scale change in the input register of another DAC. DIGITAL FEEDTHROUGH is a measure of the energy in- jected into the analog output of the DAC from the digital inputs when the DAC outputs are not updated. It is mea- sured with a full-scale code change on the data bus. FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (3FFh) loaded into the DAC and the value of V A x 1023 / 1024. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and Full- Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error. GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register changes. It is specified as the area of the glitch in nanovolt-seconds. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point method is used. INL for this product is specified over a limited range, per the Electrical Tables. LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is L S B=V REF /2 n where VREF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 10 for the DAC102S085. MAXIMUM LOAD CAPACITANCE is the maximum capaci- tance that can be driven by the DAC with output stability maintained. MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the input code increases. MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of V MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3dB below the input sine wave on V REFIN with a full-scale code loaded into the DAC. POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output currents is the power consumed by the device without a load. SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is updated. TOTAL HARMONIC DISTORTION (THD) is the measure of the harmonics present at the output of the DACs with an ideal sine wave applied to V REFIN. THD is measured in dB. WAKE-UP TIME is the time for the output to exit power- down mode. This is the time from the falling edge of the 16th SCLK pulse to when the output voltage deviates from the power-down voltage of 0V. ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been entered. DAC102S085 www.national.com7

Typical Performance Characteristics VREF =V A,f SCLK = 30 MHz, T A = 25C, Input Code Range 12 to 1011, unless otherwise stated INL at VA = 3.0V INL at V A = 5.0V 20195552 20195553 DNL at VA = 3.0V DNL at V A = 5.0V 20195554 20195555 INL/DNL vs VREFIN at VA = 3.0V INL/DNL vs V REFIN at VA = 5.0V 20195556 20195557 DAC102S085 www.national.com9

Typical Performance Characteristics VREF =V A,f SCLK = 30 MHz, T A = 25C, Input Code Range 12 to 1011, unless otherwise stated (Continued) INL/DNL vs fSCLK at VA = 2.7V INL/DNL vs V A 20195550 20195522 INL/DNL vs Clock Duty Cycle at V A = 3.0V INL/DNL vs Clock Duty Cycle at V A = 5.0V 20195524 20195525 INL/DNL vs Temperature at V A = 3.0V INL/DNL vs Temperature at V A = 5.0V 20195526 20195527 DAC102S085 www.national.com 10

Typical Performance Characteristics VREF =V A,f SCLK = 30 MHz, T A = 25C, Input Code Range 12 to 1011, unless otherwise stated (Continued) Zero Code Error vs. V A Zero Code Error vs. V REFIN 20195530 20195531 Zero Code Error vs. f SCLK Zero Code Error vs. Clock Duty Cycle 20195534 20195535 Zero Code Error vs. Temperature Full-Scale Error vs. V A 20195536 20195537 DAC102S085 www.national.com11

Typical Performance Characteristics VREF =V A,f SCLK = 30 MHz, T A = 25C, Input Code Range 12 to 1011, unless otherwise stated (Continued) Full-Scale Error vs. V REFIN Full-Scale Error vs. f SCLK 20195532 20195533 Full-Scale Error vs. Clock Duty Cycle Full-Scale Error vs. Temperature 20195538 20195539 Supply Current vs. V A Supply Current vs. Temperature 20195544 20195545 DAC102S085 www.national.com 12

Typical Performance Characteristics VREF =V A,f SCLK = 30 MHz, T A = 25C, Input Code Range 12 to 1011, unless otherwise stated (Continued) 5V Glitch Response Power-On Reset 20195546 20195547 DAC102S085 www.national.com13

1.0 Functional Description

1.1 DAC SECTION

REFIN and is shared by both DACs. For simplicity, a single resistor string is shown in Figure 3.

1.2 OUTPUT AMPLIFIERS

Electrical Characterisics Table.

1.3 RERENCE VOLTAGE

A, providing the widest possible output dynamic range.

1.4 SERIAL INTERFACE

A write sequence begins by bringing the SYNC line low. the 16-bit serial input register on the falling edges of SCLK. write sequence is initiated with a falling edge of SYNC. quences to minimize power consumption.

1.5 INPUT SHIFT REGISTER

in the mode of operation or in the DAC output voltages. FIGURE 3. DAC Resistor String FIGURE 4. Input Register Contents

1.0 Functional Description (Continued)

1.6 POWER-ON RESET

1.7 POWER-DOWN MODES

set in power-down mode by setting OP1 and OP0 to 11. causes the outputs to be tri-stated (a high impedance state). TABLE 1. Power-Down Modes

2.0 Applications Information

2.1 USING REFERENCES AS POWER SUPPLIES

2.1.1 LM4130

good choice as a reference source for the DAC102S085. comes in a space-saving 5-pin SOT23.

2.1.2 LM4050

comes in a space-saving 3-pin SOT23. FIGURE 5. The LM4130 as a power supply FIGURE 6. The LM4050 as a power supply

mum DAC102S085 supply current.

2.1.3 LP3985

5-pin SOT23 and 5-bump micro SMD packages.

2.1.4 LP2980

is available in 3.0V, 3.3V and 5V versions, among others.

2.2 BIPOLAR OPERATION

TABLE 2. Some Rail-to-Rail Amplifiers FIGURE 7. Using the LP3985 regulator FIGURE 8. Using the LP2980 regulator FIGURE 9. Bipolar Operation

2.3 DSP/MICROPROCESSOR INTERFACING

2.3.1 ADSP-2101/ADSP2103 Interfacing

SPORT mode has been enabled. is taken low when data is transmitted to the DAC102S085. first while the DAC102S085 requires data with the MSB first. figure), similar to the 80C51/80L51.

2.3.4 Microwire Interface

2.4 LAYOUT, GROUNDING, AND BYPASSING

these planes should be located in the same board layer. ways have a continuous return path below their traces. clock and data lines should have controlled impedances. FIGURE 10. ADSP-2101/2103 Interface FIGURE 11. 80C51/80L51 Interface FIGURE 12. 68HC11 Interface FIGURE 13. Microwire Interface

Physical Dimensions inches (millimeters) unless otherwise noted 10-Lead MSOP Order Numbers DAC102S085CIMM National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at: www.national.com/quality/green. Lead free products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com DAC102S085 10-Bit Micro Power DUAL Digital-to-Analog Converter with Rail-to-Rail Output