DAC1021

DAC1020 NSC | Alldatasheet

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Features

Y Linearity specified with zero and full-scale adjust only Y Non-linearity guaranteed over temperature Y Integrated thin film on CMOS structure Y 10-bit or 12-bit resolution Y Low power dissipation 10 mW @15V typ Y Accepts variable or fixed reference b25VsVREFs25V Y 4-quadrant multiplying capability Y Interfaces directly with DTL, TTL and CMOS Y Fast settling timeÐ500 ns typ Y Low feedthrough errorÐ (/2 LSB @100 kHz typ Equivalent Circuit Note. Switches shown in digital high state TL/H/5689–1 10-BIT D/A CONVERTERSOrdering Information Temperature Range 0 §Ct o7 0 §C b40§Ct o8 5 §C Non- 0.05% DAC1020LCN AD7520LN,AD7530LN DAC1020LCV DAC1020LIV Linearity 0.10% DAC1021LCN AD7520KN,AD7530KN 0.20% DAC1022LCN AD7520JN,AD7530JN Package Outline N16A V20A 12-BIT D/A CONVERTERS Temperature Range 0 §Ct o7 0 §C b40§Ct o a85§C Linearity Non- 0.05% DAC1220LCN AD7521LN,AD7531LN DAC1220LCJ AD7521LD,AD7531LD 0.20% DAC1222LCN AD7521JN,AD7531JN DAC1222LCJ AD7521JD,AD7531JD Package Outline N18A J18A Note. Devices may be ordered by either part number.

Absolute Maximum Ratings (Note 5) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. V a to Gnd 17V VREF to Gnd g25V Digital Input Voltage Range V a to Gnd DC Voltage at Pin 1 or Pin 2 (Note 3) b100 mV to V a Storage Temperature Range b65§Ct o a150§C Lead Temperature (Soldering, 10 sec.) Dual-In-Line Package (plastic) 260 §C Dual-In-Line Package (ceramic) 300 §C ESD Susceptibility (Note 4) 800V Operating Ratings Min Max Units Temperature (T A) DAC1020LIV, DAC1220LCJ, DAC1222LCJ b40 a85 §C DAC1020LCN, DAC1020LCV, DAC1021LCN 0 a70 §C DAC1022LCN, DAC1220LCN 0 a70 §C DAC1222LCN 0 a70 §C Electrical Characteristics (Va e 15V, V REF e 10.000V, T A e 25§C unless otherwise specified) DAC1020, DAC1021, DAC1220, DAC1222Parameter Conditions DAC1022 Units Min Typ Max Min Typ Max Resolution 10 12 Bits Linearity Error T MINkTAkTMAX, b10VkVREFka10V, (Note 1) End Point Adjustment Only (See Linearity Error in Definition of Terms) 10-Bit Parts DAC1020, DAC1220 0.05 0.05 % FSR 9-Bit Parts DAC1021 0.10 0.10 % FSR 8-Bit Parts DAC1022, DAC1222 0.20 0.20 % FSR Linearity Error Tempco b10VsVREFsa10V, 0.0002 0.0002 % FS/ §C (Notes 1 and 2) Full-Scale Error b10VsVREFsa10V, 0.3 1.0 0.3 1.0 % FS (Notes 1 and 2) Full-Scale Error Tempco T MINkTAkTMAX, 0.001 0.001 % FS/ §C (Note 2) Output Leakage Current T MINsTAsTMAX IOUT 1 All Digital Inputs Low 200 200 nA IOUT 2 All Digital Inputs High 200 200 nA Power Supply Sensitivity All Digital Inputs High, 0.005 0.005 % FS/V 14VsVas16V, (Note 2), (Figure 2) VREF Input Resistance 10 15 20 10 15 20 k X Full-Scale Current Settling R Le 100X from 0 to 99. 95% Time FS All Digital Inputs Switched 500 500 ns Simultaneously VREF Feedthrough All Digital Inputs Low, 10 10 mVp-p VREFe20 Vp-p @ 100 kHz J Package (Note 4) 6 9 6 9 mVp-p N Package 2 5 2 5 mVp-p Output Capacitance IOUT 1 All Digital Inputs Low 40 40 pF All Digital Inputs High 200 200 pF IOUT 2 All Digital Inputs Low 200 200 pF All Digital Inputs High 40 40 pF http:/ /www.national.com 2

using the DAC1220 and 2 additional digital inputs. strongly recommended for the DAC1020 applications. is high, and R OUT approaches infinity if all inputs are low. OS has been adjusted, remove the 1 k X.

1024 VREF

FIGURE 3. Basic Connection: Unipolar or 2-Quadrant Multiplying

0000000001 V REF c 1022/1024

0111111111 V REF c 2/1024

FIGURE 7. Bipolar 4-Quadrant Multiplying Configuration its output value to withi na1m V from ground potential. mentioned in the previous application. with the one previously discussed. FIGURE 8. Bipolar Configuration with a Single Op Amp FIGURE 9. Bipolar Configuration with

FIGURE 12. Precision Low Frequency Sine Wave Oscillator Using Sine Look-Up ROM

FIGURE 13. A Useful Digital Input Code Generator for DAC Attenuator or Amplifier Circuits

Resolution: Resolution is defined as the reciprocal of the number of discrete steps in the D/A output. It is directly related to the number of switches or bits within the D/A. For example, the DAC1020 has 2 10 or 1024 steps while the DAC1220 has 2 12 or 4096 steps. Therefore, the DAC1020 has 10-bit resolution, while the DAC1220 has 12-bit resolu- tion. Linearity Error: Linearity error is the maximum deviation from a straight line passing through the endpoints of the D/A transfer characteristic. It is measured after calibrating for zero (see V OS adjust in typical applications) and full- scale. Linearity error is a design parameter intrinsic to the device and cannot be externally adjusted. Power Supply Sensitivity: Power supply sensitivity is a measure of the effect of power supply changes on the D/A full-scale output. Settling Time: Full-scale settling time requires a zero to full- scale or full-scale to zero output change. Settling time is the time required from a code transition until the D/A output reaches within g(/2 LSB of final output value. Full-Scale Error: Full-scale error is a measure of the output error between an ideal D/A and the actual device output. Ideally, for the DAC1020 full-scale is V REFb1 LSB. For VREFe10V and unipolar operation, V FULL-SCA- LEe10.0000VÐ9.8 mV e9.9902V. Full-scale error is ad- justable to zero as shown in Figure 5 . TL/H/5689–10 ab 1 b 2 (a) End point test after zero and full-scale adjust. The DAC has 1 LSB linearity error. (b) By shifting the full-scale calibration on of the DAC of Figure (b1) we could pass the ‘‘best straight line’’ (b2) test and meet the g(/2 linearity error specification. Note. (a), (b1) and (b2) above illustrate the difference between ‘‘end point’’ National’s linearity test (a) and ‘‘best straight line’’ test. Note that both devices in (a) and (b2) meet the g(/2 LSB linearity error specification but the end point test is a more ‘‘real life’’ way of characterizing the DAC. Connection Diagrams DAC102X Dual-In-Line Package TL/H/5689–13 DAC1020 TL/H/5689–12 DAC122X Dual-In-Line Package TL/H/5689–11 http:/ /www.national.com 10

http:/ /www.national.com11

Physical Dimensions inches (millimeters) unless otherwise noted Cavity Dual-In-Line Package (J) Order Number DAC1220LCJ or DAC1222LCJ Molded Dual-In-Line Package (N) Order Number DAC1020LCN, DAC1021LCN or DAC1022LCN http:/ /www.national.com 12

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Molded Dual-In-Line Package (N) Order Number DAC1220LCN, DAC1221LCN or DAC1222LCN http:/ /www.national.com13

DAC1020/DAC1021/DAC1022 10-Bit Binary Multiplying D/A Converter DAC1220/DAC1222 12-Bit Binary Multiplying D/A Converter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Molded Plastic Leaded Chip Carrier (V) Order Number DAC1020LCV or DAC1020LIV LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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