DAC101S101CIMK/NOPB

Texas Instruments

DAC101S101 and DAC101S101Q-1 10-Bit Micro Power, RRO Digital-to-Analog Converter

Manufacturer: Texas Instruments

Document: 37 Pages / 1Mb

Request Quote Download Datasheet Read online HTML view

More from Texas Instruments Browse D parts

Online Datasheet

Read DAC101S101CIMK/NOPB online.

DAC101S101_16 TI1 | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 37

Technical content

Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC101S101,DAC101S101-Q1 SNAS321G –JUNE 2005–REVISED APRIL 2016 DAC101S101andDAC101S101Q-110-BitMicroPower,RRODigital-to-AnalogConverter

1 Features

1• DAC101S101Q is AEC-Q100 Grade 1 Qualified and is Manufactured on an Automotive Grade Flow.

Ensured Monotonicity
Low Power Operation
Rail-to-Rail Voltage Output
Power-on Reset to Zero Volts Output
Wide Temperature Range of −40°C to +125°C
Wide Power Supply Range of 2.7 V to 5.5 V
Small Packages
Power Down Feature
Resolution 10 bits
DNL +0.15, –0.05 LSB (typical)
Output Settling Time 8 μs (typical)
Zero Code Error 3.3 mV (typical)
Full-Scale Error −0.06 %FS (typical)
Power Consumption – Normal Mode, 0.63 mW (3.6 V) / 1.41 mW (5.5 V) typical – Power Down Mode, 0.14 μW (3.6 V) / 0.33 μW (5.5 V) typical

2 Applications

Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage & Current Sources
Programmable Attenuators
Automotive

3 Description

The DAC101S101 is a full-featured, general purpose 10-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7 V to 5.5 V supply and consumes just 175 µA of current at 3.6 Volts. The on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock rates up to 30 MHz over the specified supply voltage range and is compatible with standard SPI, QSPI, MICROWIRE and DSP interfaces. Competitive devices are limited to 20 MHz clock rates at supply voltages in the 2.7 V to 3.6 V range. The supply voltage for the DAC101S101 serves as its voltage reference, providing the widest possible output dynamic range. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DAC101S101 VSSOP (8) 3.00 mm × 3.00 mm DAC101S101, DAC101S101-Q1 SOT-23 (6) 1.60 mm × 2.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. DNL at VA = 3 V

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (March 2013) to Revision G Page

Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Changes from Revision E (March 2013) to Revision F Page

A IN OUT 1V 6 SYNC 2GND 5 SCLK 3V 4 D OUT IN A DAC101S101,DAC101S101-Q1 www.ti.com SNAS321G –JUNE 2005–REVISED APRIL 2016 Product Folder Links: DAC101S101 DAC101S101-Q1 Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated

5 Description (continued)

The low power consumption and small packages of the DAC101S101 make it an excellent choice for use in battery operated equipment. The DAC101S101 is a direct replacement for the AD5310 and is one of a family of pin compatible DACs, including the 8-bit DAC081S101 and the 12-bit DAC121S101. The DAC101S101 operates over the extended industrial temperature range of −40°C to +105°C while the DAC101S101Q operates over the Grade 1 automotive temperature range of −40°C to +125°C. The DAC101S101 is available in a 6-lead SOT and an 8-lead VSSOP and the DAC101S101Q is availabe in the 6-lead SOT only.

6 Pin Configuration and Functions

DAC101S101 and DAC101S101-Q1 DDC Package 6-Pin (SOT-23) Top View 8-Pin (VSSOP) Top View (1) G = Ground, I = Input, O = Output, S = Supply Pin Functions PIN I/O(1) DESCRIPTION NAME DAC101S101 DAC101S101-Q1 SOT-23 VSSOP SOT-23 DIN 4 7 4 I Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC. GND 2 8 2 G Ground reference for all on-chip circuitry. NC – 2,3 – – No Connect. There is no internal connection to these pins. SCLK 5 6 5 I Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin. SYNC 6 5 6 I Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. VA 3 1 3 S Power supply and Reference input. Should be decoupled to GND. VOUT 1 4 1 O DAC Analog Output Voltage.

DAC101S101,DAC101S101-Q1 SNAS321G –JUNE 2005–REVISED APRIL 2016 www.ti.com Product Folder Links: DAC101S101 DAC101S101-Q1 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. (3) All voltages are measured with respect to GND = 0V, unless otherwise specified (4) When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than VA), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. (5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)(3) MIN MAX UNIT Supply voltage, VA 6.5 V Voltage on any input pin –0.3 (VA + 0.3) V Input current at any pin (4) 10 mA Package input current (4) 20 mA Power consumption at TA = 25°C See (5) Storage temperature, Tstg −65 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.

7.2 ESD Ratings DAC101S101

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) ±2500 V Machine Model ±250 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 ESD Ratings DAC101S101-Q1

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2500 V Machine Model ±250

DAC101S101,DAC101S101-Q1 www.ti.com SNAS321G –JUNE 2005–REVISED APRIL 2016 Product Folder Links: DAC101S101 DAC101S101-Q1 Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. (2) All voltages are measured with respect to GND = 0V, unless otherwise specified (3) To ensure accuracy, it is required that VA be well bypassed. (4) The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not damage this device. However, errors in the conversion result can occur if any input goes above VA or below GND by more than 100 mV. For example, if VA is 2.7VDC, ensure that −100mV ≤ input voltages ≤2.8VDC to ensure accurate conversions.

7.4 Recommended Operating Conditions(1) (2)

DAC101S101 −40°C ≤ TA ≤ +105°C DAC101S101-Q1 −40°C ≤ TA ≤ +125°C Supply voltage, VA(3) 2.7 5.5 V Any input voltage (4) –0.1 (VA + 0.1) V Output load 0 1500 pF SCLK frequency Up to 30 MHz (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Thermal Information

THERMAL METRIC(1) DAC101S101, DAC101S101-Q1 DAC101S101 UNITDDC (SOT-23) DGK (VSSOP)

6 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 250 240 °C/W RθJC(top) Junction-to-case (top) thermal resistance 58.8 70.0 °C/W RθJB Junction-to-board thermal resistance 30.6 100.2 °C/W ψJT Junction-to-top characterization parameter 1.6 11.3 °C/W ψJB Junction-to-board characterization parameter 30.1 98.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

DAC101S101,DAC101S101-Q1 SNAS321G –JUNE 2005–REVISED APRIL 2016 www.ti.com Product Folder Links: DAC101S101 DAC101S101-Q1 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated (1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level). (2) This parameter is ensured by design and/or characterization and is not tested in production.

7.6 Electrical Characteristics

The following specifications apply for VA = +2.7 V to +5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011, TA = 25°C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN(1) TYP (1) MAX (1) UNIT STATIC PERFORMANCE Resolution DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 10 Bits Monotonicity DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 10 Bits INL Integral non-linearity Over decimal codes 12 to 1011 ±0.6 LSBDAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C –2.8 2.8 DNL Differential non-linearity VA = 2.7 V to 5.5 V −0.05/+0.15 LSBDAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C −0.2 0.35 ZE Zero code error IOUT = 0 3.3 mVDAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 15 FSE Full-scale error IOUT = 0 −0.06 %FSRDAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C –1 GE Gain error All ones Loaded to DAC register −0.1 %FSRDAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C –1 1 ZCED Zero code error drift −20 µV/°C TC GE Gain error tempco VA = 3 V −0.7 ppm/°C VA = 5 V −1 ppm/°C OUTPUT CHARACTERISTICS Output voltage range DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: ZCO Zero code output VA = 3 V, IOUT = 10 µA 1.8 mV VA = 3 V, IOUT = 100 µA 5 mV VA = 5 V, IOUT = 10 µA 3.7 mV VA = 5 V, IOUT = 100 µA 5.4 mV FSO Full scale output VA = 3 V, IOUT = 10 µA 2.997 V VA = 3 V, IOUT = 100 µA 2.99 V VA = 5 V, IOUT = 10 µA 4.995 V VA = 5 V, IOUT = 100 µA 4.992 V Maximum load capacitance RL = ∞ 1500 pF RL = 2 kΩ 1500 pF DC output Impedance 1.3 Ω IOS Output short circuit current VA = 5 V, VOUT = 0 V, Input code = 3FFh −63 mA VA = 3 V, VOUT = 0 V, Input code = 3FFh −50 mA VA = 5 V, VOUT = 5 V, Input code = 000h 74 mA VA = 3 V, VOUT = 3 V, Input code = 000h 53 mA

DAC101S101,DAC101S101-Q1 www.ti.com SNAS321G –JUNE 2005–REVISED APRIL 2016 Product Folder Links: DAC101S101 DAC101S101-Q1 Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated Electrical Characteristics (continued) The following specifications apply for VA = +2.7 V to +5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011, TA = 25°C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN(1) TYP (1) MAX (1) UNIT LOGIC INPUT IIN Input current (2) DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: VIL Input low voltage (2) VA = 5 V, DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 0.8 V VA = 3 V, DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: −40°C ≤ TA ≤ +125°C 0.5 V VIH Input high voltage (2) VA = 5 V, DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 2.4 V VA = 3 V, DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 2.1 V CIN Input capacitance (2) DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 3 pF POWER REQUIREMENTS IA Supply current (output unloaded) Normal Mode fSCLK = 30 MHz VA = 5.5 V 256 µA DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: 332 VA = 3.6 V 174 µA DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: 226 Normal Mode fSCLK = 20 MHz VA = 5.5 V 221 µA DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: 297 VA = 3.6 V 154 µA DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: 207 Normal Mode fSCLK = 0 VA = 5.5 V 145 µA VA = 3.6 V 113 All PD Modes, fSCLK = 30 MHz VA = 5 V 83 µA VA = 3 V 42 All PD Modes, fSCLK = 20 MHz VA = 5 V 56 µA VA = 3 V 28 All PD Modes, fSCLK = 0 (2) VA = 5.5 V 0.06 µA DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: VA = 3.6 V 0.04 µA DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q:

DAC101S101,DAC101S101-Q1 SNAS321G –JUNE 2005–REVISED APRIL 2016 www.ti.com Product Folder Links: DAC101S101 DAC101S101-Q1 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Electrical Characteristics (continued) The following specifications apply for VA = +2.7 V to +5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011, TA = 25°C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN(1) TYP (1) MAX (1) UNIT PC Power consumption (output unloaded) Normal Mode fSCLK = 30 MHz VA = 5.5 V 1.41 mW DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: 1.83 VA = 3.6 V 0.63 mW DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: 0.81 Normal Mode fSCLK = 20 MHz VA = 5.5 V 1.22 mW DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: 1.63 VA = 3.6 V 0.55 mW DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: 0.74 Normal Mode fSCLK = 0 VA = 5.5 V 0.8 µW VA = 3.6 V 0.41 µW All PD Modes, fSCLK = 30 MHz VA = 5 V 0.42 µW VA = 3 V 0.13 µW All PD Modes, fSCLK = 20 MHz VA = 5 V 0.28 µW VA = 3 V 0.08 µW All PD Modes, fSCLK = 0 (2) VA = 5.5 V 0.33 µW DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: 5.5 VA = 3.6 V 0.14 µW DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: 3.6 IOUT / IA Power efficiency ILOAD = 2 mA VA = 5 V 91% VA = 3 V 94%

DAC101S101,DAC101S101-Q1 www.ti.com SNAS321G –JUNE 2005–REVISED APRIL 2016 Product Folder Links: DAC101S101 DAC101S101-Q1 Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated (1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing Quality Level). (2) This parameter is ensured by design and/or characterization and is not tested in production. 7.7 A.C. and Timing Requirements The following specifications apply for VA = +2.7 V to +5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input code range 12 to 1011, TA = 25°C, unless otherwise specified. MIN(1) TYP(1) MAX(1) UNIT fSCLK SCLK Frequency DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 30 MHz ts Output voltage settling time (2) 100h to 300h code change, RL = 2 kΩ CL ≤ 200 pF µsDAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: 7.5 SR Output slew rate 1 V/µs Glitch impulse Code change from 200h to 1FFh 12 nV-sec Digital feedthrough 0.5 nV-sec tWU Wake-up time VA = 5 V 6 µs VA = 3 V 39 µs 1/fSCL K SCLK Cycle time DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 33 ns tH SCLK High time nsDAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 13 tL SCLK Low time nsDAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 13 tSUCL Set-up time SYNC to SCLK rising edge −15 nsDAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 0 tSUD Data set-up time 2.5 nsDAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 5 tDHD Data hold time 2.5 nsDAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q: –40°C ≤ TA ≤ +125°C 4.5 tCS SCLK fall to rise of SYNC VA = 5 V nsDAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: VA = 3 V nsDAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: tSYNC SYNC High time 2.7 ≤ VA ≤ 3.6 nsDAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q: 3.6 ≤ VA ≤ 5.5 nsDAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q:

7.8 Typical Characteristics

Figure 3. DNL at VA = 3 V Figure 4. DNL at VA = 5 V Figure 5. INL at VA = 3 V Figure 6. INL at VA = 5 V Figure 7. TUE at VA = 3 V Figure 8. TUE at VA = 5 V

Figure 33. 3-V Wake-Up Time Figure 34. 5-V Wake-Up Time

REF(+) REF(-) VA GND DAC101S101 VOUT DAC101S101,DAC101S101-Q1 www.ti.com SNAS321G –JUNE 2005–REVISED APRIL 2016 Product Folder Links: DAC101S101 DAC101S101-Q1 Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 DAC Section

The DAC101S101 is fabricated on a CMOS process with an architecture that consists of a resistor string and switches that are followed by an output buffer. The power supply serves as the reference voltage. The input coding is straight binary with an ideal output voltage of: VOUT = VA x (D / 1024) where

D is the decimal equivalent of the binary code that is loaded into the DAC register and can take on any value between 0 and 1023 (1)

8.3.2 Resistor String

The resistor string is shown in Figure 35. This string consists of 1024 equal valued resistors in series with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register determines which switch is closed, connecting the proper node to the amplifier. This configuration ensures that the DAC is monotonic.

Figure 35. DAC Resistor String

8.3.3 Output Amplifier

amplifier are described in the Electrical Characteristics Tables.

8.3.4 Power-On Reset

the output voltage is 0 Volts and remains there until a valid write sequence is made to the DAC.

8.4 Device Functional Modes

8.4.1 Power-Down Modes

Table 1. Modes of Operation

100KΩ resistor, or is in a high impedance state, as described in Table 1.

8.5 Programming

8.5.1 Serial Interface

Timing Diagram for information on a write sequence. initiate the next write cycle. write sequences to minimize power consumption.

8.5.2 Input Shift Register

serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Figure 2. Figure 36. Input Register Contents the write sequence is invalid. The DAC register is not updated and there is no change in the mode of operation.

8.5.3 DSP/Microprocessor Interfacing

to hasten the design process.

8.5.3.1 ADSP-2101/ADSP2103 Interfacing

register and should be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length. Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.

Figure 37. ADSP-2101/2103 Interface 80C51/80L51 transmits data with the LSB first while the DAC101S101 requires data with the MSB first. Figure 38. 80C51/80L51 Interface line of the DAC101S101 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51. second byte of data to the DAC, after which PC7 should be raised to end the write sequence. Figure 39. 68HC11 Interface

8.5.3.4 Microwire Interface

on the rising edges of the SCLK signal. Figure 40. Microwire Interface

0.1 PF+10 PF

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

output may be obtained with the circuit in Figure 41. This circuit will provide an output voltage range of ±5 Volts. A rail-to-rail amplifier should be used if the amplifier supplies are limited to ±5V.

9.2 Typical Application

Figure 41. Bipolar Operation

9.2.1 Design Requirements

The DAC101S101 will use a single supply.
The output is required to be bipolar with a voltage range of ±5 V.
Dual supplies will be used for the output amplifier.

9.2.2 Detailed Design Procedure

D is the input code in decimal form
With VA = 5V and R1 = R2 (2) VO = (10 x D / 1024) - 5V (3) A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2.

Table 2. Some Rail-To-Rail Amplifiers

9.2.3 Application Curve

Figure 42. Bipolar Input / Output Transfer Characteristic

10 Power Supply Recommendations

Rejection Ratio). Therefore, it is necessary to provide a noise-free supply voltage to the device.

10.1 Using References as Power Supplies

10.1.1 LM4130

Figure 43. The LM4130 as a Power Supply

10.1.2 LM4050

Figure 44. The LM4050 as a Power Supply

VZ(min) are the nominal LM4050 output voltages ± the LM4050 output tolerance over temperature
IZ(max) is the maximum allowable current through the LM4050
IA(min) is the minimum DAC101S101 supply current (4) and R(max) = ( VIN(min) − VZ(max) / (IA(max) + IZ(min) ) where
VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over temperature
IZ(min) is the minimum current required by the LM4050 for proper regulation
IA(max) is the maximum DAC101S101 supply current (5)

10.1.3 LP3985

LP3985 comes in a space-saving 5-pin SOT-23 and 5-bump micro SMD packages. Figure 45. Using The Lp3985 Regulator understanding of the capacitor specification is required to ensure correct device operation.

10.1.4 LP2980

grade. It is available in 3 V, 3.3 V and 5 V versions, among others. Figure 46. Using The Lp2980 Regulator

DAC101S101,DAC101S101-Q1 www.ti.com SNAS321G –JUNE 2005–REVISED APRIL 2016 Product Folder Links: DAC101S101 DAC101S101-Q1 Submit Documentation FeedbackCopyright © 2005–2016, Texas Instruments Incorporated Using References as Power Supplies (continued) Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor must be at least 1-µF over temperature, but values of 2.2 µF or more provide better performance. The ESR of this capacitor should be within the range specified in the LP2980 data sheet. Surface-mount solid tantalum capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to their small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic capacitors are typically not a good choice due to their large size and have ESR values that may be too high at low temperatures.

11 Layout

11.1 Layout Guidelines

separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes. continuous return path below their traces. board. The clock and data lines should have controlled impedances.

11.2 Layout Example

Figure 47. Layout Example

12 Device and Documentation Support

12.1 Device Support

12.1.1 Device Nomenclature

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB, which is VREF / 1024 = VA / 1024. DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus. FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (3FFh) loaded into the DAC and the value of VA x 1023 / 1024. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error. GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register changes. It is specified as the area of the glitch in nanovolt-seconds. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point method is used. INL for this product is specified over a limited range, per the Electrical Characteristics Tables. LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is LSB = VREF / 2n where

VREF is the supply voltage for this product
"n" is the DAC resolution in bits, which is 10 for the DAC101S101 (6) MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output stability maintained. MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the output code increases. MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of VREF.

by the device without a load. SETTLING TIME is the time for the output to settle within 1/2 LSB of the final value. commanded to the active mode from any of the power down modes.

12.2 Related Links

resources, tools and software, and quick access to sample or buy. Table 3. Related Links

12.3 Community Resources

solve problems with fellow engineers. contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 15-Apr-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DAC101S101CIMK/NOPB ACTIVE SOT DDC 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 X63C DAC101S101CIMKX/NOPB ACTIVE SOT DDC 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 X63C DAC101S101CIMM NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 105 X62C DAC101S101CIMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 X62C DAC101S101CIMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 X62C DAC101S101QCMK/NOPB ACTIVE SOT DDC 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X63Q DAC101S101QCMKX/NOPB ACTIVE SOT DDC 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X63Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

www.ti.com 15-Apr-2016 Addendum-Page 2 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF DAC101S101, DAC101S101-Q1 :

Catalog: DAC101S101
Automotive: DAC101S101-Q1 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant DAC101S101CIMKX/NOP B DAC101S101CIMMX/NOP B DAC101S101QCMK/NOP B DAC101S101QCMKX/NO PB PACKAGE MATERIALS INFORMATION www.ti.com 15-Apr-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC101S101CIMK/NOPB SOT DDC 6 1000 210.0 185.0 35.0 DAC101S101CIMKX/NOP B SOT DDC 6 3000 210.0 185.0 35.0 DAC101S101CIMM VSSOP DGK 8 1000 210.0 185.0 35.0 DAC101S101CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 DAC101S101CIMMX/NOP B VSSOP DGK 8 3500 367.0 367.0 35.0 DAC101S101QCMK/NOPB SOT DDC 6 1000 210.0 185.0 35.0 DAC101S101QCMKX/NOP B SOT DDC 6 3000 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 15-Apr-2016 Pack Materials-Page 2

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic”are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2016, Texas Instruments Incorporated

Product Information

DAC101S101CIMK/NOPB specifications and overview.

Summary

DAC101S101 and DAC101S101Q-1 10-Bit Micro Power, RRO Digital-to-Analog Converter

Description

DAC101S101 and DAC101S101Q-1 10-Bit Micro Power, RRO Digital-to-Analog Converter

Source title DAC101S101CIMK/NOPB Datasheet(PDF) - Texas Instruments

Related Parts

More parts from the same family.

Browse manufacturer