DAC101C085CIMMX/NO.A

DAC101C081 TI | Alldatasheet

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Technical content

VREF * DAC101C081 / DAC101C085 SCL SDA BUFFER VOUT 2.5k 100k

10 BIT DAC

ADR1* REF ADR0 * NOTE: ADR1 and VREF are for the DAC101C085 only. The DAC101C085 uses an external reference (VREF ), whereas, the DAC101C081 uses the supply (VA) as the reference. VA* Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC101C081,DAC101C081Q,DAC101C085 SNVS801B –APRIL 2012–REVISED JANUARY 2016 DAC101C08xx10-BitMicroPower Digital-to-AnalogConverterWithanI2C-CompatibleInterface

1 Features

1• Ensured Monotonicity to 10-bits

• Low Power Operation: 156-µA maximum at 3.3 V
• Extended Power Supply Range (2.7 V to 5.5 V)
• I2C-Compatible 2-Wire Interface Which Supports Standard (100-kHz), Fast (400-kHz), and High- Speed (3.4-MHz) Modes
• Rail-to-Rail Voltage Output
• Very Small Package
• DAC101C081Q is AEC Q100 Grade 1 Qualified and Manufactured on Automotive Grade Flow
• Resolution: 10 Bits
• INL: ±2 LSB (Maximum)
• DNL: +0.3/-0.2 LSB (Maximum)
• Setting Time: 6-µs (Maximum)
• Zero Code Error: +10-mV (Maximum)
• Full-Scale Error: −0.7 %FS (Maximum)
• Supply Power (Normal): 380-µW (3-V) / 730-µW (5-V) Typical
• Supply Power (Power Down): 0.5-µW (3-V) / 0.9- µW (5-V) Typical

2 Applications

• Industrial Process Control
• Portable Instruments
• Digital Gain and Offset Adjustment
• Programmable Voltage and Current Sources
• Test Equipment
• Automotive

3 Description

The DAC101C081 device is a 10-bit, single channel, voltage-output digital-to-analog converter (DAC) that operates from a 2.7 V to 5.5 V supply. The output amplifier allows rail-to-rail output swing and has an 6- µsec settling time. The DAC101C081 uses the supply voltage as the reference to provide the widest dynamic output range and typically consumes 132 µA while operating at 5.0 V. It is available in 6-lead SOT and WSON packages and provides three address options (pin selectable). As an alternative, the DAC101C085 provides nine I2C™ addressing options and uses an external reference. It has the same performance and settling time as the DAC101C081 and is available in an 8- lead VSSOP. The DAC101C081 and DAC101C085 use a 2-wire, I2C-compatible serial interface that operates in all three speed modes, including high speed mode (3.4 MHz). An external address selection pin allows up to three DAC101C081 or nine DAC101C085 devices per 2-wire bus. Pin compatible alternatives to the DAC101C081 are available that provide additional address options. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DAC101C081 WSON (6) 2.20 mm × 2.50 mm SOT (6) 1.60 mm × 2.90 mm DAC101C085 VSSOP (8) 3.00 mm × 3.00 mm DAC101C081Q WSON (6) 2.20 mm × 2.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Block Diagram

DAC101C081,DAC101C081Q,DAC101C085 SNVS801B –APRIL 2012–REVISED JANUARY 2016 www.ti.com Product Folder Links: DAC101C081 DAC101C081Q DAC101C085 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Table of Contents

14 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (March 2013) to Revision B Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Original (March 2013) to Revision A Page

DAC101C081,DAC101C081Q,DAC101C085 www.ti.com SNVS801B –APRIL 2012–REVISED JANUARY 2016 Product Folder Links: DAC101C081 DAC101C081Q DAC101C085 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated

5 Description (continued)

The DAC101C081 and DAC101C085 each have a 16-bit register that controls the mode of operation, the power- down condition, and the output voltage. A power-on reset circuit ensures that the DAC output powers up to zero volts. A power-down feature reduces power consumption to less than a microWatt. Their low power consumption and small packages make these DACs an excellent choice for use in battery operated equipment. Each DAC operates over the extended industrial temperature range of −40°C to +125°C. The DAC101C081 and DAC101C085 are each part of a family of pin compatible DACs that also provide 12 and 8 bit resolution. For 12-bit DACs see the DAC121C081 and DAC121C085. For 8-bit DACs see the DAC081C081 and DAC081C085. (1) All devices are fully pin and function compatible.

6 Device Comparison Table(1)

Resolution SOT-6 and WSON-6 Packages VSSOP-8 Package w/ External Reference 12-bit DAC121C081 DAC121C085 10-bit DAC101C081 DAC101C085 8-bit DAC081C081 DAC081C085

2.1k 41.5k 41.5k ADR1 SDA ADR0 VA GND VSSOP 3SCL 6 VREF VOUT DAC101C085 ADR0 SCL SDA VOUT VA GND SOT DAC101C081 ADR0 SCL SDA VOUT VA GND WSON DAC101C081 DAC101C081,DAC101C081Q,DAC101C085 SNVS801B –APRIL 2012–REVISED JANUARY 2016 www.ti.com Product Folder Links: DAC101C081 DAC101C081Q DAC101C085 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated

7 Pin Configuration and Functions

ADR0 1 6 1 Digital Input, three levels Tri-state Address Selection Input. Sets the two Least Significant Bits (A1 and A0) of the 7-bit slave address. (see Table 1) ADR1 — — 2 Digital Input, three levels Tri-State Address Selection Input. Sets Bits A6 and A3 of the 7-bit slave address. (see Table 1) GND 4 3 5 Ground Ground for all on-chip circuitry PAD PAD — — Ground Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package self-alignment during reflow. SCL 2 5 3 Digital Input Serial Clock Input. SCL is used together with SDA to control the transfer of data in and out of the device. SDA 3 4 4 Digital Input/Output Serial Data bi-directional connection. Data is clocked into or out of the internal 16-bit register relative to the clock edges of SCL. This is an open drain data line that must be pulled to the supply (VA) by an external pullup resistor. VA 5 2 6 Supply Power supply input. For the SOT and WSON versions, this supply is used as the reference. Must be decoupled to GND. VOUT 6 1 8 Analog Output Analog Output Voltage VREF — — 7 Supply Unbufferred reference voltage. For the VSSOP-8, this supply is used as the reference. VREF must be free of noise and decoupled to GND.

DAC101C081,DAC101C081Q,DAC101C085 www.ti.com SNVS801B –APRIL 2012–REVISED JANUARY 2016 Product Folder Links: DAC101C081 DAC101C081Q DAC101C085 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are measured with respect to GND = 0 V, unless otherwise specified. (3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. (4) When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. (5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)(2)(3) MIN MAX UNIT Supply voltage, VA −0.3 6.5 V Voltage on any input pin −0.3 6.5 V Input current at any pin(4) ±10 mA Package input current(4) ±20 mA Power consumption at TA = 25°C See (5) Operating junction temperature 150 °C Storage temperature, Tstg −65 150 °C

8.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 All pins except 2 and 3 ±2500 V Pins 2 and 3 ±5000 Charged-device model (CDM), per JEDEC specification JESD22-C101 All pins except 2 and 3 ±1000 Pins 2 and 3 ±1000 Machine model (MM) All pins except 2 and 3 ±250 Pins 2 and 3 ±350 DAC081C081 in DDC Package V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 All pins except 4 and 5 ±2500 V Pins 4 and 5 ±5000 Charged-device model (CDM), per JEDEC specification JESD22-C101 All pins except 4 and 5 ±1000 Pins 4 and 5 ±1000 Machine model (MM) All pins except 4 and 5 ±250 Pins 4 and 5 ±350 DAC081C085 in DGK Package V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 All pins except 3 and 4 ±2500 V Pins 3 and 4 ±5000 Charged-device model (CDM), per JEDEC specification JESD22-C101 All pins except 3 and 4 ±1000 Pins 3 and 4 ±1000 Machine model (MM) All pins except 3 and 4 ±250 Pins 3 and 4 ±350

DAC101C081,DAC101C081Q,DAC101C085 SNVS801B –APRIL 2012–REVISED JANUARY 2016 www.ti.com Product Folder Links: DAC101C081 DAC101C081Q DAC101C085 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated (1) All voltages are measured with respect to GND = 0 V, unless otherwise specified. (2) The inputs are protected as shown below. Input voltage magnitudes up to 5.5 V, regardless of VA, will not cause errors in the conversion result. For example, if VA is 3 V, the digital input pins can be driven with a 5 V logic device. (3) To ensure accuracy, it is required that VA and VREF be well bypassed.

8.3 Recommended Operating Conditions

See (1) MIN NOM MAX UNIT Operating temperature range −40 TA 125 °C Supply voltage, VA 2.7 5.5 V Reference voltage, VREFIN 1 VA V Digital input voltage(2)(3) 0 5.5 V Output load 0 1500 pF (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging. (3) Reflow temperature profiles are different for lead-free packages.

8.4 Thermal Information

THERMAL METRIC(1)(2)(3) DAC101C081 DAC101C081, DAC101C081Q DAC101C085 UNITDDC (SOT) NGF (WSON) DGK (VSSOP)

6 PINS 6 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 250 190 240 °C/W (1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing Quality Level). (2) This parameter is ensured by design and/or characterization and is not tested in production.

8.5 Electrical Characteristics

The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, CL = 200 pF to GND, input code range 12 to 1011. All Maximum and Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C (unless otherwise specified). PARAMETER TEST CONDITIONS MIN TYP(1) MAX(1) UNIT STATIC PERFORMANCE Resolution 10 Bits Monotonicity 10 Bits INL Integral non-linearity +0.6 +2 LSB −2 −0.4 LSB DNL Differential non-linearity +0.12 +0.3 LSB −0.2 −0.04 LSB ZE Zero code error IOUT = 0 +1.1 +10 mV FSE Full-scale error IOUT = 0 −0.1 −0.7 %FSR GE Gain error All ones loaded to DAC register −0.2 −0.7 %FSR ZCED Zero code error drift −20 µV/°C TC GE Gain error tempco VA = 3 V −0.7 ppm FSR/°C VA = 5 V −1 ppm FSR/°C ANALOG OUTPUT CHARACTERISTICS (VOUT) Output voltage range(2) DAC101C085 0 VREF V DAC101C081 0 VA V ZCO Zero code output VA = 3 V, IOUT = 200 µA 1.3 mV VA = 5 V, IOUT = 200 µA 7.0 mV FSO Full scale output VA = 3 V, IOUT = 200 µA 2.984 V VA = 5 V, IOUT = 200 µA 4.989 V

DAC101C081,DAC101C081Q,DAC101C085 www.ti.com SNVS801B –APRIL 2012–REVISED JANUARY 2016 Product Folder Links: DAC101C081 DAC101C081Q DAC101C085 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated Electrical Characteristics (continued) The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, CL = 200 pF to GND, input code range 12 to 1011. All Maximum and Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C (unless otherwise specified). PARAMETER TEST CONDITIONS MIN TYP(1) MAX(1) UNIT IOS Output short circuit current (ISOURCE) VA = 3 V, VOUT = 0 V, Input code = FFFh. 56 mA VA = 5 V, VOUT = 0 V, Input code = FFFh. 69 mA IOS Output short circuit current (ISINK) VA = 3 V, VOUT = 3 V, Input code = 000h. −52 mA VA = 5 V, VOUT = 5 V, Input code = 000h. −75 mA IO Continuous output current (2) Available on the DAC output 11 mA CL Maximum load capacitance RL = ∞ 1500 pF RL = 2 kΩ 1500 pF ZOUT DC output impedance 7.5 Ω REFERENCE INPUT CHARACTERISTICS- (DAC101C085 only) VREF Input range inimum 1 0.2 V Input range maximum VA V Input impedance 120 kΩ LOGIC INPUT CHARACTERISTICS (SCL, SDA) VIH Input high voltage 0.7 × VA V VIL Input low voltage 0.3 × VA V IIN Input current ±1 µA CIN Input pin capacitance(2) 3 pF VHYST Input hysteresis 0.1 × VA V LOGIC INPUT CHARACTERISTICS (ADR0, ADR1) VIH Input high voltage VA– 0.5 V VIL Input low voltage 0.5 V IIN Input current ±1 µA LOGIC OUTPUT CHARACTERISTICS (SDA) VOL Output low voltage ISINK = 3 mA 0.4 V ISINK = 6 mA 0.6 V IOZ High-impedence output leakage current ±1 µA POWER REQUIREMENTS VA Supply voltage minimum 2.7 V Supply voltage maximum 5.5 V Normal -- VOUT set to midscale. 2-wire interface quiet (SCL = SDA = VA). (output unloaded) IST_VA-1 VADAC101C081 supply current VA = 2.7 V to 3.6 V 105 156 µA VA = 4.5 V to 5.5 V 132 214 µA IST_VA-5 VADAC101C085 supply current VA = 2.7 V to 3.6 V 86 118 µA VA = 4.5 V to 5.5 V 98 152 µA IST_VREF VREF supply current (DAC101C085 only) VA = 2.7 V to 3.6 V 37 43 µA VA = 4.5 V to 5.5 V 53 61 µA PST Power consumption (VA & VREF for DAC101C085) VA = 3 V 380 µW VA = 5 V 730 µW Continuous Operation -- 2-wire interface actively addressing the DAC and writing to the DAC register. (output unloaded)

DAC101C081,DAC101C081Q,DAC101C085 SNVS801B –APRIL 2012–REVISED JANUARY 2016 www.ti.com Product Folder Links: DAC101C081 DAC101C081Q DAC101C085 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated Electrical Characteristics (continued) The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, CL = 200 pF to GND, input code range 12 to 1011. All Maximum and Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C (unless otherwise specified). PARAMETER TEST CONDITIONS MIN TYP(1) MAX(1) UNIT ICO_VA-1 VADAC101C081 supply current fSCL = 400 kHz VA = 2.7 V to

3.6 V 134 220 µA

VA = 4.5 V to

5.5 V 192 300 µA

fSCL = 3.4 MHz VA = 2.7 V to

3.6 V 225 320 µA

VA = 4.5 V to

5.5 V 374 500 µA

ICO_VA-5 VADAC101C085 supply current fSCL = 400 kHz VA = 2.7 V to

3.6 V 101 155 µA

VA = 4.5 V to

5.5 V 142 220 µA

fSCL = 3.4 MHz VA = 2.7 V to

3.6 V 193 235 µA

VA = 4.5 V to

5.5 V 325 410 µA

ICO_VREF VREF supply current (DAC101C085 only) VA = 2.7 V to 3.6 V 33.5 55 µA VA = 4.5 V to 5.5 V 49.5 71.4 µA PCO Power consumption (VA & VREF for DAC101C085) fSCL = 400 kHz VA = 3 V 480 µW VA = 5 V 1.06 mW fSCL = 3.4 MHz VA = 3 V 810 µW VA = 5 V 2.06 mW Power Down -- 2-wire interface quiet (SCL = SDA = VA) after PD mode written to DAC register. (output unloaded) IPD Supply current (VA & VREF for DAC101C085) All power-down modes VA = 2.7 V to 3.6 V 0.13 1.52 µA VA = 4.5 V to 5.5 V 0.15 3.25 µA PPD Power consumption (VA & VREF for DAC101C085) All power-down modes VA = 3 V 0.5 µW VA = 5 V 0.9 µW (1) Cb refers to the capacitance of one bus line. Cb is expressed in pF units. (2) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing Quality Level). (3) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing Quality Level). (4) This parameter is ensured by design and/or characterization and is not tested in production. (5) Applies to the Multiplying DAC configuration. In this configuration, the reference is used as the analog input. The value loaded in the DAC Register will digitally attenuate the signal at Vout.

8.6 AC and Timing Characteristics

The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, RL = Infinity, CL = 200 pF to GND. All Maximum and Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C (unless otherwise specified). PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX(1)(3) UNIT ts Output voltage settling time(4) 100h to 300h code change RL = 2 kΩ, CL = 200 pF 4.5 6 µs SR Output slew rate 1 V/µs Glitch impulse Code change from 200h to 1FFh 12 nV-sec Digital feedthrough 0.5 nV-sec Multiplying bandwidth(5) VREF = 2.5 V ± 0.1 Vpp 160 kHz Total harmonic distortion(5) VREF = 2.5 V ± 0.1 Vpp input frequency = 10 kHz 70 dB

DAC101C081,DAC101C081Q,DAC101C085 www.ti.com SNVS801B –APRIL 2012–REVISED JANUARY 2016 Product Folder Links: DAC101C081 DAC101C081Q DAC101C085 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated AC and Timing Characteristics (continued) The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, RL = Infinity, CL = 200 pF to GND. All Maximum and Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C (unless otherwise specified). PARAMETER TEST CONDITIONS(1) MIN TYP(2) MAX(1)(3) UNIT tWU Wake-up time VA = 3 V 0.8 µsec VA = 5 V 0.5 µsec DIGITAL TIMING SPECS (SCL, SDA) fSCL Serial clock frequency Standard mode 100 kHz Fast mode 400 High speed mode, Cb = 100 pF 3.4 MHz High speed mode, Cb = 400 pF 1.7 tLOW SCL low time Standard mode 4.7 µs Fast mode 1.3 High speed mode, Cb = 100 pF 160 ns High speed mode, Cb = 400 pF 320 tHIGH SCL high time Standard mode 4 µs Fast mode 0.6 High speed mode, Cb = 100 pF 60 ns High speed mode, Cb = 400 pF 120 tSU;DAT Data set-up time Standard mode 250 nsFast mode 100 High speed mode 10 tHD;DAT Data hold time Standard mode 0 3.45 µs Fast mode 0 0.9 High speed mode, Cb = 100 pF 0 70 ns High speed mode, Cb = 400 pF 0 150 tSU;STA Set-up time for a start or a repeated start condition Standard mode 4.7 µs Fast mode 0.6 High speed mode 160 ns tHD;STA Hold time for a start or a repeated start condition Standard mode 4 µs Fast mode 0.6 High speed mode 160 ns tBUF Bus free time between a stop and start condition Standard mode 4.7 µs Fast mode 1.3 tSU;STO Set-up time for a stop condition Standard mode 4 µs Fast mode 0.6 High speed mode 160 ns trDA Rise time of SDA signal Standard mode 1000 ns Fast mode 20 + 0.1Cb 300 ns High speed mode, Cb = 100 pF 10 80 ns High speed mode, Cb = 400 pF 20 160 ns tfDA Fall time of SDA signal Standard mode 250 ns Fast mode 20 + 0.1Cb 250 ns High speed mode, Cb = 100 pF 10 80 ns High speed mode, Cb = 400 pF 20 160 ns trCL Rise time of SCL signal Standard mode 1000 ns Fast mode 20 + 0.1Cb 300 ns High speed mode, Cb = 100 pF 10 40 ns High speed mode, Cb = 400 pF 20 80 ns

8.7 Typical Characteristics

VREF = VA, fSCL = 3.4 MHz, TA = 25°C, input code range 12 to 1011 (unless otherwise stated). Figure 3. Define (INL) Figure 4. Define (DNL) Figure 5. INL/DNL vs Temperature at VA = 3.0 V Figure 6. INL/DNL vs Temperature at VA = 5 V Figure 7. INL/DNL vs VREFIN at VA = 3 V Figure 8. INL/DNL vs VREFIN at VA = 5 V

VREF * DAC101C081 / DAC101C085 SCL SDA BUFFER VOUT 2.5k 100k ADR1* REF ADR0 * NOTE: ADR1 and VREF are for the DAC101C085 only. The DAC101C085 uses an external reference (VREF ), whereas, the DAC101C081 uses the supply (VA) as the reference. VA* DAC101C081,DAC101C081Q,DAC101C085 SNVS801B –APRIL 2012–REVISED JANUARY 2016 www.ti.com Product Folder Links: DAC101C081 DAC101C081Q DAC101C085 Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated

9 Detailed Description

9.1 Overview

The DAC101C081 is fabricated on a CMOS process with an architecture that consists of switches and resistor strings that are followed by an output buffer.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 DAC Section

For simplicity, a single resistor string is shown in Figure 20. This string consists of 1024 equal valued resistors with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight binary with an ideal output voltage of: VOUT = VREF × (D / 1024) where D is the decimal equivalent of the binary code that is loaded into the DAC register. D can take on any integer value between 0 and1023. This configuration ensures that the DAC is monotonic. (1)

Figure 20. DAC Resistor String

9.3.2 Output Amplifier

amplifier are described in the Electrical Characteristics table. code and full-scale outputs for given load currents are available in the Electrical Characteristics table.

9.3.3 Reference Voltage

voltage source with low output impedance. VREF be kept as clean as possible. Using References as Power Supplies for details.

9.3.4 Power-On Reset

sequence is made to the DAC.

the ADC performs as specified.

9.3.5 Simultaneous Reset

the DACs will power-down simultaneously.

9.3.6 Additional Timing Information: toutz

Figure 21. Data Output Timing The toutz specification is typically 87nsec in Standard-Fast Mode and 38nsec in Hs-Mode.

9.4 Device Functional Modes

9.4.1 Power-Down Modes

V and 0.15µA at 5 V (typ). The DAC101C081 is put into power-down mode by writing a one to PD1 and/or PD0. will be updated with the new 10-bit data value. The time to exit power-down (Wake-Up Time) is typically 0.8µsec at 3 V and 0.5µsec at 5 V.

condition, this bit must be a NACK from the master.

9.5 Programming

9.5.1 Serial Interface

mode (3.4 MHz) is an extension of Standard-Fast mode and will be referred to as Hs-mode in this document. capacitance and operating speed.

9.5.2 Basic I2C™ Protocol

the last data byte and creates a Stop condition on the bus. operate in the same speed mode as before the Repeated Start condition. idle until a master generates a Start condition. Figure 22. Basic Operation

9.5.3 Standard-Fast Mode

match, the DAC101C081 NACKs the master. For a write operation, the master follows the ACK by sending the upper eight data bits to the DAC101C081. to end communication, or generates a Repeated Start condition to communicate with another device on the bus. condition to end communication on the bus, or a Repeated Start to communicate with another device on the bus.

9.5.4 High-Speed (Hs) Mode

increasing the bus speed and generating a Repeated Start condition (driving SDA low while SCL is pulled high). above in the "Basic Operation" Diagram (see Figure 22). again before increasing the bus speed and switching to Hs-mode. Figure 23. Beginning Hs-Mode Communication

(1) Pin-compatible alternatives to the DAC101C081 options are available with additional address options.

9.5.5 I2C Slave (Hardware) Address

the broadcast address, all the DAC101C081's and DAC101C085's will respond and update synchronously. Table 1. Slave Addresses

9.5.6 Writing to the DAC Register

allows for a maximum DAC conversion rate of 188.9 kilo-conversions per second in Hs-mode. Figure 24. Typical Write to the DAC Register

9.5.7 Reading from the DAC Register

Figure 25. Typical Read from the DAC Register

9.6 Registers

9.6.1 DAC Register

Register, VOUT will update on the rising edge of the ACK following the lower data byte. Figure 26. DAC Register Contents

0.1 PF+10 PF

validate and test their design implementation to confirm system functionality.

10.1 Application Information

10.1.1 Bipolar Operation

output may be obtained with the circuit in Figure 27. This circuit will provide an output voltage range of ±5 Volts. A rail-to-rail amplifier should be used if the amplifier supplies are limited to ±5 V. Figure 27. Bipolar Operation A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2. Table 2. Some Rail-to-Rail Amplifiers

10.1.2 DSP/Microprocessor Interfacing

to simplify the design process.

10.1.2.1 Interfacing to the 2-wire Bus

threshold can be achieved. If used, RS is typically 51Ω. Figure 28. Serial Interface Connection Diagram

10.1.2.2 Interfacing to a Hs-mode Bus

tighter timing specs. Please refer to the I2C Specification for further details.

10.2 Typical Application

Figure 29. Pressure Sensor Gain Adjust

10.2.1 Design Requirements

the pressure sensor output by adjusting the bias voltage to the bridge pressure sensor.

10.2.2 Detailed Design Procedure

times the output of the DAC101C081, thus providing the desired gain correction. times relative to the ratio of the ADC input divided by the DAC101C081 output voltage.

10.2.3 Application Curve

Figure 30. INL vs Input Code

11 Power Supply Recommendations

11.1 Using References as Power Supplies

DAC101C081. When using the DAC101C081, it is important to treat the analog supply (VA) as the reference.

11.1.1 LM4132

reduce output noise. The LM4132 comes in a space-saving 5-pin SOT-23. Figure 31. The LM4132 as a Power Supply

11.1.2 LM4050

DAC101C081. It is available in 4.096-V and 5-V versions and comes in a space-saving 3-pin SOT-23. Figure 32. The LM4050 as a Power Supply

• VZ(min) and VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over temperature
• IZ(max) is the maximum allowable current through the LM4050
• IZ(min) is the minimum current required by the LM4050 for proper regulation and
• IDAC(max) is the maximum DAC101C081 supply current. (7)

11.1.3 LP3985

LP3985 comes in a space-saving 5-pin SOT-23 and 5-bump DSBGA packages. Figure 33. Using the LP3985 Regulator and understanding of the capacitor specification is required to ensure correct device operation.

11.1.4 LP2980

grade. It is available in 3.0-V, 3.3-V and 5-V versions, among others. Figure 34. Using the LP2980 Regulator

12 Layout

12.1 Layout Guidelines

ground plane design will use a fencing technique to prevent the mixing of analog and digital ground current. continuous return path below their traces. board. These clock and data lines require controlled impedances.

12.2 Layout Example

Figure 35. Layout Example

DAC101C081,DAC101C081Q,DAC101C085 www.ti.com SNVS801B –APRIL 2012–REVISED JANUARY 2016 Product Folder Links: DAC101C081 DAC101C081Q DAC101C085 Submit Documentation FeedbackCopyright © 2012–2016, Texas Instruments Incorporated

13 Device and Documentation Support

13.1 Device Support

13.1.1 Device Nomenclature

13.1.1.1 Specification Definitions

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB, which is VREF / 1024 = VA / 1024. DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital inputs when the DAC output is not updated. It is measured with a full-scale code change on the data bus. FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded into the DAC and the value of VA x 1023 / 1024. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and Full-Scale Errors as: GE = FSE - ZE where

• GE is Gain error
• FSE is Full-Scale Error
• and ZE is Zero Error. (8) GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register changes. It is specified as the area of the glitch in nanovolt-seconds. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point method is used. INL for this product is specified over a limited range, per the Electrical Characteristics Table. LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is LSB = VREF / 2n where
• VREF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 10 for the DAC101C081. (9) MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output stability maintained. MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the input code increases. MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of VA. MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3dB below the input sine wave on VREFIN with a full-scale code loaded into the DAC. POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output currents is the power consumed by the device without a load. SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is updated. TOTAL HARMONIC DISTORTION (THD) is the measure of the harmonics present at the output of the DACs with an ideal sine wave applied to VREFIN. THD is measured in dB. WAKE-UP TIME is the time for the output to exit power-down mode. This time is measured from the rising edge of SCL during the ACK bit of the lower data byte to the time the output voltage deviates from the power-down voltage of 0 V.

13.2 Related Links

resources, tools and software, and quick access to sample or buy. Table 3. Related Links

13.3 Community Resources

solve problems with fellow engineers. contact information for technical support.

13.4 Trademarks

E2E is a trademark of Texas Instruments. I2C is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners.

13.5 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

13.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 14-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DAC101C081CIMK/G4 Active Production SOT-23- THIN (DDC) | 6 1000 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 X85C DAC101C081CIMK/G4.A Active Production SOT-23- THIN (DDC) | 6 1000 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 X85C DAC101C081CIMK/NO.A Active Production SOT-23- THIN (DDC) | 6 1000 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 X85C DAC101C081CIMK/NOPB Active Production SOT-23- THIN (DDC) | 6 1000 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 X85C DAC101C081CIMKX/NO.A Active Production SOT-23- THIN (DDC) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 X85C DAC101C081CIMKX/NO.B Active Production SOT-23- THIN (DDC) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 X85C DAC101C081CIMKX/NOPB Active Production SOT-23- THIN (DDC) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 X85C DAC101C081CISD/NO.A Active Production WSON (NGF) | 6 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 X88 DAC101C081CISD/NOPB Active Production WSON (NGF) | 6 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM - X88 DAC101C081CISDX/NO.A Active Production WSON (NGF) | 6 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 X88 DAC101C081CISDX/NO.B Active Production WSON (NGF) | 6 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 X88 DAC101C081CISDX/NOPB Active Production WSON (NGF) | 6 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM - X88 DAC101C081QISD/NO.A Active Production WSON (NGF) | 6 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 Q88 DAC101C081QISD/NOPB Active Production WSON (NGF) | 6 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 Q88 DAC101C081QISDX/NO.A Active Production WSON (NGF) | 6 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 Q88 DAC101C081QISDX/NOPB Active Production WSON (NGF) | 6 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 Q88 DAC101C085CIMM/NO.A Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 X91C DAC101C085CIMM/NO.B Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 X91C DAC101C085CIMM/NOPB Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM - X91C DAC101C085CIMMX/NO.A Active Production VSSOP (DGK) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 X91C DAC101C085CIMMX/NO.B Active Production VSSOP (DGK) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 X91C DAC101C085CIMMX/NOPB Active Production VSSOP (DGK) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 X91C (1) Status: For more details on status, see our product life cycle. Addendum-Page 1

www.ti.com 14-Oct-2025 (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 5-Sep-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant DAC101C081CIMK/G4 SOT-23- THIN DAC101C081CIMK/NOPB SOT-23- THIN DAC101C081CIMKX/ NOPB SOT-23- THIN DAC101C081CISDX/ NOPB DAC101C081QISDX/ NOPB DAC101C085CIMM/ NOPB DAC101C085CIMMX/ NOPB Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 5-Sep-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC101C081CIMK/G4 SOT-23-THIN DDC 6 1000 210.0 185.0 35.0 DAC101C081CIMK/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0 DAC101C081CIMKX/ NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0 DAC101C081CISD/NOPB WSON NGF 6 1000 210.0 185.0 35.0 DAC101C081CISDX/ NOPB WSON NGF 6 4500 367.0 367.0 35.0 DAC101C081QISD/NOPB WSON NGF 6 1000 210.0 185.0 35.0 DAC101C081QISDX/ NOPB WSON NGF 6 4500 367.0 367.0 35.0 DAC101C085CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 DAC101C085CIMMX/ NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05

4.75 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8

1.1 MAX

0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023

0.13 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM

www.ti.com PACKAGE OUTLINE C 0.20

0.12 TYP

0.25 3.05 2.55 4X 0.95 1.1 0.7 0.1

0.0 TYP

6X 0.5 0.3 0.6

0.3 TYP

1.9 0 -8 TYP 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR 4214841/E 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC MO-193. 3 4

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

6X (1.1) 6X (0.6) (2.7) 4X (0.95) (R0.05) TYP 4214841/E 08/2024 SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPLOSED METAL SHOWN SCALE:15X SYMM 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDERMASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.7) 4X(0.95) 6X (1.1) 6X (0.6) (R0.05) TYP SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR 4214841/E 08/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM SYMM 3 4

www.ti.com

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