DAC101C085CIMM

DAC101C081CIMK NSC | Alldatasheet

Document overview

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Technical content

Features

■ Guaranteed Monotonicity to 10-bits ■ Low Power Operation: 156 µA max @ 3.3V ■ Extended power supply range (+2.7V to +5.5V) ■ I2C-Compatible 2-wire Interface which supports standard (100kHz), fast (400kHz), and high speed (3.4MHz) modes ■ Rail-to-Rail Voltage Output ■ Very Small Package Key Specifications ■ Resolution 10 bits ■ INL ±2 LSB (max) ■ DNL +0.3 / -0.2 LSB (max) ■ Settling Time 6 µs (max) ■ Zero Code Error +10 mV (max) ■ Full-Scale Error −0.7 %FS (max) ■ Supply Power — Normal 380 µW (3V) / 730 µW (5V) typ — Power Down 0.5 µW (3V) / 0.9 µW (5V) typ

Applications

■ Industrial Process Control ■ Portable Instruments ■ Digital Gain and Offset Adjustment ■ Programmable Voltage & Current Sources ■ Test Equipment Pin-Compatible Alternatives All devices are fully pin and function compatible. Resolution TSOT-6 and LLP-6 Packages External Reference 12-bit DAC121C081 DAC121C085 10-bit DAC101C081 DAC101C085 8-bit DAC081C081 DAC081C085 Connection Diagrams 30052201 30052202 30052210 I2C® is a registered trademark of Phillips Corporation. © 2008 National Semiconductor Corporation 300522 www.national.com DAC101C081/ DAC101C085 10-Bit Micro Power Digital-to-Analog Converter

Ordering Information

Order Code Temperature Range Package Top Mark DAC101C081CIMK −40°C ≤ TA ≤ +125°C TSOT X85C DAC101C081CIMKX −40°C ≤ TA ≤ +125°C TSOT Tape-and-Reel X85C DAC101C081CISD −40°C ≤ TA ≤ +125°C LLP X88 DAC101C081CISDX −40°C ≤ TA ≤ +125°C LLP Tape-and-Reel X88 DAC101C085CIMM −40°C ≤ TA ≤ +125°C MSOP X91C DAC101C085CIMMX −40°C ≤ TA ≤ +125°C MSOP Tape-and-Reel X91C DAC101C08XEB Evaluation Board Block Diagram 30052203 www.national.com 2 DAC101C081/ DAC101C085

Symbol Type Equivalent Circuit Description VOUT Analog Output Analog Output Voltage. VA Supply Power supply input. For the TSOT and LLP versions, this supply is used as the reference. Must be decoupled to GND. GND Ground Ground for all on-chip circuitry. SDA Digital Input/Output Serial Data bi-directional connection. Data is clocked into or out of the internal 16-bit register relative to the clock edges of SCL. This is an open drain data line that must be pulled to the supply (VA) by an external pull-up resistor. SCL Digital Input Serial Clock Input. SCL is used together with SDA to control the transfer of data in and out of the device. ADR0 Digital Input, three levels Tri-state Address Selection Input. Sets the two Least Significant Bits (A1 & A0) of the 7-bit slave address. (see Table 1) ADR1 Digital Input, three levels Tri-state Address Selection Input. Sets Bits A6 & A3 of the 7-bit slave address. (see Table 1) VREF Supply Unbufferred reference voltage. For the MSOP-8, this supply is used as the reference. VREF must be free of noise and decoupled to GND. PAD (LLP only) Ground Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB offers optimal thermal performance and enhances package self- alignment during reflow. Package Pinouts VOUT VA GND SDA SCL ADR0 ADR1 VREF PAD (LLP only) TSOT 1 2 3 4 5 6 N/A N/A N/A LLP 6 5 4 3 2 1 N/A N/A 7 MSOP-8 8 6 5 4 3 1 2 7 N/A 3 www.national.com DAC101C081/ DAC101C085

(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, VA −0.3V to +6.5V Voltage on any Input Pin −0.3V to +6.5V Input Current at Any Pin (Note 3) ±10 mA Package Input Current (Note 3) ±20 mA Power Consumption at TA = 25°C See (Note 4) ESD Susceptibility (Note 5) V A, GND, VREF, VOUT, ADR0, ADR1 pins: Human Body Model Machine Model Charged Device Model (CDM) SDA, SCL pins: Human Body Model Machine Model Charged Device Model (CDM) 2500V 250V 1000V 5000V 350V 1000V Junction Temperature +150°C Storage Temperature −65°C to +150°C Operating Ratings (Notes 1, 2) Operating Temperature Range −40°C ≤ TA ≤ +125°C Supply Voltage, VA +2.7V to 5.5V Reference Voltage, VREFIN +1.0V to VA Digital Input Voltage (Note 7) 0.0V to 5.5V Output Load 0 to 1500 pF Package Thermal Resistances Package θJA 6-Lead TSOT 250°C/W 6-Lead LLP 190°C/W 8-Lead MSOP 240°C/W Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to www.national.com/packaging. (Note 6)

Electrical Characteristics

Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREF = VA, CL = 200 pF to GND, input code range 12 to 1011. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified. Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) STATIC PERFORMANCE Resolution 10 Bits (min) Monotonicity 10 Bits (min) INL Integral Non-Linearity +0.6 +2 LSB (max) −0.4 −2 LSB (min) DNL Differential Non-Linearity +0.12 +0.3 LSB (max) −0.04 −0.2 LSB (min) ZE Zero Code Error IOUT = 0 +1.1 +10 mV (max) FSE Full-Scale Error IOUT = 0 −0.1 −0.7 %FSR (max) GE Gain Error All ones Loaded to DAC register −0.2 −0.7 %FSR (max) ZCED Zero Code Error Drift −20 µV/°C TC GE Gain Error Tempco VA = 3V −0.7 ppm FSR/°C VA = 5V −1.0 ppm FSR/°C ANALOG OUTPUT CHARACTERISTICS (VOUT) Output Voltage Range(Note 10) DAC101C085 0 VREF V (min) V (max) DAC101C081 0 VA V (min) V (max) ZCO Zero Code Output VA = 3V, IOUT = 200 µA 1.3 mV VA = 5V, IOUT = 200 µA 7.0 mV FSO Full Scale Output VA = 3V, IOUT = 200 µA 2.984 V VA = 5V, IOUT = 200 µA 4.989 V IOS Output Short Circuit Current (ISOURCE) VA = 3V, VOUT = 0V, Input Code = FFFh. 56 mA VA = 5V, VOUT = 0V, Input Code = FFFh. 69 mA www.national.com 4 DAC101C081/ DAC101C085

Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) IOS Output Short Circuit Current (ISINK) VA = 3V, VOUT = 3V, Input Code = 000h. −52 mA VA = 5V, VOUT = 5V, Input Code = 000h. −75 mA IO Continuous Output Current (Note 10) Available on the DAC output 11 mA (max) CL Maximum Load Capacitance RL = ∞ 1500 pF RL = 2kΩ 1500 pF ZOUT DC Output Impedance 7.5 Ω REFERENCE INPUT CHARACTERISTICS- (DAC101C085 only) VREF Input Range Minimum 0.2 1.0 V (min) Input Range Maximum VA V (max) Input Impedance 120 kΩ LOGIC INPUT CHARACTERISTICS (SCL, SDA) VIH Input High Voltage 0.7 x VA V (min) VIL Input Low Voltage 0.3 x VA V (max) IIN Input Current ±1 µA (max) CIN Input Pin Capacitance (Note 10) 3 pF (max) VHYST Input Hysteresis 0.1 x VA V (min) LOGIC INPUT CHARACTERISTICS (ADR0, ADR1) VIH Input High Voltage VA- 0.5V V (min) VIL Input Low Voltage 0.5 V (max) IIN Input Current ±1 µA (max) LOGIC OUTPUT CHARACTERISTICS (SDA) VOL Output Low Voltage ISINK = 3 mA 0.4 V (max) ISINK = 6 mA 0.6 V (max) IOZ High-Impedence Output Leakage Current ±1 µA (max) 5 www.national.com DAC101C081/ DAC101C085

Symbol Parameter Conditions Typical (Note 9) Limits (Note 9) Units (Limits) POWER REQUIREMENTS VA Supply Voltage Minimum 2.7 V (min) Supply Voltage Maximum 5.5 V (max) Normal -- VOUT set to midscale. 2-wire interface quiet (SCL = SDA = VA). (output unloaded) IST_VA-1 VA DAC101C081 Supply Current VA = 2.7V to 3.6V 105 156 µA (max) VA = 4.5V to 5.5V 132 214 µA (max) IST_VA-5 VA DAC101C085 Supply Current VA = 2.7V to 3.6V 86 118 µA (max) VA = 4.5V to 5.5V 98 152 µA (max) IST_VREF VREF Supply Current (DAC101C085 only) VA = 2.7V to 3.6V 37 43 µA (max) VA = 4.5V to 5.5V 53 61 µA (max) PST Power Consumption (VA & VREF for DAC101C085) VA = 3.0V 380 µW VA = 5.0V 730 µW Continuous Operation -- 2-wire interface actively addressing the DAC and writing to the DAC register. (output unloaded) ICO_VA-1 VA DAC101C081 Supply Current fSCL=400kHz VA = 2.7V to 3.6V 134 220 µA (max) VA = 4.5V to 5.5V 192 300 µA (max) fSCL=3.4MHz VA = 2.7V to 3.6V 225 320 µA (max) VA = 4.5V to 5.5V 374 500 µA (max) ICO_VA-5 VA DAC101C085 Supply Current fSCL=400kHz VA = 2.7V to 3.6V 101 155 µA (max) VA = 4.5V to 5.5V 142 220 µA (max) fSCL=3.4MHz VA = 2.7V to 3.6V 193 235 µA (max) VA = 4.5V to 5.5V 325 410 µA (max) ICO_VREF VREF Supply Current (DAC101C085 only) VA = 2.7V to 3.6V 33.5 55 µA (max) VA = 4.5V to 5.5V 49.5 71.4 µA (max) PCO Power Consumption (VA & VREF for DAC101C085) fSCL=400kHz VA = 3.0V 480 µW VA = 5.0V 1.06 mW fSCL=3.4MHz VA = 3.0V 810 µW VA = 5.0V 2.06 mW Power Down -- 2-wire interface quiet (SCL = SDA = VA) after PD mode written to DAC register. (output unloaded) IPD Supply Current (VA & VREF for DAC101C085) All Power Down Modes VA = 2.7V to 3.6V 0.13 1.52 µA (max) VA = 4.5V to 5.5V 0.15 3.25 µA (max) PPD Power Consumption (VA & VREF for DAC101C085) All Power Down Modes VA = 3.0V 0.5 µW VA = 5.0V 0.9 µW www.national.com 6 DAC101C081/ DAC101C085

A.C. and Timing Characteristics Values shown in this table are design targets and are subject to change before product release. The following specifications apply for VA = +2.7V to +5.5V, VREF = VA, RL = Infinity, CL = 200 pF to GND. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise specified. Symbol Parameter Conditions (Note 13) Typical (Note 9) Limits (Notes 9, 13) Units (Limits) ts Output Voltage Settling Time (Note 10) 100h to 300h code change RL = 2kΩ, CL = 200 pF 4.5 6 µs (max) SR Output Slew Rate 1 V/µs Glitch Impulse Code change from 200h to 1FFh 12 nV-sec Digital Feedthrough 0.5 nV-sec Multiplying Bandwidth(Note 12) VREF = 2.5V ± 0.1Vpp 160 kHz Total Harmonic Distortion(Note 12) VREF = 2.5V ± 0.1Vpp input frequency = 10kHz 70 dB tWU Wake-Up Time VA = 3V 0.8 µsec VA = 5V 0.5 µsec DIGITAL TIMING SPECS (SCL, SDA) fSCL Serial Clock Frequency Standard Mode Fast Mode High Speed Mode, Cb = 100pF High Speed Mode, Cb = 400pF 100 400 3.4 1.7 kHz (max) kHz (max) MHz (max) MHz (max) tLOW SCL Low Time Standard Mode Fast Mode High Speed Mode, Cb = 100pF High Speed Mode, Cb = 400pF 4.7 1.3 160 320 µs (min) µs (min) ns (min) ns (min) tHIGH SCL High Time Standard Mode Fast Mode High Speed Mode, Cb = 100pF High Speed Mode, Cb = 400pF 4.0 0.6 120 µs (min) µs (min) ns (min) ns (min) tSU;DAT Data Setup Time Standard Mode Fast Mode High Speed Mode 250 100 ns (min) ns (min) ns (min) tHD;DAT Data Hold Time Standard Mode 0 3.45 µs (min) µs (max) Fast Mode 0 0.9 µs (min) µs (max) High Speed Mode, Cb = 100pF 0 ns (min) ns (max) High Speed Mode, Cb = 400pF 0 150 ns (min) ns (max) tSU;STA Setup time for a start or a repeated start condition Standard Mode Fast Mode High Speed Mode 4.7 0.6 160 µs (min) µs (min) ns (min) tHD;STA Hold time for a start or a repeated start condition Standard Mode Fast Mode High Speed Mode 4.0 0.6 160 µs (min) µs (min) ns (min) tBUF Bus free time between a stop and start condition Standard Mode Fast Mode 4.7 1.3 µs (min) µs (min) tSU;STO Setup time for a stop condition Standard Mode Fast Mode High Speed Mode 4.0 0.6 160 µs (min) µs (min) ns (min) 7 www.national.com DAC101C081/ DAC101C085

Symbol Parameter Conditions (Note 13) Typical (Note 9) Limits (Notes 9, 13) Units (Limits) trDA Rise time of SDA signal Standard Mode 1000 ns (max) Fast Mode 20+0.1Cb 300 ns (min) ns (max) High Speed Mode, Cb = 100pF 10 ns (min) ns (max) High Speed Mode, Cb = 400pF 20 160 ns (min) ns (max) tfDA Fall time of SDA signal Standard Mode 250 ns (max) Fast Mode 20+0.1Cb 250 ns (min) ns (max) High Speed Mode, Cb = 100pF 10 ns (min) ns (max) High Speed Mode, Cb = 400pF 20 160 ns (min) ns (max) trCL Rise time of SCL signal Standard Mode 1000 ns (max) Fast Mode 20+0.1Cb 300 ns (min) ns (max) High Speed Mode, Cb = 100pF 10 ns (min) ns (max) High Speed Mode, Cb = 400pF 20 ns (min) ns (max) trCL1 Rise time of SCL signal after a repeated start condition and after an acknowledge bit. Standard Mode 1000 ns (max) Fast Mode 20+0.1Cb 300 ns (min) ns (max) High Speed Mode, Cb = 100pF 10 ns (min) ns (max) High Speed Mode, Cb = 400pF 20 160 ns (min) ns (max) tfCL Fall time of a SCL signal Standard Mode 300 ns (max) Fast Mode 20+0.1Cb 300 ns (min) ns (max) High Speed Mode, Cb = 100pF 10 ns (min) ns (max) High Speed Mode, Cb = 400pF 20 ns (min) ns (max) Cb Capacitive load for each bus line (SCL and SDA) 400 pF (max) tSP Pulse Width of spike suppressed (Notes 11, 10) Fast Mode High Speed Mode 50 ns (max) ns (max) toutz SDA output delay (see Section 1.9) Fast Mode High Speed Mode 270 ns (max) ns (max) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended. Note 2: All voltages are measured with respect to GND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed). Note 5: Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged through 0 Ω. Charge device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged. www.national.com 8 DAC101C081/ DAC101C085

Note 6: Reflow temperature profiles are different for lead-free packages. Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of VA, will not cause errors in the conversion result. For example, if VA is 3V, the digital input pins can be driven with a 5V logic device. 30052204 Note 8: To guarantee accuracy, it is required that VA and VREF be well bypassed. Note 9: Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 10: This parameter is guaranteed by design and/or characterization and is not tested in production. Note 11: Spike suppression filtering on SCL and SDA will supress spikes that are less than 50ns for standard-fast mode and less than 10ns for hs-mode. Note 12: Applies to the Multiplying DAC configuration. In this configuration, the reference is used as the analog input. The value loaded in the DAC Register will digitally attenuate the signal at Vout. Note 13: Cb refers to the capacitance of one bus line. Cb is expressed in pF units. Specification Definitions DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB, which is VREF / 1024 = VA / 1024. DIGITAL FEEDTHROUGH is a measure of the energy inject- ed into the analog output of the DAC from the digital inputs when the DAC output is not updated. It is measured with a full-scale code change on the data bus. FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded into the DAC and the value of VA x 1023 / 1024. GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and Full- Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error. GLITCH IMPULSE is the energy injected into the analog out- put when the input code to the DAC register changes. It is specified as the area of the glitch in nanovolt-seconds. INTEGRAL NON-LINEARITY (INL) is a measure of the de- viation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point method is used. INL for this product is specified over a limited range, per the Electrical Tables. LEAST SIGNIFICANT BIT (LSB) is the bit that has the small- est value or weight of all bits in a word. This value is LSB = VREF / 2n where VREF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 10 for the DAC101C081. MAXIMUM LOAD CAPACITANCE is the maximum capaci- tance that can be driven by the DAC with output stability maintained. MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the input code increases. MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of VA. MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3dB below the input sine wave on VREFIN with a full-scale code loaded into the DAC. POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output cur- rents is the power consumed by the device without a load. SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is updated. TOTAL HARMONIC DISTORTION (THD) is the measure of the harmonics present at the output of the DACs with an ideal sine wave applied to VREFIN. THD is measured in dB. WAKE-UP TIME is the time for the output to exit power-down mode. This time is measured from the rising edge of SCL during the ACK bit of the lower data byte to the time the output voltage deviates from the power-down voltage of 0V. ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been entered. 9 www.national.com DAC101C081/ DAC101C085

Typical Performance Characteristics VREF = VA, fSCL = 3.4MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated. INL 30052220 DNL 30052221 INL/DNL vs Temperature at VA = 3.0V 30052222 INL/DNL vs Temperature at VA = 5.0V 30052223 INL/DNL vs VREFIN at VA = 3.0V 30052224 INL/DNL vs VREFIN at VA = 5.0V 30052225 11 www.national.com DAC101C081/ DAC101C085

Zero Code Error vs. VA 30052227 Zero Code Error vs. Temperature 30052228 Full Scale Error vs. VA 30052236 Full Scale Error vs. Temperature 30052229 Total Supply Current vs. VA 30052230 www.national.com 12 DAC101C081/ DAC101C085

VREF Supply Current vs. VA 30052231 Total Supply Current vs. Temperature @ VA = 3V 30052232 Total Supply Current vs. Temperature @ VA = 5V 30052233 5V Glitch Response 30052234 Power-On Reset 30052235 13 www.national.com DAC101C081/ DAC101C085

1.0 Functional Description

1.1 DAC SECTION

are followed by an output buffer. For simplicity, a single resistor string is shown in Figure 3. FIGURE 3. DAC Resistor String

1.2 OUTPUT AMPLIFIER

Electrical Characteristics Table.

1.3 REFERENCE VOLTAGE

The DAC101C081 uses the supply (V A) as the reference. the reference appropriately. Refer to Section 2.1 for details.

1.4 SERIAL INTERFACE

capacitance and operating speed.

1.4.1 Basic I2C Protocol

creates a Stop condition on the bus. the bus varies between Standard-Fast mode and Hs-mode. section 1.4.3 for the full details of a Hs-mode Start condition. Figure 4. The bus continues to operate in the same speed mode as before the Repeated Start condition. curs when SDA is pulled from low to high while SCL is high. generates a Start condition. Jan, 2000) for a detailed description of the serial interface. FIGURE 4. Basic Operation.

1.4.2 Standard-Fast Mode

address doesn't match, the DAC101C081 NACKs the master.

1.4.3 High-Speed (Hs) Mode

bus speed and switching to Hs-mode. FIGURE 5. Beginning Hs-Mode Communication

1.4.4 I2C Slave (Hardware) Address

address the DAC responds to on the I 2C bus (see Table 1). address the DAC via the I2C-Compatible interface. ADR1 inputs TRI-STATE and the slave address is "locked". slave address until the device is power-cycled. TABLE 1. Slave Addresses

0001100 Floating Floating Floating

0001101 Floating GND GND

0001110 Floating VA VA

• Pin-compatible alternatives to the DAC101C081 options are available with additional address options.

1.4.5 Writing to the DAC Register

to the master. The master then sends out the upper data byte. kilo-conversions per second in Hs-mode. FIGURE 6. Typical Write to the DAC Register

1.4.6 Reading from the DAC Register

FIGURE 7. Typical Read from the DAC Register

1.5 DAC REGISTER

operation (normal mode or one of three power-down modes). ACK following the lower data byte. FIGURE 8. DAC Register Contents

1.6 POWER-ON RESET

register is filled with zeros and the output voltage is 0 Volts.

1.7 SIMULTANEOUS RESET

dress, all of the DACs will power-down simultaneously.

1.8 POWER-DOWN MODES

terminated by 100 kΩ to GND (see Figure 8). 0.8µsec at 3V and 0.5µsec at 5V.

1.9 ADDITIONAL TIMING INFORMATION: toutz

SDA bus will be held for a short time by the DAC101C081. to the time when the DAC begins to transition the SDA bus. FIGURE 9. Data Output Timing

2.0 Applications Information

2.1 USING REFERENCES AS POWER SUPPLIES

2.1.1 LM4132

comes in a space-saving 5-pin SOT23. FIGURE 10. The LM4132 as a power supply

2.1.2 LM4050

comes in a space-saving 3-pin SOT23. FIGURE 11. The LM4050 as a power supply

2.1.3 LP3985

SOT23 and 5-bump micro SMD packages. FIGURE 12. Using the LP3985 regulator

2.1.4 LP2980

available in 3.0V, 3.3V and 5V versions, among others. FIGURE 13. Using the LP2980 regulator should be within the range specified in the LP2980 data sheet.

2.2 BIPOLAR OPERATION

should be used if the amplifier supplies are limited to ±5V. FIGURE 14. Bipolar Operation TABLE 2. Some Rail-to-Rail Amplifiers

2.3 DSP/MICROPROCESSOR INTERFACING

2.3.1 Interfacing to the 2-wire Bus

resistors should be used to filter the voltage on SDA and SCL. FIGURE 15. Serial Interface Connection Diagram

2.3.2 Interfacing to a Hs-mode Bus

refer to the I2C Specification for further details.

2.4 LAYOUT, GROUNDING, AND BYPASSING

only be utilized when the fencing technique is inadequate. ous return path below their traces. DAC101C081 should only be used for analog circuits. clock and data lines on the component side of the board.

Physical Dimensions inches (millimeters) unless otherwise noted 6-Lead TSOT Order Numbers DAC101C081CIMK 6-Lead LLP Order Numbers DAC101C081CISD www.national.com 22 DAC101C081/ DAC101C085

Order Numbers DAC101C085CIMM 23 www.national.com DAC101C081/ DAC101C085

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