DAC1008D650_1012 NXP | Alldatasheet
Document overview
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Technical content
- General description The DAC1008D650 is a high-speed 10-bit dual channel Digital-to-Analog Converter (DAC) with selectable 2×, 4× or 8× interpolating filters optimized for multi-carrier WCDMA transmitters. Because of its digital on-chip modulation, the DAC1008D650 allows the complex pattern provided through lane 0, lane 1, lane 2 and lane 3, to be converted up from baseband to IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register. The DAC1008D650 also includes a 2×, 4× or 8× clock multiplier which provides the appropriate internal clocks and an internal regulation to adjust the output full-scale current. The input data format is serial according to JESD204A specification. This new interface has numerous advantages over the traditional parallel one: easy PCB layout, lower radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum number of lanes of the DAC1008D650 is 4 and its maximum serial data rate is 3.125 Gbps. The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output clock period between several DAC devices. MDS incorporates modes: Master/slave and All slave mode. 2. Features and benefits DAC1008D650 Dual 10-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A interface Rev. 2 — 17 December 2010 Product data sheet Dual 10-bit resolution IMD3: 80 dBc; fs =6 4 0M s p s ; fo = 140 MHz 650 Msps maximum update rate ACPR: 64 dBc; two carriers WCDMA; fs = 640 Msps; fo = 133 MHz Selectable 2×, 4× or 8× interpolation filters Typical 1.20 W power dissipation at 4× interpolation, PLL off and 640 Msps Input data rate up to 312.5 Msps Power-down mode and Sleep modes Very low noise cap free integrated PLL Differential scalable output current from 1.6 mA to 22 mA 32-bit programmable NCO frequency On-chip 1.25 V reference Four JESD204A serial input lanes External analog offset control (10-bit auxiliary DACs) 1.8 V and 3.3 V power supplies Internal digital offset control LVDS compatible clock inputs Inverse (sin x) / x function
Table 1. Ordering information
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 2 — 17 December 2010 3 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A 5. Block diagram Fig 1. Block diagram Σ 005aaa160 IOUTBP IOUTBN IOUTAP IOUTAN AUXAP AUXAN sincos OFFSET CONTROL Q DAC SINGLE SIDE BAND MODULATOR X Sin X VIRES GAPOUT Σ Sin X 10-BIT GAIN CONTROL 10-BIT OFFSET CONTROL NCO 32-bit frequency setting 16-bit phase adjustment 10-BIT GAIN CONTROL REF. BANDGAP AND BIASING I DAC AUX. DAC AUXBP AUXBN 10-BIT OFFSET CONTROL AUX. DAC 2 × FIR 2 2 × FIR 1 MULTI-DAC SYNCHRONIZATION 2 × FIR 2 2 × FIR 3 2 × FIR 3 2 × FIR 1 CLOCK GENERATOR UNIT VIN_P3 VIN_N3 DIGITAL LAYER PROCESSING JESD204A SPI CONTROL REGISTERS SDO SDIO SCS_N SCLK CLKINP CLKINN MDS_P MDS_N VIN_P2 VIN_N2 VIN_P1 VIN_N1 VIN_P0 VIN_N0 SYNC_OUTP SYNC_OUTN INTER LANE ALIGNMENT LANE PROC RESET_N DAC1008D650HN LANE PROC LANE PROC LANE PROC FRAME ASSEMBLY
6.1 Pinning
6.2 Pin description
Table 2. Pin description
Table 2. Pin description …continued
[1] P: power supply; G: ground; I: input; O: output. [2] H = heatsink (exposed die pad to be soldered to GND. A minimum of 81 thermal vias are required). [1] Complies with JEDEC test board, in free air. Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Table 4. Thermal characteristics
Table 5. Characteristics maximum sample rate; PLL off unless otherwise specified.
Table 5. Characteristics …continued maximum sample rate; PLL off unless otherwise specified.
maximum sample rate; PLL off unless otherwise specified.
maximum sample rate; PLL off unless otherwise specified.
[1] D = guaranteed by design; C = guaranteed by c haracterization; I = 100 % industrially tested. K28.5 characters in error-free conditions. Figure 15) should be connected across the pins. and the inductance between the receiver and the driver circuit ground voltage. [5] Vin_p and Vin_n inputs are differential CML input s. They are terminated internally to Vtt via 50 Ω (see Figure 4). [7] IMD3 rejection with −6 dBFS/tone.
10.1 General description
DAC1008D650 allows more flexibility for wide bandwidth and multi-carrier systems. interpolation filters which remove undesired images.
- 10-bit/8-bit decoding
- Code group synchronization
- inter-lane alignment
- 1+x 14 +x 15 scrambling polynomial
- Character replacement
- TX/RX synchronization management via SYNC signals
- Multiple Converter Device Alignment-Multiple Lanes (MCDA-ML) device DAC1008D650 can be interfaced with any logic device that features high-speed SERDES functionality. This macro is now widely available in FPGA from different vendors. Standalone SERDES ICs can also be used. To enhance the intrinsic board layout simplification of the JESD204A standard, NXP includes polarity swapping for each of the lanes and additionally offers lane swapping. Each physical lane can be configured logically as lane0, lane1, lane2 or lane3. NSD noise spectral density f s =6 4 0M s p s ; 4× interpolation; fo = 133 MHz at 0 dBFS I- −145 - dBm/Hz
maximum sample rate; PLL off unless otherwise specified.
guaranteed alignment of less than 1 DAC output clock period. information about the JESD204A interface status. separate digital and analog power supply pins. The clock input is LVDS compliant.
10.2 JESD204A receiver
configurable via the SPI registers interface. The complete Digital Layer Processing (DLP) adds a variable delay on each lane path. This is mainly because of the inter-lane alignment. [1] D = guaranteed by design. Table 6. Digital Layer Processing Latency
Product data sheet Rev. 2 — 17 December 2010 13 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A
10.2.1 Lane input
Each lane is CML compliant. It is terminated to a common voltage with an integrated 50Ω resistor. The common-mode voltage is programmable by the SET_VCM_VOLTAGE register as shown in Table 75 on page 55 DC coupling is only possible if both the DAC and the transmitter have the same common-mode voltage. If this is not the case AC coupling is required. The deserializer performs the incoming data clock recovery and also the serial-to-parallel conversion. Therefore, each lane includes its own PLL that must first lock. The clock alignment module transfers the data from the regenerated clock to the frame clock domain. The frequency of both clocks is the same but the phase relationship between the clocks is unknown.
10.2.2 Sync and word align
As stated in JESD204A, the transmitter and the receiver first have to synchronize. This is achieved through SYNC_OUT signals and a sync pattern (K28.5 symbol). The receiver (i.e. DAC1008D650) first drives its SYNC_OUT outputs. The sync pattern is continuously sent until the receiver deasserts the SYNC_OUT signal. Fig 4. Lane input termination Vtt 001aak166 50 Ω Ztt 50 Ω Vin_p Vin_n Fig 5. DC coupling Fig 6. AC coupling 001aak162 50 Ω 50 Ω 50 Ω 50 Ω Zdiff = 100 Ω data in + data in − 001aak163 50 Ω 50 Ω 50 Ω 50 Ω Zdiff = 100 Ω VDD1 VDD2 data in + data in −
Product data sheet Rev. 2 — 17 December 2010 14 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A The lane processing makes use of the sync patterns to synchronize the datastream, determine the initial running disparity and extract the 10-bit word from the incoming datastream (word-alignment). The SYNC_OUT signal is also used during normal operation by the DAC1008D650 to request a link reinitialization. This occurs when the 10b/8b module loses synchronization. The SYNC_OUT signal conforms to LVDS signaling. Its common-mode voltage and its single-ended peak amplitude can be programmed using SET_SYNC_LEVEL bits in the SET_SYNC registers (see Table 77 on page 55). SYNC_OUT is asynchronous with the frame clock. There is no timing specification with respect to the CLKINP and CLKINN inputs.
10.2.3 Comma detection and word align
This stage monitors the datastream for code characters (comma detection), decodes the words to bytes (octets) and performs optional character replacement as part of frame/lane alignment monitoring and correction. This module provides the required control signals to the RX-controller and ILA. This module decodes the 10-bit words into 8-bit words (octets). The decoding table is specified in the IEEE 802.3-2005 specification. During decoding, the disparity is calculated according to the disparity rules mentioned in the same specification IEEE 802.3-2005. When the disparity counter is more than +2 or less than −2, an error will be generated. The following comma symbols are detected during data transmission irrespective of the running disparity: /K/ = K28.5 /F/ = K28.7 /A/ = K28.3 /R/ = K28.0 /Q/ = K28.4 A flag is sent to the control interface to reflect detected commas in registers. The following flags are also triggered according to the following definitions:
- VALID: a code group that is found in the column of the 10b/8b decoding tables according to the current running disparity.
- DISPARITY ERROR: The received code group exists in the 10b/8b decoding table, but is not found in the proper column according to the current running disparity.
- NOT-IN-TABLE (NIT) ERROR: The received code group is not found in the 10b/8b decoding table for either disparity.
- INVALID: a code group that either shows a disparity error or that does not exist in the 10b/8b decoding table. DAC1008D650 supports character replacement whatever the state of the descrambler. When scrambling is not active, the received K28.3 /A/ or K28.7 /F/ will be replaced by the previous sample. When scrambling is active, the corresponding data octet D28.3 (0xC) or D28.7 (0xFC) will be used.
Product data sheet Rev. 2 — 17 December 2010 15 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A
10.2.4 Descrambler
The descrambler is a 16-bit parallel self-synchronous descrambler based on the polynomial 1 + x14 +x 15. This processing can be turned off.
10.2.5 Inter-lane alignment
This feature removes strict PCB design skew compensation between the lanes.
10.2.5.1 Single device operation
This module handles the alignment of the four data streams. Because of inter-lane skew and each PLL per lane concept, these alignment characters may be received at different times by the receivers. After the synchronization period, the lock signal will be HIGH. This enables the receipt of K28.3 /A/ characters. The ILA_CNTRL register’s SEL_ILA[1:0] bits select which K28.3 /A/ symbol triggers the initial lane alignment:“00” =1st /A/ symbol, “01” = 2nd /A/ symbol, “10” = 3rd /A/ symbol, “11” = 4th /A/ symbol; Table 86 on page 61. When all receivers have received their first selected /A/, they start propagating the received data to the frame assembly module at the same point in time. This module can compensate for up to ±7 frame clock period misalignments between the lanes. When initial lane alignment is not supported, the manual alignment mode can be used. After the initial ILA sequence, the lane alignment monitoring starts. If the received user data contains a K28.3 /A/ symbol:
- its position is compared to the value of the alignment monitor counter
- if two successive K28.3 /A/ symbols have been received at a wrong position, a realignment takes place
- if the buffers are empty or overflow, this is indicated by the registers ILA_BUF_ERR_LN0 to ILA_BUF_ERR_LN3
10.2.5.2 Multi-device operation
DAC1008D650 implements a multi-device inter-lane alignment that guarantees a skew of less than one output period between them. Two modes are available: master/slave and all slave. Both make use of the MDS_P and MDS_N pins.
Product data sheet Rev. 2 — 17 December 2010 16 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A Each DAC device of the system generates its own reference (ref_A in Figure 7). If configured as a slave, an early-late comparator compares the internal reference with the external reference provided by the MDS pins. The comparator controls an internal buffer that is used to delay the samples. Fig 7. Multi-Device Synchronization (MDS) implementation 001aal073 I BUFFER Q DIGLANES COMP MDS_Aref_A SYNC~ mds_A_out mds_A CK DAC CLK MGMT
Product data sheet Rev. 2 — 17 December 2010 17 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A
10.2.5.3 Master/slave mode
The external reference is provided by one of the DACs (the master DAC), which has to be configured to do this. The others are set to slave mode. Fig 8. Master-slave mode 001aal070 ref_A SYNC_0 mds_out mds_in I BUFFER Q DIG COMPref_A SYNC_1 mds_out mds_in DAC CLK MGMT I BUFFER MASTER DAC 0 SLAVE DAC 1 SLAVE DAC 2 Q DIG TX COMPref_A SYNC_2 mds_out mds_in DAC CLK MGMT CLOCK DISTRIBUTION REF_CLOCK Q I BUFFERDIG COMP DAC CLK MGMT
Product data sheet Rev. 2 — 17 December 2010 18 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A The MDS signal generated by the master DAC must reach all slaves within one DAC output clock period. This induces PCB layout constraints for the MDS signal and also for the clock distribution. Because trace lengths differ, the clock edges will reach each of the DACs at different times. The worst case clock skew is given by δt1 =P H 0 1− PH03, where PH0x represents the sum of the trace delay and the clock skew at the output of the clock generator. The maximum allowable trace delay for the MDS signal is given by Δt=T D A C−δ t1. Fig 9. Clock skew case 1: Master is the farthest 001aal072 ref clock TDAC master clock PH03 slave 1 clock PH02 slave 2 clock PH01
Product data sheet Rev. 2 — 17 December 2010 19 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A The worst case clock skew is given by δt2 =P H 0 3− PH01. The minimum allowable trace delay for the MDS signal is given by Δt= δt2. In real applications, the master DAC can be anywhere and both conditions must be satisfied: δt2 < Δtmds <T D A C−δ t1. Example:
- clock generator skew = ± 80 ps
- FR4 substrate ⇒ 15 cm/ns delay
- clock trace length difference = 3 cm and 4 cm
- Output sampling rate = 650 Msps ⇒ 200 ps + 80 ps < Δtmds < 1538 ps − (266 ps + 80 ps) ⇒ 280 ps < Δtmds <1 1 9 2p s ⇒ 4.2 cm < Lmds <1 7 . 8c m Fig 10. Clock skew case 2: Master is closest 001aal071 ref clock TDAC master clock PH01 slave 1 clock PH02 slave 2 clock PH03
Product data sheet Rev. 2 — 17 December 2010 20 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A
10.2.5.4 All slave mode
The external reference is provided by the JESD204A transmitter. All DACs are configured in slave mode. The MDS signal is now driven from the transmitter. It is generated at the end of the inter-lane alignment phase (see the JESD204A standard for details). The transmitter must also compensate for the DAC latency. Although the DAC has an internal samples delay line, it cannot handle large delays. In this mode, PCB layout is also important. The following delay equation applies: δt< Δtmds <T D A C−δ t, where δt is the clock skew considered close to DAC pins. Fig 11. All slave mode 001aal069 I BUFFER Q DIG COMPref_A SYNC_0 JESD204A TX mds_out mds_in DAC CLK MGMT I BUFFER Q DIG COMPref_A SYNC_1 mds_out mds_in DAC CLK MGMT I BUFFER SLAVE DAC 0 SLAVE DAC 1 SLAVE DAC 2 Q DIG /A/ INSERTION COMPref_A SYNC_2 MDSdT mds_out mds_in DAC CLK MGMT CLOCK DISTRIBUTION REF_CLOCK
Product data sheet Rev. 2 — 17 December 2010 21 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A
10.2.6 Frame assembly
DAC1008D650 supports only /F/ = 1, which means that every frame clock period carries one byte per lane. Frame assembly combines the octet of lane_0 with the two MSB bits of lane_1 and reassembles the original 10-bit sample. The same is done for lane_2 and lane_3. Tail bits are dropped. The frame assembler also handles previously triggered errors. If scrambling is enabled: If a nit_err (not-in-table error) or kout_unexp (unexpected control character) occurs in lane_0 and/or lane_1, the previous 10-bit sample is repeated twice for I (lane_0, lane_1). The same is done for Q (lane_2, lane_3). If scrambling is disabled: If a nit_err (not-in-table error) or kout_unexp (unexpected control character) occurs in lane_0 and/or lane_1, the previous 10-bit sample will be repeated once for I (lane_0, lane_1). The same is done for Q (lane_2, lane_3).
Product data sheet Rev. 2 — 17 December 2010 22 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A Fig 12. Frame assembly 005aaa153 DAC0 SERIAL CLOCK
3.125 GHz
312.5 MHz
T T T T T T byte 2 F = 1 byte M = 2 converters D09 D08 D07 D06 D05 D04 D03 D02 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 byte 3 D01 D00 T T T T T T encoded octet lane 2 b1b2b3b4b5b6b7b8b9 DESERIALIZER scrambled octet 10b/8b ON/OFF/10 DESCRAMBLER encoded octet lane 3 b1b2b3b4b5b6b7b8b9 DESERIALIZER scrambled octet 10b/8b ON/OFF/10 DESCRAMBLER DAC1
10.3 Serial Periphera l Interface (SPI)
10.3.1 Protocol description
that define the operating modes of the chip in both Write mode and Read mode. instruction byte (see Table 8). decreased after each following data phase. R/W indicates the mode access, (see Table 7). Table 7. Read or Write mode access description
0 Write mode operation
1 Read mode operation
Table 8. Number of bytes to be transferred
10.3.2 SPI timing description
The SPI timing characteristics are given in Table 9. Table 9. SPI timing characteristics
Product data sheet Rev. 2 — 17 December 2010 25 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A
10.4 Clock input
The DAC1008D650 has one differential clock input, CLKINN/CLKINP . The DAC1008D650 can operate with a clock frequency up to 312.5 MHz or up to 650 MHz if the internal PLL is bypassed. The clock input can be LVDS (see Figure 15) but it can also be interfaced with CML (see Figure 16). Error free data transition from one internal clock domain to another one is handled by Clock Domain Interface (CDI) logic. During the reset phase (RESET_N asserted), the clock must be stable and running. This ensures a proper reset of the complete device. The device has no embedded power-on-reset feature. Driving the RESET_N pin to set the device to its default state is mandatory. Fig 15. LVDS clock configuration Fig 16. Interfacing CML to LVDS 001aah021 100 Ω LVDS CLKINP CLKINN LVDS Zdiff = 100 Ω 001aah020 55 Ω 55 Ω 1.1 kΩ 2.2 kΩ 100 nF CML 100 nF 100 nF CLKINP LVDS CLKINN AGND VDDA(1V8) 1 kΩZdiff = 100 Ω
10.5 FIR filters
pass band ripple of less than 0,0005 dB. Table 10. Interpolation filter coefficients
Product data sheet Rev. 2 — 17 December 2010 27 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A
10.6 Quadrature modulator and Numerica lly Controlled Oscillator (NCO)
The quadrature modulator allows the 10-bit I and Q data to be mixed with the carrier signal generated by the NCO. The frequency of the NCO is programmed over 32 bits and the sign of the sine component can be inverted in order to operate positive or negative, lower or upper single sideband up-conversion.
10.6.1 NCO in 32-bit
When using the NCO, the frequency can be set by the four registers FREQNCO_LSB, FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits. The frequency for the NCO in 32-bit is calculated as follows: (1) where M is the decimal representation of FREQ_NCO[31:0]. The phase of the NCO can be set from 0° to 360° by both registers PHINCO_LSB and PHINCO_MSB over 16 bits. The default setting is fNCO = 96 MHz when fs = 640 Msps and the default phase is 0°.
10.6.2 Low-power NCO
When using the low-power NCO, the frequency can be set by the five MSBs of register FREQNCO_MSB. The frequency for the low-power NCO is calculated as follows: (2) where M is the decimal representation of FREQ_NCO[31:27]. The phase of the low-power NCO can be set by the five MSBs of the register PHINCO_MSB.
10.6.3 Minus_3dB
During normal use, a full-scale pattern will also be full-scale at the output of the DAC. Nevertheless, when the I and Q data are simultaneously close to full-scale, some clipping can occur and the minus_3dB function can be used to reduce the gain in the modulator by 3 dB. This is to keep a full-scale range at the output of the DAC without added interferers. 10.7 x / (sin x) The roll-off effect of the DAC causes a selectable FIR filter to be inserted to compensate for the (sin x) / x effect. This filter introduces a DC loss of 3.4 dB. The coefficients are represented in Table 11. fNCO Mf s× fNCO Mf s×
10.8 DAC transfer function
or a two’s complement input. Table 12 shows the output current as a function of the input data, when IO(fs) =2 0m A . Table 11. Inversion filter coefficients Table 12. DAC transfer function
1023 DATA–
Product data sheet Rev. 2 — 17 December 2010 29 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A
10.9 Full-scale current
10.9.1 Regulation
The DAC1008D650 reference circuitry integrates an internal bandgap reference voltage which delivers a 1.25 V reference to the GAPOUT pin. It is recommended to decouple pin GAPOUT using a 100 nF capacitor. The reference current is generated via an external resistor of 909 Ω (1 %) connected to pin VIRES. A control amplifier sets the appropriate full-scale current (IO(fs)) for both DACs (see Figure 17). This configuration is optimum for temperature drift compensation because the bandgap reference voltage can be matched to the voltage across the feedback resistor.
10.9.1.1 External regulation
The DAC current can also be set by applying an external reference voltage to the non-inverting input pin GAPOUT and disabling the internal bandgap reference voltage with bit GAP_PD (register 00h[0]; see Table 18 “COMMON register (address 00h) bit description”).
10.9.2 Full-scale current adjustment
The default full-scale current (IO(fs)) is 20 mA but further adjustments can be made by the user to both DACs independently using the serial interface from 1.6 mA to 22 mA, ± 10 %. The settings applied to DAC_A_GAIN_COARSE[3:0] (register 0Ah; see Table 28 “DAC_A_CFG_2 register (address 0Ah) bit description” and register 0Bh; see Table 29 “DAC_A_CFG_3 register (address 0Bh) bit description”) and DAC_B_GAIN COARSE[3:0] (register 0Dh; see Table 31 “DAC_B_CFG_2 register (address 0Dh) bit description” and register 0Eh; see Table 32 “DAC_B_CFG_3 register (address 0Eh) bit description”) define the coarse variation of the full-scale current (see Table 13). Fig 17. Internal reference configuration 001aaj816 REF . BANDGAP GAPOUT VIRES DAC CURRENT SOURCES ARRAY AGND AGND 100 nF 909 Ω (1 %)
define the fine variation of the full-scale current (see Table 14). The coding of the fine gain adjustment is two’s complement.
10.10 Digital offset correction
offset correction can be used to adjust the common-mode level at the output of the DAC. It adds an offset at the end of the digital part, just before the DAC. Table 13. I O(fs) coarse adjustment Default settings are shown highlighted. Table 14. I Default settings are shown highlighted.
the range of variation of the digital offset (see Table 15).
10.11 Analog output
L to the 3.3 V analog power supply (VDDA(3V3)). improving the dynamic performance of the DAC by introducing less distortion. the following stages and the targeted performances. Table 15. Digital offset adjustment Default settings are shown highlighted.
10.12 Auxiliary DACs
any offset between the DAC and the next stage in the transmission path. Table 16 shows the output current as a function of the auxiliary DAC data. Table 16. Auxiliary DAC transfer function Default settings are shown highlighted.
Product data sheet Rev. 2 — 17 December 2010 33 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A
10.13 Output c onfiguration
10.13.1 Basic output configuration
The use of a differentially-coupled transformer output provides optimum distortion performance (see Figure 19). In addition, it helps to match the impedance and provides electrical isolation. The DAC1008D650 can operate at a Vo(p-p) of 2 V differential outputs. In this configuration, it is recommended to connect the center tap of the transformer to a 62 Ω resistor connected to the 3.3 V analog power supply, in order to adjust the DC common-mode to approximately 2.7 V (see Figure 20 Fig 19. 1 V o(p-p) differential output with transformer Fig 20. 2 V o(p-p) differential output with transformer 001aaj817 50 Ω 50 Ω 50 Ω IOUTnP/IOUTnN; Vo(cm) = 2.8 V; Vo(dif)(p-p) = 1 V IOUTnP IOUTnN 0 mA to 20 mA 2:1 0 mA to 20 mA VDDA(3V3) VDDA(3V3) 001aaj818 50 Ω 100 Ω 100 Ω IOUTnP/IOUTnN; Vo(cm) = 2.7 V; Vo(dif)(p-p) = 2 V IOUTnP IOUTnN 0 mA to 20 mA 4:1 0 mA to 20 mA VDDA(3V3) 62 Ω VDDA(3V3) VDDA(3V3)
Product data sheet Rev. 2 — 17 December 2010 34 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A
10.13.2 DC interface to an Analog Quadrature Modulator (AQM)
When the system operation requires to keep the DC component of the spectrum, the DAC1008D650 must use a DC interface to connect to an AQM. In this case, the offset compensation for LO cancellation can be made with the use of the digital offset control in the DAC. Figure 21 is an example of a connection to an AQM with a common-mode input level (Vi(cm)) of 1.7 V. Figure 22 is an example of a connection to an AQM with a common-mode input level (Vi(cm)) of 3.3 V. The auxiliary DACs can be used to control the offset in a precise range or with precise steps. Fig 21. Example of a DC interface co nnection to an AQM with a Vi(cm) of 1.7 V Fig 22. Example of a DC interface co nnection to an AQM with a Vi(cm) of 3.3 V 001aaj541 51.1 Ω 51.1 Ω 442 Ω 442 Ω VDDA(3V3) IOUTnP IOUTnN 0 mA to 20 mA BBP (1) IOUTnP/IOUTnN; Vo(cm) = 2.67 V; Vo(dif)(p-p) = 1.98 V (2) BBP/BBN; Vi(cm) = 1.7 V; Vi(dif)(p-p) = 1.26 V BBN AQM (Vi(cm) = 1.7 V) 768 Ω 768 Ω (1) (2) 001aaj542 54.9 Ω 54.9 Ω 237 Ω 237 Ω VDDA(3V3) IOUTnP IOUTnN BBP BBN AQM (Vi(cm) = 3.3 V) 750 Ω 750 Ω 5 V 1.27 kΩ 1.27 kΩ (1) IOUTnP/IOUTnN; Vo(cm) = 2.75 V; Vo(dif)(p-p) = 1.97 V (2) BBP/BBN; Vi(cm) = 3.3 V; Vi(dif)(p-p) = 1.5 V (1) (2)
Product data sheet Rev. 2 — 17 December 2010 36 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A
10.13.3 AC interface to an Analog Quadrature Modulator (AQM)
When the AQM common-mode voltage is close to ground, the DAC1008D650 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 25 is an example of a connection to an AQM with a common-mode input level (Vi(cm)) of 0.5 V when using auxiliary DACs. Fig 25. Example of a DC interface co nnection to an AQM with a Vi(cm) of 0.5 V when using auxiliary DACs 001aaj589 66.5 Ω 66.5 Ω 10 nF VDDA(3V3) IOUTnP IOUTnN 0 mA to 20 mA BBP BBN AQM (Vi(cm) = 0.5 V) 2 kΩ 2 kΩ 5 V 174 Ω 174 Ω 34 Ω 34 Ω AUXnP AUXnN 1.1 mA (typ.) 10 nF (1) IOUTnP/IOUTnN; Vo(cm) = 2.65 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; Vi(cm) = 0.5 V; Vi(dif)(p-p) = 1.96 V; offset correction up to 70 mV (1) (2)
Product data sheet Rev. 2 — 17 December 2010 37 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A
10.13.4 Phase correction
The Analog Quadrature Modulator which follows the DACs may have a phase imbalance which will result in undesired sidebands. By adjusting the phase between the I and Q channels, the spur can be reduced. Without compensation the I and Q have a phase difference of Π /2 ( 9 0°). The registers PHASECORR_CNTRL0 and PHASECORR_CNTRL1 located in register page 0 allow a phase variation from 75.7° to 104.3°. The two registers define a signed value that ranges from −512 to +511. The resulting phase compensation (in radians) is given by the equation: PHASE_CORR[9:0] / 2048.
10.14 Power and grounding
The power supplies should be decoupled with the following ground pins to optimize the decoupling:
- VDDA(1V8): pin 38 with pin 37; pin 44 with pin 43; pin 11 with pin 12; pin 17 with pin 18; pin 32 with pin 31
10.15 Configuration interface
10.15.1 Register description
DAC1008D650 implements indirect addressing using a page access method. The page-address is located at address 0x1F and is by default 0x00, which selects page 0 as default page. For example, to access registers which configure the JESDRX, one must first activate page 4 by writing 0x04 to the page-address 0x1F. The DAC1008D650 contains six different pages. The device has no embedded power-on-reset feature. Driving the RESET_N pin to set the device to its default state is mandatory.
10.15.2 Detailed descriptions of registers
The register information has been provided in page form accompanied by a detailed description for each bit in the tables following the register allocation map of each page.
10.15.2.1 Page 0 allocation map description
Table 17. Page 0 register allocation map
10.15.2.2 Page 0 bit definition detailed description
values emphasized in bold are the default values. Table 18. COMMON register (address 00h) bit description Default settings are shown highlighted.
7 SPI_3W R/W serial interface bus type
6 SPI_RST R/W serial interface reset
2 DF R/W data format
1 PD_ALL R/W power-down
0 GAP_PD R/W internal bandgap power-down
Table 19. TXCFG register (address 01h) bit description Default settings are shown highlighted.
7 NCO_EN R/W NCO
6 NCO_LP_SEL R/W low-power NCO
0 NCO may use all 32 bits
1 NCO frequency and phase given by the five
5 INV_SINE_EN R/W x / (sin x) function
Default settings are shown highlighted. Table 20. PLLCFG register (a ddress 02h) bit description Default settings are shown highlighted.
7 PLL_PD R/W PLL
0 PLL_POL R/W clock edge of DAC (f s)
Table 21. FREQNCO_LSB register (address 03h) bit description Table 22. FREQNCO_LISB register (address 04h) bit description Table 23. FREQNCO_UISB register (address 05h) bit description
Table 24. FREQNCO_MSB register (address 06h) bit description Table 25. PHINCO_LSB register (address 07h) bit description Table 26. PHINCO_MSB register (address 08h) bit description Table 27. DAC_A_CFG_1 register (address 09h) bit description Default settings are shown highlighted.
7 DAC_A_PD R/W DAC A power
6 DAC_A_SLEEP R/W DAC A Sleep mode
Table 28. DAC_A_CFG_2 register (address 0Ah) bit description Table 29. DAC_A_CFG_3 register (address 0Bh) bit description
Table 30. DAC_B_CFG_1 register (address 0Ch) bit description Default settings are shown highlighted.
7 DAC_B_PD R/W DAC B power
6 DAC_B_SLEEP R/W DAC B Sleep mode
Table 31. DAC_B_CFG_2 register (address 0Dh) bit description Table 32. DAC_B_CFG_3 register (address 0Eh) bit description Table 33. DAC_CFG register (address 0Fh) bit description Default settings are shown highlighted.
1 MINUS_3DB R/W NCO gain
0 NOISE_SHAPER R/W noise shaper
Table 34. DAC_CURRENT_0 register (address 11h) bit description Default settings are shown highlighted. Table 35. DAC_CURRENT_1 register (address 12h) bit description Default settings are shown highlighted.
Table 36. DAC_CURRENT_2 register (address 13h) bit description Default settings are shown highlighted. Table 37. DAC_CURRENT_3 register (address 14h) bit description Default settings are shown highlighted. Table 38. DAC_SEL_PH_FINE register (address 15h) bit description Default settings are shown highlighted. Table 39. PHASECORR_CNTRL0 register (address 16h) bit description Default settings are shown highlighted. Table 40. PHASECORR_CNTRL1 register (address 17h) bit description Default settings are shown highlighted.
7 PHASE_CORR_ENABLE R/W phase correction
Table 41. DAC_A_AUX_MSB register (address 1Ah) bit description Table 42. DAC_A_AUX_LSB register (address 1Bh) bit description Default settings are shown highlighted.
7 AUX_A_PD R/W auxiliary DAC A power
Table 43. DAC_B_AUX_MSB register (address 1Ch) bit description
Table 44. DAC_B_AUX_LSB register (address 1Dh) bit description Default settings are shown highlighted.
7 AUX_B_PD R/W auxiliary DAC B power
Table 45. DAC_B_AUX_LSB register (address 1Dh) bit description Default settings are shown highlighted. Table 46. Bias current control table Default settings are shown highlighted.
10.15.2.3 Page 1 allocation map description
[1] u = undefined at power-up or after reset. Table 47. Page 1 register allocation map
10.15.2.4 Page 1 bit definition detailed description
tables, all the values emphasized in bold are the default values. Table 48. MDS_MAIN register (address 00h) bit description Default settings are shown highlighted.
5 MDS_RUN R/W evaluation restart
4 MDS_NCO R/W NCO synchronization
1 NCO synchronization enabled
3 MDS_SEL_LN23 R/W synchronization reference
2 MDS_32T_ENA R/W maximum delay
1 MDS_MASTER R/W MDS mode
0 MDS_ENA R/W MDS function
Table 49. MDS_WIN_PERIOD_A register (address 01h) bit description Default settings are shown highlighted. Table 50. MDS_WIN_PERIOD_B register (address 02h) bit description Default settings are shown highlighted.
Table 51. MDS_MISCCNTRL0 register (address 03h) bit description Default settings are shown highlighted.
4 MDS_EVAL_ENA R/W MDS evaluation
3 MDS_PRERUN_ENA R/W automatic MDS start-up
Table 52. MDS_MAN_ADJUSTDLY register (address 04h) bit description Default settings are shown highlighted.
7 MDS_MAN R/W adjustment delay mode
Table 53. MDS_AUTO_CYCLES register (address 05h) bit description Default settings are shown highlighted. Table 54. MDS_MISCCNTRL1 register (address 06h) bit description Default settings are shown highlighted.
7 MDS_SR_CKEN R/W lock mode
1 MDS_CKEN forced LOW
6 MDS_SR_LOCKOUT R/W lockout detector soft reset
0 MDS_SR_LOCKOUT in use
1 MDS_SR_LOCKOUT forced LOW
5 MDS_SR_LOCK R/W lock detector soft reset
0 MDS_SR_LOCK in use
1 MDS_SR_LOCK forced LOW
4 MDS_RELOCK R/W relock mode
Default settings are shown highlighted. Table 55. MDS_ADJDELAY register (address 08h) bit description Default settings are shown highlighted. Table 56. MDS_STATUS0 register (address 09h) bit description Default settings are shown highlighted.
7 EARLY R early signal (sampled) from early-late detector
6 LATE R late signal (sampled) from early-late detector
5 EQUAL R equal signal (sampled) from early-late detector
4 MDS_LOCK R result equal check
3 EARLY_ERROR R adjustment delay maximum value stops the search
2 LATE_ERROR R adjustment delay mi nimum value stops the search
1 EQUAL_FOUND R evaluation logic has detected equal condition
0 MDS_ACTIVE R evaluation logic active
Table 57. MDS_STATUS1 register (address 0Ah) bit description Default settings are shown highlighted.
3 JD_ODD R MDS start mode
0 MDS start aligned to cdi-even sample
1 MDS start aligned to cdi-odd sample (only for ^2)
2 MDS_PRERUN R MDS pre-run phase active flag
1 MDS_LOCKOUT R MDS lockout detected flag
0 MDS_LOCK R MDS lock flag
Table 58. PAGE_ADDRESS register (a ddress 1Fh) bit description Default settings are shown highlighted.
10.15.2.5 Page 2 allocation map description
Table 59. Page 2 register allocation map
10.15.2.6 Page 2 bit definition detailed description
tables, all the values emphasized in bold are the default values. Table 60. MAINCONTROL register (address 00h) bit description Default settings are shown highlighted.
5 FULL_RE_INIT R/W initialization
4 SYNC_INIT_LEVEL R/ W synchronization
1 FORCE_RESET_DCLK R/W reset_dclk
0 FORCE_RESET_FCLK R/W reset_fclk
Table 61. JCLK_CNTRL register (address 03h) bit description Default settings are shown highlighted.
7 SR_CDI R/W cdi reset
2 FCLK_POL R/W f
Table 62. RST_EXT_FCLK register (address 04h) bit description Default settings are shown highlighted. Table 63. RST_EXT_DCLK register (address 05h) bit description Default settings are shown highlighted. Table 64. DCSMU_PREDIVCNT register (address 06h) bit description Default settings are shown highlighted. Table 65. PLL_CHARGETIME register (address 07h) bit description Default settings are shown highlighted. Table 66. PLL_RUN_IN_TIME register (address 08h) bit description Default settings are shown highlighted. Table 67. CA_RUN_IN_TIME register (address 09h) bit description Default settings are shown highlighted. Table 68. SET_VCM_VOLTAGE register (address 16h) bit description Default settings are shown highlighted. Table 69. SET_SYNC register (address 17h) bit description Default settings are shown highlighted.
Table 70. TYPE_ID register (add ress 1Bh) bit description Default settings are shown highlighted.
7 DAC R part type
1 DAC
00 CMOS
01 LVDS
10 JESD204A
4 DUAL R converter structure
Table 71. DAC_VERSION register (address 1Ch) bit description Default settings are shown highlighted. Table 72. DIG_VERSION register (address 1Dh) bit description Default settings are shown highlighted. Table 73. JRX_ANA_VERSION register (address 1Eh) bit description Default settings are shown highlighted. Table 74. PAGE_ADDRESS register (a ddress 1Fh) bit description Default settings are shown highlighted.
Table 75. Lane common-mode voltage adjustment Table 76. SYNC common-mode voltage adjustment Table 77. SYNC swing voltage adjustment
10.15.2.7 Page 4 allocation map description
Table 78. Page 4 register allocation map
Table 78. Page 4 register allocation map …continued
10.15.2.8 Page 4 bit definition detailed description
tables, all the values emphasized in bold are the default values. Table 79. SR_DLP_0 register (address 00h) bit description Default settings are shown highlighted.
7 SR_SWA_LN3 R/W 0 soft reset sync_word_alignment lane 3
6 SR_SWA_LN2 R/W 0 soft reset sync_word_alignment lane 2
5 SR_SWA_LN1 R/W 0 soft reset sync_word_alignment lane 1
4 SR_SWA_LN0 R/W 0 soft reset sync_word_alignment lane 0
3 SR_CA_LN3 R/W 0 soft reset clock_alignment lane 3
2 SR_CA_LN2 R/W 0 soft reset clock_alignment lane 2
1 SR_CA_LN1 R/W 0 soft reset clock_alignment lane 1
0 SR_CA_LN0 R/W 0 soft reset clock_alignment lane 0
Table 80. SR_DLP_1 register (address 01h) bit description Default settings are shown highlighted.
7 SR_CNTRL_LN3 R/W 0 soft reset controller lane 3
6 SR_CNTRL_LN2 R/W 0 soft reset controller lane 2
5 SR_CNTRL_LN1 R/W 0 soft reset controller lane 1
4 SR_CNTRL_LN0 R/W 0 soft reset controller lane 0
3 SR_DEC_LN3 R/W 0 soft reset decoder_10b8b lane 3
2 SR_DEC_LN2 R/W 0 soft reset decoder_10b8b lane 2
1 SR_DEC_LN1 R/W 0 soft reset decoder_10b8b lane 1
0 SR_DEC_LN0 R/W 0 soft reset decoder_10b8b lane 0
Table 81. FORCE_LOCK register (address 02h) bit description Default settings are shown highlighted.
7 FORCE_LOCK_LN3 R/W lane 3 lock mode
6 FORCE_LOCK_LN2 R/W lane 2 lock mode
5 FORCE_LOCK_LN1 R/W lane 1 lock mode
4 FORCE_LOCK_LN0 R/W lane 0 lock mode
0 SR_ILA R/W soft reset inter-lane alignment
Default settings are shown highlighted. Table 82. MAN_LOCK_LN_1_0 register (address 03h) bit description Default settings are shown highlighted. Table 83. MAN_LOCK_2_0 register (address 04h) bit description Default settings are shown highlighted. Table 84. CA_CNTRL register (address 05h) bit description
7 WORD_SWAP_LN3 R/W lane 3 bit swapping
6 WORD_SWAP_LN2 R/W lane 2 bit swapping
5 WORD_SWAP_LN1 R/W lane 1 bit swapping
4 WORD_SWAP_LN0 R/W lane 0 bit swapping
3 SELECT_RF_F10_LN3 R/W lane 3 sampling mode
2 SELECT_RF_F10_LN2 R/W lane 2 sampling mode
1 SELECT_RF_F10_LN1 R/W lane 1 sampling mode
0 SELECT_RF_F10_LN0 R/W lane 0 sampling mode
Table 85. SCR_CNTRL register (address 06h) bit description
7 MAN_SCR_LN3 R/W lane 3 manual scrambling
6 MAN_SCR_LN2 R/W lane 2 manual scrambling
5 MAN_SCR_LN1 R/W lane 1 manual scrambling
4 MAN_SCR_LN0 R/W lane 0 manual scrambling
3 FORCE_SCR_LN3 R/W lane 3 scrambling mode
2 FORCE_SCR_LN2 R/W lane 2 scrambling mode
1 FORCE_SCR_LN1 R/W lane 1 scrambling mode
0 FORCE_SCR_LN0 R/W lane 0 scrambling mode
Table 86. ILA_CNTRL register (address 07h) bit description
7 SEL_421_211 R/W inter-lane alignment mode
1 SUP_LANE_SYN R/W inter-lane alignment enable
0 EN_SCR R/W data descrambling
Table 87. FORCE_ALIGN register (address 08h) bit description
1 DYN_ALIGN_ENA R/W dynamic re-alignment mode
0 FORCE_ALIGN R/W lane alignment mode
Table 88. MAN_ALIGN_LN_0_1 register (address 09h) bit description
Table 89. MAN_ALIGN_LN_2_3 register (address 0Ah) bit description Table 90. FA_ERR_HANDLING register (address 0Bh) bit description Default settings are shown highlighted.
Table 91. SYNCOUT_MODE register (address 0Ch) bit description Default settings are shown highlighted.
4 SYNC_POL R/W synchronization polarity
Table 92. LANE_POLARITY register (address 0Dh) bit description
3 POL_LN3 R/W lane 3 data polarity
2 POL_LN2 R/W lane 2 data polarity
1 POL_LN1 R/W lane 1 data polarity
0 POL_LN0 R/W lane 0 data polarity
Table 93. LANE_SELECT register (address 0Eh) bit description Default settings are shown highlighted. Table 94. SOFT_RESET_SCRAMBLER regist er (address 10h) bit description
3 SR_SCR_LN3 R/W lane 3 scrambler reset
2 SR_SCR_LN2 R/W lane 2 scrambler reset
1 SR_SCR_LN1 R/W lane 1 scrambler reset
0 SR_SCR_LN0 R/W lane 0 scrambler reset
Table 95. INIT_SCR_S15T8_LN0 register (address 11h) bit description
Table 96. INIT_SCR_S7T1_LN0 (address 12h) bit description Table 97. INIT_SCR_S15T8_LN1 register (address 13h) bit description Table 98. INIT_SCR_S7T1_LN1 register (address 14h) bit description Table 99. INIT_SCR_S15T8_LN2 register (address 15h) bit description Table 100. INIT_SCR_S7T1_LN2 register (address 16h) bit description Table 101. INIT_SCR_S15T8_LN3 register (address 17h) bit description Table 102. INIT_SCR_S7T1_LN3 register (address 18h) bit description Table 103. INIT_ILA_BUFPTR_LN01 register (address 19h) bit description Table 104. INIT_ILA_BUFPTR_LN23 register (address 1Ah) bit description
Table 105. ERROR_HANDLING register (address 1Bh) bit description Default settings are shown highlighted.
6 NAD_ERR_CORR R/W frame assembler (fa)
5 KUX_CORR R/W K-character error mode
4 NAD_CORR R/W nad error mode
1 IMPL_ALT R/W disparity error detection configuration
0 IGNORE_ERR R/W general error mode
Table 106. REINIT_CNTRL register (address 1Ch) bit description Default settings are shown highlighted.
7 REINIT_ILA_LN3 R/W lane 3, ila-buffer out-of-range check
6 REINIT_ILA_LN2 R/W lane 2, ila-buffer out-of-range check
5 REINIT_ILA_LN1 R/W lane 1, ila-buffer out-of-range check
4 REINIT_ILA_LN0 R/W lane 0, ila-buffer out-of-range check
3 RESYNC_O_L_LN3 R/W lane 3, resync over link
2 RESYNC_O_L_LN2 R/W lane 2, resync over link
1 RESYNC_O_L_LN1 R/W lane 1, resync over link
0 RESYNC_O_L_LN0 R/W lane 0, resync over link
Default settings are shown highlighted. Table 107. PAGE_ADDRESS register (address 1Fh) bit description
10.15.2.9 Page 5 allocation map description
Table 108. Page 5 register allocation map
[1] u = undefined at power-up or after reset. Table 108. Page 5 register allocation map …continued
10.15.2.10 Page 5 bit defi nition detailed description
tables, all the values emphasized in bold are the default values. Table 109. ILA_MON_1_0 register (address 00h) bit description Default settings are shown highlighted. Table 110. ILA_MON_3_2 register (address 01h) bit description Default settings are shown highlighted. Table 111. ILA_BUF_ERR register (address 02h) bit description Default settings are shown highlighted.
3 ILA_BUF_ERR_LN3 R lane 3 ila buffer error
2 ILA_BUF_ERR_LN2 R lane 2 ila buffer error
1 ILA_BUF_ERR_LN1 R lane 1 ila buffer error
0 ILA_BUF_ERR_LN0 R lane 0 ila buffer error
Table 112. CA_MON register (address 03h) bit description Default settings are shown highlighted.
Table 113. DEC_FLAGS register (address 04h) bit description
7 DEC_NIT_ERR_LN3 R - not-in-table error flag lane 3
6 DEC_NIT_ERR_LN2 R - not-in-table error flag lane 2
5 DEC_NIT_ERR_LN1 R - not-in-table error flag lane 1
4 DEC_NIT_ERR_LN0 R - not-in-table error flag lane 0
3 DEC_DISP_ERR_LN3 R - disparity error flag lane 3
2 DEC_DISP_ERR_LN2 R - disparity error flag lane 2
1 DEC_DISP_ERR_LN1 R - disparity error flag lane 1
0 DEC_DISP_ERR_LN0 R - disparity error flag lane 0
Table 114. KOUT_FLAG register (address 05h) bit description
3 DEC_KOUT_LN3 R - /K/ symbols found in lane 3
2 DEC_KOUT_LN2 R - /K/ symbols found in lane 2
1 DEC_KOUT_LN1 R - /K/ symbols found in lane 1
0 DEC_KOUT_LN0 R - /K/ symbols found in lane 0
Table 115. K28_LN0_FLAG register (address 06h) bit description
4 K28_7_LN0 R - K28_7 /F/ symbols found in lane 0
3 K28_5_LN0 R - K28_5 /K/ symbols found in lane 0
2 K28_4_LN0 R - K28_4 /Q/ symbols found in lane 0
1 K28_3_LN0 R - K28_3 /A/ symbols found in lane 0
0 K28_0_LN0 R - K28_0 /R/ symbols found in lane 0
Table 116. K28_LN1_FLAG register (address 07h) bit description
4 K28_7_LN1 R - K28_7 /F/ symbols found in lane 1
3 K28_5_LN1 R - K28_5 /K/ symbols found in lane 1
2 K28_4_LN1 R - K28_4 /Q/ symbols found in lane 1
1 K28_3_LN1 R - K28_3 /A/ symbols found in lane 1
0 K28_0_LN1 R - K28_0 /R/ symbols found in lane 1
Table 117. K28_LN2_FLAG register (address 08h) bit description
4 K28_7_LN2 R - K28_7 /F/ symbols found in lane 2
3 K28_5_LN2 R - K28_5 /K/ symbols found in lane 2
2 K28_4_LN2 R - K28_4 /Q/ symbols found in lane 2
1 K28_3_LN2 R - K28_3 /A/ symbols found in lane 2
0 K28_0_LN2 R - K28_0 /R/ symbols found in lane 2
Table 118. K28_LN3_FLAG register (address 09h) bit description
4 K28_7_LN3 R - K28_7 /F/ symbols found in lane 3
3 K28_5_LN3 R - K28_5 /K/ symbols found in lane 3
2 K28_4_LN3 R - K28_4 /Q/ symbols found in lane 3
1 K28_3_LN3 R - K28_3 /A/ symbols found in lane 3
0 K28_0_LN3 R - K28_0 /R/ symbols found in lane 3
Table 119. KOUT_UNEXPECTED_ FLAG register (address 0Ah) bit description
3 DEC_KOUT_UNEXP_LN3 R - unexpected /K/ symbols found in lane 3
2 DEC_KOUT_UNEXP_LN2 R - unexpected /K/ symbols found in lane 2
1 DEC_KOUT_UNEXP_LN1 R - unexpected /K/ symbols found in lane 1
0 DEC_KOUT_UNEXP_LN0 R - unexpected /K/ symbols found in lane 0
Table 120. LOCK_CNT_MON_LN01 register (address 0Bh) bit description Default settings are shown highlighted. Table 121. LOCK_CNT_MON_LN23 register (address 0Ch) bit description Default settings are shown highlighted. Table 122. CS_STATE_LNX register (address 0Dh) bit description Default settings are shown highlighted. Table 123. RST_BUF_ERR_FLAGS register (address 0Eh) bit description Default settings are shown highlighted.
7 RST_BUF_ERR_FLAGS R/W 0 reset ILA_BUF_ERR_LNn flags
Table 124. INTR_MISC_ENA register (address 0Fh) bit description Default settings are shown highlighted.
7 INTR_ENA_CS_INIT_LN3 R/W 0 intr_misc in case cs_state_ln3 = cs_init
6 INTR_ENA_CS_INIT_LN2 R/W 0 intr_misc in case cs_state_ln2 = cs_init
5 INTR_ENA_CS_INIT_LN1 R/W 0 intr_misc in case cs_state_ln1 = cs_init
4 INTR_ENA_CS_INIT_LN0 R/W 0 intr_misc in case cs_state_ln0 = cs_init
3 INTR_ENA_BUF_ERR_LN3 R/W 0 generate interrupt if ILA_BUF_ERR_LN3 = 1
2 INTR_ENA_BUF_ERR_LN2 R/W 0 generate interrupt if ILA_BUF_ERR_LN2 = 1
1 INTR_ENA_BUF_ERR_LN1 R/W 0 generate interrupt if ILA_BUF_ERR_LN1 = 1
0 INTR_ENA_BUF_ERR_LN0 R/W 0 generate interrupt if ILA_BUF_ERR_LN0 = 1
Table 125. FLAG_CNT_LSB_LN0 register (address 10h) bit description Default settings are shown highlighted. Table 126. FLAG_CNT_MSB_LN0 regist er (address 11h) bit description Default settings are shown highlighted. Table 127. FLAG_CNT_LSB_LN1 register (address 12h) bit description Default settings are shown highlighted. Table 128. FLAG_CNT_MSB_LN1 regist er (address 13h) bit description Default settings are shown highlighted. Table 129. FLAG_CNT_LSB_LN2 register (address 14h) bit description Default settings are shown highlighted. Table 130. FLAG_CNT_MSB_LN2 regist er (address 15h) bit description Default settings are shown highlighted. Table 131. FLAG_CNT_LSB_LN3 register (address 16h) bit description Default settings are shown highlighted.
Table 132. FLAG_CNT_MSB_LN3 regist er (address 17h) bit description Default settings are shown highlighted. Table 133. BER_LEVEL_LSB register (address 18h) bit description Default settings are shown highlighted. Table 134. BER_LEVEL_MSB register (address 19h) bit description Default settings are shown highlighted. Table 135. INTR_ENA register (address 1Ah) bit description
7 INTR_ENA_NIT R/W not-in-table interrupt
6 INTR_ENA_DISP R/W disparity-error interrupt
5 INTR_ENA_KOUT R/W K-character interrupt
4 INTR_ENA_KOUT_UNEXP R/W unexpected K-character interrupt
3 INTR_ENA_K28_7 R/W K28_7 interrupt
2 INTR_ENA_K28_5 R/W K28_5 interrupt
1 INTR_ENA_K28_3 R/W K28_3 interrupt
0 INTR_ENA_MISC R/W miscellaneous interrupt
Table 136. CNTRL_FLAGCNT_LN01 register (address 1Bh) bit description Default settings are shown highlighted.
7 RST_CFC_LN1 R/W 0 reset FLAG_CNT_LN1
3 RST_CFC_LN0 R/W 0 reset FLAG_CNT_LN0
Table 137. CNTRL_FLAGCNT_LN23 register (address 1Ch) bit description Default settings are shown highlighted.
7 RST_CFC_LN3 R/W 0 reset FLAG_CNT_LN3
3 RST_CFC_LN2 R/W 0 reset FLAG_CNT_LN2
Table 138. MON_FLAGS_RESET register (address 1Dh) bit description
7 RST_NIT_ERR-FLAGS R/W 0 reset nit-error monitor flags
6 RST_DISP_ERR_FLAGS R/W 0 res et disparity monitor flags
5 RST_KOUT_FLAGS R/W 0 reset K symbols monitor flags
4 RST_KOUT_UNEXPECTED_FLA GS R/W 0 reset unexpected K symbols monitor flags
3 RST_K28_LN3_FLAGS R/W 0 reset K28_x monitor flags for lane 3
2 RST_K28_LN2_FLAGS R/W 0 reset K28_x monitor flags for lane 2
1 RST_K28_LN1_FLAGS R/W 0 reset K28_x monitor flags for lane 1
0 RST_K28_LN0_FLAGS R/W 0 reset K28_x monitor flags for lane 0
Table 139. DBG_CNTRL register (a ddress 1Eh) bit description
7 BER_MODE R/W simple BER-measurement
6 INTR_CLEAR R/W interrupts clear
Table 140. PAGE_ADDRESS register (address 1Fh) bit description Table 141. Counter source Default settings are shown highlighted.
010 K symbol found
100 K28_7 (/F/) symbol found
101 K28_5 (/K/) symbol found
110 K28_3 (/A/) symbol found
111 K28_0 (/R/) symbol found
Table 142. Code group synchronization state machine
10.15.2.11 Page 6 allocation map description
Table 143. Page 6 register allocation map
[1] u = undefined at power-up or after reset.
10.15.2.12 Page 6 bit defi nition detailed description
tables, all the values emphasized in bold are the default values. Table 144. LN0_CFG_0 register (a ddress 00h) bit description Default settings are shown highlighted. Table 145. LN0_CFG_1 register (a ddress 01h) bit description Default settings are shown highlighted. Table 146. LN0_CFG_2 register (a ddress 02h) bit description Default settings are shown highlighted. Table 147. LN0_CFG_3 register (a ddress 03h) bit description Default settings are shown highlighted.
7 LN0_SCR R - scrambling on
Table 148. LN0_CFG_4 register (a ddress 04h) bit description Default settings are shown highlighted. Table 149. LN0_CFG_5 register (a ddress 05h) bit description Default settings are shown highlighted. Table 150. LN0_CFG_6 register (a ddress 06h) bit description Default settings are shown highlighted. Table 151. LN0_CFG_7 register (a ddress 07h) bit description Default settings are shown highlighted.
Table 152. LN0_CFG_8 register (a ddress 08h) bit description Default settings are shown highlighted. Table 153. LN0_CFG_9 register (a ddress 09h) bit description Default settings are shown highlighted. Table 154. LN0_CFG_10 register (a ddress 0Ah) bit description Default settings are shown highlighted.
7 LN0_HD R - high density
Table 155. LN0_CFG_11 register (address 0Bh) bit description Default settings are shown highlighted. Table 156. LN0_CFG_12 register (a ddress 0Ch) bit description Default settings are shown highlighted. Table 157. LN0_CFG_13 register (a ddress 0Dh) bit description Default settings are shown highlighted. Table 158. LN1_CFG_0 register (a ddress 10h) bit description Default settings are shown highlighted. Table 159. LN1_CFG_1 register (address 11h) bit description Default settings are shown highlighted. Table 160. LN1_CFG_2 register (a ddress 12h) bit description Default settings are shown highlighted.
Table 161. LN1_CFG_3 register (a ddress 13h) bit description Default settings are shown highlighted.
7 LN1_SCR R - scrambling on
Table 162. LN1_CFG_4 register (a ddress 14h) bit description Default settings are shown highlighted. Table 163. LN1_CFG_5 register (a ddress 15h) bit description Default settings are shown highlighted. Table 164. LN1_CFG_6 register (a ddress 16h) bit description Default settings are shown highlighted. Table 165. LN1_CFG_7 register (a ddress 17h) bit description Default settings are shown highlighted. Table 166. LN1_CFG_8 register (a ddress 18h) bit description Default settings are shown highlighted. Table 167. LN1_CFG_9 register (a ddress 19h) bit description Default settings are shown highlighted. Table 168. LN1_CFG_10 register (a ddress 1Ah) bit description Default settings are shown highlighted.
Table 169. LN1_CFG_11 register (address 1Bh) bit description Default settings are shown highlighted. Table 170. LN1_CFG_12 register (a ddress 1Ch) bit description Default settings are shown highlighted. Table 171. LN1_CFG_13 register (a ddress 1Dh) bit description Default settings are shown highlighted. Table 172. PAGE_ADDRESS register (address 1Fh) bit description Default settings are shown highlighted.
10.15.2.13 Page 7 allocation map description
Table 173. Page 7 register allocation map
[1] u = undefined at power-up or after reset.
10.15.2.14 Page 7 bit defi nition detailed description
tables, all the values emphasized in bold are the default values. Table 174. LN2_CFG_0 register (a ddress 00h) bit description Default settings are shown highlighted. Table 175. LN2_CFG_1 register (a ddress 01h) bit description Default settings are shown highlighted. Table 176. LN2_CFG_2 register (a ddress 02h) bit description Default settings are shown highlighted. Table 177. LN2_CFG_3 register (a ddress 03h) bit description Default settings are shown highlighted.
7 LN2_SCR R - scrambling on
Table 178. LN2_CFG_4 register (a ddress 04h) bit description Default settings are shown highlighted. Table 179. LN2_CFG_5 register (a ddress 05h) bit description Default settings are shown highlighted. Table 180. LN2_CFG_6 register (a ddress 06h) bit description Default settings are shown highlighted. Table 181. LN2_CFG_7 register (a ddress 07h) bit description Default settings are shown highlighted.
Table 182. LN2_CFG_8 register (a ddress 08h) bit description Default settings are shown highlighted. Table 183. LN2_CFG_9 register (a ddress 09h) bit description Default settings are shown highlighted. Table 184. LN2_CFG_10 register (a ddress 0Ah) bit description Default settings are shown highlighted.
7 LN2_HD R - high density
Table 185. LN2_CFG_11 register (address 0Bh) bit description Default settings are shown highlighted. Table 186. LN2_CFG_12 register (a ddress 0Ch) bit description Default settings are shown highlighted. Table 187. LN2_CFG_13 register (a ddress 0Dh) bit description Default settings are shown highlighted. Table 188. LN3_CFG_0 register (a ddress 10h) bit description Default settings are shown highlighted. Table 189. LN3_CFG_1 register (address 11h) bit description Default settings are shown highlighted. Table 190. LN3_CFG_2 register (a ddress 12h) bit description Default settings are shown highlighted.
Table 191. LN3_CFG_3 register (a ddress 13h) bit description Default settings are shown highlighted.
7 LN3_SCR R - scrambling on
Table 192. LN3_CFG_4 register (a ddress 14h) bit description Default settings are shown highlighted. Table 193. LN3_CFG_5 register (a ddress 15h) bit description Default settings are shown highlighted. Table 194. LN3_CFG_6 register (a ddress 16h) bit description Default settings are shown highlighted. Table 195. LN3_CFG_7 register (a ddress 17h) bit description Default settings are shown highlighted. Table 196. LN3_CFG_8 register (a ddress 18h) bit description Default settings are shown highlighted. Table 197. LN3_CFG_9 register (a ddress 19h) bit description Default settings are shown highlighted. Table 198. LN3_CFG_10 register (a ddress 1Ah) bit description Default settings are shown highlighted.
7 LN3_HD R - high density
Table 199. LN3_CFG_11 register (address 1Bh) bit description Default settings are shown highlighted. Table 200. LN3_CFG_12 register (a ddress 1Ch) bit description Default settings are shown highlighted. Table 201. LN3_CFG_13 register (a ddress 1Dh) bit description Default settings are shown highlighted. Table 202. PAGE_ADDRESS register (address 1Fh) bit description Default settings are shown highlighted.
Product data sheet Rev. 2 — 17 December 2010 89 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A 11. Package outline Fig 26. Package outline SOT804 (HVQFN64) ReferencesOutline version European projection Issue date IEC JEDEC JEITA sot804-3_po Unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.30 0.21 0.18 0.2 9.1 9.0 8.9 9.1 9.0 8.9 0.5 0.1 0.05 A Dimensions Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm SOT804-3 A1 bc D (1) 0.1 y1Dh 7.25 7.10 6.95 E (1) Eh 7.25 7.10 6.95 ee 7.5 7.5 L 0.5 0.4 0.3 vw 0.05 y 0 2.5 5 mm scale terminal 1 index area terminal 1 index area BD A E b e AC Bv Cw17 32 e Dh 4964 Eh L C yCy1 X detail X A1A c 1/2 e 1/2 e 09-02-24 10-08-06
Table 203. Abbreviations
Table 204. Revision history
- Data sheet status changed from Preliminary to Product.
- Text and drawings updated throughout entire data sheet.
- Values in Table 5 “Characteristics” have been updated.
- Section 10.2.2 “Sync and word align” has been updated.
- Table 142 “Code group synchronization state machine” added to the data sheet. DAC1008D650 v.1 20101001 Preliminary data sheet - -
Product data sheet Rev. 2 — 17 December 2010 92 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A 14. Legal information
14.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This docu ment contains the product specification.
Product data sheet Rev. 2 — 17 December 2010 93 of 98 NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
Table 13. I Table 18. COMMON register (address 00h) Table 19. TXCFG register (address 01h) Table 20. PLLCFG register (address 02h) Table 21. FREQNCO_LSB register (address 03h) Table 22. FREQNCO_LISB register (address 04h) Table 23. FREQNCO_UISB register (address 05h) Table 24. FREQNCO_MSB register (address 06h) Table 25. PHINCO_LSB r egister (address 07h) Table 26. PHINCO_MSB register (address 08h) Table 27. DAC_A_CFG_1 register (address 09h) Table 28. DAC_A_CFG_2 register (address 0Ah) Table 29. DAC_A_CFG_3 register (address 0Bh) Table 30. DAC_B_CFG_1 register (address 0Ch) Table 31. DAC_B_CFG_2 register (address 0Dh) Table 32. DAC_B_CFG_3 register (address 0Eh) Table 33. DAC_CFG register (address 0Fh) Table 34. DAC_CURRENT_0 register (address 11h) Table 35. DAC_CURRENT_1 register (address 12h) Table 36. DAC_CURRENT_2 register (address 13h) Table 37. DAC_CURRENT_3 register (address 14h) Table 38. DAC_SEL_PH_FINE register (address 15h) Table 39. PHASECORR_CNTRL0 register Table 40. PHASECORR_CNTRL1 register Table 41. DAC_A_AUX_MSB register (address 1Ah) Table 42. DAC_A_AUX_LSB register (address 1Bh) Table 43. DAC_B_AUX_MSB register (address 1Ch) Table 44. DAC_B_AUX_LSB register (address 1Dh) Table 45. DAC_B_AUX_LSB register (address 1Dh) Table 48. MDS_MAIN register (address 00h) Table 49. MDS_WIN_PERIOD_A register Table 50. MDS_WIN_PERIOD_B register Table 51. MDS_MISCCNTRL0 register Table 52. MDS_MAN_ADJUSTDLY register Table 53. MDS_AUTO_CYCLES register (address 05h) Table 54. MDS_MISCCNTRL1 register (address 06h) Table 55. MDS_ADJDELAY register (address 08h) Table 56. MDS_STATUS0 register (address 09h) Table 57. MDS_STATUS1 register (address 0Ah) Table 58. PAGE_ADDRESS register (address 1Fh)
Table 60. MAINCONTROL r egister (address 00h) Table 61. JCLK_CNTRL register (address 03h) Table 62. RST_EXT_FCLK register (address 04h) Table 63. RST_EXT_DCLK register (address 05h) Table 64. DCSMU_PREDIVCNT register (address 06h) Table 65. PLL_CHARGETIME register (address 07h) Table 66. PLL_RUN_IN_TIME register (address 08h) Table 67. CA_RUN_IN_TIME register (address 09h) Table 68. SET_VCM_VOLTAGE register (address 16h) Table 69. SET_SYNC register (address 17h) Table 70. TYPE_ID register (address 1Bh) Table 71. DAC_VERSION register (address 1Ch) Table 72. DIG_VERSION register (address 1Dh) Table 73. JRX_ANA_VERSION register (address 1Eh) Table 74. PAGE_ADDRESS register (address 1Fh) Table 79. SR_DLP_0 register (address 00h) Table 80. SR_DLP_1 register (address 01h) Table 81. FORCE_LOCK register (address 02h) Table 82. MAN_LOCK_LN_1_0 register (address 03h) Table 83. MAN_LOCK_2_0 register (address 04h) Table 84. CA_CNTRL register (address 05h) Table 85. SCR_CNTRL register (address 06h) Table 86. ILA_CNTRL register (address 07h) Table 87. FORCE_ALIGN register (address 08h) Table 88. MAN_ALIGN_LN_0_1 register (address 09h) Table 89. MAN_ALIGN_LN_2_3 register (address 0Ah) Table 90. FA_ERR_HANDLING register (address 0Bh) Table 91. SYNCOUT_MODE register (address 0Ch) Table 92. LANE_POLARITY register (address 0Dh) Table 93. LANE_SELECT register (address 0Eh) Table 94. SOFT_RESET_S CRAMBLER register Table 95. INIT_SCR_S15T8_LN0 register (address 11h) Table 96. INIT_SCR_S7T1_LN0 (address 12h) Table 97. INIT_SCR_S15T8_LN1 register (address 13h) Table 98. INIT_SCR_S7T1_LN1 register (address 14h) Table 99. INIT_SCR_S15T8_LN2 register (address 15h) Table 100. INIT_SCR_S7T1_LN2 register (address 16h) Table 101. INIT_SCR_S15T8_LN3 register (address 17h) Table 102. INIT_SCR_S7T1_LN3 register (address 18h) Table 103. INIT_ILA_BUFPTR_LN01 register (address 19h) Table 104. INIT_ILA_BUFPTR_LN23 register (address 1Ah) Table 105. ERROR_HANDLING register (address 1Bh) Table 106. REINIT_CNTRL register (address 1Ch) Table 107. PAGE_ADDRESS register (address 1Fh) Table 109. ILA_MON_1_0 register (address 00h) Table 110. ILA_MON_3_2 register (address 01h) Table 111. ILA_BUF_ERR register (address 02h) Table 112. CA_MON register (address 03h)
Table 113. DEC_FLAGS register (address 04h) Table 114. KOUT_FLAG register (address 05h) Table 115. K28_LN0_FLAG register (address 06h) Table 116. K28_LN1_FLAG register (address 07h) Table 117. K28_LN2_FLAG register (address 08h) Table 118. K28_LN3_FLAG register (address 09h) Table 119. KOUT_UNEXPECTED_FLAG register Table 120. LOCK_CNT_MON_LN01 register Table 121. LOCK_CNT_MON_LN23 register Table 122. CS_STATE_LNX register (address 0Dh) Table 123. RST_BUF_ERR_FLAGS register Table 124. INTR_MISC_ENA register (address 0Fh) Table 125. FLAG_CNT_LSB_LN0 register (address 10h) Table 126. FLAG_CNT_MSB_LN0 register (address 11h) Table 127. FLAG_CNT_LSB_LN1 register (address 12h) Table 128. FLAG_CNT_MSB_LN1 register (address 13h) Table 129. FLAG_CNT_LSB_LN2 register (address 14h) Table 130. FLAG_CNT_MSB_LN2 register (address 15h) Table 131. FLAG_CNT_LSB_LN3 register (address 16h) Table 132. FLAG_CNT_MSB_LN3 register (address 17h) Table 133. BER_LEVEL_LSB register (address 18h) Table 134. BER_LEVEL_MSB register (address 19h) Table 135. INTR_ENA register (address 1Ah) Table 136. CNTRL_FLAGCNT_LN01 register Table 137. CNTRL_FLAGCNT_LN23 register Table 138. MON_FLAGS_RESET register (address 1Dh) Table 139. DBG_CNTRL register (address 1Eh) Table 140. PAGE_ADDRESS register (address 1Fh) Table 142. Code group synchronization state machine . . 76 Table 144. LN0_CFG_0 register (address 00h) Table 145. LN0_CFG_1 register (address 01h) Table 146. LN0_CFG_2 register (address 02h) Table 147. LN0_CFG_3 register (address 03h) Table 148. LN0_CFG_4 register (address 04h) Table 149. LN0_CFG_5 register (address 05h) Table 150. LN0_CFG_6 register (address 06h) Table 151. LN0_CFG_7 register (address 07h) Table 152. LN0_CFG_8 register (address 08h) Table 153. LN0_CFG_9 register (address 09h) Table 154. LN0_CFG_10 register (address 0Ah) Table 155. LN0_CFG_11 register (address 0Bh) Table 156. LN0_CFG_12 register (address 0Ch) Table 157. LN0_CFG_13 register (address 0Dh) Table 158. LN1_CFG_0 register (address 10h) Table 159. LN1_CFG_1 register (address 11h) Table 160. LN1_CFG_2 register (address 12h) Table 161. LN1_CFG_3 register (address 13h) Table 162. LN1_CFG_4 register (address 14h) Table 163. LN1_CFG_5 register (address 15h) Table 164. LN1_CFG_6 register (address 16h)
Table 165. LN1_CFG_7 register (address 17h) Table 166. LN1_CFG_8 register (address 18h) Table 167. LN1_CFG_9 register (address 19h) Table 168. LN1_CFG_10 register (address 1Ah) Table 169. LN1_CFG_11 register (address 1Bh) Table 170. LN1_CFG_12 register (address 1Ch) Table 171. LN1_CFG_13 register (address 1Dh) Table 172. PAGE_ADDRESS register (address 1Fh) Table 174. LN2_CFG_0 register (address 00h) Table 175. LN2_CFG_1 register (address 01h) Table 176. LN2_CFG_2 register (address 02h) Table 177. LN2_CFG_3 register (address 03h) Table 178. LN2_CFG_4 register (address 04h) Table 179. LN2_CFG_5 register (address 05h) Table 180. LN2_CFG_6 register (address 06h) Table 181. LN2_CFG_7 register (address 07h) Table 182. LN2_CFG_8 register (address 08h) Table 183. LN2_CFG_9 register (address 09h) Table 184. LN2_CFG_10 register (address 0Ah) Table 185. LN2_CFG_11 register (address 0Bh) Table 186. LN2_CFG_12 register (address 0Ch) Table 187. LN2_CFG_13 register (address 0Dh) Table 188. LN3_CFG_0 register (address 10h) Table 189. LN3_CFG_1 register (address 11h) Table 190. LN3_CFG_2 register (address 12h) Table 191. LN3_CFG_3 register (address 13h) Table 192. LN3_CFG_4 register (address 14h) Table 193. LN3_CFG_5 register (address 15h) Table 194. LN3_CFG_6 register (address 16h) Table 195. LN3_CFG_7 register (address 17h) Table 196. LN3_CFG_8 register (address 18h) Table 197. LN3_CFG_9 register (address 19h) Table 198. LN3_CFG_10 register (address 1Ah) Table 199. LN3_CFG_11 register (address 1Bh) Table 200. LN3_CFG_12 register (address 1Ch) Table 201. LN3_CFG_13 register (address 1Dh) Table 202. PAGE_ADDRESS register (address 1Fh)
NXP Semiconductors DAC1008D650 2×, 4× or 8× interpolating DAC with JESD204A © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 December 2010 Document identifier: DAC1008D650 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 17. Contents