DAC1006LCJ

DAC1000 NSC | Alldatasheet

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Technical content

5 A National

i—J S$ | DAC1000/DAC 1001/DAC 1002/DAC 1006/DAC1007/ o . z DAC 1008 .P Compatible, 3 | Double-Buffered D to A Converters = | General Description Features g The DAC1000/1/2 and DAC1006/7/8 are advanced ™ Uses easy to adjust END POINT specs, NOT BEST Q | CMOS/Si-Cr 10-, 9 and 8-bit accurate multiplying DACs = STRAIGHT LINE FIT a which are designed to interface directly with the 8080, 8048, = Low power consumption 8s 8085, Z-80 and other popular microprocessors. These ™ Direct interface to all popular microprocessors. & | DACs appear as a memory location or an I/O portto the #P integrated thin film on CMOS structure s& | and no interfacing logic is needed. 1 Double-buffered, single-butfered or flow through digital Q | These devices, combined with an external amplifier and data inputs. 3 voltage reference, can be used as standard D/A converters; Loads two 8-bit bytes or a single 10-bit word. and they are very attractive for multiplying applications —@ | ogic inputs which t TTL voltage level 1.4V 5 | (such as cigtatly controlled gain blocks) since their inearity "coe threshold). specs (1. error is essentially independent of the voltage reference. i‘ ‘olica. a They become equally attractive in audio signal processing Works with +10V reference—full 4-quadrant multiplica- © | equipment as audio gain controls or as programmable at- ” p o . | tenuators which marry high quality audio signal processing _'™ Operates STAND ALONE (without »P) if desired. 3 to digitally based systems under microprocessor control. . aaa in 0.3" standard 20-pin and 0.6" 24-pin pack- ‘| Allof these DACs are double buffered. They can load all 10 oe aa . . 2 | bits or two 8-bit bytes and the data format can be either right | ™ Diferential non-linearity selection available as special justified or left justified. The analog section of these DACs is order. essentially the same as that of the DAC1020. ., The DAC1000 series are the 10-bit members of a family of Key Specifications microprocessor-compatible DAC’s (MICRO-DACTM’s), For ™ Output Current Settling Time 500 ns applications requiring other resolutions, the DACO830 series © ™ Resolution 10 bits (8 bits) and the DAC1208 and DAC1230 (12 bits) are avail ™ Linearity 10, 9, and 8 bits able alternatives. (guaranteed over temp.) = Gain Tempco —0,0003% of FS/°C | rane | Accwme | rn | Decroton | nocing leader “omni (including ladder) [ Dacto00 | '§ Single Power Sy 5 to 15 V, paciooo| 10 | Has al r ply oc paciooz| 8 | features joacioos | to | gore. Typical Application DAC1006/1007/1008 < CONTROL Bus Ly —— +¥er (+ 95¥och Pe | ™ Deo! ” 0 ft) 4 + + * NOTE: FOR DETAILS OF BUS: LJ seo aus =Vner = CONNECTION SEE SECTION 6.0 TUH/S608-1 4-56

Absolute Maximum Ratings (notes 1 & 2) is) If Military/Aerospace specified devices are required, ESD Susceptibility (Note 11) 800v please contact the National Semiconductor Sales Lead Temp. (Soldering, 10 seconds) 3 Office/Distributors for availability and specifications. Dual-In-Line Package (plastic) 2c |G Supply Voltage (Voc) 17 Voc Dual-In-Line Package (ceramic) sore | & Voltage at Any Digital Input Voc to GND = Voltage at Ver Input +25v Operating Ratings (note 1) 3 Storage Temperature Range —65°C to + 150°C Temperature Flange SLOW sult Tin S oA < TMAX 5 Package Dissipation at Ta = 25°C (Note 3) 500 mW Part numbers with LOY! sutfbe -arcto sarc || > DC Voltage Applied to lours oF lout2 Part numbers with ‘Lu’ suffix -s5Cto +126 | 2 (Note 4) —100 mV to Voc Voltage at Any Digital input Voc to GND 8 Electrical Characteristics 4 Tested at Voc = 4.75 Voc and 15.75 Voc, Ta=25°C, Vrer= 10.000 Vpc unless otherwise noted 9 Voco=12Vp¢ + 5% _ Parameter Conditions s to 15Vp¢ 5% Voo=5Vpc +5% Units 3 g Resolution Po toto tits S Linearity Error Endpoint adjust only 47 s Twin<Ta<TMax 6 s —10V<Vpers + 10V 5 > DAC1000 and 1008 0.05 0.05 | %ofFsR | D DAC1001 and 1007 0.1 01 | %ofFSR 1G DAC1002 and 1008 02 0.2 | %ofFSR | = Differential Endpoint adjust only 47 s Nonlinearity TMIn<Ta<Tmax 6 ~10V<Vpers + 10V 5 DAC1000 and 1006 0.1 | %ofFSR DAC1001 and 1007 0.2 | %ofFSR DAC1002 and 1008 0.4 | %ofFSR Monotonicity TMIN<TA<TMAX —10V<Vpgr< +10V DAC1000 and 1006 10 10 bits DAGC1001 and 1007 9 9 bits DAC1002 and 1008 8 8 bits Gain Error Using internal Rp —10V<Vpers +10V +03 +03 % of FS Gain Error Tempco Twin<Ta<Twax Using internal Rp —0.0003 —0.0006 % of FS/*C Power Supply All digital inputs Rejection latched high Voc = 14.5V to 15.5V 0.003 | 0.008 % FSR/V 11.5V to 12.5V 0.004 | 0.010 % FSR/V 4,75V to 5.25V 0.10 | %FSR/V Reference input Resistance kao Output Feedthrough | Vper = 20Vp.p, f= 100 kHz Error All data inputs latched low D Package 130 130 Vp-p N Package 90 90 "Vp-p Output tours | All data inputs 60 60 pF Capacitance loutz| _ latched low 250 250 pF fours | All data inputs 250 250 pF lourz2| _latched high 60 60 pF Supply Current Drain [TwwsTasTwax | 6 [| os | as [| os [3s [ma 4.57

s Electrical Characteristics Q | __ Tested at Voc = 4.75 Voc and 15.75 Voc, Ta=25°C, VaEF= 10.000 Voc unless otherwise noted (Continued) a S Veo= 12Vpc+5% _

5 Parameter | to 15Vp¢+5% Vec=8Voc+5% Units

o Fr | win. | typ. | Max | min | typ. | Max | {| Output Leakage Twins TAS Tmax a Current lour1 All data inputs. latched low 200 200 nA 8 loure All data inputs bry latched high 200 200 nA | Digital Input TMINSTASTMax S| Voltages Low level g LU suffix 08 0.6 Voc 3 LCJ, LON suffix 0.8,0.8 07,08 | Vpc o High level (all parts) Voc & | Digital input TMINSTASTMAX S Currents Digital inputs <0.8V —150 =150 | pApe Ss Digital inputs >2.0V +10 +10 | pApc So += | Current Settling ts. | ViL=OV, Vin=5V ns Q|__ Time Q | write and XFER tw | ViL=OV, Vin=5V, s Pulse Width Ta=25°C 8 60 ns = TwinSTaSTMAX 9 100 ns © | Data Set Up Time tos | Vir=OV, Vin=5V, F4 Ta=25°C 80 170 ns Twins TaSTMAX 120 250 ns Data Hold Time ton | Vir=OV, Vin=5V Ta=25C ns TainSTASTMax ns Control Set Up tes | Vii=OV, ViL=5V, Time Ta=25C 60 180 ns TMINSTASTMAX 100 260 ns Control Hold Time tc | Vic=OV. Vin=SV, Ta=25°C 10 ns Twins TAS Tax 10 ns Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to GND, unless otherwise specified. Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify the power dissipation) removes concern for heat sinking. ‘Note 4: For current switching applications, both lout: and loyt2 must go to ground or the “Virtual Ground” of an operational amplifier. The linearity error is degraded by approximately Vos ~ Vrer. For example, if Vaer= 10V then a 1 mV offset, Vos, on lour: OF IouT2 will introduce an additional 0.01% linearity error. Note 5: Guaranteed at Vacr= + 10 Voc and VagF= +1 Voc. Note 6: Tyiy=0°C and Tyyax= 70°C for “LCN” suffix parts. Twin= —40°C and Tyax= 85°C for “LCJ” suffix parts. Twin=55°C and Tyax= 125°C for “LU” sutfix parts. Note 7: The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate dependence on a Particular Vaer value and to indicate the true performance of the part. The “Linearity Error” specification of the DAC1000 is “0.05% of FSR (MAX).” This guarantees that after performing a zero and full scale adjustment (See Sections 2.5 and 2.6), the plot of the 1024 analog voltage outputs will each be within 0.05% X Ver Of a straight line which passes through zero and full scale. Note 8: This specification implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (ty) of 320 ns. A typical part will operate with ty of only 100 ns. The entire write pulse must occur within the valid data interval for the specified ty, tpg, tox, and ts to apply. Note 9: Guaranteed by design but not tested. Note 10: A 200 nA leakage current with Ri» =20K and Var = 10V corresponds to a zero error of (200 x 10-9 20x 103) x 100 + 10 which is 0.04% of FS. Note 11: Human body model, 100 pF discharged through a 1.5 kf resistor. : 4-58

i=] Switching Waveforms 8 --—s tcH ke =] “> — g 8, avve/8¥TEz 50%: 0% 2 Mm oO im aK f= 2 vit el al J 3 Ty ry s lute PhLB > Typical Performance Characteristics 8 Errors vs. Supply Voltage ome Errors vs. Temperature Write Width, tw r= [ a umeany exnon] | |_| mt S eet t Pert) oem Tl beter HH 3 :.., / ant a tncmry emeel | Ee 5 pecolye pee HH 3 PI pee oe oars I 5 IN Ss Pees See se OF Peer 88 eee SSO e 3 TY 55-95-15 5 28 45 GS AS 108 125 “S5-B5-18 5 25 4S 65 85 105 125 ‘SUPPLY VOLTAGE Vcc [¥pc) AMBIENT TEMPERATURE (*C) AMBIENT TEMPERATURE (*C) foe itt) rele Tt sale TLD = wo 2 so = so preset] pspetert tt stb ¥ :“ 7” PEO PST E an aad H ~ Pi Nee E ™ tae 5 BN Lent | | eee (SEEEEET TH sEEEL TH Co “B5-35-15 5 25 45 6S 85 105 125 65-35-15 5 25 45 6S BS 105 125 55-35-15 5S 25 45 65 85 105 125 ‘AMBIENT TEMPERATURE (°C) ‘Ta. AMBIENT TEMPERATURE (°C) ‘Ta. AMBIENT TEMPERATURE (°C) Digital Threshold Digital Input Threshold ts vs. Supply Voltage a vs. Temperature 4 | wt TTT LL TT uneeeee eR AEE COTE 4 ee emaae GEESE PLETE a LH LTT Titty | wt LLITT TTT oo rr Ss5-35—15 5 25 45 66 a8 108 125 ‘SUPPLY WOLTAGE ¥cc (¥) ‘TEMPERATURE (°C) ‘TL/H/5688-3 4-59

8 Block and Connection Diagrams

a DAC1000/1001/ 1002 (24-Pin Parts) DAC1000/ 1001/1002 g (24-Pin Parts) $ 8 Dual-In-Line Package J ee wee fast steer _ U g m tt pacee a! uf—ve 6 ~ jt so-8T om U2 apa x Dig 21 —! on tac Whi: 3 2 Ld $ ne {—=| Byte 1/Byt9 2—y 4 an 14 = 0 e—— 18 nee wis 20; ory rs} (U8) 019 17: isa FER 6 OAC 1000, 19 Org 1001, 1002 < Os: 1 1. Dy a Dig? ' W Dig (L8B) a 1st tnd XFER u 1 8 16; Ss stmoie strane SE coTnoL Love “Wee o 10 15 ver 3 ono (uss) " uf—tours < Ont ard 3 louT2 i=] yoy fT Ff Ff vo view = 0 a ee) 3 am Rien we TUH/se08-4 Oo BYTE? Cy a

5 DAC1006/1007/ 1008 (20-Pin Parts) DAC1006/1007/1008

s (20-Pin Parts) s | re _] a ey Dual-in-Line Package oO (use) Dig 3} — usa 2 VReF a o ; | =n Youte &. 1 U » rd a pana w—, wh ou Dis Spel {9.817 Oya 1/577 — 3 1} Dig 19: | MULTIPLYING 3 Ln ed D/® CONVERTER a4 1p i ie me] tatoo POH Dy (16. AFB Dig: e 6 Dig (88) (188) O19 15—-—e uss wo lon ’ {M88} Dip: a 2h ist 2nd XFER STROBE CONTROL LOBE Sa ono TUH/s688-28 Top View ‘oe See Ordering Information = = c= USE DAC1006/1007/1008 CS Wn OXFEN BYTE FOR LEFT JUSTIFIED DATA BYTE2 ‘TL/H/5688-5 4-60

DAC1000/1001/1002—Simpie Hookup for a “Quick Look” is) 9 +15¥DC 9+15¥0C 8 i=] 1 4 > +S¥0C Ow 5 mse it 8 : oar sh, = ™ e A OVour o e > - a oO > iss 7 fs iz oye | Your 00 Vner (188) 2 *A TOTAL OF 10 ‘ s INPUT SWITCHES f 8 & 1K RESISTORS O-vaer = = FS 6-150 TLH/5688-6 Pe] Notes: > 1. For Vazr= — 10.240 Vpg the output voltage stops are approximately 10 mV each. 9 2. Operation is set up for flow through—no latching of digital input data. 3 ‘8. Single point ground is strongly recommended. 2 i=] DAC 1006/1007/1008—Simple Hookup for a “Quick Look” Ss +500 A, > te 9 +15¥00 9+15¥o¢ 3 +5¥0c wsB 9 19 0 4 EN? oe ° A Swe — DAC1006 ‘ o« : tacos > | ail e ad 1" F) = 0 Voc < Your <+¥1 satoracor 0 " Ld Oe mer CHR) INPUT SWITCHES r 4 & 1K RESISTORS o-var = = > 6-150 ruivseen-7 Notes: 1. For Vaer= — 10.240 Vc the output voltage steps are approximately 10 mV each. 2. SW1 is a normally closed switch. While SW1 is closed, the DAC register is latched and new data can be loaded into the input latch via the 10 SW2 switches. When SW1 is momentarily opened the new data is transferred from the input latch to the DAC register and is latched when SW1 again closes. 4-61

s 1.0 DEFINITION OF PACKAGE PINOUTS oO 1.1 Control Signals (All control signals are level actuated.) Reg: Feedback Resistor — This is provided on the IC chip s CS: Chip Select — active low, it will enable WR (DAC1003- for use as the shunt feedback resistor when an external op = 1008) or WR, (DAG1000-1002). amp is used to provide an output voltage for the DAC. This 3 WR or WR;: Write — The active low WR (or WR, — on-chip resistor should always be used (not an external re- | DAc1000-1002) is used to load the digital data bits (Dl) into ren) because maiches the resistors used in the on-chip & | the input latch. The data in the input latch is latched when rs | peratixe. G | WA (or WR)) is high. The 10-bit input latch is split into two Vrer: Reference Voltage Input — This is the connection for SS | _ latches; one holds 8 bits and the other holds 2 bits. The the external precision voltage source which drives the R-2R &S | _ Bytet/Byte2 control pin is used to select both input latches ladder. VreF can range from — 10 to + 10 volts. This is also i} when Byte1/Byte2=1 or to overwrite the 2-bit input latch the analog voltage input for a 4-quadrant multiplying DAC © | when in the low state. application. P3 WRo: Extra Write (DAC1000- 1002) — The active low WR Vcc: Digital Supply Voltage — This is the power supply pin ‘ai | _ iS Used to load the data from the input latch to the DAC for the part. Vcc can be from +5 to +15 Vpc. Operation is © | _ register while XFER is low. The data in the DAC register is optimum for + 15V. The input threshold voltages are nearly 2 | latched when WR is high. independent of Voc. (See Typical Performance Characteris- Q|__ Byter/Bytez Byte Sequence Control — When this control er Description in Section 3.0, T2L compatible logic a is high, all ten locations of the input latch are enabled. When puts. . >| __ low, only two locations of the input latch are enabled and GND: Ground — the ground pin for the part. & | _ these two locations are overwritten on the second byte 1.3 Definition of Terms = | write. On the DAC1006, 1007, and 1008, the Byte1/Byte2 Resolution: Resolution is directly related to the number of & | _ must be low to transfer the 10-bit data in the input latch to switches or bits within the DAC. For example, the DAC1000 O | the DAC register. has 210 or 1024 steps and therefore has 10-bit resolution. s XFER: Transfer Controt Signal, active low — This signal, in Linearity Error: Linearity error is the maximum deviation Ss combination with others, is used to transfer the 10-bit data from a straight line passing through the endpoints of the = | which is available in the input latch to the DAC register — DAC transfer characteristic. \\t is measured after adjusting g ‘see timing diagrams. for zero and full-scale. Linearity error is a parameter intrinsic Q | LU/Rd: Left Justify/Right Justify (OAC1000-1002) — When to the device and cannot be externally adjusted. LJ/AY is high the part is set up for left justified (fractional) National's linearity test (a) and the “best straight line” test data format. (DAC1006-1008 have this done internally.) (b) used by other suppliers are illustrated below. The “best When LJ/Rd is low, the part is set up for right justified (inte- straight line” requires a special zero and FS adjustment for ger) data. each part, which is almost impossible for user to determine.

1.2 Other Pin Functions The “end point test” uses a standard zero and FS adjust-

Di, (i=0 to 9): Digital Inputs — Dig is the least significant bit ment procedure and is a much more stringent test for DAC (LSB) and Dig is the most significant bit (MSB). linearity. lour1: DAC Current Output 1 — Iour1 is a maximum for a Power Supply Sensitivity: Power supply sensitivity is a digital input code of all 1s and is zero for a digital input code measure of the effect of power supply changes on the DAC of all Os. full-scale output (which is the worst case). loutz: DAC Current Output 2 — loute is a constant minus lout1, or ours +loyre = oes REE 1OUT1 + !OUT2 7024R where R = 15 kf. a. End Point Test After Zero and FS Adj. b, Best Straight Line t' LSB ERROR BAND BE] Acro. z ap 3 a 3 ¥ LSB ERROR a bl IDEAL RESPONSE : "DEAL ‘DIGITAL INPUT ‘DIGITAL INPUT TUH/5688-8 4-62

critical. When all DACs are updated, a common strobe sig- used for the op amp are adequate for the DAC.

1 J = == “VTHRESHOLD = 20

FIGURE 1. Basic Logic Threshold Loop

5.1.2 Providing a Bipolar Output Voltage with the ofa true tina a Vout can be found by: 3

FIGURE 4. Providing a Unipolar Output Voltage FIGURE 5. Providing a Bipolar Output Voltage with the DAC in the Current Switching Mode

S| gain stage as shown in Figure 9.

3 Pi tity evi TTT

FIGURE 8. Voltage Mode Switching = FIGURE 9. Amplitying the Voltage Mode Output (Single Supply Operation)

FIGURE 11. Increasing the Output Voltage Swing S range from —10 Voc to + 10V (1023/1024) when using a of the op amp and make the zeroing easier to sense. detail in an application to achieve the available performance This completes the DAC calibration.

FIGURE 14. Voltage Switching with a Bipolar Output Voltage 3

6.0 DIGITAL CONTROL DESCRIPTION F4

The first consideration is “will the DAC be interfaced to a pP of 6.1 through 6.4 need be considered.

Ss All of these DACs load 10 bits on the 1st write cycle. A (Input Latch and DAC Register) is shown in Figure 18. a cycle, depending on the justification of the data. This re- transferred on the 1st write cycle.

4 XFER strobe or external update timing control via an exter-

2 nal strobe. The details of these options are now shown.

3 FEEEEEEE EE ST

FIGURE 15. Fitting a 10-Bit Data Word into 16 Available Bit Locations

0 Tot BD ih | Bk iit

FIGURE 16. Input Connections and Controls for DAC 1000-1002 Right Justified Data Option

S| 62.1 Automatic Transfer oO This makes use of a double byte (double precision) write. The first byte (8 bits) is strobed into the input latch and the second <= byte causes a simultaneous strobe of the two remaining bits into the input latch and also the transfer of the complete 10-bit word iJ from the input latch to the DAC register. This is shown in the following timing diagrams; the point in time where the analog output 5 is updated is also indicated on these diagrams. Ps) DAC1000/ 1001/1002 (24-Pin Parts) DAC 1006/ 1007/1008 (20-Pin Parts) a s = LOAD By 1 LOAD eye 2 LOAD byte 1 LOAD Dye 2 8 XFER 2 “UK | waren / are DAE Whe wa | rex / Laren oat a pet > REGISTER tet seRTER a wie Ge 8 — ——a 5 =] reer . bye 1/878 So < TLH/5688-18 iJ “SIGNIFIES CONTROL INPUTS WHICH ARE DRIVEN IN PARALLEL = | 6.2.2 Transfer Using »P Write Stroke s The input latch is loaded with the first two write strobes. The XFER signal is provided by external logic, as shown below, to cause oO the transfer to be accomplished on a third write strobe. This is shown in the following diagrams:

2 DAC 1000/1001/1002 (24-Pin Parts) DAC 1006/ 1007/1008 (20-Pin Parts)

s S = VY ff “\\ /\\_f a ‘ase

2 OUTPUT LaTcH Dac SUTRUT Laren oat

a LOAD By 1 Lon oye 2 UATE ESTER Loan By nap oye 2 UPDATED — mm [ " Aen Oye 1 "i frown VI KN f \\4 \\/ KN f WE oh) awa mm Avi ae —_-Y 11 Saat —-—7j le byte 1/ Bye? ’ ope 1/F7at / Vom e--- == [WHERE THE XFER CONTROL CAM BE GENERATED BY USING A SECOWO CHIP BELECT AS: of) ‘Avo THE BYTE CONTROL. CAM WE DERIVED FROM THE ADORESS BUS SGNALS. TUH/S688-19

6.2.3 Transfer Using an External Strobe

This is similar to the previous operation except the XFER signal is not provided by the P. The timing diagram for this is: DAC 1000/ 1001/1002 (24-Pin Parts) DAC1006/ 1007/1008 (20-Pin Parts) VS VW SVS a a - LOAD Byte 1 \\0A0 bya 2 oa 7 aye 1010 oye 2 ae Vr * VL Korennes Ve —— ln Yo te 7a? : aK ana.oa i et -—-—— Oro ‘uicn pac — ———E ----- RE on SE ‘amnuoe ‘ay i Haute Bs +7 Bane Lathan nn aren MESBTER TLH/5888-20 4-72

6.3 Interfacing to a 16-Bit Data Bus 4

086 Dio (Ls8) uss —_

FIGURE 19. Input Connections and Logic for DAC 1000-1002 with 16-Bit Data Bus ous 1 OUTPUTS FOLLOW D INPUTS. FIGURE 20. Input Connections and Logic for DAC1006/ 1007/1008 with 16-Bit Data Bus

S| Three operating modes are possible: flow through, single buffered, or double buffered. The timing diagrams for these are shown & | below: G| 6.3.1 Single Buttered rz DAC 1000/ 1001/1002 (24-Pin Parts) DAC1006/ 1007/1008 (20-Pin Parts) 8 8 \\ / a \\ kL...

5 Naa

= a pee eee 4 S Cot Petry a ‘avaioe = wae LOAD evr varcH & LOAD aru LATCH o FER TO OAC REDISTER Q Nx 6.3.2 Double Buffered

8 DAC 1000/1001/1002 (24-Pin Parts) DAC1006/1007/1008 (20-Pin Parts)

o — a & on bs \\ / S = INPUT OATA 1S LATEHED INPUT DATA S LATCHED 3 wi \\ e \\ ~ 7 \\ y wi \\ 4 g Sono nour un So wet urea a a oe Seleietetettetated — mabe s wevint NLL a oureut — \\ DAC REBISTEN ened bye vigwt=s poate TS LATCHED. J g ‘FER on Wi2 ANALOG = 4 oureut one REGISTER wis on eto ul iurone aren TLsH/5688-22

6.4 Stand Alone Operation

For applications for a DAC which are not under »P control (stand alone) there are two basic operating modes, single buffered and double buffered. The timing diagrams for these are shown below:

6.4.1 Single Buffered

DAC 1000/ 1001/1002 (24-Pin Parts) DAC1006/ 1007/1008 (20-Pin Parts) " XFEN TO OAC REGISTER wm \\ fase WMPUT LATCH Wyte rE ye arr \\ / I X aren ‘uuoas LATCHES DATA 1N OAC REOISTER

6.4.2 Double Butfered

DAC1000/ 1001/1002 (24-Pin Parts) DAC1006/ 1007/1008 (20-Pin Parts)* wm \\___ Recannine a \\ SY Rwamnue LOAD iwPuT LATCH wren aa eae ere e— = a-wm-0 vesareo—"" AEBETER amas gue MPN urea tye VT <1 roaren REGISTER TLH/5888-23, “For a connection diagram of this operating mode use Figure 18 for the Logic and Figure 20 tor the Data Input connections. 4-74

6.4.3 Flow Through 3

7.0 MICROPROCESSOR INTERFACE 3

7.1 DAC1001/1/2 ta INS8080A Interface Since a double byte write is necessary to control the DAC >

NOTE: DOUBLE BYTE STORES CAN BE USED. TRANSFERS THE RESULT TO THE DAC REGISTER. BE AN ODD ADDRESS FOR PROPER TRANSFER. FIGURE 21. Interfacing the DAC 1000 to the INS8080A CPU Group

3 auto-decrementing of the stack pointer during a PUSH al- brought back HIGH. 4 DAC chip select (CS) and synchronize this CS to the two be required. = | memory write strobes of the PUSH instruction. 3 generate the byte number and transfer strobes. value of the feedback capacitor (Cc in Figure 3). and B of the PIA the 10-bit data transfer, assumed right nating noise spikes when changing digital codes. FIGURE 22. DAC 1000 to MC6620/1 PIA Interface

FIGURE 23. isolating Data Bus from DAC Circultry to Eliminate Digital Noise Coupling F-4 FIGURE 24. Digitally Controlled Amplifier/Attenuator

7.4 Digitally Controlled Amplifier/Attenuator

op amp automatically adjusts the VreF in voltage such that +Vmax, depending on the sign of Vin. M fractional binary number).

rs) [=] VREF ‘DAcs000 rn LF13333 ‘SERIES " s Ly 2 * o ° 82 < ° st L vnersine=x L s “oteane 7 . gs VAEF ‘LOGIC 3 ; 3 : a Q 8 | vee ES] ‘SERIES TA 3 ner => FS = ner cose =¥ 8 P= => >= J TL/H/5688-27 8 FIGURE 25. Digital to Synchro Converter $| Ordering Information So So 3 4. All Logic Features — 24-pin package. a 0.05% (10-bit) DAC1000LCJ DAC1000LJ DAC 1000LCN 0.10% (9-bit) DAC1001LCN 0.20% (8-bit) DAC1002LCJ DAC1002LJ DAC1002LCN 2. For Left Justified Data — 20-pin package. Temperature Range ~arcto +85°c | —s5°C to +125°C 0.05% (10-bit) DAC1006LCJ DAC1006LJ DAC1006LCN 0.10% (9-bit) DAC1007LCN 0.20% (8-bit) DACIO0BLCM DAC1008LJ DAG1008LCN 478