DAC1005D750

Renesas Technology Corp

Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating 2 July 2012

Manufacturer: Renesas Technology Corp

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DAC1005D750 RENESAS | Alldatasheet

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General description The DAC1005D750 is a high-speed 10-bit dual channel Digital-to-Analog Converter (DAC) with selectable 4 or 8 interpolating filters optimized for multi-carrier wireless transmitters. Thanks to its digital on-chip modulation, the DAC1005D750 allows the complex I and Q inputs to be converted from BaseBand (BB) to IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register. Two modes of operation are available: separate data ports or a single interleaved high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched. A 4 and 8 clock multiplier enables the DAC1005D750 to provide the appropriate internal clocks from the internal PLL. The internal PLL can be bypassed enabling the use of an external high frequency clock. The voltage regulator enables adjustment of the output full-scale current. 2. Features and benefits DAC1005D750 Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating Rev. 05 — 2 July 2012 Product data sheet  Dual 10-bit resolution  IMD3: 74 dBc; fs = 737.28 Msps; fo = 140 MHz  750 Msps maximum update rate  ACPR: 64 dBc; 2-carrier WCDMA; fs = 737.28 Msps; fo =1 5 3 . 6M H z  Selectable 4 or 8 interpolation filters  Typical 1.2 W power dissipation at 4 interpolation, PLL off and 740 Msps  Input data rate up to 185 Msps  Power-down and Sleep modes  Very low noise cap-free integrated PLL  Differential scalable output current from 1.6 mA to 22 mA  32-bit programmable NCO frequency  On-chip 1.29 V reference  Dual port or Interleaved data modes  External analog offset control (10-bit auxiliary DACs)  1.8 V and 3.3 V power supplies  Internal digital offset control  LVDS compatible clock  Inverse x / (sin x) function  Two’s complement or binary offset data format  Fully compatible SPI port  1.8 V/3.3 V CMOS input data buffers  Industrial temperature range from 40 C to +85 C

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1005D750 5© IDT 2012. All rights reserved. Product data sheet Rev. 05 — 2 July 2012 3 of 43 Integrated Device TechnologyDAC1005D750 Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating 5. Block diagram Fig 1. Block diagram 001aam191 DAC1005D750 FIR1 2 × 2 × FIR1 FIR2 2 × 2 × FIR2 FIR3 2 × 2 × FIR3 NCO cos sin 63 65 64 CLOCK GENERATOR/PLL COMPLEX MODULATOR LATCH Q LATCH I CLKP RESET_N SYNCP DAC A AUXILIARY DAC AUXILIARY DAC DAC B REFERENCE BANDGAP OFFSET CONTROL 10-BIT GAIN CONTROL 10-BIT OFFSET CONTROL 10-BIT GAIN CONTROL 10-BIT OFFSET CONTROL SYNCN SCLK SCS_N SDIO SDO CLKN Q0 to Q9 dual port/ interleaved data modes I0 to I9 41, 42, 45 to 48, 51 to 54 18 to 25, 28, 29 SPI AUXAN GAPOUT AUXAP IOUTAN VIRES IOUTAP IOUTBN IOUTBP AUXBN AUXBP mixer A B mixer mixer mixer x sin x x sin x

DAC1005D750 5 © IDT 2012. All rights reserved. Product data sheet Rev. 05 — 2 July 2012 4 of 43 Integrated Device Technology DAC1005D750 Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating 6. Pinning information

6.1 Pinning

Fig 2. Pin configuration DAC1005D750 VDDA(3V3) VDDA(3V3) AUXAP AUXBP AUXAN AUXBN AGND AGND VDDA(1V8) VDDA(1V8) VDDA(1V8) VDDA(1V8) AGND GAPOUT CLKP VIRES CLKN d.n.c. AGND RESET_N VDDA(1V8) SCS_N SYNCP SCLK SYNCN SDIO TM1 SDO I7 n.c. I6 n.c. I5 Q0 I4 Q1 TM0 VDD(IO)(3V3) GNDIO TM3 V DD(IO)(3V3) GNDIO n.c. n.c. I2 Q3 VDDD(1V8)AGND DGNDVDDA(1V8) I1AGND I0VDDA(1V8) n.c.AGND n.c.VDDA(1V8) VDDD(1V8)AGND DGNDVDDA(1V8) n.c.AGND n.c.IOUTAN VDDD(1V8)IOUTAP DGNDAGND TM2n.c. DGNDAGND Q7VDDA(1V8) Q6AGND Q5VDDA(1V8) Q4AGND DGND VDDD(1V8) Q9/SELIQ DGND VDDD(1V8) VDDA(1V8) IOUTBP IOUTBN AGND V DDA(1V8) AGND VDDD(1V8)AGND 001aam192 100 AGND

6.2 Pin description

Table 2. Pin description

DAC1005D750 5 © IDT 2012. All rights reserved. [1] In compliance with JEDEC test board, in free air. Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Table 4. Thermal characteristics

DAC1005D750 5 © IDT 2012. All rights reserved. [1] D = guaranteed by design; C = guaranteed by c haracterization; I = 100 % industrially tested. be connected across the pins (see Figure 8). and the inductance between the receiver and the driver circuit ground voltages. [4] IMD3 rejection with 6 dBFS/tone.

DAC1005D750 5 © IDT 2012. All rights reserved. Product data sheet Rev. 05 — 2 July 2012 14 of 43 Integrated Device Technology DAC1005D750 Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating 10. Application information

10.1 General description

The DAC1005D750 is a dual 10-bit DAC which operates at up to 750 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 4-bit binary weighted sub-DAC. The input data rate of up to 185 MHz combined with the maximum output sampling rate of

750 Msps make the DAC1005D750 extremely flexible in wide bandwidth and multi-carrier

systems. The device’s quadrature modulator and 32-bit NCO simplifies system frequency selection. This is also possible because the 4 and 8 interpolation filters remove undesired images. A SYNC signal is provided to synchronize data when the PLL is in the off state. Two modes are available for the digital input. In Dual-port mode, each DAC uses its own data input line. In Interleaved mode, both DACs use the same data input line. The on-chip PLL enables generation of the internal clock signals for the digital circuitry and the DAC from a low speed clock. The PLL can be bypassed enabling the use of an external, high-speed clock. Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and IOUTBP/IOUTBN. This provides a full-scale output current (IO(fs)) up to 22 mA. An internal reference is available for the reference current which is externally adjustable using pin VIRES. There are also some embedded features to provide an analog offset correction (auxiliary DACs) and digital offset control as well as for gain adjustment. All the functions can be set using the SPI. The DAC1005D750 operates at both 3.3 V and 1.8 V each of which has separate digital and analog power supplies. The digital input is 1.8 V and 3.3 V compliant and the clock input is LVDS compliant.

10.2 Serial peripheral interface

10.2.1 Protocol description

The DAC1005D750 Serial Peripheral Interface (SPI) is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. It provides access to the registers that define the operating modes of the chip in both write and read modes. This interface can be configured as a 3-wire type (SDIO as a bidirectional pin) or a 4-wire type (SDIO and SDO as unidirectional pins, input and output port respectively). In both configurations, SCLK acts as the serial clock and SCS_N acts as the serial chip select bar. If several DAC1005D750 devices are connected to an application on the same SPI-bus, only a 3-wire type can be used. Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW assertion to drive the chip with 1 to 4 bytes, depending on the content of the instruction byte (see Table 7).

DAC1005D750 5 © IDT 2012. All rights reserved. In Table 7 N1 and N0 indicate the number of bytes transferred after the instruction byte. decreasing order according to Table 9 “Register allocation map”.

10.2.2 SPI timing description

R/W indicates the mode access, (see Table 6). Table 6. Read or Write mode access description

0 Write mode operation

1 Read mode operation

Table 7. Number of bytes transferred

10.2.3 Detailed descriptions of registers

An overview of the details for all registers is provided in Table 9. Table 9. Register allocation map

10.2.4 Detailed register descriptions

following tables, all the values shown in bold are the default values. Table 10. COMMon register (a ddress 00h) bit description Default settings are shown highlighted.

6 SPI_RST R/W serial interface reset

5 CLK_SEL R/W data input latch

3 MODE_SEL R/W input data mode

2 CODING R/W coding

1 IC_PD R/W power-down

0 GAP_PD R/W internal bandgap power-down

Table 11. TXCFG register (address 01h) bit description Default settings are shown highlighted.

7 NCO_ON R/W NCO

6 NCO_LP_SEL R/W low-power NCO

1 NCO frequency and phase given by the five

5 INV_SIN_SEL R/W x / (sin x) function

7 PLL_PD R/W PLL

5 PLL_DIV_PD R/W PLL divider undefined

11 X 580 ps

0 DAC_CLK_POL R/W clock edge of DAC (f s) undefined

Table 13. FREQNCO_LSB register (address 03h) bit description Table 11. TXCFG register (address 01h) bit description …continued Default settings are shown highlighted.

DAC1005D750 5 © IDT 2012. All rights reserved. Table 14. FREQNCO_LISB register (address 04h) bit description Table 15. FREQNCO_UISB register (address 05h) bit description Table 16. FREQNCO_MSB register (address 06h) bit description Table 17. PHINCO_LSB register (address 07h) bit description Table 18. PHINCO_MSB register (address 08h) bit description Table 19. DAC_A_Cfg_1 register (a ddress 09h) bit description Default settings are shown highlighted.

7 DAC_A_PD R/W DAC A power

6 DAC_A_SLEEP R/W DAC A Sleep mode

Table 20. DAC_A_Cfg_2 register (a ddress 0Ah) bit description

DAC1005D750 5 © IDT 2012. All rights reserved. Table 21. DAC_A_Cfg_3 register (a ddress 0Bh) bit description Table 22. DAC_B_Cfg_1 register (a ddress 0Ch) bit description Default settings are shown highlighted.

7 DAC_B_PD R/W DAC B power

6 DAC_B_SLEEP R/W DAC B Sleep mode

Table 23. DAC_B_Cfg_2 register (a ddress 0Dh) bit description Table 24. DAC_B_Cfg_3 register (address 0Eh) bit description Table 25. DAC_Cfg register (add ress 0Fh) bit description Default settings are shown highlighted.

1 MINUS_3DB R/W NCO gain

0 NOISE_SHPER R/W noise shaper

7 SYNC_DIV R/W f s divided by

6 SYNC_SEL R/W SYNC selection

Table 27. DAC_A_Aux_MSB register (address 1Ah) bit description Table 28. DAC_A_Aux_LSB register (address 1Bh) bit description Default settings are shown highlighted.

7 AUX_A_PD R/W auxiliary DAC A power

Table 29. DAC_B_Aux_MSB register (address 1Ch) bit description Table 30. DAC_B_Aux_LSB register (address 1Dh) bit description Default settings are shown highlighted.

7 AUX_B_PD R/W auxiliary DAC B power

10.2.5 Recommended configuration

10.3 Input data

10.3.1 Dual-port mode

edge of the internal clock signal and is transferred to the DAC latch. Table 31. Recommended configuration Table 32. Mode selection

0 Dual port mode active active Q9

1 Interleaved mode active off SELIQ

10.3.2 Interleaved mode

The data input for the Interleaved mode operation is illustrated in Figure 6 “Interleaved mode operation”. In Interleaved mode, both DACs use the same data input at twice the Dual-port mode frequency. Data enters the latch on the rising edge of the internal clock signal. The data is sent to either latch I or latch Q, depending on the SELIQ signal. The SELIQ input (pin 41) allows the synchronization of the internally demultiplexed I and Q channels; see Figure 7 “Interleaved mode timing (8x interpolation, latch on rising edge)”. The SELIQ signal can be either synchronous or asynchronous (single rising edge, single pulse). The first data following the SELIQ rising edge is sent in channel I and following data is sent in channel Q. After this, data is distributed alternately between these channels. Fig 6. Interleaved mode operation CLKdig = internal digital clock Fig 7. Interleaved mode timing (8x in terpolation, latch on rising edge) 001aam219 LATCH I 2 × 2 × 2 × FIR 1 FIR 1 FIR 2 FIR 2 FIR 3 FIR 3 LATCH Q 2 × 2 × 2 × I9 to I0 Q9/SELIQ 001aaj814 NIn SELIQ (synchronous alternative) SELIQ (asynchronous alternative 1) SELIQ (asynchronous alternative 2) CLKdig Latch I output Latch Q output XX N N + 2 N + 1 N + 2 N + 3 N + 4 N + 5 XX N + 1 N + 3

10.4 Input clock

The DAC1005D750 can operate at the following clock frequencies: PLL on: up to 185 MHz in Dual-port mode and up to 370 MHz in Interleaved mode PLL off: up to 750 MHz The input clock is LVDS compliant (see Figure 8) but it can also be interfaced with CML differential sine wave signal (see Figure 9).

10.5 Timing

The DAC1005D750 can operate at a sampling frequency (fs) up to 750 Msps with an input data rate (fdata) up to 185 MHz. When using the internal PLL, the input data is referenced to the CLK signal. When the internal PLL is bypassed, the SYNC signal is used as a reference. The input timing in the second case is shown in Figure 10. Fig 8. LVDS clock configuration Fig 9. Interfacing CML to LVDS 001aah021 100 Ω LVDS CLKINP CLKINN LVDS Zdiff = 100 Ω 001aah020 55 Ω 55 Ω 1.1 kΩ 2.2 kΩ 100 nF CML 100 nF 100 nF CLKINP LVDS CLKINN AGND VDDA(1V8) 1 kΩZdiff = 100 Ω

10.5.1 Timing when using the internal PLL (PLL on)

the frequency between the digital part and the DAC core to be adjusted. examples are given in Table 34.

10.5.2 Timing when using an external PLL (PLL off)

obtain optimum device performance up to750 Msps.

10.6 FIR filters

Table 33. Frequencies Table 34. Sample clock phase and polarity examples Table 35. Optimum external PLL timing settings

10.7 Quadrature modulator and Numerica lly Controlled Oscillator (NCO)

signal generated by the NCO. negative, lower or upper single sideband up-conversion. Table 36. Interpolation filter coefficients

10.7.1 NCO in 32-bit

FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits. where M is the decimal representation of FREQ_NCO[31:0].

10.7.2 Low-power NCO

where M is the decimal representation of FREQ_NCO[31:27]. The phase of the low-power NCO can be set by the 5 MSB of the register PHINCO_MSB.

10.7.3 Minus_3dB function

During normal use, a full-scale pattern will also be full scale at the output of the DAC. Table 37. Inversion filter coefficients

10.9 DAC transfer function

Table 38 shows the output current as a function of the input data, when IO(fs) = 20 mA.

10.10 Full-scale current

10.10.1 Regulation

GAPOUT using a 100 nF capacitor. Table 38. DAC transfer function

1023 DATA–

10.10.2 Full-scale current adjustment

user to both DACs independently via the serial interface from 1.6 mA to 22 mA, 10 %. 0Eh) bit description”) define the coarse variation of the full-scale current (see Table 39). Table 39. I O(fs) coarse adjustment Default settings are shown highlighted.

10.11 Digital offset adjustment

offset correction can be used to adjust the common-mode level at the output of the DAC. It adds an offset at the end of the digital part, just before the DAC. description”) define the range of variation of the digital offset (see Table 41). Table 40. I Default settings are shown highlighted. Table 39. I Default settings are shown highlighted.

10.12 Analog output

L to the 3.3 V analog power supply (VDDA(3V3)). improving the dynamic performance of the DAC by introducing less distortion. following stages and the targeted performances. Table 41. Digital offset adjustment Default settings are shown highlighted.

10.13 Auxiliary DACs

offset between the DAC and the next stage in the transmission path. Table 42 shows the output current as a function of the auxiliary DAC data.

10.14 Output c onfiguration

10.14.1 Basic output configuration

Table 42. Auxiliary DAC transfer function Default settings are shown highlighted.

DAC1005D750 5 © IDT 2012. All rights reserved. Product data sheet Rev. 05 — 2 July 2012 35 of 43 Integrated Device Technology DAC1005D750 Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating The DAC1005D750 differential outputs can operate up to 2 Vo(p-p). In this configuration, it is recommended to connect the center tap of the transformer to a 62  resistor connected to the 3.3 V analog power supply, in order to adjust the DC common-mode to approximately 2.7 V (see Figure 14).

10.14.2 DC interface to an Analog Quadrature Modulator (AQM)

When the system operation requires to keep the DC component of the spectrum, the DAC1005D750 can use a DC interface to connect to an AQM. In this case, the offset compensation for LO cancellation can be made with the use of the digital offset control in the DAC. Figure 15 provides an example of a connection to an AQM with a 1.7 VI(cm) common-mode input level. Figure 16 provides an example of a connection to an AQM with a 3.3 VI(cm) common-mode input level. Fig 14. 2 V o(p-p) differential output with transformer 001aaj818 50 Ω 100 Ω 100 Ω IOUTnP/IOUTnN; Vo(cm) = 2.7 V; Vo(dif)(p-p) = 2 V IOUTnP IOUTnN 0 mA to 20 mA 4:1 0 mA to 20 mA VDDA(3V3) 62 Ω VDDA(3V3) VDDA(3V3) Fig 15. An example of a DC interface to a 1.7 V I(cm) AQM 001aaj541 51.1 Ω 51.1 Ω 442 Ω 442 Ω VDDA(3V3) IOUTnP IOUTnN 0 mA to 20 mA BBP (1) IOUTnP/IOUTnN; Vo(cm) = 2.67 V; Vo(dif)(p-p) = 1.98 V (2) BBP/BBN; Vi(cm) = 1.7 V; Vi(dif)(p-p) = 1.26 V BBN AQM (Vi(cm) = 1.7 V) 768 Ω 768 Ω (1) (2)

DAC1005D750 5 © IDT 2012. All rights reserved. Product data sheet Rev. 05 — 2 July 2012 37 of 43 Integrated Device Technology DAC1005D750 Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating The constraints to adjust the interface are the output compliance range of the DAC and the auxiliary DACs, the input common-mode level of the AQM, and the range of offset correction.

10.14.3 AC interface to an Analog Quadrature Modulator (AQM)

When the AQM common-mode voltage is close to ground, the DAC1005D750 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 19 provides an example of a connection to an AQM with a 0.5 V I(cm) common-mode input level using auxiliary DACs. Fig 18. An example of a DC interface to a 3.3 V I(cm) AQM using auxiliary DACs 001aaj544 54.9 Ω 54.9 Ω 237 Ω 237 Ω 3.3 V IOUTnP IOUTnN AUXnP AUXnN BBP BBN AQM (Vi(cm) = 3.3 V) 750 Ω 750 Ω 5 V 634 Ω 634 Ω 442 Ω 442 Ω (1) IOUTnP/IOUTnN; Vo(cm) = 2.75 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; Vi(cm) = 3.3 V; Vi(dif)(p-p) = 1.5 V; offset correction up to 36 mV (1) (2) Fig 19. An example of an AC interface to a 0.5 V I(cm) AQM using auxiliary DACs 001aaj589 66.5 Ω 66.5 Ω 10 nF VDDA(3V3) IOUTnP IOUTnN 0 mA to 20 mA BBP BBN AQM (Vi(cm) = 0.5 V) 2 kΩ 2 kΩ 5 V 174 Ω 174 Ω 34 Ω 34 Ω AUXnP AUXnN 1.1 mA (typ.) 10 nF (1) IOUTnP/IOUTnN; Vo(cm) = 2.65 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; Vi(cm) = 0.5 V; Vi(dif)(p-p) = 1.96 V; offset correction up to 70 mV (1) (2)

10.15 Power and grounding

In order to obtain optimum performance, it is recommended that the 1.8 V analog power supplies on pins 5, 11, 71, 77 and 99 should not be connected with the ones on pins 6, 70, 79, 81, 83, 93, 95 and 97 on the top layer. To optimize the decoupling, the power supplies should be decoupled with the following ground pins:

VDDD(1V8): pin 26 with 27; pin 32 with 33; pin 36 with 37; pin 40 with 39; pin 44 with 43 and pin 50 with 49.
VDD(IO)(3V3): pin 16 with 17 and pin 60 with 59.
VDDA(1V8): pin 5 with 4; pin 6 with 7; pin 11 with 10; pin 71 with 72; pin 77 with 78; pins 79, 81, 83 with 80, 82, 84; pins 93, 95, 97 with 92, 94, 96 and pin 99 with 98.
VDDA(3V3): pin 1 with 100 and pin 75 with 76.

DAC1005D750 5 © IDT 2012. All rights reserved. Product data sheet Rev. 05 — 2 July 2012 39 of 43 Integrated Device Technology DAC1005D750 Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating 11. Package outline Fig 20. Package outline SOT638-1 (HTQFP100) UNIT A max. A1 A2 A3 bp HD HE Lp ZD(1) ZE(1)ce L y wv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.15 15.85 1.15 0.85 0°0.08 0.080.21 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT638-1 MS-026 03-04-07 05-02-02 D(1) E(1) 14.1 13.9 16.15 15.85 Dh Eh 7.1 6.1 7.1 6.1 1.15 0.85 bp bp e θ E A1A Lp detail X L (A3) B HD HE A2 v M B D ZD A c ZE e v M A X 100 75 51 y pin 1 index w M w M 0 10 mm scale HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad SOT638-1 Dh Eh exposed die pad side

DAC1005D750 5 © IDT 2012. All rights reserved. Product data sheet Rev. 05 — 2 July 2012 41 of 43 Integrated Device Technology DAC1005D750 Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating 13. Glossary Spurious-Free Dynamic Range (SFDR): — The ratio between the RMS value of the reconstructed output sine wave and the RMS value of the largest spurious observed (harmonic and non-harmonic, excluding DC component) in the frequency domain. Intermodulation Distortion (IMD): — From a dual-tone digital input sine wave (these two frequencies being close together), the intermodulation distortion products IMD2 and IMD3 (respectively, second and third-order components) are defined below. IMD2 — The ratio of the RMS value of either tone to the RMS value of the worst second order intermodulation product. IMD3 — The ratio of the RMS value of either tone to the RMS value of the worst third order intermodulation product. Restricted Bandwidth Spurious Free Dynamic Range — The ratio of the RMS value of the reconstructed output sine wave to the RMS value of the noise, including the harmonics, in a given bandwidth centered around f offset.

Section 2 “Features and benefits” has been updated.
The values for VO(ref) in Table 5 “Characteristics” have been updated.
Section 10.2.1 “Protocol description” has been updated.
Section 10.10.1 “Regulation” has been updated. DAC1005D750 v.3 20110607 Product data sheet - DAC1005D750 v.2 DAC1005D750 v.2 20100910 Product data sheet - DAC1005D750 v.1 DAC1005D750 v.1 20100727 Product data sheet - -

DAC1005D750 5 © IDT 2012. All rights reserved. Product data sheet Rev. 05 — 2 July 2012 43 of 43 Integrated Device Technology DAC1005D750 Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating 16. Contents

10.5.1 Timing when using the internal PLL

10.5.2 Timing when using an external PLL

10.7 Quadrature modulator and Numerically

10.14.2 DC interface to an Analog Quadrature

10.14.3 AC interface to an Analog Quadrature

Product Information

DAC1005D750 specifications and overview.

Summary

Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating 2 July 2012

Description

Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating 2 July 2012

Source title DAC1005D750 Datasheet(PDF) - Renesas Technology Corp

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