DAC1005D650HW/C1

NXP Semiconductors

Dual 10-bit DAC, up to 650 Msps; 2쨈 4쨈 and 8쨈 interpolating Rev. 01-28 July 2009

Manufacturer: NXP Semiconductors

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General description The DAC1005D650 is a high-speed 10-bit dual-channel Digital-to-Analog Converter (DAC) with selectable 2×, 4× or 8× interpolating ﬁlters optimized for multi-carrier wireless transmitters. Thanks to its digital on-chip modulation, the DAC1005D650 allows the complex I and Q inputs to be converted up from BaseBand (BB) to IF . The mixing frequency is adjusted using a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO). The phase is controlled by a 16-bit register. Two modes of operation are available: separate data ports or a single interleaved high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched. The DAC1005D650 also includes a 2×, 4× and 8× clock multiplier which provides the appropriate internal clocks and an internal regulator to adjust the output full-scale current. 2. Features DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating Rev. 01 — 28 July 2009 Product data sheet n Dual 10-bit resolution n IMD3: 79 dBc; fs = 640 Msps; fo =9 6M H z n 650 Msps maximum update rate n SFDR: 75 dBc; fdata= 80 MHz; fs = 640 Msps; fo = 19 MHz; PLL on n Selectable 2×, 4× or 8× interpolation ﬁlters n Typical 0.95 W power dissipation at 4× interpolation n Input data rate up to 160 Msps n Power-down and Sleep modes n Very low noise cap-free integrated PLLn Differential scalable output current from 1.6 mA to 20 mA n 32-bit programmable NCO frequencyn On-chip 1.25 V reference n Dual-port or Interleaved data modesn External analog offset control (10-bit auxiliary DACs) n 1.8 V and 3.3 V power supplies n Internal digital offset control n LVDS compatible clock n Inverse (sin x) / x function n Two’s complement or binary offset data format n Fully compatible SPI port n 3.3 V CMOS input buffers n Industrial temperature range from −40 °Ct o+ 8 5°C

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1005D650_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 28 July 2009 3 of 41 NXP Semiconductors DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating 5. Block diagram Fig 1. Block diagram 001aak158 DAC1005D650 FIR1 2 · 2 · FIR1 FIR2 2 · 2 · FIR2 FIR3 2 · 2 · FIR3 NCO cos sin CLOCK GENERATOR/ PLL COMPLEX MODULATOR LATCH Q LATCH I CLKP RESET_N DAC AUXILIARY DAC AUXILIARY DAC DAC REFERENCE BANDGAP OFFSET CONTROL 10-BIT GAIN CONTROL 10-BIT OFFSET CONTROL 10-BIT GAIN CONTROL 10-BIT OFFSET CONTROL SCLK SCS_N SDIO SDO 41, 42 45 to 48, 51 to 54 18 to 25, 28, 29 63 65 64 CLKN Q0 to Q9 dual port/ interleaved data modes I0 to I9 SPI AUXAN GAPOUT AUXAP IOUTAN VIRES IOUTAP IOUTBN IOUTBP AUXBN AUXBP mixer A B mixer mixer mixer x sin x x sin x

DAC1005D650_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 28 July 2009 4 of 41 NXP Semiconductors DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating 6. Pinning information

6.1 Pinning

Fig 2. Pin conﬁguration DAC1005D650HW VDDA(3V3) VDDA(3V3) AUXAP AUXBP AUXAN AUXBN AGND AGND VDDA(1V8) VDDA(1V8) VDDA(1V8) VDDA(1V8) AGND GAPOUT CLKP VIRES CLKN d.n.c. AGND RESET_N VDDA(1V8) SCS_N d.n.c. SCLK d.n.c. SDIO TM1 SDO I7 n.c. I6 n.c. I5 Q0 I4 Q1 TM0 VDD(IO)(3V3) GNDIO TM3 V DD(IO)(3V3) GNDIO n.c. n.c. I2 Q3 VDDD(1V8) AGND DGND VDDA(1V8) I1 AGND I0 VDDA(1V8) n.c. AGND n.c. VDDA(1V8) VDDD(1V8) AGND DGND VDDA(1V8) n.c. AGND n.c. IOUTAN VDDD(1V8) IOUTAP DGND AGND TM2 n.c. DGND AGND Q7 VDDA(1V8) Q6 AGND Q5 VDDA(1V8) Q4 AGND DGND VDDD(1V8) Q9/SELIQ DGND VDDD(1V8) VDDA(1V8) IOUTBP IOUTBN AGND V DDA(1V8) AGND VDDD(1V8) AGND 001aak159 100 AGND

6.2 Pin description

Table 2. Pin description

DAC1005D650_1 © NXP B.V. 2009. All rights reserved. [1] In compliance with JEDEC test board, in free air. Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Table 4. Thermal characteristics

DAC1005D650_1 © NXP B.V. 2009. All rights reserved. [1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. be connected across the pins (seeFigure8). and the inductance between the receiver and the driver circuit ground. [4] IMD3 rejection with−6 dBFS/tone.

3.51 MHz≤ foffset≤ 4 MHz;

4 MHz ≤ foffset≤ 40 MHz;

DAC1005D650_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 28 July 2009 13 of 41 NXP Semiconductors DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating 10. Application information

10.1 General description

The DAC1005D650 is a dual 10-bit DAC operating at up to 650 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 4-bit binary weighted sub-DAC. With an input data rate of up to 160 MHz, and a maximum output sampling rate of

650 Msps, the DAC1005D650 allows more ﬂexibility for wide bandwidth and multi-carrier

systems. Combined with its quadrature modulator and its 32-bit NCO, the DAC1005D650 simpliﬁes the frequency selection of the system. This is also possible because of the 2×, 4× and 8× interpolation ﬁlters that remove undesired images. Two modes are available for the digital input. In the Dual-port mode, each DAC uses its own data input line. In Interleaved mode, both DACs use the same data input line. Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and IOUTBP/IOUTBN. This provides a full-scale output current (I O(fs)) up to 20 mA. An internal reference is available for the reference current which is externally adjustable using pin VIRES. There are embedded features which provide analog offset correction (internal auxiliary DACs), digital offset control and gain adjustment. All the functions can be set using a SPI. The DAC1005D650 operates at both 3.3 V and 1.8 V using separate digital and analog power supplies. The digital input is 3.3 V compliant and the clock input is LVDS compliant.

10.2 Serial interface (SPI)

10.2.1 Protocol description

The DAC1005D650 serial interface is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. It provides access to the registers that deﬁne the operating modes of the chip in both write and read modes. This interface can be conﬁgured as a 3-wire type (SDIO as bidirectional pin) or a 4-wire type (SDIO and SDO as unidirectional pin, input and output port respectively). In both conﬁgurations, SCLK acts as the serial clock, and SCS_N acts as the serial chip select bar. Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW assertion to drive the chip with between 2 to 5 bytes, depending on the content of the instruction byte (see Table7).

10.2.2 SPI timing description

SPI can operate at a frequency of up to 15 MHz. The SPI timing is shown inFigure4. R/W indicates the mode access (seeTable6). Table 6. Read or Write mode access description

0 Write mode operation

1 Read mode operation

Table 7. Number of bytes to be transferred

10.2.3 Detailed descriptions of registers

An overview of the details for all registers is provided inTable9. Table 8. SPI timing characteristics

10.2.4 Registers detailed description

tables, all default results are shown highlighted. Table 10. COMMon register (address 00h) bit description Default settings are shown highlighted.

6 SPI_RST R/W serial interface reset

5 CLK_SEL R/W data input latch

3 MODE_SEL R/W input data mode

2 CODING R/W coding

1 IC_PD R/W power-down

0 GAP_PD R/W internal bandgap power-down

Table 11. TXCFG register (address 01h) bit description Default settings are shown highlighted.

7 NCO_ON R/W NCO

6 NCO_LP_SEL R/W low-power NCO

1 NCO frequency and phase given by the ﬁve

7 PLL_PD R/W PLL

5 PLL_DIV_PD R/W PLL divider

0 PLL_POL R/W DAC clock edge

Table 13. FREQNCO_LSB register (address 03h) bit description Table 14. FREQNCO_LISB register (address 04h) bit description Table 11. TXCFG register (address 01h) bit description …continued Default settings are shown highlighted.

DAC1005D650_1 © NXP B.V. 2009. All rights reserved. Table 15. FREQNCO_UISB register (address 05h) bit description Table 16. FREQNCO_MSB register (address 06h) bit description Table 17. PHINCO_LSB register (address 07h) bit description Table 18. PHINCO_MSB register (address 08h) bit description Table 19. DAC_A_Cfg_1 register (address 09h) bit description Default settings are shown highlighted.

7 DAC_A_PD R/W DAC A power

6 DAC_A_SLEEP R/W DAC A Sleep mode

Table 20. DAC_A_Cfg_2 register (address 0Ah) bit description Table 21. DAC_A_Cfg_3 register (address 0Bh) bit description

7 DAC_B_PD R/W DAC B power

6 DAC_B_SLEEP R/W DAC B Sleep mode

Table 23. DAC_B_Cfg_2 register (address 0Dh) bit description Table 24. DAC_B_Cfg_3 register (address 0Eh) bit description Table 25. DAC_Cfg register (address 0Fh) bit description Default settings are shown highlighted.

1 MINUS_3DB R/W NCO gain

0 NOISE_SHPER R/W noise shaper

Table 26. DAC_A_Aux_MSB register (address 1Ah) bit description Table 27. DAC_A_Aux_LSB register (address 1Bh) bit description Default settings are shown highlighted.

7 AUX_A_PD R/W auxiliary DAC A power

10.3 Input data

10.3.1 Dual-port mode

edge of the internal clock signal and is transferred to the DAC latch.

10.3.2 Interleaved mode

Table 28. DAC_B_Aux_MSB register (address 1Ch) bit description Table 29. DAC_B_Aux_LSB register (address 1Dh) bit description Default settings are shown highlighted.

7 AUX_B_PD R/W auxiliary DAC B power

Table 30. Mode selection

0 Dual-port mode (pin Q9) active active

1 Interleaved mode (pin SELIQ) active off

n in Qn = 0 to 9 and for In is 0 to 9.

DAC1005D650_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 28 July 2009 22 of 41 NXP Semiconductors DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating In the Interleaved mode, both DACs use the same data input at twice the Dual-port mode frequency. Data enters the latch on the rising edge of the internal clock signal. The data is sent to either latch I or latch Q, see Figure 6 “Interleaved mode operation” andFigure 7 “Interleaved mode timing (8x interpolation, latch on rising edge)”. The SELIQ input (pin 41) allows the synchronization of the internally de-multiplexed I and Q channels. SELIQ can be either a synchronous or asynchronous (single rising edge, single pulse) signal. The ﬁrst data bits following the SELIQ rising edge are sent in channel I and the following data bits are sent in channel Q. After this, the data is distributed alternately between both channels.

10.4 Input clock

The DAC1005D650 can operate with a clock frequency of 160 MHz in the Dual-port mode and up to 320 MHz in the Interleaved mode. The input clock is LVDS (see Figure8) but it can also be interfaced with CML (seeFigure9). n in Qn = 9 and for In is 0 to 9. Fig 6. Interleaved mode operation Fig 7. Interleaved mode timing (8x interpolation, latch on rising edge) 001aaj586 LATCH I 2 × 2 × 2 × FIR 1 FIR 1 FIR 2 FIR 2 FIR 3 FIR 3 LATCH Q 2 × 2 × 2 × In Qn/SELIQ 001aaj814 NIn SELIQ (synchronous alternative) SELIQ (asynchronous alternative 1) SELIQ (asynchronous alternative 2) CLK dig Latch I output Latch Q output XX N N + 2 N + 1 N + 2 N + 3 N + 4 N + 5 XX N + 1 N + 3

10.5 Timing

The DAC1005D650 can operate at an update rate (fs) of up to 650 Msps and with an input data rate (fdata) of up to 160 MHz. The input timing is shown inFigure 10 “Input timing diagram”. The typical performances are measured at 50 % duty cycle but any timing within the limits of the characteristics will not alter the performance. InTable 31 “Frequencies”, the links between internal and external clocking are deﬁned. The setting applied to PLL_DIV[1:0] (register 02h[4:3]; seeTable 12 “PLLCFG register (address02h)bitdescription”) allows the frequency between the digital part and the DAC core to be adjusted. Fig 8. LVDS clock conﬁguration Fig 9. Interfacing CML to LVDS 001aah021 Z = 50 Ω Zdiff = 100 Ω LVDS CLKP CLKNZ = 50 Ω LVDS 001aah020 55 Ω 55 Ω Z = 50 Ω 1.1 kΩ 2.2 kΩ 100 nF CML 100 nF 100 nF CLKP LVDS CLKN AGND VDDA(1V8) Z = 50 Ω Zdiff = 100 Ω n in Qn = 0 to 9 and for In is 0 to 9. Fig 10. Input timing diagram 001aaj815 N tsu(i) 90 % 50 % 90 %In/Qn CLK (CLKP-CLKN) th(i) tw(CLK) N + 1 N + 2

10.6 FIR ﬁlters

which enable the device to use interpolation rates of 2×, 4× or 8×. pass-band ripple of less than 0.0005 dB. [1] H(n) is the digital ﬁlter coefﬁcient. Table 33. Interpolation ﬁlter coefﬁcients

10.7 Quadrature modulator and NCO

The quadrature modulator allows the 10-bit I and Q data to be mixed with the carrier signal generated by the Numerically Controlled Oscillator (NCO). The frequency of the NCO is programmed over 32-bit and allows the sign of the sine component to be inverted in order to operate positive or negative, lower or upper single sideband up-conversion.

10.7.1 NCO in 32-bit

When using the NCO, the frequency can be set by the four registers FREQNCO_LSB, FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits. The frequency for the NCO in 32-bit is calculated as follows: (1) where M is the decimal representation of FREQ_NCO[31:0]. The phase of the NCO can be set from 0° to 360° by both registers PHINCO_LSB and PHINCO_MSB over 16 bits. The default setting is f NCO = 96 MHz when fs = 640 Msps and the default phase is 0°.

10.7.2 Low-power NCO

When using the low-power NCO, the frequency can be set by the 5 MSB of register FREQNCO_MSB. The frequency for the low-power NCO is calculated as follows: (2) where M is the decimal representation of FREQ_NCO[31:27]. The phase of the low-power NCO can be set by the 5 MSB of the register PHINCO_MSB.

10.7.3 Minus 3 dB

During normal use, a full-scale pattern will also be full scale at the output of the DAC. Nevertheless, when the I and Q data are simultaneously close to full scale, some clipping can occur and the Minus_3dB function can be used to reduce gain by 3 dB in the modulator. This is to keep a full-scale range at the output of the DAC without added interferers. 10.8 x / (sin x) Due to the roll-off effect of the DAC, a selectable FIR ﬁlter is inserted to compensate for the (sin x) / x effect. This ﬁlter introduces a DC loss of 3.4 dB. The coefﬁcients are represented in Table 34 “Inversion ﬁlter coefﬁcients”. fNCO Mf s× fNCO Mf s×

10.9 DAC transfer function

10.10 Full-scale current

10.10.1 Regulation

GAPOUT using a 100 nF capacitor. Table 34. Inversion ﬁlter coefﬁcients Table 35. DAC transfer function

1023 DATA–

10.10.2 Full-scale current adjustment

using SPI. The adjustment range is between 1.6 mA to 22 mA± 10 %. Table 36. IO(fs) coarse adjustment Default settings are shown highlighted.

10.11 Digital offset adjustment

adds an offset at the end of the digital part, just before the DAC. variation of the digital offset (seeTable 38 “Digital offset adjustment”). Table 37. I Default settings are shown highlighted. Table 36. I Default settings are shown highlighted.

10.12 Analog output

L to the 3.3 V analog power supply (VDDA(3V3)). improving the dynamic performance of the DAC by introducing less distortion. following stages and the targeted performances. Table 38. Digital offset adjustment Default settings are shown highlighted.

10.13 Auxiliary DACs

offset between the DAC and the next stage in the transmission path. ground). The settings applied to AUX_A[9:0] and AUX_B[9:0] deﬁne the offset data. Table 39. Auxiliary DAC transfer function Default settings are shown highlighted.

10.14 Output conﬁguration

10.14.1 Basic output conﬁguration

The use of a differentially-coupled transformer output provides optimum distortion performance (seeFigure 13 “Differential output with transformer; Vo(dif)(p-p) = 1 V”). In addition, it helps to match the impedance and provides electrical isolation. The DAC1005D650 can operate up to 2 Vo(p-p) differential outputs. In this conﬁguration, it is recommended to connect the center tap of the transformer to a 62Ω resistor connected to the 3.3 V analog power supply, in order to adjust the DC common mode to approximately 2.7 V (see Figure 14 “Differential output with transformer; Vo(dif)(p-p) = 2 V”).

10.14.2 DC interface to an AQM

When the system operation requires to keep the DC component of the spectrum, the DAC1005D650 can use a DC interface to connect to an Analog Quadrature Modulator (AQM). In this case, the offset compensation for LO cancellation can be made with the use of the digital offset control in the DAC. Figure15 provides an example of a connection to an AQM with a 1.7 V common mode input level. Fig 13. Differential output with transformer; Vo(dif)(p-p) = 1 V Fig 14. Differential output with transformer; Vo(dif)(p-p) = 2 V 001aaj817 50 Ω 50 Ω 50 Ω IOUTnP/IOUTnN; Vo(cm) = 2.8 V; Vo(dif)(p-p) = 1 V IOUTnP IOUTnN 0 mA to 20 mA 2:1 0 mA to 20 mA 3.3 V 3.3 V 001aaj818 50 Ω 100 Ω 100 Ω IOUTnP/IOUTnN; Vo(cm) = 2.7 V; Vo(dif)(p-p) = 2 V IOUTnP IOUTnN 0 mA to 20 mA 4:1 0 mA to 20 mA 3.3 V 62 Ω 3.3 V 3.3 V

DAC1005D650_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 28 July 2009 33 of 41 NXP Semiconductors DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating Figure16 provides an example of a connection to an AQM with a 3.3 Vi(cm)common mode input level. Fig 15. An example of a DC interface to a 1.7 V AQM Fig 16. An example of a DC interface to a 3.3 V AQM 001aaj541 51.1 Ω 51.1 Ω 442 Ω 442 Ω 3.3 V IOUTnP IOUTnN 0 mA to 20 mA BBP (1) IOUTnP/IOUTnN; Vo(cm) = 2.67 V; Vo(dif)(p-p) = 1.98 V (2) BBP/BBN; Vi(cm) = 1.7 V; Vi(dif)(p-p) = 1.26 V BBN AQM (V i(cm) = 1.7 V) 768 Ω 768 Ω (1) (2) 001aaj542 54.9 Ω 54.9 Ω 237 Ω 237 Ω 3.3 V IOUTnP IOUTnN BBP BBN AQM (V i(cm) = 3.3 V) 750 Ω 750 Ω 5 V 1.27 kΩ 1.27 kΩ (1) IOUTnP/IOUTnN; Vo(cm) = 2.75 V; Vo(dif)(p-p) = 1.97 V (2) BBP/BBN; Vi(cm) = 3.3 V; Vi(dif)(p-p) = 1.5 V (1) (2)

DAC1005D650_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 28 July 2009 34 of 41 NXP Semiconductors DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating The auxiliary DACs can be used to control the offset in a precise range or with precise steps. Figure17 provides an example of a DC interface with the auxiliary DACs to an AQM with a 1.7 V common mode input level. Figure18 provides an example of a DC interface with the auxiliary DACs to an AQM with a 3.3 V common mode input level. Fig 17. An example of a DC interface to a 1.7 Vi(cm) AQM using auxiliary DACs Fig 18. An example of a DC interface to a 3.3 Vi(cm) AQM using auxiliary DACs 001aaj543 51.1 Ω 51.1 Ω 442 Ω 442 Ω 3.3 V IOUTnP IOUTnN 0 mA to 20 mA BBP BBN AQM (V i(cm) = 1.7 V) 698 Ω 698 Ω 51.1 Ω 51.1 Ω AUXnP AUXnN 1.1 mA (typ.) (1) IOUTnP/IOUTnN; Vo(cm) = 2.67 V; Vo(dif)(p-p) = 1.94 V (2) BBP/BBN; Vi(cm) = 1.7 V; Vi(dif)(p-p) = 1.23 V; offset correction up to 36 mV (1) (2) 001aaj544 54.9 Ω 54.9 Ω 237 Ω 237 Ω 3.3 V IOUTnP IOUTnN AUXnP AUXnN BBP BBN AQM (V i(cm) = 3.3 V) 750 Ω 750 Ω 5 V 634 kΩ 634 kΩ 442 kΩ 442 kΩ (1) IOUTnP/IOUTnN; Vo(cm) = 2.75 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; Vi(cm) = 3.3 V; Vi(dif)(p-p) = 1.5 V; offset correction up to 36 mV (1) (2)

DAC1005D650_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 28 July 2009 35 of 41 NXP Semiconductors DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating The constraints to adjust the interface are the output compliance range of the DAC and the auxiliary DACs, the input common mode level of the AQM, and the range of offset correction required.

10.14.3 AC interface to an AQM

When the Analog Quadrature Modulator (AQM) common mode voltage is close to ground, the DAC1005D650 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure18 provides an example of a connection to an AQM with a 0.5 V common mode input level when using auxiliary DACs.

10.15 Power and grounding

In order to obtain optimum performance, it is recommended that the 1.8 V analog power supplies on pins 5, 11, 71, 77 and 99 should not be connected with those on pins 70, 79, 81, 83, 93, 95 and 97 on the top layer. To optimize the decoupling, the power supplies should be decoupled with the following pins:

VDDD(1V8) : pin 26 with 27; pin 32 with 33; pin 36 with 37; pin 40 with 39; pin 44 with 43 and pin 50 with 49.
VDD(IO)(3V3): pin 16 with 17 and pin 60 with 59.
VDDA(1V8): pin 5 with 4; pin 6 with 7; pin 11 with 10; pin 71 with 72; pin 77 with 78; pins 79, 81, 83 with 80, 82, 84; pins 93, 95, 97 with 92, 94, 96 and pin 99 with 98.
VDDA(3V3): pin 1 with 100 and pin 75 with 76. Fig 19. An example of an AC interface to a 0.5 Vi(cm) AQM using auxiliary DACs 001aaj589 66.5 Ω 66.5 Ω 10 nF 3.3 V IOUTnP IOUTnN 0 mA to 20 mA BBP BBN AQM (V i(cm) = 0.5 V) 2 kΩ 2 kΩ 5 V 174 Ω 174 Ω 34 Ω 34 Ω AUXnP AUXnN 1.1 mA (typ.) 10 nF (1) IOUTnP/IOUTnN; Vo(cm) = 2.65 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; Vi(cm) = 0.5 V; Vi(dif)(p-p) = 1.96 V; offset correction up to 70 mV (1) (2)

10.16 Alternative parts

The following alternative parts are available. Table 40. Alternative parts

DAC1005D650_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 28 July 2009 37 of 41 NXP Semiconductors DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating 11. Package outline Fig 20. Package outline SOT638-1 (HTQFP100) UNIT A max. A 1 A 2 A 3 bp H D H E Lp ZD (1) ZE(1)ce L y wv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.15 15.85 1.15 0.85 0°0.08 0.080.21 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT638-1 MS-026 03-04-07 05-02-02 D (1) E(1) 14.1 13.9 16.15 15.85 D h Eh 7.1 6.1 7.1 6.1 1.15 0.85 bp bp e q E A1A Lp detail X L (A3) B H D H E A2 v M B D ZD A c ZE e v M A X 100 75 51 y pin 1 index w M w M 0 10 mm scale HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad SOT638-1 D h Eh exposed die pad side

DAC1005D650_1 © NXP B.V. 2009. All rights reserved. (harmonic and non-harmonic, excluding DC component) in the frequency domain. nd and 3rd order components) are deﬁned below. Table 42. Revision history

DAC1005D650_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 28 July 2009 40 of 41 NXP Semiconductors DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating 15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

15.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control —This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit:http://www.nxp.com For sales ofﬁce addresses, please send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 July 2009 Document identifier: DAC1005D650_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 17. Contents

Product Information

DAC1005D650HW/C1 specifications and overview.

Summary

Dual 10-bit DAC, up to 650 Msps; 2쨈 4쨈 and 8쨈 interpolating Rev. 01-28 July 2009

Description

Dual 10-bit DAC, up to 650 Msps; 2쨈 4쨈 and 8쨈 interpolating Rev. 01-28 July 2009

Source title DAC1005D650HW/C1 Datasheet(PDF) - NXP Semiconductors

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