DAC1005D650

Renesas Technology Corp

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 2 July 2012

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General description The DAC1005D650 is a high-speed 10-bit dual-channel Digital-to-Analog Converter (DAC) with selectable 2, 4 or 8 interpolating filters optimized for multi-carrier wireless transmitters. Thanks to its digital on-chip modulation, the DAC1005D650 allows the complex I and Q inputs to be converted up from BaseBand (BB) to IF. The mixing frequency is adjusted using a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO). The phase is controlled by a 16-bit register. Two modes of operation are available: separate data ports or a single interleaved high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched. The DAC1005D650 also includes a 2, 4 and 8 clock multiplier which provides the appropriate internal clocks and an internal regulator to adjust the output full-scale current. 2. Features and benefits DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Rev. 04 — 2 July 2012 Product data sheet  Dual 10-bit resolution  IMD3: 79 dBc; fs = 640 Msps; fo =9 6M H z  650 Msps maximum update rate  SFDR: 75 dBc; fdata =8 0M H z ; fs = 640 Msps; fo = 19 MHz; PLL on  Selectable 2, 4 or 8 interpolation filters  Typical 0.95 W power dissipation at 4 interpolation  Input data rate up to 160 Msps  Power-down and Sleep modes  Very low noise cap-free integrated PLL  Differential scalable output current from 1.6 mA to 20 mA  32-bit programmable NCO frequency  On-chip 1.29 V reference  Dual-port or Interleaved data modes  External analog offset control (10-bit auxiliary DACs)  1.8 V and 3.3 V power supplies  Internal digital offset control  LVDS compatible clock  Inverse (sin x) / x function  Two’s complement or binary offset data format  Fully compatible SPI port  3.3 V CMOS input buffers  Industrial temperature range from 40 C to +85 C

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx DAC1005D650 4© IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 3 of 41 Integrated Device TechnologyDAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 5. Block diagram Fig 1. Block diagram 001aak158 DAC1005D650 FIR1 2 × 2 × FIR1 FIR2 2 × 2 × FIR2 FIR3 2 × 2 × FIR3 NCO cos sin CLOCK GENERATOR/ PLL COMPLEX MODULATOR LATCH Q LATCH I CLKP RESET_N DAC AUXILIARY DAC AUXILIARY DAC DAC REFERENCE BANDGAP OFFSET CONTROL 10-BIT GAIN CONTROL 10-BIT OFFSET CONTROL 10-BIT GAIN CONTROL 10-BIT OFFSET CONTROL SCLK SCS_N SDIO SDO 41, 42 45 to 48, 51 to 54 18 to 25, 28, 29 63 65 64 CLKN Q0 to Q9 dual port/ interleaved data modes I0 to I9 SPI AUXAN GAPOUT AUXAP IOUTAN VIRES IOUTAP IOUTBN IOUTBP AUXBN AUXBP mixer A B mixer mixer mixer x sin x x sin x

DAC1005D650 4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 4 of 41 Integrated Device Technology DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 6. Pinning information

6.1 Pinning

Fig 2. Pin configuration DAC1005D650HW VDDA(3V3) VDDA(3V3) AUXAP AUXBP AUXAN AUXBN AGND AGND VDDA(1V8) VDDA(1V8) VDDA(1V8) VDDA(1V8) AGND GAPOUT CLKP VIRES CLKN d.n.c. AGND RESET_N VDDA(1V8) SCS_N d.n.c. SCLK d.n.c. SDIO TM1 SDO I7 n.c. I6 n.c. I5 Q0 I4 Q1 TM0 VDD(IO)(3V3) GNDIO TM3 V DD(IO)(3V3) GNDIO n.c. n.c. I2 Q3 VDDD(1V8)AGND DGNDVDDA(1V8) I1AGND I0VDDA(1V8) n.c.AGND n.c.VDDA(1V8) VDDD(1V8)AGND DGNDVDDA(1V8) n.c.AGND n.c.IOUTAN VDDD(1V8)IOUTAP DGNDAGND TM2n.c. DGNDAGND Q7VDDA(1V8) Q6AGND Q5VDDA(1V8) Q4AGND DGND VDDD(1V8) Q9/SELIQ DGND VDDD(1V8) VDDA(1V8) IOUTBP IOUTBN AGND V DDA(1V8) AGND VDDD(1V8)AGND 001aak159 100 AGND

6.2 Pin description

Table 2. Pin description

DAC1005D650 4 © IDT 2012. All rights reserved. [1] In compliance with JEDEC test board, in free air. Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Table 4. Thermal characteristics

DAC1005D650 4 © IDT 2012. All rights reserved. [1] D = guaranteed by design; C = guaranteed by c haracterization; I = 100 % industrially tested. be connected across the pins (see Figure 8). and the inductance between the receiver and the driver circuit ground. [4] IMD3 rejection with 6 dBFS/tone.

3.51 MHz  foffset  4 MHz;

4 MHz  foffset  40 MHz;

DAC1005D650 4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 13 of 41 Integrated Device Technology DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 10. Application information

10.1 General description

The DAC1005D650 is a dual 10-bit DAC operating at up to 650 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 4-bit binary weighted sub-DAC. With an input data rate of up to 160 MHz, and a maximum output sampling rate of

650 Msps, the DAC1005D650 allows more flexibility for wide bandwidth and multi-carrier

systems. Combined with its quadrature modulator and its 32-bit NCO, the DAC1005D650 simplifies the frequency selection of the system. This is also possible because of the 2, 4 and 8 interpolation filters that remove undesired images. Two modes are available for the digital input. In the Dual-port mode, each DAC uses its own data input line. In Interleaved mode, both DACs use the same data input line. Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and IOUTBP/IOUTBN. This provides a full-scale output current (IO(fs)) up to 20 mA. An internal reference is available for the reference current which is externally adjustable using pin VIRES. There are embedded features which provide analog offset correction (internal auxiliary DACs), digital offset control and gain adjustment. All the functions can be set using a SPI. The DAC1005D650 operates at both 3.3 V and 1.8 V using separate digital and analog power supplies. The digital input is 3.3 V compliant and the clock input is LVDS compliant.

10.2 Serial interface (SPI)

10.2.1 Protocol description

The DAC1005D650 serial interface is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. It provides access to the registers that define the operating modes of the chip in both write and read modes. This interface can be configured as a 3-wire type (SDIO as bidirectional pin) or a 4-wire type (SDIO and SDO as unidirectional pin, input and output port respectively). In both configurations, SCLK acts as the serial clock, and SCS_N acts as the serial chip select bar. If several DAC1005D650 devices are connected to an application on the same SPI-bus, only a 3-wire type can be used. Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW assertion to drive the chip with between 2 to 5 bytes, depending on the content of the instruction byte (see Table 7).

DAC1005D650 4 © IDT 2012. All rights reserved. In Table 7 N1 and N0 indicate the number of bytes transferred after the instruction byte. decreasing order according to Table 9 “Register allocation map”.

10.2.2 SPI timing description

SPI can operate at a frequency of up to 15 MHz. The SPI timing is shown in Figure 4. R/W indicates the mode access (see Table 6). Table 6. Read or Write mode access description

0 Write mode operation

1 Read mode operation

Table 7. Number of bytes to be transferred

10.2.3 Detailed descriptions of registers

An overview of the details for all registers is provided in Table 9. Table 8. SPI timing characteristics

10.2.4 Registers detailed description

tables, all default results are shown highlighted. Table 10. COMMon register (a ddress 00h) bit description Default settings are shown highlighted.

6 SPI_RST R/W serial interface reset

5 CLK_SEL R/W data input latch

3 MODE_SEL R/W input data mode

2 CODING R/W coding

1 IC_PD R/W power-down

0 GAP_PD R/W internal bandgap power-down

Table 11. TXCFG register (address 01h) bit description Default settings are shown highlighted.

7 NCO_ON R/W NCO

6 NCO_LP_SEL R/W low-power NCO

1 NCO frequency and phase given by the five

7 PLL_PD R/W PLL

5 PLL_DIV_PD R/W PLL divider

0 PLL_POL R/W DAC clock edge

Table 13. FREQNCO_LSB register (address 03h) bit description Table 14. FREQNCO_LISB register (address 04h) bit description Table 11. TXCFG register (address 01h) bit description …continued Default settings are shown highlighted.

DAC1005D650 4 © IDT 2012. All rights reserved. Table 15. FREQNCO_UISB register (address 05h) bit description Table 16. FREQNCO_MSB register (address 06h) bit description Table 17. PHINCO_LSB register (address 07h) bit description Table 18. PHINCO_MSB register (address 08h) bit description Table 19. DAC_A_Cfg_1 register (a ddress 09h) bit description Default settings are shown highlighted.

7 DAC_A_PD R/W DAC A power

6 DAC_A_SLEEP R/W DAC A Sleep mode

Table 20. DAC_A_Cfg_2 register (a ddress 0Ah) bit description Table 21. DAC_A_Cfg_3 register (a ddress 0Bh) bit description

7 DAC_B_PD R/W DAC B power

6 DAC_B_SLEEP R/W DAC B Sleep mode

Table 23. DAC_B_Cfg_2 register (a ddress 0Dh) bit description Table 24. DAC_B_Cfg_3 register (address 0Eh) bit description Table 25. DAC_Cfg register (add ress 0Fh) bit description Default settings are shown highlighted.

1 MINUS_3DB R/W NCO gain

0 NOISE_SHPER R/W noise shaper

Table 26. DAC_A_Aux_MSB register (address 1Ah) bit description Table 27. DAC_A_Aux_LSB register (address 1Bh) bit description Default settings are shown highlighted.

7 AUX_A_PD R/W auxiliary DAC A power

10.3 Input data

10.3.1 Dual-port mode

edge of the internal clock signal and is transferred to the DAC latch.

10.3.2 Interleaved mode

Table 28. DAC_B_Aux_MSB register (address 1Ch) bit description Table 29. DAC_B_Aux_LSB register (address 1Dh) bit description Default settings are shown highlighted.

7 AUX_B_PD R/W auxiliary DAC B power

Table 30. Mode selection

0 Dual-port mode (pin Q9) active active

1 Interleaved mode (pin SELIQ) active off

n in Qn = 0 to 9 and for In is 0 to 9.

DAC1005D650 4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 22 of 41 Integrated Device Technology DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating In the Interleaved mode, both DACs use the same data input at twice the Dual-port mode frequency. Data enters the latch on the rising edge of the internal clock signal. The data is sent to either latch I or latch Q, see Figure 6 “Interleaved mode operation” and Figure 7 “Interleaved mode timing (8x interpolation, latch on rising edge)”. The SELIQ input (pin 41) allows the synchronization of the internally de-multiplexed I and Q channels. SELIQ can be either a synchronous or asynchronous (single rising edge, single pulse) signal. The first data bits following the SELIQ rising edge are sent in channel I and the following data bits are sent in channel Q. After this, the data is distributed alternately between both channels.

10.4 Input clock

The DAC1005D650 can operate with a clock frequency of 160 MHz in the Dual-port mode and up to 320 MHz in the Interleaved mode. The input clock is LVDS (see Figure 8) but it can also be interfaced with CML (see Figure 9). n in Qn = 9 and for In is 0 to 9. Fig 6. Interleaved mode operation Fig 7. Interleaved mode timing (8x in terpolation, latch on rising edge) 001aaj586 LATCH I 2 × 2 × 2 × FIR 1 FIR 1 FIR 2 FIR 2 FIR 3 FIR 3 LATCH Q 2 × 2 × 2 × In Qn/SELIQ 001aaj814 NIn SELIQ (synchronous alternative) SELIQ (asynchronous alternative 1) SELIQ (asynchronous alternative 2) CLKdig Latch I output Latch Q output XX N N + 2 N + 1 N + 2 N + 3 N + 4 N + 5 XX N + 1 N + 3

10.5 Timing

The DAC1005D650 can operate at an update rate (fs) of up to 650 Msps and with an input data rate (fdata) of up to 160 MHz. The input timing is shown in Figure 10 “Input timing diagram”. The typical performances are measured at 50 % duty cycle but any timing within the limits of the characteristics will not alter the performance. In Table 31 “Frequencies”, the links between internal and external clocking are defined. The setting applied to PLL_DIV[1:0] (register 02h[4:3]; see Table 12 “PLLCFG register (address 02h) bit description”) allows the frequency between the digital part and the DAC core to be adjusted. Fig 8. LVDS clock configuration Fig 9. Interfacing CML to LVDS 001aah021 100 Ω LVDS CLKINP CLKINN LVDS Zdiff = 100 Ω 001aah020 55 Ω 55 Ω 1.1 kΩ 2.2 kΩ 100 nF CML 100 nF 100 nF CLKINP LVDS CLKINN AGND VDDA(1V8) 1 kΩZdiff = 100 Ω n in Qn = 0 to 9 and for In is 0 to 9. Fig 10. Input timing diagram 001aaj815 N tsu(i) 90 % 50 % 90 %In/Qn CLK (CLKP-CLKN) th(i) tw(CLK) N + 1 N + 2

10.6 FIR filters

which enable the device to use interpolation rates of 2, 4 or 8. pass-band ripple of less than 0.0005 dB. Table 31. Frequencies Table 32. Sample clock phase and polarity examples

10.7 Quadrature modulator and NCO

The quadrature modulator allows the 10-bit I and Q data to be mixed with the carrier signal generated by the Numerically Controlled Oscillator (NCO). The frequency of the NCO is programmed over 32-bit and allows the sign of the sine component to be inverted in order to operate positive or negative, lower or upper single sideband up-conversion.

10.7.1 NCO in 32-bit

When using the NCO, the frequency can be set by the four registers FREQNCO_LSB, FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits. The frequency for the NCO in 32-bit is calculated as follows: (1) where M is the decimal representation of FREQ_NCO[31:0]. The phase of the NCO can be set from 0 to 360 by both registers PHINCO_LSB and PHINCO_MSB over 16 bits. The default setting is fNCO = 96 MHz when fs = 640 Msps and the default phase is 0.

10.7.2 Low-power NCO

When using the low-power NCO, the frequency can be set by the 5 MSB of register FREQNCO_MSB. The frequency for the low-power NCO is calculated as follows: (2) where M is the decimal representation of FREQ_NCO[31:27]. The phase of the low-power NCO can be set by the 5 MSB of the register PHINCO_MSB.

10.7.3 Minus 3 dB

During normal use, a full-scale pattern will also be full scale at the output of the DAC. Nevertheless, when the I and Q data are simultaneously close to full scale, some clipping can occur and the Minus_3dB function can be used to reduce gain by 3 dB in the modulator. This is to keep a full-scale range at the output of the DAC without added interferers. 10.8 x / (sin x) Due to the roll-off effect of the DAC, a selectable FIR filter is inserted to compensate for the (sin x) / x effect. This filter introduces a DC loss of 3.4 dB. The coefficients are represented in Table 34 “Inversion filter coefficients”. fNCO Mf s fNCO Mf s

10.9 DAC transfer function

Table 34. Inversion filter coefficients Table 35. DAC transfer function

1023 DATA–

10.10 Full-scale current

10.10.1 Regulation

The DAC1005D650 reference circuitry integrates an internal bandgap reference voltage which delivers a 1.29 V reference to the GAPOUT pin. It is recommended to decouple pin GAPOUT using a 100 nF capacitor. The reference current is generated using an external resistor of 953  (1 %) connected to pin VIRES. A control amplifier sets the appropriate full-scale current (IO(fs)) for both DACs (see Figure 11 “Internal reference configuration”). This configuration is optimum for temperature drift compensation because the bandgap reference voltage can be matched to the voltage across the feedback resistor. The DAC current can also be set by applying an external reference voltage to the non-inverting input pin GAPOUT and disabling the internal bandgap reference voltage with GAP_PD (register 00h[0]; see Table 10 “COMMon register (address 00h) bit description”).

10.10.2 Full-scale current adjustment

The default full-scale current (IO(fs)) is 20 mA. It can be further adjusted for each DAC using SPI. The adjustment range is between 1.6 mA to 22 mA  10 %. The settings applied to DAC_A_GAIN_COARSE[3:0] (register 0Ah; see Table 20 “DAC_A_Cfg_2 register (address 0Ah) bit description” and register 0Bh; see Table 21 “DAC_A_Cfg_3 register (address 0Bh) bit description”) and to DAC_B_GAIN COARSE[3:0] (register 0Dh; see Table 23 “DAC_B_Cfg_2 register (address 0Dh) bit description” and register 0Eh; see Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit description”) define the coarse variation of the full-scale current (see Table 36 “IO(fs) coarse adjustment”). Fig 11. Internal reference configuration aaa-002266 REF. BANDGAP GAPOUT VDDA(1V8) VIRES DAC CURRENT SOURCES ARRAY AGND AGND 100 nF 953 Ω (1 %) 100 kΩ

10.11 Digital offset adjustment

adds an offset at the end of the digital part, just before the DAC. Table 36. I O(fs) coarse adjustment Default settings are shown highlighted. Table 37. I Default settings are shown highlighted.

10.12 Analog output

a load resistor RL to the 3.3 V analog power supply (VDDA(3V3)). improving the dynamic performance of the DAC by introducing less distortion. following stages and the targeted performances. Table 38. Digital offset adjustment Default settings are shown highlighted.

10.13 Auxiliary DACs

any offset between the DAC and the next stage in the transmission path. ground). The settings applied to AUX_A[9:0] and AUX_B[9:0] define the offset data. Table 39. Auxiliary DAC transfer function Default settings are shown highlighted.

10.14 Output c onfiguration

10.14.1 Basic output configuration

The use of a differentially-coupled transformer output provides optimum distortion performance (see Figure 13 “Differential output with transformer; Vo(dif)(p-p) = 1 V”). In addition, it helps to match the impedance and provides electrical isolation. The DAC1005D650 can operate up to 2 Vo(p-p) differential outputs. In this configuration, it is recommended to connect the center tap of the transformer to a 62  resistor connected to the 3.3 V analog power supply, in order to adjust the DC common mode to approximately 2.7 V (see Figure 14 “Differential output with transformer; V o(dif)(p-p) = 2 V”).

10.14.2 DC interface to an AQM

When the system operation requires to keep the DC component of the spectrum, the DAC1005D650 can use a DC interface to connect to an Analog Quadrature Modulator (AQM). In this case, the offset compensation for LO cancellation can be made with the use of the digital offset control in the DAC. Figure 15 provides an example of a connection to an AQM with a 1.7 V common mode input level. Fig 13. Differential output with transformer; V o(dif)(p-p) = 1 V Fig 14. Differential output with transformer; V o(dif)(p-p) = 2 V 001aaj817 50 Ω 50 Ω 50 Ω IOUTnP/IOUTnN; Vo(cm) = 2.8 V; Vo(dif)(p-p) = 1 V IOUTnP IOUTnN 0 mA to 20 mA 2:1 0 mA to 20 mA VDDA(3V3) VDDA(3V3) 001aaj818 50 Ω 100 Ω 100 Ω IOUTnP/IOUTnN; Vo(cm) = 2.7 V; Vo(dif)(p-p) = 2 V IOUTnP IOUTnN 0 mA to 20 mA 4:1 0 mA to 20 mA VDDA(3V3) 62 Ω VDDA(3V3) VDDA(3V3)

DAC1005D650 4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 33 of 41 Integrated Device Technology DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating Figure 16 provides an example of a connection to an AQM with a 3.3 Vi(cm) common mode input level. Fig 15. An example of a DC interface to a 1.7 V AQM Fig 16. An example of a DC interface to a 3.3 V AQM 001aaj541 51.1 Ω 51.1 Ω 442 Ω 442 Ω VDDA(3V3) IOUTnP IOUTnN 0 mA to 20 mA BBP (1) IOUTnP/IOUTnN; Vo(cm) = 2.67 V; Vo(dif)(p-p) = 1.98 V (2) BBP/BBN; Vi(cm) = 1.7 V; Vi(dif)(p-p) = 1.26 V BBN AQM (Vi(cm) = 1.7 V) 768 Ω 768 Ω (1) (2) 001aaj542 54.9 Ω 54.9 Ω 237 Ω 237 Ω VDDA(3V3) IOUTnP IOUTnN BBP BBN AQM (Vi(cm) = 3.3 V) 750 Ω 750 Ω 5 V 1.27 kΩ 1.27 kΩ (1) IOUTnP/IOUTnN; Vo(cm) = 2.75 V; Vo(dif)(p-p) = 1.97 V (2) BBP/BBN; Vi(cm) = 3.3 V; Vi(dif)(p-p) = 1.5 V (1) (2)

DAC1005D650 4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 35 of 41 Integrated Device Technology DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating The constraints to adjust the interface are the output compliance range of the DAC and the auxiliary DACs, the input common mode level of the AQM, and the range of offset correction required.

10.14.3 AC interface to an AQM

When the Analog Quadrature Modulator (AQM) common mode voltage is close to ground, the DAC1005D650 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 18 provides an example of a connection to an AQM with a 0.5 V common mode input level when using auxiliary DACs.

10.15 Power and grounding

In order to obtain optimum performance, it is recommended that the 1.8 V analog power supplies on pins 5, 11, 71, 77 and 99 should not be connected with those on pins 70, 79, 81, 83, 93, 95 and 97 on the top layer. To optimize the decoupling, the power supplies should be decoupled with the following pins:

VDDD(1V8): pin 26 with 27; pin 32 with 33; pin 36 with 37; pin 40 with 39; pin 44 with 43 and pin 50 with 49.
VDD(IO)(3V3): pin 16 with 17 and pin 60 with 59.
VDDA(1V8): pin 5 with 4; pin 6 with 7; pin 11 with 10; pin 71 with 72; pin 77 with 78; pins 79, 81, 83 with 80, 82, 84; pins 93, 95, 97 with 92, 94, 96 and pin 99 with 98.
VDDA(3V3): pin 1 with 100 and pin 75 with 76. Fig 19. An example of an AC interface to a 0.5 V i(cm) AQM using auxiliary DACs 001aaj589 66.5 Ω 66.5 Ω 10 nF VDDA(3V3) IOUTnP IOUTnN 0 mA to 20 mA BBP BBN AQM (Vi(cm) = 0.5 V) 2 kΩ 2 kΩ 5 V 174 Ω 174 Ω 34 Ω 34 Ω AUXnP AUXnN 1.1 mA (typ.) 10 nF (1) IOUTnP/IOUTnN; Vo(cm) = 2.65 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; Vi(cm) = 0.5 V; Vi(dif)(p-p) = 1.96 V; offset correction up to 70 mV (1) (2)

10.16 Alternative parts

The following alternative parts are available. Table 40. Alternative parts

DAC1005D650 4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 37 of 41 Integrated Device Technology DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 11. Package outline Fig 20. Package outline SOT638-1 (HTQFP100) UNIT A max. A1 A2 A3 bp HD HE Lp ZD(1) ZE(1)ce L y wv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.15 15.85 1.15 0.85 0°0.08 0.080.21 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT638-1 MS-026 03-04-07 05-02-02 D(1) E(1) 14.1 13.9 16.15 15.85 Dh Eh 7.1 6.1 7.1 6.1 1.15 0.85 bp bp e θ E A1A Lp detail X L (A3) B HD HE A2 v M B D ZD A c ZE e v M A X 100 75 51 y pin 1 index w M w M 0 10 mm scale HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad SOT638-1 Dh Eh exposed die pad side

DAC1005D650 4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 39 of 41 Integrated Device Technology DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 13. Glossary Spurious-Free Dynamic Range (SFDR): — The ratio between the RMS value of the reconstructed output sine wave and the RMS value of the largest spurious observed (harmonic and non-harmonic, excluding DC component) in the frequency domain. Intermodulation Distortion (IMD): — From a dual-tone digital input sine wave (these two frequencies being close together), the intermodulation distortion products IMD2 and IMD3 (respectively, 2 nd and 3rd order components) are defined below. IMD2 — The ratio of the RMS value of either tone to the RMS value of the worst 2nd order intermodulation product. IMD3 — The ratio of the RMS value of either tone to the RMS value of the worst 3rd order intermodulation product. Restricted Bandwidth Spurious-Free Dynamic Range — The ratio of the RMS value of the reconstructed output sine wave to the RMS value of the noise, including the harmonics, in a given bandwidth centered around foffset.

Section 2 “Features and benefits” has been updated.
The values for VO(ref) in Table 5 “Characteristics” have been updated.
Section 10.2.1 “Protocol description” has been updated.
Section 10.10.1 “Regulation” has been updated. DAC1005D650 v2 20100903 Product data sheet - DAC1005D650 v1 DAC1005D650 v1 20090728 Product data sheet - -

DAC1005D650 4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 41 of 41 Integrated Device Technology DAC1005D650 Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 16. Contents

Product Information

DAC1005D650 specifications and overview.

Summary

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 2 July 2012

Description

Dual 10-bit DAC, up to 650 Msps; 2 4 and 8 interpolating 2 July 2012

Source title DAC1005D650 Datasheet(PDF) - Renesas Technology Corp

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