DAC1003D160 | DigiCamel IC Datasheet

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Dual 10 bits DAC, up to 160 MHz, 2 x interpolation Rev. 03 — 2 July 2012 Product data sheet 1. General description The DAC1003D160 is optimized to reduce architecture complexity and overall system cost. The Digital-to-Analog Converter (DAC) lea ds dynamic performance in multi-carrier support because of its direct IF conversion capabilities. With an internal sampling rate up to 160 MHz, the DAC1003D160 is an extremely competitive solution for broadband wireless systems transmitters, as well as a wide range of applications. 2. Features  Dual 10-bit resolution  S purious Free Dynamic Range (SFDR) = 80 dBc at 2.5 MHz  Input dat a rate up to 80 MHz  2  interpolation filter  Output dat a rate up to 160 Mhz  Sing le 3.3 V power supply  L ow noise capacitor free integrated Phase-Locked Loop (PLL)  Low power diss ipation  HTQF P80 package  Am bient temperature from 40 C to + 85 C 3. Applications  Broadband wireless systems  Digit al radio links  Cellular base stations  Instru mentation  Ca ble modems  Ca ble Modem Termination System (CMTS) /Data Over Cable Service Interface Specification (DOCSIS)

72 IOUT

57 GAPD

60 IVIRES

59 QVIRES

6.1 Pinning

6.2 Pin description

Table 2. Pin description

DAC1003D160_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 6 of 18 Integrated Device Technology DAC1003D160 Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 7. Functional description The DAC1003D160 is a segmented architecture composed of a 7-bit thermometer sub-DAC and the remaining 3-bit in a binary weighted sub-DAC. The device produces two complementary current ou tputs on both channels, respectively pins IOUT/IOUTN and QOUT/QOUTN which need to be connected via a load resistor to the ground. Figure 3 shows the equivalent analog output circuit of one D AC, which consists of a parallel combination of PMOS current sources and associated switches for each segment. The cascade source configuration enables the increase of the output impedance of the sou rce and the improvement of the dynamic performance of the DAC by introducing less distortion. Figure 4 shows the internal reference configuration. I n this case the bias current is given by the output of the internal regulator connected to the inverting input of the internal operational amplifiers, while external resistors RI and RQ are connected respectively to pins IVIRES and QVIRES. Thus the output current of the two DACs is typically fixed to 20 mA with an appropriate choice of these resistor s. This configuration is optimal for temperature drift compensation because the band gap can be matched with the voltage on the feedback resistors. The relation between full-scale output current IO(fs) and the RI (RQ) is: RI

2048 V GAPOUT

The output current can also be adjusted by im posing an external reference voltage to the inverting input pin GAPOUT and disabling the internal band gap with pin GAPD set to HIGH. At a voltage lower than 1.2 V the current can be set at values lower than 20 mA. Th e input references at pins IVIRES and QVIRES may also be driven by separate reference voltages to adjust independently the two DAC currents. 014aaa537 AGND RL RL AGND IOUT/QOUT IOUTN/QOUTN DAC1003D160 014aaa538 QVIRES IVIRES GAPOUT AGND GAPD INTERNAL BAND GAP I DAC current sources array DAC1003D160 Q DAC current sources array R I RQ Fig 3. Equivalent analog output circuit Fig 4. Internal reference configuration

DAC1003D160_3 © IDT 2012. All rights reserved. Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). [1] All supplies are connected together. Table 4. Thermal characteristics Table 5. Characteristics Figure 10; unless otherwise specified.

tsu(i) th(i) CLKN CLK IOUT/IOUTN, QOUT/QOUTN 50 % I0 to I9, Fig 5. Input timing diagram DAC1003D160_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 10 of 18 Integrated Device Technology DAC1003D160 Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

DAC1003D160_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 12 of 18 Integrated Device Technology DAC1003D160 Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 11. Application information 014aaa539 1 kΩ 100 nF Vth 1 kΩ AGND CLKN VCCA CLK DAC1003D160 Rs 014aaa540 1 kΩ 100 nF 1 kΩ CLKN VCCA AGND AGND AGND CLK DAC1003D160 1 kΩ 1 kΩ 100 nF 100 nF Fig 8. Single-ended clock schematic Fig 9. Differential clock schematic

DAC1003D160_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 13 of 18 Integrated Device Technology DAC1003D160 Dual 10 bits DAC, up to 160 MHz, 2 x interpolation C DAC1003D160 VCCA IVIRES i.c. QVIRES VCCA GAPOUT AGND GAPD CLK DGND CLKN DGND AGND DGND AGND 3.3 V AGND 3.3 V AGND DGND 3.3 V DGND DGND DGND DGND DGND 3.3 V DGND DGND i.c. DGND DGND DGND VCCD VCCD I9 DGND I8 DGND I7 n.c. I6 n.c. I5 n.c. I4 n.c. DGND DGND DEC DEC I3 Q0 I2 Q1 I1 VCCA I0 AGND n.c. DEC n.c. AGND DGND VCCA DEC AGND n.c. AGND n.c. IOUT DGND IOUTN DGND AGND Q9 AGND Q8 QOUT Q7 QOUTN Q6 AGND DGND DEC AGND VCCA Q5 AGND Q4 DEC Q3 AGND Q2 VCCA 014aaa541 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 C C C C C 1.5 kΩ 1.5 kΩ C C C AGND AGND AGND AGND AGNDAGNDAGND 3.3 V 3.3 V 3.3 V 3.3 V CC CC CC C 50 Ω 50 Ω (RLOAD) 50 Ω AGND AGND C 50 Ω 50 Ω (RLOAD) 50 Ω AGND AGND AGND AGND 1:1 1:1 All resistors are 1 % precision resistors. C = 100 nF. Fig 10. Application diagram

11.1 Alternative parts

Table 8. Alternative parts

DAC1003D160_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 15 of 18 Integrated Device Technology DAC1003D160 Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 12. Package outline REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT841-1 MS-026 SOT841-1 04-01-15 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included UNIT A max mm 1.2 0.15 0.05 1.05 0.95 0.27 0.17 0.20 0.09 12.1 11.9 12.1 11.9 14.15 13.85 14.15 13.85 0.75 0.45 1.45 1.05 1.45 1.05 A DIMENSIONS (mm are the original dimensions) HTQFP80: plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad 80 21 61 40 12 0 60 41 bp bp D HD EH E B ADh Eh y ZD ZE e e w M w M pin 1 index vBM vAM c exposed die pad X θ A Lp detail X L (A3)A2 0 5 10 mm scale A2 A3 0.25 bp c D(1) E(1) e 0.5 HD 6.05 5.95 Dh 6.05 5.95 Eh HE L Lp v 0.2 w 0.08 y 0.1 ZD(1) ZE(1) θ Fig 11. Package outline SOT841-1 (HTQFP80)

14.1 Static parameters

tput value between successive DAC codes. line (linear regression computation).

14.2 Dynamic parameters

(harmonic and non-harmonic, excluding DC component) in the frequency domain. wave to the RMS value of the noise excluding the harmonics and the DC component. THD is done on the first 5 harmonics.

DAC1003D160_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 18 of 18 Integrated Device Technology DAC1003D160 Dual 10 bits DAC, up to 160 MHz, 2 x interpolation 17. Contents

Product Information

DAC1003D160 specifications and overview.

Summary

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

Description

Dual 10 bits DAC, up to 160 MHz, 2 x interpolation

Source title DAC1003D160 Datasheet(PDF) - Integrated Device Technology

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