DAC1001D125 | DigiCamel IC Datasheet

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General description The DAC1001D125 is a dual-port high-speed 2-channel CMOS Digital-to-Analog Converter (DAC), optimized for high dynamic performance with low power dissipation. The Supporting an update rate of up to 125 Msps, the DAC1001D125 is suitable for Direct IF applications. Separate write inputs allow data to be written to the two DAC ports independently of one another. Two separate clocks control the update rate of each DAC port. The DAC1001D125 can interface two separate data ports or one single interleaved high-speed data port. In Interleaved mode, the input data stream is demultiplexed into its original I and Q data and latched. The I and Q data is then converted by the two DACs and updated at half the input data rate. Each DAC port has a high-impedance differential current output, suitable for both single-ended and differential analog output configurations. The DAC1001D125 is pin compatible with the AD9763, DAC2900 and DAC5652. 2. Features and benefits 3. Applications DAC1001D125 Dual 10-bit DAC, up to 125 Msps Rev. 03 — 2 July 2012 Product data sheet  Dual 10-bit resolution  Typical 185 mW power dissipation  125 Msps update rate  16 mW power-down  Single 3.3 V supply  SFDR: 80 dBc; fo = 1 MHz; fs = 52 Msps  Dual-port or Interleaved data modes  SFDR: 77 dBc; fo = 10.4 MHz; fs = 78 Msps  1.8 V, 3.3 V and 5 V compatible digital inputs  SFDR: 72 dBc; fo = 1 MHz; fs = 52 Msps; 12 dBFS  Internal and external reference  LQFP48 package  2 mA to 20 mA full-scale output current  Industrial temperature range of 40 Ct o+ 8 5C  Quadrature modulation  Direct digital frequency synthesis  Medical/test instrumentation  Arbitrary waveform generator  Direct IF applications

6.1 Pinning

6.2 Pin description

Table 2. Pin description

DAC1001D125 3 © IDT 2012. All rights reserved. [1] All supplies are connected together. Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Table 4. Thermal characteristics Table 5. Characteristics

10 MHz span

DAC1001D125 3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 8 of 25 Integrated Device Technology DAC1001D125 Dual 10-bit DAC, up to 125 Msps (1) f o =5M H z . (2) f o =1 0M H z . (3) f o =1 5M H z . (4) f o =2 0M H z . Fig 3. SFDR as a function of the ambient temperature at 125 Msps T (°C) −60 10060200−20 001aai996 (1) (2) (3) (4) SFDR (dBc)

DAC1001D125 3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 9 of 25 Integrated Device Technology DAC1001D125 Dual 10-bit DAC, up to 125 Msps fs = 52 Msps; fc = 5.24 MHz;  =0d B F S fs = 100 Msps; fc = 20 MHz;  =0d B F S Fig 4. 1-tone SFDR f (MHz) 0 302010 001aai984 −60 −40 −80 −20 α (dBm) −100 f (MHz) 0 504020 3010 001aai986 −60 −40 −80 −20 α (dBm) −100

DAC1001D125 3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 10 of 25 Integrated Device Technology DAC1001D125 Dual 10-bit DAC, up to 125 Msps fs = 78 Msps; fc = 9.44 MHz, fc = 10.44 MHz;  =0d B F S Fig 5. 2-tone SFDR fs = 52 Msps; fc = 6.25 MHz, fc = 6.75 MHz; fc =7 . 2 5 M H z , fc = 7.75 MHz;  =0d B F S Fig 6. 4-tone SFDR f (MHz) 0 40302010 001aai988 −60 −40 −80 −20 α (dBm) −100 f (MHz) 0 302010 001aai989 −60 −40 −80 −20 α (dBm) −100

DAC1001D125 3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 11 of 25 Integrated Device Technology DAC1001D125 Dual 10-bit DAC, up to 125 Msps fs = 78 Msps; from fc = 9.5 MHz, 110 kHz spacing;  =0d B F S Fig 7. 8-tone SFDR Fig 8. INL as a function of the input code f (MHz) 0 40302010 001aai990 −60 −40 −80 −20 α (dBm) −100 001aaj000 −0.1 0.1 0.2 INL (dB) −0.2 input code 0 960768 1152576192 384

DAC1001D125 3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 12 of 25 Integrated Device Technology DAC1001D125 Dual 10-bit DAC, up to 125 Msps Fig 9. DNL as a function of the input code (1) f o =0d B F S . (2) f o = 6 dBFS. (3) f o = 12 dBFS. Fig 10. SFDR full-scale at 78 Msps as a function of the output frequency 001aai999 0.02 0.04 0.06 DNL (dB) −0.02 input code 0 960768 1152576192 384 fo (MHz) 0 2015105 001aaj046 SFDR (dBc) (1) (2) (3)

DAC1001D125 3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 13 of 25 Integrated Device Technology DAC1001D125 Dual 10-bit DAC, up to 125 Msps (1) f o =0d B F S . (2) f o = 6 dBFS. (3) f o = 12 dBFS. Fig 11. SFDR full-scale at 125 Msps as a function of the output frequency (1) f s = 125 Msps. (2) f s = 100 Msps. (3) f s = 78 Msps. (4) f s = 52 Msps. Fig 12. Digital supply current as a function of f o/fs fo (MHz) 0 2515 20105 001aaj04785 SFDR (dBc) (1) (2) (3) fo/fs 0 0.50.30.20.1 001aai938 IDDD (mA) 0.4 (1) (2) (3) (4)

10.1 General description

The DAC1001D125 is a dual 10-bit DAC operating up to 125 Msps. Each DAC consists of a segmented architecture, comprising a 7-bit thermometer sub-DAC and a 3-bit binary weighted sub-DAC. Two modes are available for the digital input depending on the status of the pin MODE. In Dual-port mode, each DAC uses its own data input line at the same frequency as the update rate. In Interleaved mode, both DACs use the same data input line at twice the update rate. Each DAC generates on pins IOUTAP/IOUTAN and IOUTBP/IOUTBN two complementary current outputs. This provides a full-scale output current (IO(fs)), up to 20 mA. A single common or two independent full-scale current controls can be selected for both channels using pin GAINCTRL. An internal reference is available for the reference current, which is externally adjustable using pin REFIO. The DAC1001D125 operates at 3.3 V and has separate digital and analog power supplies. Pin PWD is used to power-down the device. The digital input is 1.8 V compliant, 3.3 V compliant and 5 V tolerant.

10.2 Input data

The DAC1001D125 input follows a straight binary coding where DA9 and DB9 are the Most Significant Bits (MSB) and DA0 and DB0 are the Least Significant Bits (LSB). The setting applied to pin MODE defines whether the DAC1001D125 operates in Dual-port mode or in Interleaved mode (see Table 6). Fig 13. Analog supply current as a function of the output current 001aaj032 lO (mA) 0 2015105 I DDA (mA)

10.2.1 Dual-port mode

The data and clock circuit for Dual-port mode operation is shown in Figure 14. output is updated on the rising edge of the CLKA/CLKB signal. Table 6. Mode selection

0 Interleaved mode active off IQWRT IQCLK IQRESET IQSEL

1 Dual-port mode active active WRTA CLKA CLKB WRTB

10.2.2 Interleaved mode

The data and clock circuit for Interleaved mode operation is illustrated in Figure 16. In Interleaved mode, both DACs use the same data and clock inputs at twice the update rate. Data enters the latch on the rising edge of IQWRT. The data is sent to either latch A or latch B, depending on the value of IQSEL. The IQSEL transition must occur when IQWRT and IQCLK are LOW. The IQCLK is divided by 2 internally and the data is transferred to the DAC latch. It is updated on its rising edge. When IQRESET is HIGH, IQCLK is disabled, see Figure 17. Fig 16. Interleaved mode Fig 17. Interleaved mode timing 001aai952 ÷ 2 10 10DA9 to DA0 IQWRT IQSEL IQCLK IQRESET INPUT A LATCH DAC A LATCH 10 10INPUT B LATCH DAC B LATCH 001aaj065 DA9 to DA0/ DB9 to DB0 N N+1 XX XX N+1 N N+3 N+5 N+2 N+4 N+2 IQRESET IOUTAP , IOUTAN IOUTBP , IOUTBN N+3 N+4 N+5 N+6 N+7 IQSEL IQWRT IQCLK

10.3 Timing

The DAC1001D125 can operate at an update rate of 125 Msps, which generates an input data rate of 125 MHz in Dual-port mode and 250 MHz in Interleaved mode. The timing of the DAC1001D125 is shown in Figure 18. The typical performances are measured at 50 % duty cycle but any timing within the limits of the characteristics will not alter the performance.

A configuration resulting in the same timing for the signals WRTA/WRTB and CLKA/CLKB, can be achieved either by synchronizing them or by connecting them together.
The rising edge of the CLKA/CLKB signal can also be placed in a range from half a period in front of the rising edge of the WRTA/WRTB signal to half a period minus 1 ns after the rising edge of the WRTA/WRTB signal. A typical set-up time of 0 ns and a hold time of 0.6 ns enable the DAC1001D125 to be easily integrated into any application.

10.4 DAC transfer function

The full-scale output current for each DAC is the sum of the two complementary current outputs: (1) The output current depends on the digital input data: Fig 18. Timing of the DAC1001D125 001aaj066 tsu(i) tw(WRT) DA9 to DA0/ DB9 to DB0 WRTA/ WRTB CLKA/ CLKB IOUTAP , IOUTAN/ IOUTBP , IOUTBN td(clk) tw(CLK) 10 % 90 % td tt ts th(i) IOf s IIOUTP IIOUTN+= IIOUTP IOf s DATA

1023 DATA–

=

10.5 Full-scale current adjustment

full-scale current in both DACs. The internal reference configuration is shown in Figure 19. RB are set to 1.5 k. The operational range of DAC1001D125 is from 2 mA to 20 mA. It is recommended to decouple pin REFIO with a 100 nF capacitor. Table 7. DAC transfer function

1.25 V REFERENCE

10.6 Gain control

Table 8 shows how to select the different gain control modes. A on pin AVIRES and RB on pin BVIRES. and divided by two in both DACs.

10.7 Analog outputs

combination of PMOS current sources and associated switches for each segment. increased, thus improving the dynamic performance by reducing distortion.

a differential output, coupled to a transformer (or operational amplifier) to reduce even-order harmonics and noise
or a single-ended output for applications requiring unipolar voltage. The typical configuration is to use 1 V p-p level on each output IOUTAP/IOUTBP and IOUTAN/IOUTBN but several combinations can be used as far as they respect the voltage compliance range.

Table 8. Gain control

10.7.1 Differential output using transformer

10.7.2 Single-ended output

typically from 0 V to 0.5 V with a 20 mA full-scale current at a 50  load. The resistor on the other current output is 25 .

10.8 Power-down function

Table 9. Power-down

10.9 Alternative parts

The following alternative parts are also available.

10.10 Application diagram

Table 10. Alternative parts

5 DB0DA5 32

6 DB1DA4 31

7 DB2DA3 30

8 DB3DA2 29

9 DB4DA1 28

10 DB5DA0 27

15 IOUTAPDGND

16 IOUTANVDDD

17 AVIRESIQWRT

18 REFIOIQCLK

19 GAINCTRLIQRESET

20 BVIRESIQSEL

21 IOUTBNDGND

22 IOUTBPVDDD

23 AGND

24 PWDDB8

DAC1001D125 3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 22 of 25 Integrated Device Technology DAC1001D125 Dual 10-bit DAC, up to 125 Msps 11. Package outline Fig 24. Package outline SOT313-2 (LQFP48) UNIT A max. A1 A2 A3 bp cE (1) eH E LL p Zywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 o o0.12 0.10.21 DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 SOT313-2 MS-026 136E05 00-01-19 03-02-25 D(1) (1)(1) 7.1 6.9 HD 9.15 8.85 EZ 0.95 0.55 D bp e E B DH bp EH v M B D ZD A ZE e v M A 36 25 θ A Lp detail X L (A )3 X y c w M w M 0 2.5 5 mm scale pin 1 index LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2

Table 4 “Thermal characteristics” has been updated.
Section 10.6 “Gain control” has been updated. DAC1001D125 v.1 20081124 Product data sheet - -

Product Information

DAC1001D125 specifications and overview.

Summary

Dual 10-bit DAC, up to 125 Msps

Description

Dual 10-bit DAC, up to 125 Msps

Source title DAC1001D125 Datasheet(PDF) - Integrated Device Technology

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