DAC10

DAC10 AD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 10

Technical content

REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a DAC10* Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 10-Bit High Speed Multiplying D/A Converter (Universal Digital Logic Interface)

FEATURES

Fast Settling: 85 ns Low Full-Scale Drift: 10 ppm/ 8C Nonlinearity to 0.05% Max Over Temperature Range Complementary Current Outputs: 0 mA to 4 mA␣ Wide Range Multiplying Capability: 1 MHz Bandwidth Wide Power Supply Range: +5, –7.5 Min to 618 V Max Direct Interface to TTL, CMOS, ECL, PMOS, NMOS Availability in Die Form␣ GENERAL DESCRIPTION The DAC10 series of 10-bit monolithic multiplying digital-to- analog converters provide high speed performance and full-scale accuracy. Advanced circuit design achieves 85 ns settling times with very low “glitch” energy and low power consumption. Direct inter- face to all popular logic families with full noise immunity is provided by the high swing, adjustable threshold logic inputs. SIMPLIFIED SCHEMATIC

4 IOUT

B 1 B 2 B 3 B 4 B 5 B 6 B 7 B 8 B 9 B 10 LSB 15 1 5 6 7 8 9 10 11 12 13 14 BIAS NETWORK CURRENT SWITCHES REFERENCE AMPLIFIER VREF (+) VREF (–) COMP V– 18 3 All DAC10 series models guarantee full 10-bit monotonicity, and nonlinearities as tight as +0.05% over the entire operating temperature range are available. Device performance is essen- tially unchanged over the ± 18 V power supply range, with 85 mW power consumption attainable at lower supplies. A highly stable, unique trim method is used, which selectively shorts Zener diodes, to provide 1/2 LSB full-scale accuracy without the need for laser trimming. Single-chip reliability, coupled with low cost and outstanding flexibility, make the DAC10 device an ideal building block for A/D converters, Data Acquisition systems, CRT displays, pro- grammable test equipment and other applications where low power consumption, input/output versatility and long-term stability are required. *Protected by Patent Nos. 4,055,770, 4,056,740 and 4,092,639.

REV. D DAC10–SPECIFICATIONS –2–

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Min Typ Max Units MONOTONICITY 10 10 Bits NONLINEARITY NL 0.3 0.5 0.6 1 LSB DIFFERENTIAL NONLINEARITY DNL 0.3 1 0.7 LSB SETTLING TIME t S All Bits Switched ON or OFF Settle to 0.05% of FS (See Note) 85 135 85 150 ns OUTPUT CAPACITANCE C O 18 18 pF PROPAGATION DELAY t PLH All Bits Switched R L = 5 kΩ 50 50 ns tPHL RL = 0 k Ω 50 50 ns OUTPUT VOLTAGE Full-Scale Current Change –5.5 –5.5 V COMPLIANCE V OC <1 LSB +10 +10 V GAIN TEMPCO TCI FS (See Note) ± 10 ± 25 ± 10 ± 50 ppm/ °C FULL-SCALE SYMMETRY I FSS IFR–IFR 0.1 4 0.1 4 µA ZERO-SCALE CURRENT I ZS 0.01 0.5 0.01 0.5 µA REFERENCE INPUT SLEW RATE DI/dt 6 6 mA/ µs REFERENCE BIAS CURRENT I B –1 –3 –1 –3 µA SENSITIVITY PPS/ FS– –18 V ≤ V– ≤ –10 V 0.0012 0.01 0.0012 0.01 % ΔIFS/%ΔV POWER SUPPLY CURRENT I+ V S = ± 15 V; IREF = 2 mA 2.3 4 2.3 4 mA I+ V S = +5 V; –7.5 V; I REF = 1 mA 1.8 4 1.8 4 mA POWER DISSIPATION P D VS = ± 15 V; IREF = 2 mA 231 285 231 285 mW PD VS = +5 V; –7.5 V; I REF = 1 mA 85 88 85 88 mW LOGIC INPUT LEVELS V IL VLC = 0 0.8 0.8 V VIH VLC = 0 2 2 V LOGIC INPUT CURRENTS I IL VLC = 0; VIN = 0.8 V –10 –5 –10 –5 µA IIH VIN = 2.0 V 0.001 10 0.001 10 µA Parameter Symbol Conditions Min Typ Max Min Typ Max Units MONOTONICITY 10 10 Bits NONLINEARITY NL 0.3 0.5 0.6 1 LSB DIFFERENTIAL NONLINEARITY DNL 0.3 1 0.7 LSB OUTPUT VOLTAGE COMPLIANCE V OC Full-Scale Current Change, <1 LSB –5 –6/+18 +10 –5 –6/+15 +10 V FULL-SCALE CURRENT I FS VREF = 10.000 V, FULL-SCALE SYMMETRY I FSS IFR–IFR 0.1 4 0.1 0.4 µA ZERO-SCALE CURRENT I ZS 0.01 0.5 0.01 0.5 µA NOTE: Guaranteed by design. (@ VS = 615 V; IREF = 2 mA; 08C ≤ TA ≤ +708C for DAC10F and G, unless otherwise noted. Output characteristics apply to both I OUT and IOUT.) (@ VS = 615 V; IREF = 2 mA; TA = +258C, unless otherwise noted. Output characteristics apply to both IOUT and IOUT.)

–3–REV. D DAC10 WAFER TEST LIMITS DAC10N Parameter Symbol Conditions Limit Units RESOLUTION 10 Bits min MONOTONICITY 10 Bits min NONLINEARITY NL ± 0.5 LSB max OUTPUT VOLTAGE COMPLIANCE V OC True 1 LSB +10 V max –5 V min OUTPUT CURRENT RANGE I FS ± 3.996 mA ± 18 µA max ZERO-SCALE CURRENT I ZS All Bits OFF 0.5 µA max LOGIC INPUT “1” V IH IIN = 100 nA 2 V min LOGIC INPUT “0” V IL VLC @ Ground 0.8 V max IIN = –100 µA POSITIVE SUPPLY CURRENT I+ V+ = 15 V 4 mA max NEGATIVE SUPPLY CURRENT I– V+ = –15 V –15 mA max NOTE: Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard produce dice. TYPICAL ELECTRICAL CHARACTERISTICS DAC10F Parameter Symbol Conditions Typ Units SETTLING TIME t S To ± 1/2 LSB When Output Is Switched from 0 to FS 85 ns GAIN TEMPERATURE COEFFICIENT (TC) V REF Tempco Excluded ± 10 ppm FS/ °C OUTPUT CAPACITANCE 18 pF OUTPUT RESISTANCE 10 M Ω (@ VS = 615 V, IREF = 2 mA, TA = +258C, unless otherwise noted. Output characteristics refer to both IOUT and IOUT). (@ VS = 615 V, IREF = 2 mA, unless otherwise noted. Output characteristics refer to both IOUT and IOUT). DICE CHARACTERISTICS DIE SIZE 0.091 3 0.087 inch, 7,917 sq. mils (2.311 3 2.210 mm, 5.107 sq. mm)

–4– REV. D ABSOLUTE MAXIMUM RATINGS 1 Operating Temperature V Reference Input Differential Voltage (V 16 to V17) . . . . ± 18 V Package Type uJA 2 uJC Units 18-Lead Hermetic DIP (X) 48 15 °C/W 18-Lead SOIC (S) 89 28 °C/W 18-Lead Plastic DIP (P) 74 33 °C/W NOTES 1Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2θJA is specified for worst case mounting conditions, i.e., θJA is specified for device in socket for Cerdip packages. ORDERING GUIDE INL Temperature Package Package Model (LSB) Range Description Options DAC10FX 0.5 0 °C to +70°C Cerdip Q-18 DAC10GX 1 0 °C to +70°C Cerdip Q-18 DAC10GS 1 0 °C to +70°C SOIC R-18 DAC10GP 1 0 °C to +70°C Plastic DIP N-18 PIN CONNECTIONS 18-Lead Hermetic DIP 18-Lead Plastic DIP 18-Lead SOIC TOP VIEW (Not to Scale) DAC10 VLC IO IO (MSB) B1 COMP VREF (–) VREF (+) B10 (LSB)

Figure 15. Positive Low Impedance Output Operation Figure 16. Negative Low Impedance Output Operation Figure 17. Interfacing with Various Logic Families Figure 14. Settling Time Measurement

0 TO +IFR 3 RL

O (PIN 2); CONNECT IO (PIN 4) TO GROUND.

0 TO –IFR 3 RL

O PIN 2); CONNECT IO (PIN 4) TO GROUND.

1. CASE OF 2N918s MUST BE GROUNDED.
2. RESISTORS ARE 1/4W MF, 1% UNLESS OTHERWISE SPECIFIED.
3. USE FET PROBE (7A11 SCOPE PLUGIN).

–8– REV. D

APPLICATIONS

+VREF R EQ = 800V NO CAP TYPICAL VALUES: R IN = 1kV +VIN = 2V R IN R P R REF +R EQ = + Figure 18. Pulsed Reference Operation where IREF equals current flowing into Pin 16. R17 may be eliminated with only a minor increase in error. amplifier is given by: V CM– = V– plus (IREF × 2 kΩ ) plus 2 V. The positive common-mode range is V+ less 1.8 V. to ground with a 0.1 µF capacitor. shown in the Recommended Full-Scale Adjustment circuit. typical range of IREF from 100 µA to 2 mA. proportionately increased values of C C for proper phase margin. enabling a transition from I REF = 0 to IREF = 2 mA in 500 ns. µs, which is relatively independent of R IN and VIN values. signed to accommodate this current. should be bypassed to ground by a 0.01 µF capacitor.

REV. D –9– ANALOG OUTPUT CURRENTS Both true and complemented output sink currents are provided where IO + IO = IFS . Current appears at the “true” output when a “1” is applied to each logic input. As the binary count increases, the sink current at Pin 4 increases proportionally, in the fashion of a “positive logic” D/A converter. When a “0” is applied to any input bit, that current is turned off at Pin 4 and turned on at Pin 2. A decreasing logic count increases IO as in a negative or inverted logic D/A converter. Both outputs may be used simultaneously. If one of the outputs is not required, it must still be connected to ground or to a point capable of sourc- ing I FS. DO NOT LEAVE AN UNUSED OUTPUT PIN OPEN. Both outputs have an extremely wide voltage compliance en- abling fast direct current-to-voltage conversion through a resis- tor tied to ground or other voltage source. Positive compliance is 36 V above V– and is independent of the positive supply. Negative compliance is +10 V above V–. The dual outputs enable double the usual peak-to-peak load swing when driving loads in quasi-differential fashion. This feature is especially useful in cable driving, CRT deflection and in other balanced applications such as driving center-tapped coils and transformers. POWER SUPPLIES The DAC10 operates over a wide range of power supply volt- ages from a total supply of 9 V to 36 V. When operating with V– supplies of –10 V or less, I REF ≤ 1 mA is recommended. Low reference current operation decreases power consumption and increases negative compliance, reference amplifier negative common-mode range, negative logic input range and negative logic threshold range; consult the various figures for guidance. For example, operation at –9 V with I REF = 2 mA is not recom- mended because negative output compliance would be reduced to near zero. Operation from lower supplies is possible, however at least 8 V total must be applied to ensure turn-on of the inter- nal bias network. Symmetrical supplies are not required, as the DAC10 is quite insensitive to variations in supply voltage. Battery operation is feasible as no ground connection is required; however, an artifi- cial ground may be used to ensure that logic swings, etc., remain within acceptable limits. TEMPERATURE PERFORMANCE The nonlinearity and monotonicity specifications of the DAC10 are guaranteed to apply over the entire rated operating tempera- ture range. Full-scale output current drift is tight, typically +10 ppm/°C, with zero-scale output current and drift essentially negligible compared to 1/2 LSB. The temperature coefficient of the reference resistor, R14, should match and track that of the output resistor for minimum overall full-scale drift. Settling times of the DAC10 decrease approximately 10% at –55°C; an increase of about 15% is typi- cal at +125°C. SETTLING TIME The DAC10 is capable of extremely fast settling times; typically 85 ns at IREF = 2 mA. Judicious circuit design and careful board layout must be employed to obtain full performance potential during testing and application. The logic switch design enables propagation delays of only 35 ns for each of the 10 bits. Settling time to within 1/2 LSB of the LSB is therefore 35 ns, with each progressively larger bit taking successively longer. The MSB settles in 85 ns, thus determining the overall settling time of 130 ns. Settling to 8-bit accuracy requires about 60 ns to 78 ns. The output capacitance of the DAC10, including the package, is approximately 18 pF; therefore, the output RC time constant dominates settling time if R L > 500 Ω . Settling time and propagation delay are relatively insensitive to logic input amplitude and rise and fall times, due to the high gain of the logic switches. Settling time also remains essentially constant for I REF values down to 1 mA, with gradual increases for lower IREF values. The principal advantage of higher I REF values lies in the ability to attain a given output level with lower load resistors, thus reducing the output RC time constant. Measurement of settling time requires the ability to accurately resolve ± 2 µA; therefore, a 4 kΩ load is needed to provide ad- equate drive for most oscilloscopes. The settling time fixture of schematic titled “Settling Time Measurement” uses a cascode design to permit driving a 4 k Ω load with less than 5 pF of para- sitic capacitance at the measurement node. At I REF values of less than 1 mA, excessive RC damping of the output is difficult to prevent while maintaining adequate sensitivity. However, the major carry from 0111111111 to 1000000000 provides an accu- rate indicator of settling time. This code change does not re- quire the normal 6.2 time constants to settle to within ± 0.2% of the final value, and thus settling times may be observed at lower values of I REF. DAC10 switching transients or “glitches” are very low and may be further reduced by small capacitive loads at the output with a minor sacrifice in settling time. Fastest operation can be obtained by using short leads, minimiz- ing output capacitance and load resistor values, and by adequate bypassing at the supply, reference and V LC terminals. Supplies do not require large electrolytic bypass capacitors as the supply current drain is independent of input logic states; 0.1 µF capaci- tors at the supply pins provide full transient protection.

–10– REV. D OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 18-Lead Cerdip (Q-18) 1 9 0.310 (7.87) 0.220 (5.59) PIN 1 0.005 (0.13) MIN 0.098 (2.49) MAX SEATING PLANE 0.023 (0.58) 0.014 (0.36) 0.200 (5.08) MAX 0.960 (24.38) MAX 0.150 (3.81) MIN 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 15° 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) 18-Lead Plastic DIP (N-18) 0.925 (23.49) 0.845 (21.47) 0.280 (7.11) 0.240 (6.10) PIN 1 SEATING PLANE0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) BSC 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 18-Lead Wide Body SOL (R-18) 0.4193 (10.65) 0.3937 (10.00) 18 10 0.4625 (11.75) 0.4469 (11.35) PIN 1 0.2992 (7.60) 0.2914 (7.40) SEATING PLANE 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 0.0291 (0.74) 0.0098 (0.25)x 45° C3134–0–5/98PRINTED IN U.S.A.