DAC081S101 TI | Alldatasheet

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www.ti.com SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 DAC081S1018-BitMicroPowerDigital-to-AnalogConverterwithRail-to-RailOutput Check forSamples: DAC081S101 1FEATURES DESCRIPTION The DAC081S101 isa full-featured,generalpurpose 23• Guaranteed Monotonicity 8-bitvoltage-outputdigital-to-analogconverter(DAC)• Low Power Operation thatcan operatefrom a single+2.7V to5.5V supply

  • Rail-to-RailVoltageOutput and consumes just175 µA of currentat 3.6 Volts. The on-chipoutputamplifierallowsrail-to-railoutput• Power-on Reset toZero VoltsOutput swing and thethreewireserialinterfaceoperatesat• SYNC InterruptFacility clockratesup to 30 MHz over the specifiedsupply
  • Wide Power Supply Range (+2.7Vto+5.5V) voltagerangeand iscompatiblewithstandardSPI™ , QSPI, MICROWIRE and DSP interfaces.Competitive• Small Packages devicesare limitedto 20 MHz clockratesat supply• Power Down Feature voltagesinthe2.7Vto3.6Vrange. The supplyvoltagefortheDAC081S101 servesas itsAPPLICATIONS voltage reference,providingthe widest possible• Battery-PoweredInstruments output dynamic range. A power-on reset circuit
  • DigitalGain and OffsetAdjustment ensuresthattheDAC outputpowers up tozerovolts and remainsthereuntilthereisa validwriteto the• Programmable Voltage& CurrentSources device. A power-down feature reduces power• Programmable Attenuators consumptiontolessthana microWatt. The low power consumptionand smallpackages of theDAC081S101 make itan excellentchoiceforuse inbatteryoperatedequipment. The DAC081S101 is a directreplacementforthe AD5300 and is one of a familyof pin compatible DACs, includingthe10-bitDAC101S101 and the12- bitDAC121S101. The DAC081S101 operatesover the extended industrialtemperaturerange of −40°C to+105°C. Table1.Key Specifications VALUE Resolution 8 bits DNL +0.04,-0.02LSB (typ) OutputSettlingTime 3 µs (typ) ZeroCode Error 3.8mV (typ) Full-ScaleError −0.07%FS (typ) Normal Mode 0.63mW (3.6V)/1.41mW (5.5V)typ Power Consumption Pwr Down Mode 0.14µW (3.6V)/0.33µW (5.5V)typ Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2SPI isa trademarkofMotorola,Inc.. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2005–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

REF(+) REF(-) VA GND DAC081S101 VOUT DIN SCLK VA GND VOUT 1 SYNC GND DIN SCLK VA NC NC VOUT SYNC DAC081S101 SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com Pin Configuration SOT VSSOP Block Diagram Pin Descriptions SOT-23 VSSOPName DescriptionPin No. Pin No. VOUT 1 4 DAC AnalogOutputVoltage. GND 2 8 Ground referenceforallon-chipcircuitry. VA 3 1 Power supplyand Referenceinput.Shouldbe decoupledtoGND. SerialData Input.Data isclockedintothe16-bitshiftregisteron thefallingD IN 4 7 edges ofSCLK afterthefallofSYNC. SerialClockInput.Data isclockedintotheinputshiftregisteron thefallingSCLK 5 6 edges ofthispin. Frame synchronizationinputforthedatainput.When thispingoes low,it enablestheinputshiftregisterand dataistransferredon thefallingedges SYNC 6 5 ofSCLK. The DAC isupdatedon the16thclockcycleunlessSYNC is broughthighbeforethe16thclock,inwhichcase therisingedge ofSYNC actsas an interruptand thewritesequence isignoredby theDAC. NC 2,3 No Connect.Thereisno internalconnectiontothesepins. These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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www.ti.com SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 AbsoluteMaximum Ratings (1)(2) SupplyVoltage,VA 6.5V Voltageon any InputPin −0.3Vto(VA + 0.3V) InputCurrentatAny Pin(3) 10 mA Package InputCurrent(3) 20 mA Power ConsumptionatTA = 25°C See (4) ESD Susceptibility(5) Human Body Model 2500V Machine Model 250V SolderingTemperature,Infrared,

10 Seconds (6) 235°C

StorageTemperature −65°C to+150°C (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notguaranteespecificperformancelimits.Forguaranteedspecificationsand testconditions,see theElectricalCharacteristics.The guaranteedspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristics may degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (2) Allvoltagesaremeasured withrespecttoGND = 0V,unlessotherwisespecified (3) When theinputvoltageatany pinexceedsthepower supplies(thatis,lessthanGND, orgreaterthanVA),thecurrentatthatpinshould be limitedto10 mA. The 20 mA maximum package inputcurrentratinglimitsthenumber ofpinsthatcan safelyexceed thepower supplieswithan inputcurrentof10 mA totwo. (4) The absolutemaximum junctiontemperature(TJmax) forthisdeviceis150°C. The maximum allowablepower dissipationisdictatedby TJmax, thejunction-to-ambientthermalresistance(θJA),and theambienttemperature(TA),and can be calculatedusingtheformula PD MAX = (TJmax − TA)/θJA.The valuesformaximum power dissipationwillbe reachedonlywhen thedeviceisoperatedina severe faultcondition(e.g.,when inputoroutputpinsaredrivenbeyond thepower supplyvoltages,orthepower supplypolarityisreversed). Obviously,such conditionsshouldalwaysbe avoided. (5) Human body model is100 pF capacitordischargedthrougha 1.5kΩ resistor.Machine model is220 pF dischargedthroughZERO Ohms. (6) See thesectionentitled"SurfaceMount"foundinany post1986 NationalSemiconductorLinearData Book formethods ofsoldering surfacemount devices. OperatingRatings (1)(2) OperatingTemperatureRange −40°C ≤ TA ≤ +105°C SupplyVoltage,VA (3) +2.7V to5.5V Any InputVoltage(4) −0.1V to(VA + 0.1V) OutputLoad 0 to1500 pF SCLK Frequency Up to30 MHz (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notguaranteespecificperformancelimits.Forguaranteedspecificationsand testconditions,see theElectricalCharacteristics.The guaranteedspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristics may degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (2) Allvoltagesaremeasured withrespecttoGND = 0V,unlessotherwisespecified (3) To guaranteeaccuracy,itisrequiredthatVA be wellbypassed. (4) The analoginputsareprotectedas shown below.Inputvoltagemagnitudesup toVA + 300 mV orto300 mV belowGND willnot damage thisdevice.However,errorsintheconversionresultcan occurifany inputgoes above VA orbelowGND by more than100 mV. Forexample,ifVA is2.7VDC ,ensurethat−100mV ≤ inputvoltages≤2.8VDC toensureaccurateconversions. Package Thermal Resistances Package θJA 8-LeadVSSOP 240°C/W 6-LeadSOT 250°C/W Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DAC081S101

SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com ElectricalCharacteristics Values shown inthistablearedesign targetsand aresubjecttochange beforeproductrelease. The followingspecificationsapplyforVA = +2.7V to+5.5V,R L = 2kΩ toGND, C L = 200 pF toGND, fSCLK = 30 MHz, input code range4 to251.BoldfacelimitsapplyforTMIN ≤ TA ≤ TMAX :allotherlimitsTA = 25°C, unlessotherwisespecified. UnitsParameter TestConditions Typical(1) Limits(1) (Limits) STATIC PERFORMANCE Resolution 8 Bits(min) Monotonicity 8 Bits(min) INL IntegralNon-Linearity +0.16 +0.75 LSB (max) −0.12 −0.75 LSB (min) +0.04 +0.1 LSB (max) DNL DifferentialNon-Linearity −0.02 −0.1 LSB (min) ZE ZeroCode Error IOUT = 0 +3.8 +15 mV (max) FSE Full-ScaleError IOUT = 0 −0.07 −1.0 %FSR (max) GE Gain Error Allones Loaded toDAC register −0.10 ±1.0 %FSR (max) ZCED ZeroCode ErrorDrift −20 µV/°C VA = 3V −0.7 ppm/°C TC GE Gain ErrorTempco VA = 5V −1.0 ppm/°C OUTPUT CHARACTERISTICS

0 V (min)OutputVoltageRange (2)

VA V (max) VA = 3V,IOUT = 10 µA 2.0 mV VA = 3V,IOUT = 100 µA 5.0 mV ZCO ZeroCode Output VA = 5V,IOUT = 10 µA 3.0 mV VA = 5V,IOUT = 100 µA 5.4 mV VA = 3V,IOUT = 10 µA 2.986 V VA = 3V,IOUT = 100 µA 2.976 V FSO FullScaleOutput VA = 5V,IOUT = 10 µA 4.976 V VA = 5V,IOUT = 100 µA 4.970 V R L = ∞ 1500 pF Maximum Load Capacitance R L = 2kΩ 1500 pF DC OutputImpedance 1.3 Ohm VA = 5V,VOUT = 0V, −63 mAInputcode = FFh VA = 3V,VOUT = 0V, −50 mAInputcode = FFh IOS OutputShortCircuitCurrent VA = 5V,VOUT = 5V, 74 mAInputcode = 00h VA = 3V,VOUT = 3V, 53 mAInputcode = 00h (1) TypicalfiguresareatTJ = 25°C, and representmost likelyparametricnorms.TestlimitsareguaranteedtoTI's AOQL (Average OutgoingQualityLevel). (2) Thisparameterisguaranteedby designand/orcharacterizationand isnottestedinproduction.

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www.ti.com SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 ElectricalCharacteristics(continued) Values shown inthistablearedesign targetsand aresubjecttochange beforeproductrelease. The followingspecificationsapplyforVA = +2.7V to+5.5V,R L = 2kΩ toGND, C L = 200 pF toGND, fSCLK = 30 MHz, input code range4 to251.BoldfacelimitsapplyforTMIN ≤ TA ≤ TMAX :allotherlimitsTA = 25°C, unlessotherwisespecified. UnitsParameter TestConditions Typical(1) Limits(1) (Limits) LOGIC INPUT IIN InputCurrent(3) ±1 µA (max) VA = 5V 0.8 V (max) VIL InputLow Voltage(3) VA = 3V 0.5 V (max) VA = 5V 2.4 V (min) VIH InputHighVoltage(3) VA = 3V 2.1 V (min) C IN InputCapacitance(3) 3 pF (max) POWER REQUIREMENTS VA = 5.5V 256 328 µA (max)Normal Mode fSCLK = 30 MHz VA = 3.6V 174 224 µA (max) VA = 5.5V 221 294 µA (max)Normal Mode fSCLK = 20 MHz VA = 3.6V 154 200 µA (max) VA = 5.0V 142 µA (max)Normal Mode fSCLK = 0 VA = 3.0V 107 µA (max) IA SupplyCurrent(outputunloaded) VA = 5.0V 83 µA (max)AllPD Modes, fSCLK = 30 MHz VA = 3.0V 42 µA (max) VA = 5.0V 56 µA (max)AllPD Modes, fSCLK = 20 MHz VA = 3.0V 28 µA (max) VA = 5.5V 0.06 1.0 µA (max)AllPD Modes, fSCLK = 0 (3) VA = 3.6V 0.04 1.0 µA (max) VA = 5.5V 1.41 1.80 mW (max)Normal Mode fSCLK = 30 MHz VA = 3.6V 0.63 0.81 mW (max) VA = 5.5V 1.22 1.62 mW (max)Normal Mode fSCLK = 20 MHz VA = 3.6V 0.55 0.72 mW (max) VA = 5.0V 0.71 µW (max)Normal Mode fSCLK = 0 VA = 3.0V 0.32 µW (max)Power Consumption(outputPC unloaded) VA = 5.0V 0.42 µW (max)AllPD Modes, fSCLK = 30 MHz VA = 3.0V 0.13 µW (max) VA = 5.0V 0.28 µW (max)AllPD Modes, fSCLK = 20 MHz VA = 3.0V 0.08 µW (max) VA = 5.5V 0.33 5.5 µW (max)AllPD Modes, fSCLK = 0 (3) VA = 3.6V 0.14 3.6 µW (max) VA = 5V 91 % IOUT /IA Power Efficiency ILOAD = 2mA VA = 3V 94 % (3) Thisparameterisguaranteedby designand/orcharacterizationand isnottestedinproduction. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DAC081S101

SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com AC and Timing Characteristics Values shown inthistablearedesign targetsand aresubjecttochange beforeproductrelease. The followingspecificationsapplyforVA = +2.7V to+5.5V,R L = 2kΩ toGND, C L = 200 pF toGND, fSCLK = 30 MHz, input code range4 to251.BoldfacelimitsapplyforTMIN ≤ TA ≤ TMAX :allotherlimitsTA = 25°C, unlessotherwisespecified. UnitsParameter TestConditions Typical Limits (Limits) fSCLK SCLK Frequency 30 MHz (max) OutputVoltageSettlingTime 40h toC0h codets C L ≤ 200 pF 3 5 µs (max)(1) change,R L = 2kΩ SR OutputSlew Rate 1 V/µs GlitchImpulse Code change from80h to7Fh 12 nV-sec DigitalFeedthrough 0.5 nV-sec VA = 5V 6 µs tWU Wake-Up Time VA = 3V 39 µs 1/fSCLK SCLK CycleTime 33 ns (min) tH SCLK Hightime 5 13 ns (min) tL SCLK Low Time 5 13 ns (min) Set-upTime SYNC toSCLK RisingtSUCL −15 0 ns (min)Edge tSUD Data Set-UpTime 2.5 5 ns (min) tDHD Data HoldTime 2.5 4.5 ns (min) VA = 5V 0 3 ns (min) tCS SCLK falltoriseofSYNC VA = 3V −2 1 ns (min) 2.7≤ VA ≤ 3.6 9 20 ns (min) tSYNC SYNC HighTime 3.6≤ VA ≤ 5.5 5 10 ns (min) (1) Thisparameterisguaranteedby designand/orcharacterizationand isnottestedinproduction. SpecificationDefinitions DIFFERENTIAL NON-LINEARITY (DNL) isthemeasure ofthemaximum deviationfromtheidealstepsizeof1 LSB, whichisVREF /256 = VA /256. DIGITAL FEEDTHROUGH isa measure oftheenergyinjectedintotheanalogoutputoftheDAC fromthedigital inputswhen theDAC outputsarenotupdated.Itismeasured witha full-scalecode change on thedatabus. FULL-SCALE ERROR isthedifferencebetween theactualoutputvoltagewitha fullscalecode (FFh)loaded intotheDAC and thevalueofVA x 255 /256. GAIN ERROR isthedeviationfrom theidealslopeofthetransferfunction.Itcan be calculatedfrom Zero and Full-ScaleErrorsas GE = FSE -ZE, where GE isGain error,FSE isFull-ScaleErrorand ZE isZeroError. GLITCH IMPULSE is the energy injectedintothe analog outputwhen the inputcode to the DAC register changes.Itisspecifiedas theareaoftheglitchinnanovolt-seconds. INTEGRAL NON-LINEARITY (INL)isa measure of the deviationof each individualcode from a straightline throughtheinputtooutputtransferfunction.The deviationofany givencode fromthisstraightlineismeasured fromthecenterofthatcode value.The end pointmethod isused.INL forthisproductisspecifiedovera limited range,pertheElectricalTables. LEAST SIGNIFICANT BIT (LSB) isthebitthathas thesmallestvalueorweightofallbitsina word.Thisvalueis LSB = VREF /2n (1) where VREF isthe supplyvoltageforthisproduct,and "n"isthe DAC resolutionin bits,which is8 forthe DAC081S101. MAXIMUM LOAD CAPACITANCE isthe maximum capacitancethatcan be drivenby the DAC withoutput stabilitymaintained.

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||| |||| 1 2 13 14 15 16 fCLK OUTPUT VOLTAGE DIGITAL INPUT CODE 0 255 ZE FSE GE = FSE - ZE FSE = GE + ZE 255 x VA 256 DAC081S101 www.ti.com SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 MONOTONICITY istheconditionofbeingmonotonic,where theDAC has an outputthatneverdecreaseswhen theoutputcode increases. MOST SIGNIFICANT BIT (MSB) isthebitthathas thelargestvalueor weightofallbitsina word.Itsvalueis 1/2ofVA. POWER EFFICIENCY istheratiooftheoutputcurrenttothetotalsupplycurrent.The outputcurrentcomes from thepower supply.The differencebetween thesupplyand outputcurrents,isthepower consumed by thedevice withouta load. SETTLING TIME isthe timeforthe outputto settlewithin1/2 LSB of the finalvalueafterthe inputcode is updated. WAKE-UP TIME isthe time forthe outputto settleto within1/2 LSB of the finalvalueafterthe deviceis commanded totheactivemode fromany ofthepower down modes. ZERO CODE ERROR istheoutputerror,or voltage,presentattheDAC outputaftera code of00h has been entered. TransferCharacteristic Figure1. Input/Output TransferCharacteristic Timing Diagram Figure2. DAC081S101 Timing Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DAC081S101

SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com TypicalPerformance Characteristics fSCLK = 30 MHz, TA = 25C, InputCode Range 4 to251,unlessotherwisestated DNL atVA = 3.0V DNL atVA = 5.0V Figure3. Figure4. INL atVA = 3.0V INL atVA = 5.0V Figure5. Figure6. TUE atVA = 3.0V TUE atVA = 5.0V Figure7. Figure8.

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www.ti.com SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 TypicalPerformance Characteristics(continued) fSCLK = 30 MHz, TA = 25C, InputCode Range 4 to251,unlessotherwisestated DNL INL vs. vs. VA VA Figure9. Figure10. 3V DNL 5V DNL vs. vs. fSCLK fSCLK Figure11. Figure12. 3V DNL 5V DNL vs. vs. Clock Duty Cycle Clock Duty Cycle Figure13. Figure14. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DAC081S101

SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com TypicalPerformance Characteristics(continued) fSCLK = 30 MHz, TA = 25C, InputCode Range 4 to251,unlessotherwisestated 3V DNL 5V DNL vs. vs. Temperature Temperature Figure15. Figure16. 3V INL 5V INL vs. vs. fSCLK fSCLK Figure17. Figure18. 3V INL 5V INL vs. vs. Clock Duty Cycle Clock Duty Cycle Figure19. Figure20.

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www.ti.com SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 TypicalPerformance Characteristics(continued) fSCLK = 30 MHz, TA = 25C, InputCode Range 4 to251,unlessotherwisestated 3V INL 5V INL vs. vs. Temperature Temperature Figure21. Figure22. Zero Code Error Zero Code Error vs. vs. fSCLK Clock Duty Cycle Figure23. Figure24. Zero Code Error Full-ScaleError vs. vs. Temperature fSCLK Figure25. Figure26. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DAC081S101

SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com TypicalPerformance Characteristics(continued) fSCLK = 30 MHz, TA = 25C, InputCode Range 4 to251,unlessotherwisestated Full-ScaleError Full-ScaleError vs. vs. Clock Duty Cycle Temperature Figure27. Figure28. Supply Current Supply Current vs. vs. VA Temperature Figure29. Figure30. 5V GlitchResponse Power-On Reset Figure31. Figure32.

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www.ti.com SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 TypicalPerformance Characteristics(continued) fSCLK = 30 MHz, TA = 25C, InputCode Range 4 to251,unlessotherwisestated 3V Wake-Up Time 5V Wake-Up Time Figure33. Figure34. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DAC081S101

R R R R To Output Amplifier R DAC081S101 SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com FUNCTIONAL DESCRIPTION DAC SECTION The DAC081S101 isfabricatedon a CMOS processwithan architecturethatconsistsofswitchesand a resistor stringthatarefollowedby an outputbuffer.The power supplyservesas thereferencevoltage.The inputcoding isstraightbinarywithan idealoutputvoltageof: VOUT = VA x (D /256) (2) where D isthedecimalequivalentofthebinarycode thatisloadedintotheDAC registerand can takeon any valuebetween 0 and 255. RESISTOR STRING The resistorstringisshown inFigure35.Thisstringconsistsof4096 equalvaluedresistorswitha switchateach junctionoftwo resistors,plusa switchtoground.The code loadedintotheDAC registerdetermineswhichswitch isclosed,connectingthepropernode totheamplifier.ThisconfigurationguaranteesthattheDAC ismonotonic. Figure35. DAC ResistorString OUTPUT AMPLIFIER The outputbufferamplifierisa rail-to-railtype,providingan outputvoltagerangeof0V toVA.Allamplifiers,even rail-to-railtypes,exhibita lossoflinearityas theoutputapproachesthesupplyrails(0V and VA,inthiscase).For thisreason,linearityisspecifiedoverlessthanthefulloutputrange oftheDAC. The outputcapabilitiesofthe amplifieraredescribedintheElectricalTables. SERIAL INTERFACE The three-wireinterfaceiscompatiblewithSPI,QSPI and MICROWIRE as wellas most DSPs. See theTiming Diagram forinformationon a writesequence. A writesequence beginsby bringingtheSYNC linelow.Once SYNC islow,thedataon theD IN lineisclocked intothe16-bitserialinputregisteron thefallingedges ofSCLK. On the16thfallingclockedge,thelastdatabitis clockedinand theprogrammed function(achange inthemode ofoperationand/ora change intheDAC register contents)isexecuted.At thispointtheSYNC linemay be keptlow or broughthigh.Ineithercase,itmust be broughthighfortheminimum specifiedtimebeforethenextwritesequence as a fallingedge ofSYNC isused to initiatethenextwritecycle.

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/c87 /c87 MSB X X PD1 PD0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X Power-Down Modes LSB DAC081S101 www.ti.com SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 SincetheSYNC and D IN buffersdraw more currentwhen theyarehigh,theyshouldbe idledlow between write sequencestominimizepower consumption. INPUT SHIFT REGISTER The inputshiftregister,Figure36,has sixteenbits.The firsttwo bitsare "don'tcares"and are followedby two bitsthatdeterminethemode ofoperation(normalmode orone ofthreepower-down modes).The contentsofthe serialinputregisterare transferredto the DAC registeron the sixteenthfallingedge of SCLK. See Timing Diagram,Figure2. Figure36. InputRegisterContents Normally,theSYNC lineiskeptlow foratleast16 fallingedges ofSCLK and theDAC isupdatedon the16th SCLK fallingedge.However,ifSYNC isbroughthighbeforethe16thfallingedge,theshiftregisterisresetand thewritesequence isinvalid.The DAC registerisnotupdatedand thereisno change inthemode ofoperation orintheoutputvoltage. POWER-ON RESET The power-on resetcircuitcontrolsthe outputvoltageduringpower-up.Upon applicationof power the DAC registerisfilledwithzerosand theoutputvoltageis0 Voltsand remainsthereuntila validwritesequence is made totheDAC. POWER-DOWN MODES The DAC081S101 has fourmodes of operation.These modes are setwithtwo bits(DB13 and DB12) inthe controlregister. Table2.Modes ofOperation DB13 DB12 OperatingMode 0 0 Normal Operation 0 1 Power-Down with1kΩ toGND 1 0 Power-Down with100kΩ toGND 1 1 Power-Down withHi-Z When bothDB13 and DB12 are 0,thedeviceoperatesnormally.For theotherthreepossiblecombinationsof thesebitsthesupplycurrentdropstoitspower-down leveland theoutputispulleddown witheithera 1kΩ ora 100KΩ resistor,orisina highimpedance state,as describedinTable2. The biasgenerator,outputamplifier,theresistorstringand otherlinearcircuitryare allshutdown inany ofthe power-down modes. However, thecontentsoftheDAC registerare unaffectedwhen inpower-down,so when coming outofpower down theoutputvoltagereturnstothesame voltageitwas beforeenteringpower down. Minimum power consumptionisachievedinthepower-down mode withSCLK disabledand SYNC and D IN idled low.The time to exitpower-down (Wake-Up Time) is typicallytWU µsec as statedin the A.C. and Timing CharacteristicsTable.

APPLICATION INFORMATION

The simplicityof the DAC081S101 impliesease of use. However, itisimportantto recognizethatany data converterthatutilizesitssupplyvoltageas itsreferencevoltagewillhave essentiallyzeroPSRR (Power Supply RejectionRatio).Therefore,itisnecessarytoprovidea noise-freesupplyvoltagetothedevice. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DAC081S101

P3.3 TXD RXD SCLK DIN SYNC ADSP-2101/ ADSP2103 DAC081S101 TFS DT SCLK DIN SCLK SYNC DAC081S101 SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com DSP/MICROPROCESSOR INTERFACING InterfacingtheDAC081S101 tomicroprocessorsand DSPs isquitesimple.The followingguidelinesareoffered tohastenthedesignprocess. ADSP-2101/ADSP2103 Interfacing Figure37 shows a serialinterfacebetween theDAC081S101 and theADSP-2101/ADSP2103. The DSP should be settooperateintheSPORT TransmitAlternateFramingMode. Itisprogrammed throughtheSPORT control registerand shouldbe configuredforInternalClock Operation,ActiveLow Framing and 16-bitWord Length. Transmissionisstartedby writinga word totheTx registeraftertheSPORT mode has been enabled. Figure37. ADSP-2101/2103 Interface 80C51/80L51 Interface A serialinterfacebetween theDAC081S101 and the80C51/80L51 microcontrollerisshown inFigure38.The SYNC signalcomes froma bit-programmablepinon themicrocontroller.The example shown hereuses portline P3.3.Thislineistakenlow when dataistotransmittedtotheDAC081S101. Sincethe80C51/80L51 transmits8- bitbytes,onlyeightfallingclockedges occurinthetransmitcycle.To loaddataintotheDAC, theP3.3 linemust be leftlow afterthefirsteightbitsaretransmitted.A second writecycleisinitiatedtotransmitthesecond byteof data,afterwhich portlineP3.3 isbroughthigh.The 80C51/80L51 transmitroutinemust recognizethatthe 80C51/80L51 transmitsdatawiththeLSB firstwhiletheDAC081S101 requiresdatawiththeMSB first. Figure38. 80C51/80L51 Interface 68HC11 Interface A serialinterfacebetween theDAC081S101 and the68HC11 microcontrollerisshown inFigure39.The SYNC lineoftheDAC081S101 isdrivenfroma portline(PC7 inthefigure),similartothe80C51/80L51. The 68HC11 shouldbe configuredwithitsCPOL bitas a zero and itsCPHA bitas a one. Thisconfiguration causes dataon theMOSI outputtobe validon thefallingedge ofSCLK. PC7 istakenlow totransmitdatatothe DAC. The 68HC11 transmitsdatain8-bitbyteswitheightfallingclockedges.Data istransmittedwiththeMSB first.PC7 must remainlow afterthefirsteightbitsaretransferred.A second writecycleisinitiatedtotransmitthe second byteofdatatotheDAC, afterwhichPC7 shouldbe raisedtoend thewritesequence. Figure39. 68HC11 Interface MicrowireInterface Figure40 shows an interfacebetween a Microwirecompatibledeviceand theDAC081S101. Data isclockedout on therisingedges oftheSCLK signal.

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LM4050-4.1 or LM4050-5.0 DAC081S101 DIN SCLK SYNC VOUT = 0V to 5V 0.47 PF Input Voltage R VZ LM4130-4.1 DAC081S101 DIN SCLK SYNC VOUT = 0V to 4.080V 0.1 PF 2.2 PF Input Voltage MICROWIRE DEVICE DAC081S101 CS SK SO SCLK DIN SYNC DAC081S101 www.ti.com SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 Figure40. MicrowireInterface USING REFERENCES AS POWER SUPPLIES Recalltheneed fora quietsupplysourcefordevicesthatuse theirpower supplyvoltageas a referencevoltage. SincetheDAC081S101 consumes verylittlepower,a referencesourcemay be used as thesupplyvoltage.The advantagesof usinga referencesourceover a voltageregulatorare accuracyand stability.Some low noise regulatorscan alsobe used forthe power supplyof the DAC081S101. Listedbelow are a few power supply optionsfortheDAC081S101. LM4130 The LM4130 reference,withits0.05% accuracyovertemperature,isa good choiceas a power sourceforthe DAC081S101. Itsprimarydisadvantageisthelackof3V and 5V versions.However,the4.096V versionisuseful ifa 0 to4.095V outputrange isdesirableor acceptable.BypassingtheLM4130 VIN pinwitha 0.1µF capacitor and theVOUT pinwitha 2.2µF capacitorwillimprovestabilityand reduceoutputnoise.The LM4130 comes ina space-saving5-pinSOT23. Figure41. The LM4130 as a power supply LM4050 Availablewithaccuracyof0.44%,theLM4050 shuntreferenceisalsoa good choiceas a power regulatorforthe DAC081S101. Itdoes not come ina 3 Voltversion,but 4.096V and 5V versionsare available.Itcomes ina space-saving3-pinSOT-23. Figure42. The LM4050 as a power supply Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DAC081S101

VOUT = 0V to 5V 1 PF Input Voltage ON / OFF VIN VOUT LP3985 DAC081S101 DIN SCLK SYNC VOUT = 0V to 5V 1 PF 0.1 PF Input Voltage 0.01 PF DAC081S101 SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com The minimum resistorvalueinthecircuitofFigure42 shouldbe chosen such thatthemaximum currentthrough theLM4050 does notexceed its15 mA rating.The conditionsformaximum currentincludetheinputvoltageat itsmaximum, theLM4050 voltageatitsminimum, theresistorvalueatitsminimum due totolerance,and the DAC081S101 draws zero current.The maximum resistorvaluemust allowthe LM4050 to draw more than its minimum currentforregulationplusthe maximum DAC081S101 currentin fulloperation.The conditionsfor minimum currentincludetheinputvoltageatitsminimum, theLM4050 voltageatitsmaximum, theresistorvalue at itsmaximum due to tolerance,and the DAC081S101 draws itsmaximum current.These conditionscan be summarized as R(min)= (VIN(max)− VZ(min)/(IA(min)+ IZ(max)) (3) and R(max) = (VIN(min)− VZ(max)/(IA(max)+ IZ(min)) (4) where VZ(min)and VZ(max) are the nominal LM4050 outputvoltages± the LM4050 outputtoleranceover temperature,IZ(max) isthe maximum allowablecurrentthroughthe LM4050, IZ(min)isthe minimum current requiredby theLM4050 forproperregulation,IA(max)isthemaximum DAC081S101 supplycurrent,and IA(min) istheminimum DAC081S101 supplycurrent. LP3985 The LP3985 isa low noise,ultralow dropoutvoltageregulatorwitha 3% accuracyovertemperature.Itisa good choiceforapplicationsthatdo notrequirea precisionreferencefortheDAC081S101. Itcomes in3.0V,3.3V and 5V versions,among others,and sportsa low 30 µV noisespecificationatlow frequencies.Sincelow frequency noiseisrelativelydifficulttofilter,thisspecificationcouldbe importantforsome applications.The LP3985 comes ina space-saving5-pinSOT-23 and 5-bump DSBGA packages. Figure43. Using theLP3985 regulator An inputcapacitanceof 1.0µF withoutany ESR requirementisrequiredat the LP3985 input,whilea 1.0µF ceramiccapacitorwithan ESR requirementof 5m Ω to 500m Ω isrequiredat the output.Carefulinterpretation and understandingofthecapacitorspecificationisrequiredtoensurecorrectdeviceoperation. LP2980 The LP2980 isan ultralow dropoutregulatorwitha 0.5% or 1.0% accuracyovertemperature,dependingupon grade.Itisavailablein3.0V,3.3Vand 5V versions,among others. Figure44. Using theLP2980 regulator

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0.1 PF+10 PF

+5V R 1 R 2 -5V +5V ±5V 10 pF DAC081S101 www.ti.com SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 Likeany low dropoutregulator,theLP2980 requiresan outputcapacitorforloopstability.Thisoutputcapacitor must be atleast1.0µF overtemperature,butvaluesof2.2µF ormore willprovideeven betterperformance.The ESR of thiscapacitorshould be withinthe range specifiedin the LP2980 data sheet.Surface-mountsolid tantalumcapacitorsoffera good combinationofsmallsizeand ESR. Ceramic capacitorsare attractivedue to theirsmallsizebutgenerallyhave ESR valuesthatare toolow foruse withtheLP2980. Aluminum electrolytic capacitorsaretypicallynota good choicedue totheirlargesizeand have ESR valuesthatmay be toohighat lowtemperatures. BIPOLAR OPERATION The DAC081S101 isdesignedforsinglesupplyoperationand thushas a unipolaroutput.However, a bipolar outputmay be obtainedwiththecircuitinFigure45.Thiscircuitwillprovidean outputvoltagerangeof±5 Volts. A rail-to-railamplifiershouldbe used iftheamplifiersuppliesarelimitedto±5V. Figure45. BipolarOperation The outputvoltageofthiscircuitforany code isfoundtobe VO = (VA x (D /256)x ((R1+ R2) /R1) -VA x R2 /R1) (5) where D istheinputcode indecimalform.WithVA = 5V and R1 = R2, A listofrail-to-railamplifierssuitableforthisapplicationareindicatedinTable3. Table3.Some Rail-to-RailAmplifiers AMP PKGS Typ VOS Typ ISUPPLY PDIP-8LMC7111 0.9mV 25 µASOT-23-5 SO-8LM7301 0.03mV 620 µASOT-23-5 LM8261 SOT-23-5 0.7mV 1 mA LAYOUT, GROUNDING, AND BYPASSING For best accuracyand minimum noise,the printedcircuitboard containingthe DAC081S101 should have separateanalogand digitalareas.The areasaredefinedby thelocationsoftheanalogand digitalpower planes. Both oftheseplanesshouldbe locatedinthesame boardlayer.There shouldbe a singlegroundplane.A single ground planeispreferredifdigitalreturncurrentdoes not flowthroughthe analogground area.Frequentlya singleground planedesignwillutilizea "fencing"techniquetopreventthemixingofanalogand digitalground current.Separategroundplanesshouldonlybe utilizedwhen thefencingtechniqueisinadequate.The separate ground planesmust be connectedinone place,preferablynear theDAC081S101. Specialcareisrequiredto guaranteethatdigitalsignalswithfastedge ratesdo notpass oversplitgroundplanes.They must alwayshave a continuousreturnpathbelowtheirtraces. The DAC081S101 power supplyshouldbe bypassed witha 10µF and a 0.1µF capacitoras closeas possibleto thedevicewiththe0.1µF rightatthedevicesupplypin.The 10µF capacitorshouldbe a tantalumtypeand the 0.1µF capacitorshouldbe a low ESL, low ESR type.The power supplyforthe DAC081S101 shouldonlybe used foranalogcircuits. Avoidcrossoverofanalogand digitalsignalsand keep theclockand datalineson thecomponent sideofthe board.The clockand datalinesshouldhave controlledimpedances. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:DAC081S101

SNAS323C –JUNE 2005–REVISED FEBRUARY 2013 www.ti.com

REVISION HISTORY

Changes from RevisionB (February2013)toRevisionC Page

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www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DAC081S101CIMK/NO.A Active Production SOT-23- THIN (DDC) | 6 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 105 X65C DAC081S101CIMK/NOPB Active Production SOT-23- THIN (DDC) | 6 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 105 X65C DAC081S101CIMKX/NO.A Active Production SOT-23- THIN (DDC) | 6 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 105 X65C DAC081S101CIMKX/NOPB Active Production SOT-23- THIN (DDC) | 6 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 105 X65C DAC081S101CIMM/NO.A Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 105 X64C DAC081S101CIMM/NOPB Active Production VSSOP (DGK) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 105 X64C DAC081S101CIMMX/NO.A Active Production VSSOP (DGK) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 105 X64C DAC081S101CIMMX/NOPB Active Production VSSOP (DGK) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 105 X64C (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 23-May-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant DAC081S101CIMK/NOPB SOT-23- THIN DAC081S101CIMKX/ NOPB SOT-23- THIN DAC081S101CIMMX/ NOPB Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC081S101CIMK/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0 DAC081S101CIMKX/ NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0 DAC081S101CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 DAC081S101CIMMX/ NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 6X 0.65 1.95 8X 0.38 0.25 5.05

4.75 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8

1.1 MAX

0.23 0.13 B 3.1 2.9 NOTE 4 A 3.1 2.9 NOTE 3 0.7 0.4 VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023

0.13 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. PowerPAD is a trademark of Texas Instruments. A 20 DETAIL A TYPICAL SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. TM SOLDER PASTE EXAMPLE SCALE: 15X SYMM SYMM

www.ti.com PACKAGE OUTLINE C 0.20

0.12 TYP

0.25 3.05 2.55 4X 0.95 1.1 0.7 0.1

0.0 TYP

6X 0.5 0.3 0.6

0.3 TYP

1.9 0 -8 TYP 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR 4214841/E 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC MO-193. 3 4

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

6X (1.1) 6X (0.6) (2.7) 4X (0.95) (R0.05) TYP 4214841/E 08/2024 SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPLOSED METAL SHOWN SCALE:15X SYMM 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDERMASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.7) 4X(0.95) 6X (1.1) 6X (0.6) (R0.05) TYP SOT-23 - 1.1 max heightDDC0006A SMALL OUTLINE TRANSISTOR 4214841/E 08/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM SYMM 3 4

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