DAC0631N

DAC0630 NSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 15

Technical content

8 ZA National

8 DAC0630/ DAC0631 ;

Triple 6-Bit Video DAC with Color Palette a General Description Features The DACO630 and DACO631 are monolithic triple 6-bit video ™ Pixel rates of 50 MHz (DACO630) and 35 MHz digital-to-analog converters with on-chip 256 x 18 bit color (DAC0631) palettes and are intended for graphics applications. The col. m 256 x 18 bit color palette or palette makes possible the display of 256 colors selected +m 256K possible colors from a total of 256K possible colors through the internal im Color palette read-back 6-bit video DACs. The DACs are capable of driving 752 or Three internal 6-bit DAC: 37.50 loads to normal video lavels at pixel rates of 50 MHz : Direly driv (75) vi eo cable (BAC030) and 35 MHz (DACO631). The DACO630 and 8 aoe iad on i video DAC0631 provide a bi-directional microprocessor interface ™ analog outpul with TTL compatible inputs. The DACO630 and DACOes1 —™ Composite blank are pin- and functionally-compatible with the Inmos IMS ™ Single +5V supply G171-50 and IMS G171-35 and IMS G176-50 and IMS — ™ Low power, high performance CMOS/bipolar G176-35, processing @ TTL compatible inputs

8 Full asynchronous yP interface

@ 28-pin package a Block and Connection Diagrams Dual-In-Line Package Tien VY + PCLK 9 ve RDI © 2-ev (Generator GREEN] 2 27 PRs, GND BLUE] 3 26 F=RSp leer 4 25 WR Color Palette Pomys 24y-0, 256x 18 Bit Ps 23-0, Po= Py Address Pa“]7 ~— pACo630 22 F—Ds, Ps48 DACOBS! = ay D4 ys 20}—Ds, P5410 19, Peay 18}=D, Pyqi2 17-0 13 16 F= BLANK M-0,€ 8-Bit POLK — Mlero- GNO—414 15 FRO WR RED ra} tntarace Triple TL/H/9696-2 6~Bit GREEN BS, 18-Bit Data taten [aa)) DAC Top View RS, BLUE Order Number DACO0630CCD or DAC0631CCD — See NS Package Number D28D BLANK: IREF Order Number DACO631CCN ‘See NS Package Number N26B TLM/eeae=1

— > Absolute Maximum Ratings (wotes1 a2) Power Dissipation (Note 5) ow 16 If Military/Aerospace specified devices are required, ESD Susceptability (Note 6) 2000V please contact the National Semiconductor Sales Soldering Information Office/Distributors for avallability and specifications. D Package (10 sec) 300°C S Positive Supply Voltage (V+) GND — 0.3Vto7V N Package (10 sec) 260°C 3 Voltage at Logic Inputs (Note 3) GND — 0.5V to Storage Temperature — 65°C to 150°C 3 V+ + 0.5V ao Voltage at Analog Pins 1-4 (Note 3) GND ~ 0.5Vto Operating Ratings (notes 1 a 2) = V+ + 0.5V Temperature Range Analog Output Current, Pins 1-3 45mA TMIN $ Ta $ Twax OC <Tas + 70°C Reference Current, Pin 4 15mA Positive Supply Voltage 4.5 to 5.5V DC Digital Output Current (Note 4) 25mA AC and DC Electrical Characteristics The following specifications apply for V+ = +5vV, unless otherwise specified. Boldface limits apply for Tun to Tmax; all other limits Ta = 25°C. DACO630 DAC0631 ‘Symbol Conditions Tested Design Units en Limit Limit (Note 8) | (Note 9) Tmer | Rerence Curent | Minimum | mA [Maximum | mA lave Maximum Average | DACO630 | Poi = 50 MHz mA Supply Current DAC0631 Pouk = 35 MHz mA Ine = 10 mA Digital Outputs Unloaded VrEFmin | Minimum Reference Voltage at V+ = 45V vi-s v Iner Pin Ine = 8.88 mA im Maximum Digital input Current V+ = 5.5V £10 A (Pins 5-13, 15, 16, 25-27) GND < Vin < V+ iat loz Maximum Tri-State Digital Output V+ = 55V +50 A Current (Pins 17-24) GND < Vin < V+ Vou Minimum Logic “1” Output V+ = 4.5V,lo = —5mA V Voltage Vor Maximum Logic “0” Output V+ = 4.5V, lo = +5mA v Voltage Vina Minimum Logic “1” Input Voltage 45V V+ <55V re ee Vit Maximum Logic “0” Input Voltage | 4.5V < V+ < 65V [| on [| ~~ vv [ pacnesowton PT ts Vout Minimum Output Voltage lout < 10 mA v Compliance (Pins 1-3)

$| AC and DC Electrical Characteristics (continues) © | The following specifications apply for V+ = +5V, unless otherwise specified. Bokiface limits apply for Tyan to Tyax; all G |__ other limits T, = 25°C. Ss DAC0630 s DAC0831 2] symbol Conditions Tested | Design | Units Typical a (Note 7) | Umit Umit (Note 8) | (Note 9) lout Maximum Output Current Vout < 1V mA Compliance (Pins 1-3) IREF < 10 mA Full-Scale Gain Error ZL = 752 + 30 pF —8,+2 % (Note 10) IneF = 4.44 mA lar = 8.88 mA DAC-to-DAC Mismatch Zi = 75M + 30 pF Iner = 4.44 mA +2 % (See Note 11) Integral Non-Linearity ZL = 752 + 30 pF (Note 12) lace = 4.44mA 40.5 ise ton Rise Time 2, = 750 + 30 pF ns {Note 13) lner = 4.44 mA Maximum Full-Scale | DACO630 | Z, = 752 + 30pF 20 ns Settling Time DACo631 Iner = 4.44 mA 28 ns (See Note 14) Maximum Glitch Energy ZL = 750 + 30 pF Ine = 4.44 mA +200 +400 | pV-sec (See Note 15) Cin Digital Input Capacitance (Pins 7 F Court Digital Output Capacitance (Pins RD = Logic High 7 pF 17-24) Couta Analog Output Capacitance BLANK = Logic Low pF (Pins 1-3) VouTeLANk | Maximum Blanking Output BLANK = Logic Low Voltage ZL = 750 + 30 pF 40.8 LsB Incr = 4.44 mA Unadjusted Output Offset Error BLANK = Logic High Z, = 750 + 30 pF 10.8 LsB ther = 4.44mA Clock Feedthrough | DACO630D | Poik = 50MHz aB (Note 16) DACO631D | Poik = 35 MHz 4B DACOE3IN | Poik = 35MHz aB ZL = 75M + 30 pF Inge = 4.44 mA PSs Power Supply Sensitivity 45V < Vt < 55V lout = Full Scale Z, = 750 + 30 pF *N laer = 4.44 mA

i=] 1 " > Tain to Twax; all other limits Ta = 25°C. Design Limits apply for 4.5V < V+ < 5.5V. 8 s io] Symbol Parameter Typicai | Tested | Design / 71.4, | Tested | Design | ing 3 (Note 7)} Limit) Limit | oe 7)| Limit | Limit (Note 8)| (Note 9) (Note 8) | (Note 9) EA tonon | Minimum POLK Period a ee Aono | Maximum POLK ster [room [ses ff [ees [Tw tron [Minimumpoikwiamtow | | Ts Te ff 8 | 8 | ts tenor [Minimumpcuxwiamrign [Te Toe ff 7 [ 2? Ios tpvcH _| Minimum Pixel Word Setup Time | (Note 18) a ee ns tcxex | Minimum PuetwordHoldTime [ivory | [4 | «@ | | 4 | «| ns tevon [Minimum BLANK Setup Time [(wotora) [| [4 [| « | [| 4 | « | ns tovex |MinimumBCANK HoldTime [wotore) [| [| « | [4 | « | ns tonay | POLK 0 Vata DAG Ce ns Output AtcHav | Maximum Differential Output (Note 20) Delay ns uw [Minimum WA Puisewith tow | | Tso | se | | 50 | #0 | ns taunt |MiimumRBPusewidtntow | | [so | se | | 50 | 0 | ns tsvwi_ | Minimum Register Select Setup _| (Write Cycle) ns Time ‘a time Reamer seeaseue [esdcvee | fof ol [iw] | ns Time twisx | Minimum Register Select Hold _| (Write Cycle) ns Time me ete fesse) | fe fw] fw fw | ns Time ‘wiox |Minimum WR DataHodTine [| [0 | se [ [as | as | ns tmuox [Minimum Ouputtumondela | | Ts | os | [ s [ 5 | ns trtav | Maximum RD Enable Access ns Time taixox [Minimum Ourpurviotine | | Ts Tos [Ts | os | m terior _|Maximum OutputTum-orf Delay [inotwaty | [20 | 20 | | 2 | 20 | ns twHwz1 | Minimum Successive Write 4 | Interval S¢icHcH) 3(tcHcH) | SteneH) twi Minimum WR followed by Read MRL Interval 3(tcHcH) | Steen) 3(tcHcH) | Steen) tRHRL1 | Minimum Successive Read Interval 3(tcHcH) S(tcHcH) | 3teHeHy tre Minimum RD followed by Write wet Interval 3itcHcH) | Sener) 3(tcHcH) | Steer) ‘wawi2| Minimum WR atterColorwrte [(wote22) | [atencn| Stenew| | Secxony| Stonew |

$| AC Electrical Characteristics (Continued) The following specifications apply for Vt = +5V. Boldface | _limits apply for Tin to Tuaxs all othor limits Th = 25°C, Design Limits apply for 4.5V < V+ < 5.5V. So & | symbol Typical Design | typical | Tested | Design | writs 8 (Note 7) Limit (Note 7) Limit Limit g (Note 9) (Note 8)| (Note 9) | twari2 [Minimum AD atterColorwrte | (ote22) | [Stcnow| atencm| | tcc | Stoner | truaz [Minimum RD atterColorRead | (Note 22) | [Stcucw| Stencw| | con) | Brtenern | truwi2 |MinimumWR atter Color Read | (Note22) | | 6toucrn| @temem| | fcrcrn | @xtonecsn | Minimum RD after Read (Note 22) cee et er Transition Time Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating ratings. Note 2: All voltages are measured with respect to ground, unless otherwise specified. Note 3: When the input voltage (Vix) at any pin exceeds the power supply rails (Vin < GND or Vin > V+) the absolute value of current at that pin should be limited to 5 mA or less. The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed 20 mA. Note 4: One output at any time. The maximum time for this output level is one second. Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by Tyyax, 8a, and the ambient temperature, Ts. The maximum. allowable power dissipation at any temperature is Pp = (Tyax-Ta)/@ ja oF the number given in the Absolute Maximum Ratings, whichever is lower. For this device, Tyyax = 125°C, and the typical thermal resistance (@ sa) of the DACO630/0631CCD when board mounted is 40°C/W. The typical thermal resistance for the DAC0630/631CCN when board mounted is 85°C/W. . Note 6: Human body model, 100 pF discharged through a 1.5 kN resistor. Note 7: Typicals are at 25°C and represent most likely parametric norm. Note 8: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level). Note 9: Design limits are guaranteed to National's AOQL (Average Outgoing Quality Level) but not 100% tested. ‘Note 11: The fisted value is relative to the midpoint of the full-scale distribution of the internal three DACs. Note 12: Zero and full-scale adjusted linearity error = [Vout—Vottset-(D X Visall/Visa. Visa = (Vfull scale-Vottset)/63. Note 13: The rise time is measured from 10% to 90% of the full scale transition. Note 14: The output signal's settling time is measured from a 2% change at the transition’s initial value until it has settled to within 2% of the final value, excluding clock feedthrough. Note 15: This value is determined using triangle approximation: glitch energy = (area of positive transient)-(area of negative transient). Note 16: The vakue shown is the ratio of the RMS value of any PCLK signal on the analog outputs to the full-scale output voltage (700 mV). Nate 17: This parameter is the allowed variation in the pixel clock frequency. It does not permit the pixel clock period to vary below the minimum value for pixel clock (IcHcH) Period specified above. ‘Note 18: It is necessary that the color palette’s pixel address be a valid logic level with the appropriate setup and hold times at each rising edge of Pk (this requirement includes the bianking period, Nate 19: A valid analog output is defined as the 50% point between successive values. This parameter is stable with time but can vary between different devices: and may vary with different de operating conditions. Note 20: This applies to different analog outputs on the same device. Note 21: Measured at +200 mV from initial steady state output voltage. Note 22: This parameter allows synchronization between operations on the microprocessor interface and the pixel stream being processed by the color palette, 4-10

8 KXXXXXXXXXXXKXRKREK— A in a ae

FIGURE 1. System Timing Diagram FIGURE 2. Expanded Timing Diagram Detailing Timing Specifications

8 Timing Waveforms (continued)

FIGURE 3. Basic Write Cycle FIGURE 4. Basic Read Cycle FIGURE 5. Write to Pixel Mask Register Followed by a)Write, b)Read FIGURE 6a. Read from Pixel Mask or Pixel Address FIGURE 6b. Read from Pixel Mask or Pixel Address.

8 RHR RHR ‘trun

FIGURE 10. Read Color Value then Read Pixel Address Register (Read Mode) FIGURE 11. Color Value Write Followed by Any Read FIGURE 12. Color Value Write Followed by Any Write

PCLK (13) The high-speed Pixel Clock signal is ap-

3 Connection Diagram plied to this pin, The rising edge controls

< Plastic & Cavity the latching of the Pixel Address and a Duat-In-Line Package Blanking inputs. It also controls the prog- 3 ress of these values through the three a, . stage pipeline of the Color Palette and 8 RD—1e Brv through the DACs to the outputs. < GREEN 2 27 PRs, GND (14) This is the ground power supply connec- a BLUE—]3 26; Rso tion. trey 4 25-—-WR RD (15) This is the active low Read bus control Pos 2h, signal. When active, any information Present on the internal data bus is avail- Le cd able on the Data I/O lines, Dp—D7. Po~17 — pacos3o 22 Ds, BLANK (16) This is an active low signal that forces the Pz—y8 DACOBST yh, DACs outputs to zero. When BLANK is Fee 200s asserted a video monitor's screen be- Pefio too, comes black and the DACs ignore any 5 output values from the Color Palette. Peay 18F-0, However, the Color Palette can still be Piz 17-0, updated through Do-D7. POLK 413 165 BLANK Do-D7 (17-24) These are the bidirectional Data I/O lines GND—414 15RD used by the host microprocessor to write information (using the active low WR) into TLH/9638-18 and read information (using the active low Top View RD) from the DACO630 and DACO631’s internal registers (Pixel Address register, Pin Descriptions ied Value register, and Pixel Mask reg- ister). RED (1), These are the analog output pins of the . won GREEN (2), Sit DACs, The output currents from WR latches the data Into the selacted BLUE (3) these pins flow through the terminating register. resistors and develop the RGB (red, _- . green and blue) voltages that drive the The rising edge of RD determines the monitor. Each DAC is composed of 63 end of the read cycle. current sources. The output of each of With FID and WR equal to a logic high, these current sources is summed togeth- the Data I/O lines will no longer contain er according to the applied 6-bit binary information from the selected register value. and will go into a tristate mode. trer (4) This is the Reference Current input. The WR (25) This is the active low Write signal. It con- current forced out of this pin to ground trols the timing of the write operations on determines the current sourced by each the microprocessor interface inputs, Do- of the 63 current sources in each of the D7. When active, any information present three 6-bit DACs. Each current source ‘on the external data bus is available to produces 1/30 of IRer when activated by the Data {/O lines, Do-Dz. the 6-bit digital input code. RSo, RS; These are the Register Select lines which Po-P7 (5-12) These are the high-speed Pixel Address (26, 27) control the selection of one of the three inputs. This byte-wide information is internal registers. These two lines are latched and masked by the Pixel Mask sampled during the falling edges of the Register. The resulting value is used as enable signals (RD or WA). See Func- an address of a location in the Color Pal- tional Description for more information re- ette RAM. garding the internal registers. V+ (28) This is the positive supply pin. It is nor- mally connected to +5 Vde and by- passed with a 10 uF tantalum capacitor and a 0.1 yF chip capacitor. 416

i=] . . > Functional Description ° The DAC0630 (or DACO631) forms the output stage for high It is possible to read the color definitions stored in the | & resolution raster scan RGB video systems. It contains a Col- DAC's color palette. After setting RSp and RS, equal to 1, gs or Palette with 256 memory locations that are 18 bits wide. the desired color palette address is stored in the Pixel Ad- o The color palette’s output is connected to three high speed dress register. The color definition (18-bits) in the desired > current output 6-bit video DACs. The devices use on-board color palette location is then automatically transferred to the registers to interface easily with microprocessors. Color Value register and the Pixel Address is auto-incre- 2 ICROPRI mented. With successive read cycles, the color definitions MI OCESSOR INTERFACE . . Pointed to by the incremented address are transferred to = The DACO630 and DACO631’s microprocessor interface the color value ragister. Refer to Figure 73. Consists of three internal registers; Pixel Address register, The Pixel Mask register is a byte-wide latch. by setting Color Value register, and Pixel Mask register. These are in- Sq = 0 and RS; = 1, the Pixel Mask register can be dividually accessed by register select signals, RSp and RS. accessed by the microprocessor interface, Do Dy. This reg- The following table defines which of the thrae internal regis- ister is used to mask selected bits of the pixel address val- bel is Sorectod by each Of the four combinations of logic ues applied to the Pixel Address inputs (Pp-Pz). A “1” in states of RSo 2 any location in the Pixel Mask register leaves the corre- [Rs | RS; [ _—Reglster i ‘sponding bit in the pixel address unchanged. A “0” will reset . the corresponding bit to zero. The operation of the Pixel ° 0 Pixel Address (Write Mode) Mask register does not affect the address of the color defi- 1 1 Pixel Address (Read Mode) nition when the microprocessor accesses the color palette. 1 0 Color Value The masking operation makes it possible to alter the dis- 0 1 Pixel Mask played colors without altering the contents of external video memory or the DACO630/631's color palette. The contents of the color palette can be accessed through the Color Value and Pixel Address registers. WRITING TO THE COLOR PALETTE All of the operations on the microprocessor interface can naw sratying the wal be stored nme color patio by take place asynchronously to the pixel information currenth irst_ specifying the i address while in write mi being processed by the nly Palette. ¥ (RSp = RS; = WA = 0). This address is stored in the Pixel . \\ ' Address register. The initial address is followed by the red, The Pixel Address register is a byte-wide latch that re- green and blue color definition data (RSp = 1, RS; = Geives and latches address information applied to pins 17~ WR = 0). These three six-bit values are collected together ae can ba used in state of Ree an dNS: Wit Fis 2 iN the Color Value register fr a total of 18 bits, The internal Be, 9 (0 vator solect 0 0}, the Pixel exicross rogetor logic then transfers this new color definition to the location ig id the write mode. 7 ‘wo events normally precede voting pointed to by the address stored in the Pixel Address regis- ,. oe ter. As soon as this transfer is completed, the Pixe! Address one or more new color definitions to the color paletts. The ragister is auto-incremented. This allows consecutive color first is the specification of a color palette address. Second, lette locations to be ted without the mi the Color Value register must be loaded with a color defini- Baletie locations to be updat 1 microprocessor tion, The sequence of data transfer is 1) the desired color ‘specifying each address. All that is necessary is to continue Palette address (this address is stored in the Pixel Addess _-—SUBPIiNG the red. green and blue data for each consecutive register) and 2) the olor detnitons: red, green and blue Attompting to Update the color palette when BLANK i not Refer to Figures 17 and 12. BILAN RSq = RS; = 1 (register select = 1,1), the Pixel asserted results in the data from the Color Value register wr rose. nagh ‘tor i in thew inode, Ones casi, twa taking precedence over the DACO630 and DAC0631’s bit owonte take lace and normally Woceds readin one oy mapping operation. The output of the three 6-bit DACs will more color deinions inthe colo plato. The fst action is D2 Based on the color definition from the memory location 0 ths " specified by the pixel address register and not the address 10 spec ity an anes Ino vogietor at ako conta woes found on Po-P7. This conflict results in the DAC’s generat- color palette location whose address is stored in the Pixel po Unexpested output levels. This can last as long as two Address Register. The color definition data transfer se- ‘CLK Periods. quence is red, green and blue. Refer to Figures 10, 13 and READING FROM THE COLOR PALETTE 4, To read a location in the color palette an address is sent on The Color Value register is an internal 18-bit wide register the Data I/O lines (Dp-D7) while in read mode (RSp = used as a buffer between the microprocessor interface and RS, = 1, WR = 0) and stored in the Pixel Address register. the color palette. It is accessed by setting RSg = 1 and The color definition in the specified color palette location is RS, = 0. A color definition can be read from or written to then transferred to the Color Value register and the Pixel this register by a sequence of three byte-wide transfers to Address register is auto-incremented. The color definition this register address. When a byte is written to this register, can now be retrieved with three sequential read operations only the least significant six bits (Dp-Ds) contain color intor- (RSp = 1, RS; = RD = 0). The first byte placed on the mation. When a byte is read from this register address, only Data |/O lines contains the red value. The next is green, the six least significant bits contain information—the most and the last is blue. The two most significant bits are set to significant two bits are set to zero. Refer to Figures 10-14. zero in each case. Once again, the Pixel Address register is After the write sequence is completed, the Color Value reg- auto-incremented, and consecutive color palette locations ister’s contents are written to the specified color palette ad- can be read simply by specifying the beginning address and dress stored in the Pixel Address register. Finally, the Pixel reading the color palette one or more times. Refer to Fig- Address register is automatically incremented. ures 10, 13 and 14. AAT

8] Functional Description (continues) ANALOG OUTPUT—LINE DRIVING Q | _ Ir the Pixel address register is ever updated during aread or The connection between the DAG’ outputs and the RGB | write operation, the current data sequence is terminated inputs of the video monitor it is driving viewed as 3 | and anew read or write operation is initialized. a transmission line. Impedance changes along this fine will 3 . result in the reflection of part of the video signal back to the g VIDEO PATH DAC'’s outputs. These reflections may result in a degrada- © | The video path consists of the Pixel Latch and Mask (inputs tion of the picture quality displayed on the monitor. 4 Pp-P7), color palette (256 x 18-bit wide RAM), 18-bit wide To ensure good signal fidelity, RF techniques should be ob- bus, and an 18-bit wide latch on the inputs of the three 6-bit served. Any traces connecting the DACO630 or DAC0631 to high-speed video DACs. The video path uses a three clock an on-board connector should form a transmission line of cycle (Pci) pipeline for the pixel address and BLANK in- 75Q impedance. However, the need to ensure that the con- puts. These signals are latched on the rising edge of PoLK. Necting traces form a transmission line can be eliminated by At each rising edge of Poi, the Color Palette address ap- Placing the DAC's output termination resistors at the output plied to Pp-P7 is stored in the Pixel Latch and defines a connector instead of the DAC's output pins. location in the Color Palette. The color definition in that lo- The coaxial cable that connects the DAC’s outputs to a vid- cation is then transferred to the three 6-bit DAC input latch- 0 monitor should have a characteristic impedance of 750. es. Connectors on the coaxial line can cause impedance The analog outputs are designed to drive 759 loads with a IneF set to 4.44 mA or 37.59 loads with Iper set to Comet four different methods of terminating the DAC 8.88 mA. For both loads the peak-white amplitude is 0.7V. 4) Sin le termination at the DAC (75) The analog outputs can be set to zero by using the BLANK 2) Single termination at the destination (759) input. This is an active iow signal that forces the analog 3) Double termination (37.59) outputs to ground by placing all zeros on the DACs’ inputs. 4) Buffered signal ° The color definition selected by the pixel address is ignored. { ie termination at the involves placi The DAC0630/631's DACs use switched current sources ) single term pases paeilnaait art tel io that are summed together, thus generating the output cur- a output 0 - i and DAC0631 (or at the connector, as described above). No rent. Each6-bit DAC Consiats of 63 current Sources, each of other terminating load is present. Therefore, a high-input and contributing to the total output current. This output cur- the DACs outputs isthe transmission ine impedance in ar rent, in conjunction with a termination resistance connected in ‘ ance should match the impedance of the load resistor. between each DAC output and ground, sets the full-scale Thus, the DAC’s output has an initial signal amplitude that is magnitude of the output voltage as determined by * ital sig plitude that i half the de value expected. This half-amplitude signal is VPEAK WHITE = 2.1(IREF)RL 100% reflected by the open circuit presented by the monitor VBLACK LEVEL = 0V input. This restores the signal amplitude to the expected value. The reflections from the monitor propagate back Application Hints towards the DAC outputs. The load resistor at each DAC POWER SUPPLY output presents a correctly terminated transmission line so no further reflections occur. This arrangement is relatively The DACO630 and DAC0631 draw large transient currents tolerant to mismatches in the transmission line between the from the power supply. To ensure proper operation it is nec- DAC and the monitor because no reflections occur at the essary to utilize standard high frequency board layout and DAC end of the transmission line. However, multiple moni- power supply distribution techniques. tors should not be connected in parallel despite each moni- The transient currents drawn by the DACO630 and tor's high input impedance. DAC0631 dictate that the ac impedance at the supply pins 2) Single termination at the destination has the termina- must be kept to a minimum. This is accomplished by using tion impedance at the input of the monitor acting as both the the recommended decoupling capacitors, C1 and C2, as load resistor for the DAC and the termination impedance of shown in Figure 15. These capacitors must have leads that ‘the cable (transmission line). If the connection between the are as short as possible. High frequency decoupling is ac- DAC0630/631 is correctly terminated there will be no reflec- complished with a 0.1 4F chip capacitor, C1. A bead tanta- tions. However, if there are any line impedance variations lum, between 10 pF to 47 uF, should be used for Co. along the cable, reflections will occur and create “ghost im- Differential ground noise can be created when a voltage ages” on the display. This occurs because there is a reflec- difference appears between pin 14 and the ground of the tion from the point where the mismatch occurs back to the digital devices driving the DACO630 or DAC0631. This volt- DAC’s output. The signal then reflects off the DAC’s output age difference is caused by series impedance in the ground back toward the monitor. It arrives with a significant time path and the current transients drawn by the DACO630 or delay following the original signal, and “ghosting” results. DAC0631. The differential ground noise can be minimized 3) Double termination of the DAC outputs allow each end by using large, low inductance ground paths between the of the transmission line to be correctly matched. This results digital devices that drive the DACO630 or DACO631 and pin in the least amount of reflection and the highest signal and 14. Therefore, a ground plane layout is recommended. display fidelity. This termination method also allows for the 4-18

19 DACOB30 = —

Data input/output 4 py Ps RED H——_p ‘To monitor's RED input. GREEN] 5——p To monitor's GREEN input.

27 RS, 75 75*

18) STANK BLUE, J——B To monitor's BLUE input. FIGURE 15. Typical Connection Showing Iper Generator and Double Termination the slower the fall time. Therefore, the fall time will be mini- that the DACs have predictable and stable output currents. matched to the interconnecting cable with a series resistor. a negative supply is available.