DAC-8841

DAC-8841 AD | Alldatasheet

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| ANALOG 8-Bit Octal, 2-Quadrant DEVICES Multiplying, CMOS TrimDAC FEATURES FUNCTIONAL BLOCK DIAGRAM Replaces 8 Potentiometers Operates From Single +5 V Supply bv a

1 MHz 2-Quadrant Multiplying Bandwidth DRESS "

No Signal Inversion Yoo? 5 Eight Individual Channels oes ® veces 3-Wire Serial Input Loo Ea D mu pvour 500 kHz Update Data Loading Rate a : +3 Volt Output Swing Dac . Midscale Preset REGISTER v4 Low 95 mW Power Dissipation 7 APPLICATIONS sg | vac ) Your H Dynamic Level Adjustment © o © o Special Waveform Generation and Modulation GND S00 PRESET Vert Programmable Gain Amplifiers ‘The DAC-8841 consumes only 95 mW from a +5 V power sup- ply. For dual polarity applications see the DAC-8840 which pro- SE ES CRON os vides full 4-quadrant-multiplying +3 V signal capability while 4 provides eight general purpose digitally controlled rating from -5 V pow i voltage adjustment devices. The TrimDAC™ capability replaces CP**#UN tom => V’ power supplics. the mechanical trimmer function in new designs. It is ideal for The DAC-8841 is available in 24-pin plastic DIP, cerdip, and ac or de gain control of up to 1 MHz bandwidth signals. SOIC-24 packages. For MIL-STD/883 applications, contact Internally the DAC-8841 contains eight voltage output CMOS ADI sales for the DAC-8541BW/883 data sheet which specifies digital-to-analog converters, each with separate reference inputs. °PeTation over ~55°C to + 125°C, Each DAC has its own DAC register which holds its output state. These DAC registers are updated from an internal serial- to-parallel shift register which is loaded from a standard 3-wire serial input digital interface. Twelve data bits make up the data word clocked into the serial input register. This data word is decoded where the first 4 bits determine the address of the DAC register to be loaded with the last 8 bits of data. A serial data output pin at the opposite end of the serial register allows sim- ple daisy-chaining in multiple DAC applications without addi- tional external decoding logic. TrimDAC is a trademark of Analog Devices, Inc. REV.A Information furnished by Analog Devices is believed to be accurate and which may result from its use. No license is granted by implication or Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577 otherwise under any patent or patent rights of Analog Devices. Telex: 924491 Cable: ANALOG NORWOODMASS

J Vo = +5 °V, All ViyX = +1.5 V, Veerl = OV, T, = —40°C to +85°C apply for DAC- ELECTRICAL CHARACTERISTICS 8841F, unless otherwise noted. STATIC ACCURACY All Specifications Apply for DACs A, B, C, D, E,F,G,H Resolution N 8 Bits Integral Nonlinearity INL | Note 1 +2 +15 | LSB Differential Nonlinearity DNL All Devices Monotonic, Note 1 +1 | LSB Half-Scale Output Voltage Vus PR = OV, Sets D = 80, 1.475 1.500 1.525] V Zero-Scale Output Voltage Vis Digital Code = 00;; 20 100 | mV Output Voltage Drift TCVys | PR = 0 V, Sets D = 80,4 10 pVPC SIGNAL INPUTS Applies to All Inputs VpyX or VagrL Input Voltage Range IVR 0 1S |v Input Resistance Rw D = 5544; Code Dependent 4 10 ka Input Capacitance Cry Code Dependent 19 30 pF REF Low Resistance RrerL | D = ABy; Code Dependent 0.3 0.75 kQ REF Low Capacitance CprerL | Code Dependent 190 250 | pF DAC OUTPUTS Applies to All Outputs VoyrX Voltage Range OVR Ry = 10k 0 3 Vv Output Current Iour | AVour < 25 mV, VayX = 1.375V, PR = 0V +5 67 mA Capacitive Load CL No Oscillation 200 | pF DYNAMIC PERFORMANCE, Applies to All DACs Multiplying Gain Bandwidth GBW | V;xX = 100 mV p-p + 1.0 Vde 1 2.5 MHz Slew Rate Measured 10% to 90% +8R | AVou7X = +3V 13° 4.0 Vips -SR AVourX = -3 V. 130 2.5 Vips Total Harmonic Distortion THD VinX = 1 V p-p+ 1.0 V de, D = FFy, f = 1 kHz, 0.01 % fyp = 80 kHz Spot Noise Voltage en f= 1kHz 0.17 pV//Hz Output Settling Time ts +1 LSB Error Band, 819 to 2555 35 6 ps Channel to Channel Crosstalk Cy Measured Between Adjacent Channels, f = 100 kHz | 60 70 dB Digital Feedthrough Q Varerl = +1.5 V, D = 0 to FFy 6 nVs POWER SUPPLIES Positive Supply Current Ipp PR=0V 19 26 «| mA Power Dissipation Poiss 95 130 | mW DC Power Supply Rejection Ratio | PSRR | PR = 0V 0.01 | %/% Power Supply Range PSR | Vpp 4.75 5.00 5.25 |V DIGITAL INPUTS Logic High Vin 2.4 Vv Logic Low Vin 08 |v Input Current IL +10 | pA Input Capacitance Cr 8 pF Input Coding Binary DIGITAL OUTPUT Logic High Vou | lou = -0.4mA v Logic Low Vor | lor = 1.6mA Vv TIMING SPECIFICATIONS Input Clock Pulse Width tow ter 80 ms Data Setup Time tps 40 ms Data Hold Time tow 20 ns CLK to SDO Propagation Delay | tpp 120 | ns DAC Register Load Pulse Width | tip 70 ns Preset Pulse Width ter 50 ns Clock Edge to Load Time tox 30 ns Load Edge to Next Clock Edge | tuocx 60 ns NOTE TNL and DNL tests do not include operation at codes 0 thru 7 due to zero-scale output voltage, For bias voltages above 100 mV on VerL, INL and DNL are maintained over all codes. Specifications subject to change without notice. -2- REV. A

WAFER TEST LIMITS: v,, = +5 v, all VX = +1.5 V, Vogel = 0V, T, = 25°C, unless otherwise noted.

1 DAC REGISTER LOAD -\\

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATIONS (T, = +25°C, unless otherwise noted) VinX toGND oo... cece eee e cece teen eee ees Vpp VourX to GND . 2.2.02. eee eee eee eee eee ee) Vip YourA [3] [22] Vin Operating Temperature Range " (Not to Scale) Thermal Resistance 6,4 Cerdip o.oo eee ce cece eee e eee eee ORCAT Your [i fs) vw PDIP 20.2.0. 2c cece eee e cece eee ee SPCW YourF [i] [*4] Yin SOIC-24 0c eee cece eee ee CW Yours [Fr [3] Your DAC-8841 PIN DESCRIPTION DICE CHARACTERISTICS (2.9718 x 4.699 mm, 13.964 sq. mm) } Maint pag 5 Output The die backside is electrically common to Vpp- 3 | VourA DAC A Output yf? 7 Hi s 4 a

4 Ves DAC B Reference Input —

5 | VwA DAC A Reference Input fe CSO. RC 1 6 | Vert DAC Input Reference Low des PRET. cpyscs - SO 7 | PR Precet Input, Active Low, All DAC Registers fog ie ye: ee | ial = ia ERD TE oe .ovy 8 | aE DAC E Reference Input 2] bi He clo tiewr it aH | 2 9 | Var DAC F Reference Input (oof bt gall meen 24 Peel ’ 10 | VourE DAC E Output aosfape. 2 2 Fur GS ete lL Soe Se 11 | Vou DAC F Output hes PE Psi] e|icee 2 ali. 12 | VourS DAC G Output 3 {oe Hes Sr drips is 23 al 4 13 | VourH DAC H Output “ een Fa dace: Gallon in 14 | VeG DAC G Reference input Cc > 4 > 15 | Val DAC H Reference Input Joo ose oon 3} 16 | LD Load DAC Register Strobe, Active High Input % 6 + 8 18 » oA that Transfers the Data Bits from the Serial Input Register into the Decoded DAC Register. See Table | 1. Voure 13. VourH 17 | cLK Serial Clock Input, Positive Edge Triggered 2. VourB 14. VinG 18 | SDO ‘Serial Data Output, Active Totem Pole Output 3. VourA 15. VinH 19 | GND Ground 4. VinB 16. LD 20 | SDI Serial Data Input 5. VinA 17, CLK 21 | Voo Positive 5 V Power Supply 6. Veer 18. SDO 22 | VyD DAC D Reference Input 7. PR 19. GND 23 | Vac DAC C Reference Input 8. VinE 20. SDI 24 | VourD DAC D Output 9. VinF 21. Vow 10. VourE 22. VinD 11. VourF 23. Vine 12.VourG | 24. VourD CAUTION ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; WARNING! —~| however, permanent damage may occur on unconnected devices subject to high energy electro- <—sS ( static fields. Unused devices must be stored in conductive foam or shunts. The protective foam Sarre Ath should be discharged to the destination socket before devices are inserted. ESD SENSITIVE DEVICE -4- REV. A

Model ‘Temperature Range | Package Option DAC8841FP —40°C to +85°C Plastic DIP DAC8841FW | —40°C to +85°C Cerdip DAC8841FS —40°C to +85°C SOIC DAC8841GBC | —25°C Dice For devices processed in total compliance to MIL-STD 883, contact your local sales office for the DAC8841BW/883 data sheet. Table I. Serial Input Decode Table Last. ———- FIRST [isomfo [om fm fo fo] m [own fue] ws | o [oan] DATA ADDRESS MSB LsB 0 0 0 0 No Operation rr er DACA o 09 4 0 DACB 0 0 1 1 DACC 0 1 oO o pAcD 0 1 0 1 DACE 0 1 1 o DAC F 0 1 1 1 DACG 1 0 0 0 DAC H 1 oo 1 No Operation 1 1 : 1 1 Né Operation MSB LSB DAC Output Volt [o» [oe [os [oe [om [oe [on [oe | Wocraiba Wi vnem + ver | o 0 e 0 0 0 0 o VREFL o o e 0 0 o o 1 1/128 (VIN — VREFL) + VREFL_ o 1 1 1 1 1 i 1 127/128 (VIN - VREFL) + VREFL 1 0 o ° o o 0 o VIN (Preset Value) 1 ° 6 0 0 o o 1 129/128 (VIN - VREFL) + VREFL. 1 1 1 1 1 1 i o (254/128 (VIN _VREFL) + VREFL 1 1 Li 1 1 1 LS 1 (255/128 (VIN - VREFL) + VREFL Table Il. Logic Control Input Truth Table spt] CLK | LD | PR | Input Shift Register Operation x L L_ | H_ | No Operation x L_ | H_ | Shift One Bit In from SDI (Pin 20), Shift One Bit* Out from SDO (Pin 18) X |X |L_ |L | ANDAC Registers = 80, x L H. | H_ | Load Serial Register Data into DACC(X) Register *Data shifted into the SDI pin appears twelve clocks later at the SDO pin. REV. A -5-

The DAC and amplifier combination shown in Figure 18 pro- pose adjustment applications. Ye oVoac where D is a decimal number between 0 and 255.

2 Your on Vpy and VagpL = 0 V are summarized in this table.

**Figure 18. DAC Plus Amplifier Combine to Produce Two- —-*0-012-V.** sen. This interface can be easily adapted to almost all microcom- tential, it saturates and appears like a $0 © resistor to ground. changed without disturbing the other devices. A serial data out- —eeween code 8,5 and code 2559 to avoid this saturation effect. 0 to 1 may not change the output voltage when Vag¢l = 0 V.

and data hold time requirements. After the twelfth clock pulse, pat . ments are in the electrical characteristic table and in the Figure to . Figure 21. Three-Wire Interface

2 Eee EN THI

2 PCRS

3 Eee

Figure 22. Gain (Vou7/Vin) and Feedthrough vs. Frequency