DAC-7134B

DAC-7134B CANDD | Alldatasheet

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Technical content

. SMlcrasecond maximum output current settling time (0.918, errors introduced by the thermal stresses of packaging. directly from the data inputs. Figure 1. DAC-7134 Simplified Block Diagram

DATEL INC O?7E D MM 2651561 0000866 6 mm DAC-7134B, DAC-7134U T-S\\-0C4.90_S GATEL ‘ABSOLUTE MAXIMUM RATINGS [pescrerion [ winmun [rveicaL] maximum [ units | POWER ‘Supply Voltage: V* toDGND -03V de to +78V de Reba Votece 438 +00 | vee Si Ci : 2. ma Analog Stoel: y Gedueing Teodor) 6 Vertu VAFM: Piny: Rpg toOGND —+/-15V do Power Dissipation . 500 mw QUT. Ree Rens 2AV dotov# Current in AGNDg, AGNDg 2. 25 mi Operating Temperature Digital Signals: __ . ne . ° +7 “e ‘ rage Temperature Aa. At, Do 10 Dg, WA, CS, PROG -03V 1oV Strage Tempo ‘ss am | FUNCTIONAL SPECIFICATIONS peiooe — Valid at +25 degrees C, +5V de power supply, and Vagr = +10V do, unless otherwise specified. The timing diagram represented in Figure 2 shows the relation- ships between the various bus interface signals. These AC charac- [oescriprion | _mumum [rveica. | maximum | units | teristics are listed in Table 1. INPUT Resolution : bits yo Levels tegen o . 08 v Logical 1 v Logic Input Currents 100 yA Referance Input Resistance 10 | Kohms Votage Rane a2 |v DETAILED DESCRIPTION Gosing The DAC-7134 consists of a 14-bit primary DAC, two PROM- tron controlled correction DAC's, input buffer registers, and microprocessor interface logic (refer back to Figure 1). The 14-bit ‘ACCURACY primary DAC is an R-2R thin film resistor ladder with N-channel Nonsinearty “® MOS SPOT current steering switches. Precise balancing of the z : : bors | ae ESE switch resistances, and all other resistances in the ladder, results t : I aos | 4S in excellent temperature stability. Nontinearity True 14-bit linearity is achieved by programming a floating poly- Temp. Gael. : 1 2 | ppmec silicon gate PROM array which controls two correction DAC cir- Gain Ener’? . coos Vaersr cuits. A 6-bit gain correction DAC (G-DAC) diverts up to 2% of the K : t oo | % FSR feedback resistor’s current to analog ground and reduces the gain t : : 006 | % FSR error to less than 1 LSB, or 0.006%. Gain enor The 5 most significant outputs of the DAC register address a Tamp. Coat. : a 8 | ppmiec 31-word PROM array that controls a 12-bit linearity correction DAC Monotonicity (C-DAO). For every combination of the primary DAC's most signiti- x] 2 : 2 ys cant bits, a different C-DAC code is selected. This corrects sum- t} ot : > | Bie mation errors (caused when more than one bit is turned on Setting Time . rr a | see. simultaneously) and voltage non-linearity in the feedback resistor, Power Supply Rejection . 10 100 pemivy ouTPUT ange oe ec ce Qutput Capacitance = —_ DAG all t's : 235 : ot ame re - Output Noise (Equiv. . 7 - K ohm 3 ER. Fe Johnson Noise) Sacco SES Feedthrough Error | “en DAG TIS4U . 250 : wep ww DAG-71348 : 500 : Wer . ‘owe town 1. Fttecat ango (FSA) i 10 vol for unipoae noes, 20 vt (2 10 vs NE ee CIs for bipolar mode. 2, Using internal feedback and reference inverting resistors. Figure 2. DAC-7196 Timing Diagram 226 DATEL, Ino, 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/F AX (508) 339-6356

Table 1. AC Characteristics Table 2. Pin Assignment and Function Description wr [a] a: | 20 _| VREF for MSB only (bipolar).

$< Eee DATEL INC O?7E D MM 26515b1 OO0086S 1 me DAC-7134B, DAC-7134U DATEL Since the PROM correction codes required are different for bipo- vor aw TSI & 0 larand unipolar operation, the DAC-7134 Is avallable in two ditfer- [a 1» | “is ent versions; the DAC-7134U, which Is corrected for unipolar ake operation, and the DAG-7134B, which Is programmed for bipotar otros te application. The feedback resistance is also different in the two ° a versions, and is switched under PROM control from "A" in the 1 ‘ow unipolar device to “2R" in the bipolar part. These teedback resis- | tors have a dummy (always ON) switch in series to compensate wey | oacriee forthe effect of the ladder switches. This greatly improves the gain H a temperature coefficient and the power supply rejection of the i device. i — nanos o——fofoasn= anor +a fenoa “ban WR Sky te DIGITAL SECTION b ft fo te, ‘Two levels of input butter registers allow loading of data from an B-bitor 16-bitdatabus. The Agand Aj pins select one of four oper- Figure 5. Unipolar Binary, Two-Quadrant Multiplying ations: Clreult 4. Load the LS buffer register with the data at inputs Dg to D7, 2. Load the MS buffer register with the data at Inputs Dg to Dis, Table 4, Code Table—Unipolar Binary Operation Load the DAC register with the contents of the MS and LS butter registers, and, 4, Load the DAC register directly from the data input pins. (See a Table). The OB ond WF pina must be tow tg allow data transfer to occur. it] te rm | When direct loading Is selected (CS, WR, Ag and Aj low), the sare Kaas registers are transparentand the data input pins control the DAC —e ‘output directly. The other modes of operation allow double buttered = 05X(VreF) loading of the DAC from an &-bit bus. ‘These input data pins are also used to program the PROM under es Le control of the PROG pin. This Is done in manufacturing, and for normal read-only use the PROG pin should be tied to V+ (+5V do). Zero Offset Adjustment Toot Load (See Figure §) le.3. Data Leading Controls 4. Connect all data inputs and WA, CS, Ag and Ay toDGND. (Con- ect pins 1 through 16, 27, and 28 to pin 22). 2. Adjust the offset zero-adjust trim-pot of op-amp A2, ifused, for [Ao Ar 6S WA | 3, Adjust the offset zero-adjust trim-pot of output op-amp At for No operation, device ‘maximum of OV £50,V de at VouT. retecectod re Gain Adjustment (Optional) a | 4. Connect all data inputs (pins 1 through 16) to V+ (pin 26} : |. Conne 1s 1 throug} to in 26). to DGND (pin 22). Note: Data [s latched on lowo-high transitions of elther WA 2, Honttor Your fore (VER + 1 LSB) reading, orcs. 8, To decrease VouT, connect a series resistor of 100 ohms or less between the reference voltage and the VRFM and VAFL terminals (pins 20 and 18). 4. Toincrease Vou, connecta serles resistor of 100 ohms or less UNIPOLAR BINARY OPERATION between OP-AMP At’s output and the Reg terminal (pin 21). Figure 5 shows a typical circult configuration for unipolar mode ‘operation using a DAC-7134U. With positive and negative VREF For applications where the output reference ground pointis estab- values, the circuits capable of two-quadrant multiplication. Table lished somewhere other than at the DAC, a circult similar to that A presents a digital input code/analog output value’ reference for shown in Figure 6 could be used. Here, op-amp A2 removes the unipolar mode operation. The Schottky diode (HP5082-2811 or slight error due to IR voltage drop between the internal analog equivalent) protects out from negative excursions which could ground node and the external ground connection. For 13-bit or damage the device, andis only necessary with certain high speed lower accuracy, omit A2 and connect AGNDF and AGNDS directly amplifiers. to ground through as low a resistance as possible. 228 DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (608) 339-3000/TLX 174388/FAX (508) 339-6356 i t i . Z

DATEL INC O?7E D MM 2651561 0000870 T mm ‘DAC-7134B, DAC-7134U TT S\\ -H -40 S OATEL Operational Amplifier Selection The op-amp requirements can be readily met using an AM-7650 chopper stabilized device. For faster settling time, DATEL’s AM-460 To maintain static accuracy, the Iour potential must be exactly ‘or AM-462 can be used with an AM-7650 providing automatic off- equal to the AGNDs potential. Thus, output amplifier selection is set null. critical, in particular low input bias current(less than 2nA), low off- set voltage drift (depending on the temperature range) and low olf- The output amplitier’s non-inverting input should be tied directly set voltage (less than 25,V) are advisable if the highest accuracy to AGNDg. Abias current compensation resistor is of limited use Isneeded. Maintaining alow input offset over a OV to 10Vdc range since the output impedance at the summing node depends on the also requires that the output amplifier has a high open loop gain code being converted in an unpredictable way. If gain adjustment (Avo. > 400k for effective input offset less than 25,V). is required, low tempoo (approximately SOppm/C) resistors ortrim- pots should be selected, The reference inverting amplifier used in the biopolar mode cir- cuit must also be selected carefully. If 14-bit accuracy is desired without adjustment, low input bias current (less than 1nA), low off- PACKAGE DIMENSIONS set voltage (less than 50,V), and high gain (greater than 400k) are recommended. If a fixed reference voltage is used, the gain The DAC-7134B and DAC-1734U differ only in the programming requirement can be relaxed. For highest accuracy (better than 13 instructions, Therefore, the same package dimensions, as shown bits), an additional op-amp may be needed to correct for IR drop in Figure 8, apply to both model numbers. The deviceis available ‘on the analog ground line (op-amp Az in Figure 6). This op-amp only in a standard 28-pin CERDIP package. should be selected for low bias current (less than 2nA) and low off- Set voltage (less than 50:V). ”ACKAGE DIMENSIONS Ali dimensions in inches (millimeters) epg neaee - | tesa Po ses eras vgvag 1 L Lassen CCT] ae Sif oman Figure 8, 28-Pin CERDIP Package Dimensions

ORDERING INFORMATION

LY = 12.Bit Linearity (0.01% FSR) = 13-Bit Linearity (0.006% FSR) L = 14-Bit Linearity (0.003% FSR) = Bipolar Version U= Unipolar Version 290 DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (608) 339-3000/TLX 174388/FAX (508) 339-6356 i i