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Technical content
Figure 1. DAC-1412 Functional Block Diagram stations, and medical/test instruments. screening are also available. well as fully screened High-Reliability -QL and /883 models.
FEATURES
n35 ns settling time to ±0.05% nOperates from single +3V to +5V supply nHumidity and stress resistant ceramic LCC package for -QL and /883 models n-40°C to +105°C and -55°C to +125°C operating temperature ranges n100% testing over temperature n)JHI3FMQSPDFTTøPX CVSOJO FOWJSPONFOUBM MPUBOE"5& traceability nLow power, 150mW (5V supply) 76mW (+3V supply) nInternal +1.2V temperature compensated bandgap reference with an external reference option nOutstanding dynamic performance nGuaranteed monotonicity over temperature n-4#%JòFSFOUJBM/PO-JOFBSJUZ .BY PWFSUFNQFSBUVSF n±2 LSB Integral Non-Linearity (Max) over temperature nTSSOP package (SE,SM models), Pb-free RoHS compliant INPUT/OUTPUT CONNECTIONS PIN FUNCTION PIN FUNCTION
1 BIT 1 (MSB) 28 CLK
2 BIT 2 27 DVDD
3 BIT 3 26 DGND
4 BIT 4 25 AGND
5 BIT 5 24 AVDD
6 BIT 6 23 NC
7 BIT 7 22 IOUTA
8 BIT 8 21 IOUTB
9 BIT 9 20 AGND
10 BIT 10 19 COMP
11 BIT 11 18 GAINADJ
12 BIT 12 17 REFI/O
13 BIT 13 16 REFSEL
14 BIT14 (LSB) 15 SHTDWN*Pinout TSSOP package
APPLICATIONS
nDefense/ aerospace applications nSignal reconstruction nHigh resolution imaging nCellular base stations n4DJFOUJöDUFTUJOTUSVNFOUT %"5&- *OD$BCPU#PVMFWBSE .BOTöFME ."64" t 5FM t XXXEBUFMDPN t FNBJMIFMQ!EBUFMDPN DAC-1412 14-Bit, 125MSPS, Low-Power D/A Converters 30 October 2015 MDA_DAC-1212.a02 Page 1 of 6
FUNCTIONAL SPECIFICATIONS 1 (Typical at +25°C, AVDD %7%% 73&' *OUFSOBM *065GVMMTDBMF N"VOMFTTPUIFSXJTFTQFDJöFE ABSOLUTE MAXIMUM RATINGS PARAMETERS LIMITS UNITS DV to DGND (Pins 27/26) +5.5 Volts AV to AGND (Pins 24/20) +5.5 Volts AGND to DGND (Pins 20/26) -0.3 to +0.3 Volts Digital Inputs (Pins 1-10, 15,28) DVDD to DVDD+0.3 Volts Reference Output Current (Pin 17) ±50µA Volts Analog Output Current (21,22) 24mA °C PHYSICAL/ENVIRONMENTAL PARAMETERS MIN. TYP . MAX. UNITS Operating Temp. Range, Case $TVóY 0 — +70 °C &TVóY –40 — +85 °C TVóY –55 — +125 °C Thermal Impedance ɁKB40*$QBDLBHF — 75 — °C/Watt ɁKB54401QBDLBHF — 135 — °C/Watt Maximum Junction Temperature +150 °C Storage Temperature Range –65 — +150 °C Maximum Lead Temperature 10s (SOIC lead tips only) +300 °C DIGITAL INPUT TEST CONDITION MIN. TYP . MAX. UNITS Resolution 14 Logic Levels Logic "1" DVDD = +5V 3.5 5 Volts Logic "1" DVDD = +3V 2.1 3 Volts Logic "0" DVDD = +5V 0 1.3 Volts Logic "0" DVDD = +3V 0 0.9 Volts Input Current HI -10 +10 µA Input Current LO -10 +10 µA SHTDWN Input Current -27 +27 µA Digital Input Capacitance 3 pf STATIC PERFORMANCE Full Scale Output Current 2 20 mA %JòFSFOUJBM/POMJOFBSJUZ -3 ±1.5 +3 LSB Integral Nonlinearity Best Fit Method -5 ±2.5 +5 LSB 0òTFU&SSPS -0.025 +0.025 % FSR 0òTFU5FNQDP 0.1 ppm FSR/°C Gain Error2 Internal Reference -10 ±0.8 +10 % FSR Gain Error2 External Reference -10 ±1.8 +10 % FSR Gain Tempco Internal Reference ±95 ppm FSR/°C Gain Tempco External Reference ±45 ppm FSR/°C Output Compliance Voltage -0.3 1.25 Volts Output Capacitance 10 pf DYNAMIC PERFORMANCE Conversion Rate 125 MHz Output Settling Time 0.05% FSR (±8 LSB) 35 ns Glitch Area 3- Ȱ 5 pV/s Output Rise Time Full Scale Step 2.4 ns Output Fall Time Full Scale Step 2.4 ns Output Noise Iout = 2mA 28 Q"ƃ)[ Output Noise Iout = 20mA 50 Q"ƃ)[ Total Harmonic Distortion5 (AVDD = +5V, DVDD = +5V) Fout = 4.0MHz, Fclk = 100MHz Up to Nyquist -71 dBc Fout = 2.0MHz, Fclk = 50MHz Up to Nyquist -76 dBc Fout = 1.0MHz, Fclk = 25MHz Up to Nyquist -77 dBc Spurious Free Dynamic Range5 (within a window, AVDD = +5V, DVDD = +5V) Fout = 20.2MHz, Fclk = 100MHz 30MHz Span 78 dBc Fout = 5.02MHz, Fclk = 100MHz 8MHz Span 97 dBc Fout = 5.02MHz, Fclk = 50MHz 8MHz Span 97 dBc Spurious Free Dynamic Range5 (up to Nyquist, AVDD = +5V, DVDD = +5V) Fout = 40.2MHz, Fclk = 125MHz Up to Nyquist 56 dBc Fout = 10.2MHz, Fclk = 125MHz Up to Nyquist 68 dBc Fout = 5.02MHz, Fclk = 125MHz, Up to Nyquist 74 dBc Fout = 40.2MHz, Fclk = 100MHz Up to Nyquist 56 dBc Fout = 20.2MHz, Fclk = 100MHz Up to Nyquist 63 dBc Fout = 5.02MHz, Fclk = 100MHz, Up to Nyquist 75 dBc Note: &YDFFEJOHTQFDJöDBUJPOTMJTUFEJO"CTPMVUF.BYJNVN3BUJOHTNBZDBVTFQFSNBOFOUEBNBHFUPUIFEFWJDF 2. ɁKBJTNFBTVSFEXJUIEFWJDFTPMEFSFEUPB1$#JOTUJMMBJS DYNAMIC PERFORMANCE ŷCont.) TEST CONDITION MIN. TYP . MAX. UNITS Fout = 2.52MHz, Fclk = 100MHz, Up to Nyquist 76 dBc Fout = 20.2MHz, Fclk = 50MHz, Up to Nyquist 66 dBc Fout = 5.02MHz, Fclk = 50MHz, Up to Nyquist 75 dBc Fout = 2.52MHz, Fclk = 50MHz, Up to Nyquist 77 dBc Fout = 1.02MHz, Fclk = 50MHz, Up to Nyquist 79 dBc Fout = 1.02MHz, Fclk = 25MHz, Up to Nyquist 80 dBc Multi-Tone Power Ratio (8 Tones, AVDD = +5V, DVDD = +5V) Fout=2MHz to 2.9MHz, Fclk = 20 MHz Tones shifted by 112kHz 77 dBc Fout=10MHz to 14.9MHz, Fclk=100 MHz Tones shifted by 112kHz 76 dBc Total Harmonic Distortion5 (AVDD = +3V, DVDD = +3V) Fout = 4.0MHz, Fclk = 100MHz Up to Nyquist -70 dBc Fout = 2.0MHz, Fclk = 50MHz Up to Nyquist -74 dBc Fout = 1.0MHz, Fclk = 25MHz Up to Nyquist -76 dBc Spurious Free Dynamic Range5 (within a window, AVDD = +3V, DVDD = +3V) Fout = 20.1MHz, Fclk = 100MHz 30MHz Span 80 dBc Fout = 5.02MHz, Fclk = 100MHz 8MHz Span 96 dBc Fout = 5.02MHz, Fclk = 50MHz 8MHz Span 95 dBc Spurious Free Dynamic Range5 (up to Nyquist, AVDD = +3V, DVDD = +3V) Fout = 40.2MHz, Fclk = 125MHz Up to Nyquist 49 dBc Fout = 10.2MHz, Fclk = 125MHz Up to Nyquist 67 dBc Fout = 5.02MHz, Fclk = 125MHz, Up to Nyquist 74 dBc Fout = 40.2MHz, Fclk = 100MHz Up to Nyquist 50 dBc Fout = 20.2MHz, Fclk = 100MHz Up to Nyquist 59 dBc Fout = 5.02MHz, Fclk = 100MHz, Up to Nyquist 73 dBc Fout = 2.52MHz, Fclk = 100MHz, Up to Nyquist 77 dBc Fout = 20.2MHz, Fclk = 50MHz, Up to Nyquist 56 dBc Fout = 5.02MHz, Fclk = 50MHz, Up to Nyquist 74 dBc Fout = 2.52MHz, Fclk = 50MHz, Up to Nyquist 76 dBc Fout = 1.02MHz, Fclk = 50MHz, Up to Nyquist 79 dBc Fout = 1.02MHz, Fclk = 25MHz, Up to Nyquist 79 dBc Multi-Tone Power Ratio (8 Tones, AVDD = +3V, DVDD = +3V) Fout=2MHz to 2.9MHz, Fclk = 20 MHz Tones shifted by 112kHz 76 dBc Fout=10MHz to 14.9MHz, Fclk=100 MHz Tones shifted by 112kHz 77 dBc REFERENCE Internal Reference Voltage 1.13 1.2 1.28 Volts Reference Voltage Drift ±58 ppm/°C Reference Current Sink/Source 50 µA Reference Input Impedance 1 .Ȱ Reference Input Mutiplying Bandwidth 1.4 MHz %"5&- *OD$BCPU#PVMFWBSE .BOTöFME ."64" t 5FM t XXXEBUFMDPN t FNBJMIFMQ!EBUFMDPN DAC-1412 14-Bit, 125MSPS, Low-Power D/A Converters 30 October 2015 MDA_DAC-1212.a02 Page 2 of 6
TIMING CHARACTERISTICS TEST CONDITION MIN. TYP . MAX. UNITS Data Setup Time7 (tsu) 1.5 ns Data Hold Time7 (thld) 1.3 ns Propagation Delay Time7 (tpd) 2.3 ns Clock (CLK) Pulse Width HI7 4 ns Clock (CLK) Pulse Width LO7 4 ns POWER REQUIREMENTS Power Supply Ranges AVDD3 2.7 5.0 5.5 Volts DVDD3 2.7 5.0 5.5 Volts Power Supply Currents AVDD4 (3V to 5V) IOUT = 20mA 24 mA AVDD4 (3V to 5V) IOUT = 2mA 6 mA DVDD4 5V 12 mA DVDD4 3V 6 mA AVDD Shut-Down Mode 3V or 5V 2.7 mA Power Dissipation 5V, IOUT = 2mA 4 80 mW 5V, IOUT = 20mA 6 150 mW 3V, IOUT = 2mA 4 32 mW 3V, IOUT = 20mA 6 76 mW Power Supply Rejection Ratio -0.2 +0.2 % FSR/V 4FF(MPTTBSZPG4QFDJöDBUJPOT (BJO&SSPSTQFDJöFEBTSBUJPPGPVUQVUDVSSFOUUPDVSSFOUUISPVHI3TFU QJO Ideal ratio = 31.969. 3. For optimal performance, when operating with supply voltages below 3V IOUT should be less than 12mA. 4. fclock = 100MHz, fout = 39MHz. 4QFDUSVN"OBMZTJTVTJOHEJòFSFOUJBMDPVQMFEUSBOTGPSNFS 6. fclock = 50MHz, fout = 2MHz 7. See Figure 4 Theory of Operation The DAC-1412 is a 14-bit, 20mA current output, CMOS, digital to analog converter. The maximum conversion rate is 125MSPS with an operating power supply range of +3V to +5V. The design topology incorporates segmented current source circuitry that reduces transient glitches. The upper bits are divided into major current sources of equivalent current. The re- maining lower bits are comprised of binary weighted current sources. In the situation where an input waveform to the converter is ramped through all the codes from 0 to 16383, when UIFMPXFSCJUDVSSFOUTPVSDFTBSFBMMPOBOESFBDIUIFöSTUVQQFSCJUUSBOTJUJPO UIFMPXFSCJUT BMMUVSOPòBOEUIFöSTUNBKPSDVSSFOUTPVSDFUVSOTPO"TUIFJOQVUDPOUJOVFTUPSBNQVQ UIF lower bits will again count up until the next major current source turns on and the lower bits UVSOPò*OFBSMJFS%"BSDIJUFDUVSFTUIFDPOWFSUFSIBEBTVCTUBOUJBMMZMBSHFSBNPVOUPGDVS SFOUUVSOJOHPOBOEPòBUNBKPSDPEFUSBOTJUJPOTTVDIBT BOE£TDBMFPGUIFGVMMTDBMF SBOHF5IFSFEVDUJPOPGDVSSFOUTXJUDIJOHBUUIFTFNBKPSUSBOTJUJPOTTJHOJöDBOUMZSFEVDFTUIF overall glitch of the converter thereby improving output settling times and transient spikes. Digital Inputs / Termination ThF%"$EJHJUBMJOQVUTBSFTQFDJöFEUP$.04MPHJDMFWFMT)PXFWFS MPXFSJOHUIFTVQQMZ voltage to 3V will reduce the logic threshold level and thereby provide TTL compatible inputs. The internal CMOS register is updated on the rising edge of the clock. To minimize SFøFDUJPOT QSPQFSUFSNJOBUJPOTIPVMECFJNQMFNFOUFE*GUIFJOQVUTBSFESJWFOGSPNȰ ESJWFSTUIFOȰUFSNJOBUJPOSFTJTUPSTTIPVMECFMPDBUFEBTDMPTFUPUIFJOQVUTBOE%(/%BT possible. Voltage Reference ThFJOUFSOBM 7WPMUBHFSFGFSFODFPGUIFEFWJDFIBTBESJGUTQFDJöDBUJPOPGQQN¡$ over the full temperature range. It is recommended that a bypass capacitor be placed as close as possible to the REFI/O pin, connected to AGND. The REFSEL (pin 16) selects whether an internal or external reference is used.. The internal reference can be selected if pin 16 is tied low (AGND). If an external reference is desired, then pin 16 should be tied high (AVDD) and the external reference driven into REFI/O, pin 17. The full scale output current of the converter is a function of both the reference voltage and the value of RSET. IOUT should be within the 2mA to 20mA range. Performance may degrade at 2mA FS Iout. If the internal reference is used, the voltage at GAINADJ (VGAINADJ) will equal approxi- mately 1.16V (pin 18). If an external reference is used, the voltage at GAINADJ will equal the external reference. IOUT Full Scale can be calculated as: IOUT FS = (VGAINADJ/RSET)x 32 If the full scale output current is set to 20mA by using the internal voltage reference (1.16V) BOEBLƆ34&5SFTJTUPS UIFOUIFJOQVUDPEJOHUPPVUQVUDVSSFOUWTJOQVUDPEJOHXJMMCF as follows: INPUT CODE / IOUT INPUT CODE (B1 - B14) IOUTA (mA) IOUTB (mA) 11 1111 1111 1111 20 0 10 0000 0000 0000 10 10 00 0000 0000 0000 0 20 Output Current IOUTA and IOUTB provide complementary output current. The sum of IOUTA and IOUTB is always equal to the full scale output current minus one LSB. For single-ended applications, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be terminated with an equivalent value resistance or connected to AGND. The voltage developed at the output must not exceed the output voltage compliance SBOHF TFFTQFDJöDBUJPOT 5IFUFSNJOBUJPOSFTJTUPSJTDIPTFOUPQSPEVDFUIFEFTJSFEPVUQVU voltage: VOUT = IOUT X RLOAD 5IFTFPVUQVUTDBOCFVTFEJOBEJòFSFOUJBMUPTJOHMFFOEFEBSSBOHFNFOUUPBDIJFWFCFUUFS harmonic rejection. The SFDR measurements in this data sheet were attained using a 1:1 transformer on the output of the DAC (see Figure 2). With the center tap grounded, the output swing of pins 21 and 22 will be biased at zero volts. It is important to note here that the negative voltage output compliance range limit is -300mV, imposing a maximum of N7QQBNQMJUVEFXJUIUIJTDPOöHVSBUJPO5IFMPBEJOHBTTIPXOJO'JHVSFXJMMSFTVMUJO a 500mV signal at the output of the transformer if the full scale output current of the DAC is set to 20mA. 7PVU Y*PVUY3FRVJWBMFOU 3FRVJWBMFOU_Ȱ Figure 2 %"5&- *OD$BCPU#PVMFWBSE .BOTöFME ."64" t 5FM t XXXEBUFMDPN t FNBJMIFMQ!EBUFMDPN DAC-1412 14-Bit, 125MSPS, Low-Power D/A Converters 30 October 2015 MDA_DAC-1212.a02 Page 3 of 6
If separate DGND and AGND planes are used, then all of the digital functions of the device and the corresponding components should be located over the DGND plane and terminated to the DGND plane. The same is true for the analog components and the AGND. If proper grounding practices are implemented the converter will function properly with a single common ground plane. Supply Bypassing To minimize power supply noise, 0.1uF capacitors should be placed as close as possible to the converter’s power supply pins, AVDD and DVDD. Be assured that capacitors are bypassed to their proper AGND or DGND planes. Humidity Susceptibility Plastic mold compounds that are used to house ICs can absorb moisture. When these devices are exposed to humidity the plastic package can undergo slight changes that can apply pressure to the internal die. Stresses placed on a precision data converters can cause changes in its QFSGPSNBODFJOUIFPSEFSPGQQN5IFGVMMZIFSNFUJDQBDLBHFPòFSFEGPSUIFo2-BOE WFSTJPOTBSFOPUBòFDUFECZIVNJEJUZ BOEBSFUIFSFGPSFNPSFTUBCMFJOFOWJSPONFOUTXIFSF humidity is a concern. Board Mounting Considerations For applications requiring the highest accuracy, attention should be paid to the board mounting location of SE and SM devices. These models use a plastic TSSOP package that could subject the die to mild stresses when the printed circuit board is cooled or heated. Placing the device in areas subject to slight twisting may cause die stresses and consequently degradation in the accuracy of the converter. It is preferred that the device be placed in the center of the PCB PSOFBSUIFFEHFPGUIFTIPSUFTUTJEFXIFSFTUSFTTFTEVFUPøFYJOHBSFSFEVDFE.PVOUJOH UIFEFWJDFJOBDVUPVUBMTPNJOJNJ[FTøFY.PVOUJOHUIFEFWJDFPOBOFYUSFNFMZUIJO1$#PS øFYQSJOUXJMMJODSFBTFUIFQPUFOUJBMGPSMPTTPGBDDVSBDZEVFUPTUSFTT5IF$-$$QBDLBHFPòFSFE for -QL and /883 devices eliminates the potential for die stress. GLOSSARY OF SPECIFICATIONS DIFFERENTIAL LINEARITY ERROR: The maximum deviation of any quantum (LSB change) in the transfer function of a data converter from its ideal size of FSR/2n. DIFFERENTIAL LINEARITY TEMPCO: 5IFDIBOHFJOEJòFSFOUJBMMJOFBSJUZFSSPSXJUIUFNQFSBUVSFGPSBEBUBDPOWFSUFS FYQSFTTFEJOQQN¡$PG'43 'VMM4DBMF3BOHF GAIN ERROR: 5IFEJòFSFODFJOTMPQFCFUXFFOUIFBDUVBMBOEJEFBMUSBOTGFSGVODUJPOTGPSBEBUBDPOWFSUFSPSPUIFSDJSDVJU*UJTFYQSFTTFEBTBQFSDFOUPGBOBMPHNBHOJUVEF GAIN TEMPCO: The change in gain (or scale factor) with temperature for a data converter or other circuit, generally expressed in ppm/°C. INTEGRAL LINEARITY ERROR:5IFNBYJNVNEFWJBUJPOPGBEBUBDPOWFSUFSUSBOTGFSGVODUJPOGSPNUIFJEFBMTUSBJHIUMJOFXJUIPòTFUBOEHBJOFSSPST[FSPFE*UJTHFOFSBMMZFYQSFTTFEJO-4#hTPSJO percent of FSR. INTERNAL REFERENCE VOLTAGE DRIFT : The maximum deviation from the measured value at room temperature as compared with the value measured at either Tmin or Tmax. OUTPUT COMPLIANCE RANGE: The allowable Maximum Voltage at the output of a D/A. OFFSET ERROR: The deviation from the ideal at analog zero output OFFSET DRIFT: The change with temperature of analog zero for a data converter operating in the bipolar mode. It is generally expressed in ppm/°C of FSR. 108&34611-:3&+&$5*0/3"5*0ŷ1433Ÿ: 5IFPVUQVUDIBOHFJOBEBUBDPOWFSUFSDBVTFECZBDIBOHFJOQPXFSTVQQMZWPMUBHF1PXFSTVQQMZTFOTJUJWJUZJTHFOFSBMMZTQFDJöFEJO7PSJO supply change. REFERENCE INPUT MULTIPLYING BANDWIDTH: The -3dB reduction in the output when applying a sinusoidal voltage to the external reference (digital inputs are set to all 1s). The frequency is increased until the amplitude of the output waveform is -3dB of its original value. SETTLING TIME: 5IFUJNFFMBQTFEGSPNUIFBQQMJDBUJPOPGBGVMMTDBMFTUFQJOQVUUPBDJSDVJUUPUIFUJNFXIFOUIFPVUQVUIBTFOUFSFEBOESFNBJOFEXJUIJOBTQFDJöFEFSSPSCBOEBSPVOEJUTöOBM WBMVF5IJTUFSNJTBOJNQPSUBOUTQFDJöDBUJPOGPSPQFSBUJPOBMBNQMJöFST BOBMPHNVMUJQMFYFST BOE%"DPOWFSUFST TOTAL HARMONIC DISTORTION:5IFSBUJPPGUIFSNTTVNPGUIFöSTUIBSNPOJDTUPUIFSNTPGUIFGVOEBNFOUBMTJHOBM VTVBMMZFYQSFTTFEJOE# GLITCH AREA: The transient appearing at the output when the input switches from one code to another. Typically the worst case is found at the MSB code transition. It is measured as the area VOEFSUIFPWFSTIPPUQPSUJPOPGUIFDVSWFBOEJTFYQSFTTFEBTB7PMU5JNFTQFDJöDBUJPO SPURIOUS FREE DYNAMIC RANGE (SFDR): The largest harmonic, spurious frequency or noise component in a signal FFT. It is expressed in db with respect to the fundamental frequency. PIN DESCRIPTIONS PIN PIN NAME DESCRIPTION 1 -14 BIT 1(MSB) through B14 (LSB) Digital Data input bits. B1 (MSB), B14 (LSB).
15 SHTDWN
Control pin to power-down the DAC. Sleep = HI, On = LO. Internal 20µA active pull-down current.
16 REFSEL
Connect to AGND to enable internal 1.2V reference. Connect to AVDD to disable internal reference.
17 REFI/O
Reference voltage output when using internal 1.2V refer- ence Input pin when supplying external reference.
18 GAINADJ
Full Scale current adjustment (gain). Use resistor to AGND to set current (see technical notes). 19 COMP External capacitor to AGND helps to reduce bandwidth.
20 AGND Analog Ground
21 IOUTB
Complimentary output current. Full scale is attained when digital inputs are at all 0's.
22 IOUTA
True output current. Full scale is attained when digital inputs are at all 1's. 23 NC Do not connect. Internal resistive connection to AGND. 24 AVDD Supply for analog circuitry (typically +3V to +5V).
25 AGND Analog Ground
26 DGND Digital Ground
27 DVDD Supply for digital circuitry (typically +3V to +5V).
28 CLK
Rising edge of clock latches data into input registers thereby updating converter. Board Assembly Considerations Precision converters provide high accuracy over temperature extremes, but some PC board assembly precautions are necessary. Changes in DC parameters can be expected with Pb-free SFøPXQSPöMFTPSXBWFTPMEFSPONVMUJMBZFS'31$CPBSET1SFDBVUJPOTTIPVMECFUBLFOUP BWPJEFYDFTTJWFIFBUPSFYUFOEFEFYQPTVSFUPIJHISFøPXPSXBWFTPMEFSUFNQFSBUVSFT UIJTNBZ reduce device initial accuracy. %"5&- *OD$BCPU#PVMFWBSE .BOTöFME ."64" t 5FM t XXXEBUFMDPN t FNBJMIFMQ!EBUFMDPN DAC-1412 14-Bit, 125MSPS, Low-Power D/A Converters 30 October 2015 MDA_DAC-1212.a02 Page 4 of 6
MECHANICAL DIMENSIONS - INCHES (mm)
ORDERING INFORMATION
0.382±.004 0.173±.004 0.252 0.026 Detail "A" GAUGE PLANE REF 0.01±.002 C H SEATING PLANE .004 C B A .002 B .047 MAX .039 0.0108° 0° -8° 0.024±.006 0.004±.002 SEE DETAIL "A" 0.035+.006 -.004 (.222) (.057) (.014)(.026) Dimension does not include mold flash, protrusions or gate burrs Mold flash, protrusions or gate burrs shall not exceed 0.006 per side Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.010 per side Dimension are measured at datum plane H Dimension and tolerancing per ASME Y14.5M-1994. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.003in total in excess of dimension at maximun material condition. Minimum space between protrusion and adjacent lead is 0.003in. Dimensions in ( ) are for reference only Conforms to JEDEC MO-153 0.006±.002 5&.13"/(&ŷ¡$Ÿ PACKAGE SHIPPING DAC-1412SE -40 to +105 28 Pin TSSOP Tube DAC-1412SM -55 to +125 28 Pin TSSOP Tube DAC-1412-QL -55 to +125 Ceramic LCC Tray DAC-1412/883 -55 to +125 Ceramic LCC Tray %"5&- *OD$BCPU#PVMFWBSE .BOTöFME ."64" t 5FM t XXXEBUFMDPN t FNBJMIFMQ!EBUFMDPN DAC-1412 14-Bit, 125MSPS, Low-Power D/A Converters 30 October 2015 MDA_DAC-1212.a02 Page 6 of 6