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DATEL, Inc. 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
FEATURES
100MHz conversion rate Low power, 650mW, typical Low glitch energy, 3.0pV-s Excellent dynamic specifi cations TTL/CMOS compatible inputs 20ns settling time Packaged in a hermetic ceramic LCC package (0.450 X 0.450 inches) Standard versions come with solder dipped leads Low cost Models available in commercial (0 to + 70°C), indus- trial (–40 to +100°C), or military (–55 to +125°C) operating temperature ranges Full 883 and LM/QL versions available If needed a ROHS version is available DAC-12100 12-Bit, 100MHz, Low-Power D/A Converters 26 Jun 2015 MDA_DAC-12100.B03 Page 1 of 7 PRODUCT OVERVIEW The DAC-12100 is a 12-bit, ultra high speed, current output digital-to-analog converter. This TTL/CMOS compatible device converts at a rate of 100MHz and features a 3.0 pV-s glitch energy and excellent frequency domain specifi cations. The DAC-12100 develops complementary current outputs of 0 to –20.48mA and can directly drive 50 Ohm loads. The excellent dynamic specifi cations (to Nyquist at fOUT=2.02MHz) include an SFDR of –85dB. Static performance includes maximum over temperature specifi cations of +/- 1.75LSB and +/-1LSB for integral and differential nonlinearity, respectively. The DAC-12100 achieves low power and high speed performance from an advanced BiCMOS process. The architecture employs an R/2R resistor network and a segmented switching current cell arrange- ment to reduce glitch. Laser trimming assures that 12-bit linearity is achieved and maintained over the transfer curve. It also incorporates a 12-bit input data register and bandgap voltage reference with a buffer amplifi er. The DAC-12100 runs on +5V and –5.2V supplies and dissipates a maximum of 800mW. It is avail- able in a 28-pin CLCC solder dipped leads package with an operating temperature range of 0 to 70°C and –55 to +125°C. If needed a RoHS version is available upon request. FUNCTIONAL BLOCK DIAGRAM Data Clock 26 12-BIT MASTER REGISTER C T R L IN UPPER 4-BIT DECODER OVERDRIVEABLE VOLTAGE REFERENCE REF OUT R SET I OUT 25 Ω DATA BUFFER LEVEL SHIFTER SLAVE REGISTER SWITCHED CURRENT CELLS REF CELL R / 2R NETWORK – C T R L O U T BIT 1 ( MSB ) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 ( LSB )
8 LSBs
24 RefGND 22 27
15,25 –5.2V ANALOG SUPPLY +5V SUPPLY 12,21 –5.2V DIGITAL SUPPLY I OUT
17 Ref In
Figure 1. Functional Block Diagram
DATEL, Inc. 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com DAC-12100 12-Bit, 100MHz, Low-Power D/A Converters 26 Jun 2015 MDA_DAC-12100.B03 Page 2 of 7 PHYSICAL/ENVIRONMENTAL PARAMETERS MIN. TYP . MAX. UNITS Operating Temperature Range DAC-12100LC 0 — +70 °C DAC-12100LE –40 — +100 °C DAC-12100LM –55 — +125 °C Storage Temperature Range –65 — +150 °C Thermal Resistance, θja 24 (°C/W) Junction Temperature — — +150 °C Package Type 28 Pin CLCC ABSOLUTE MAXIMUM RATINGS PARAMETERS LIMITS UNITS +5V Digital Supply +5.5 Volts –5.2V Digital Supply –5.5 Volts –5.2V Analog Supply –5.5 Volts Digital Input Voltages –0.5 to +5V Supply level Volts Internal Reference Output Current ±2.5 mA Voltage from CTRL IN to –5.2V (A) Supply 2.5 to 0 Volts CTRL OUT Output Current ±2.5 mA Reference Input Voltage Range –5.2V (A) Supply Level to –3.7 Volts Analog Output Current, IOUT 30 mA Lead Temperature (10 seconds) 300 °C
0 TO +70°C –55 TO +125°C
Resolution 12 — — 12 — — Bits Logic Levels Logic "1" +2.0 — — +2.0 — — Volts Logic "0" — — +0.8 — — +0.8 Volts Logic Loading "1" — — 400 — — 400 μA Logic Loading "0" — — 700 — — 700 μA Digital Input Capacitance, CIN — 3.0 15 — 3.0 15 pF TIMING CHARACTERISTICS Data setup time, tSU 3 2 — 3 2 — ns Data Hold Time, tHLD 0.5 0.25 — 0.5 0.25 — ns Propagation Delay Time, tPD — 4.5 7 — 4.5 7 ns CLOCK Pulse Width, TPW1, TPW2 3 — — 3 — — ns STATIC PERFORMANCE Integral Nonlinearity ➀ — ±0.75 ±1.0 — ±1.0 ±1.75 LSB Differential Nonlinearity — ±0.5 ±.75 — 0.5 ±1 LSB Offset Error — 20 75 — 20 75 μA Gain Error ➁ — ±1 ±10 — ±1 ±10 % DYNAMIC PERFORMANCE Conversion Rate ➂ 100 — — 100 — — MHz Output Voltage Settling Time, tSET Full Scale Step to ±1LSB — 11 13 — 12 15 ns Full Scale Step to ±0.5LSB — 20 22 — 20 22 ns Glitch Area Singlet (Peak) — 2 10 — 2 10 pV-s Doublet (Net) — 3 — — 3 — pV-s Output Slew Rate 900 1000 — 900 1000 — V/μs Output Rise Time 625 675 — 625 675 — ps Output Fall Time 425 470 — 425 470 — ps Differential Gain — 0.15 — — 0.15 — % Differential Phase — 0.07 — — 0.07 — Deg Spurious Free Dynamic Range, S FDR fCLK=10MSPS, fOUT=1.23MHz — — — — 82 77 dB fCLK=20MSPS, fOUT=5.055MHz — — — — 77 74 dB fCLK=40MSPS, fOUT=16 MHz — — — — 75 71 dB fCLK=50MSPS, fOUT= 10.1MHz — — — — 80 76 dB fCLK=80MSPS, fOUT= 5.1MHz — — — — 78 75 dB fCLK=100MSPS, fOUT=10.1MHz — — — — 79 75 dB Throughput rate 100 — — 100 — — MSPS ANALOG OUTPUT Full Scale Output Current — –20.48 — — –20.48 — mA Output Voltage Compliance ➃ –1.25 — 0 –1.25 — 0 Volts FUNCTIONAL SPECIFICATIONS
➁ Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (1.28mA typ.). Ideally the ratio should be 16. ➂ Clock frequency range is from DC to the guaranteed minimum conversion rate. ➃ Dynamic Range must be limited to a 1V swing within the compliance range. times will be effected by the shunt termination resistor. puts. Current is steered to either IOUT or IOUT in proportion to the input code. where 227 Ohms is the nominal DAC output resistance. Table 1. Input Coding Table
Figure 2. Typical Connection Diagram
© 2015 DATEL, Inc. DATEL, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technica l information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the g ranting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifi cations are subject to change without notice. www.datel.com • e-mail: help@datel.com DATEL is a registered trademark of DATEL, Inc.
11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA
ITAR and ISO 9001/14001 REGISTERED DAC-12100 12-Bit, 100MHz, Low-Power D/A Converters 26 Jun 2015 MDA_DAC-12100.B03 Page 7 of 7 INPUT/OUTPUT CONNECTIONS
ORDERING INFORMATION
MECHANICAL DIMENSIONS (inches (mm)) SYMBOL INCHES A 0.300 B 0.466 C 0.450 D 0.090 E 0.420 F 0.050 G 0.055 A BC D E F G 17 16 15 14 13 12 2 6 2 7 2 8 1234 DATEL DAC-S PIN FUNCTION PIN FUNCTION
1 D2, Digital input bit 2 28 D1 (MSB), Digital input bit 1
2 D3, Digital input bit 3 27 DGND, Digital Ground
3 D4, Digital input bit 4 26 Data Clock Pin (Rising Edge)
4 D5, Digital input bit 5 25 ANALOG VEE, Nomimally –5.2V
5 D6, Digital input bit 6 24 RSET, where RSET=(VREF OUT/ FS
IOUT) x 16
6 D7, Digital input bit 7 23 DIGITAL VCC, Nomimally +5V
7 D8, Digital input bit 8 22 REF GND, Connected closely to
pin 13 & RSET ground side 8 D9, Digital input bit 9 21 DIGITAL VEE, Nomimally –5.2 9 D10, Digital input bit 10 20 REF OUT, –1.23V typ. connected to CTRL AMP IN (Pin 19), Can be connected to an External Ref
10 D11, Digital input bit 11 19 CONTROL AMP IN, Connected
to REF OUT (Pin 20), Can be connected to an External Ref
11 D12, (LSB) Digital input bit 12 18 CONTROL AMP OUT, Usually
connected to REF IN (Pin 17)
12 DIGITAL V
EE, Nomimally –5.2V 17 REF IN, Usually connected to CTRL AMP OUT (Pin 18)
13 ANALOG GND, Connected
closely to pin 22 & RSET ground side
16 IOUT, Complementary analog
output current, Zero scale output when all “1” 14 I OUT, Analog output current, Full scale output when inputs all "1"
15 ANALOG V
EE, Analog VEE, Nominally -5.2V MODEL OPERATING TEMPERATURE RANGE PACKAGE ROHS DAC-12100LC 0 to 70°C 28-PIN CLCC No DAC-12100LC-C 0 to 70°C 28-PIN CLCC Yes DAC-12100LE –40 to 100°C 28-PIN CLCC No DAC-12100LE-C –40 to 100°C 28-PIN CLCC Yes DAC-12100LM –55 to 125°C 28-PIN CLCC No DAC-12100LM-C –55 to 125°C 28-PIN CLCC Yes DAC-12100/883 –55 to 125°C 28-PIN CLCC No DAC-12100/883-C –55 to 125°C 28-PIN CLCC Yes Solder dipping is available on Non-RoHs compliant parts. DATEL DAC-12100