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Technical content
Figure 1. DAC-1012 Functional Block Diagram stations, and medical/test instruments. screening are also available. well as fully screened High-Reliability -QL and /883 models.
FEATURES
n34 ns settling time to 1/2 LSB nOperates from single +3V to +5V supply nHumidity and stress resistant ceramic LCC package for -QL and /883 models n-40°C to +105°C and -55°C to +125°C operating tempera- ture ranges n100% testing over temperature n)JHI3FMQSPDFTTøPX CVSOJO FOWJSPONFOUBM MPUBOE"5& traceability nLow power, 165mW (5V supply) 75mW (+3V supply) nInternal +1.2V temperature compensated bandgap reference with an external reference option nOutstanding dynamic performance nGuaranteed monotonicity over temperature n-4#%JòFSFOUJBM/PO-JOFBSJUZ .BY PWFSUFNQFSBUVSF n±1 LSB Integral Non-Linearity (Max) over temperature nTSSOP package (SE,SM models), Pb-free RoHS compliant INPUT/OUTPUT CONNECTIONS PIN FUNCTION PIN FUNCTION
1 BIT 1 (MSB) 28 CLK
2 BIT 2 27 DVDD
3 BIT 3 26 DGND
4 BIT 4 25 NC
5 BIT 5 24 AVDD
6 BIT 6 23 NC
7 BIT 7 22 IOUTA
8 BIT 8 21 IOUTB
9 BIT 9 20 AGND
10 BIT 10 (LSB) 19 COMP
11 NC 18 GAINADJ
12 NC 17 REFI/O
13 NC 16 REFSEL
14 NC 15 SHTDWN*Pinout TSSOP package
APPLICATIONS
nDefense/ aerospace applications nSignal reconstruction nHigh resolution imaging nCellular base stations n4DJFOUJöDUFTUJOTUSVNFOUT %"5&- *OD$BCPU#PVMFWBSE .BOTöFME ."64" t 5FM t XXXEBUFMDPN t FNBJMIFMQ!EBUFMDPN DAC-1012 10-Bit, 125MSPS, Low-Power D/A Converters 01 Feb 2016 MDA_DAC-1012.C01.D1 Page 1 of 12
FUNCTIONAL SPECIFICATIONS 1 (Typical at +25°C, AVDD %7%% 73&' *OUFSOBM *065GVMMTDBMF N"VOMFTTPUIFSXJTFTQFDJöFE ABSOLUTE MAXIMUM RATINGS PARAMETERS LIMITS UNITS DV to DGND (Pins 27/26) +5.5 Volts AV to AGND (Pins 24/20) +5.5 Volts AGND to DGND (Pins 20/26) -0.3 to +0.3 Volts Digital Inputs (Pins 1-10, 15,28) DVDD to DVDD+0.3 Volts Reference Output Current (Pin 17) ±50µA Volts Analog Output Current (21,22) 24mA °C PHYSICAL/ENVIRONMENTAL PARAMETERS MIN. TYP . MAX. UNITS Operating Temp. Range, Case $TVóY 0 — +70 °C &TVóY –40 — +85 °C TVóY –55 — +125 °C Thermal Impedance ɁKB40*$QBDLBHF — 75 — °C/Watt ɁKB54401QBDLBHF — 135 — °C/Watt Maximum Junction Temperature +150 °C Storage Temperature Range –65 — +150 °C Maximum Lead Temperature 10s (SOIC lead tips only) +300 °C DIGITAL INPUT TEST CONDITION MIN. TYP . MAX. UNITS Resolution 10 Logic Levels Logic "1" DVDD = +5V 3.5 5 Volts Logic "1" DVDD = +3V 2.1 3 Volts Logic "0" DVDD = +5V 0 1.3 Volts Logic "0" DVDD = +3V 0 0.9 Volts Input Current HI -10 +10 µA Input Current LO -10 +10 µA SHTDWN Input Current -27 +27 µA Digital Input Capacitance 3 pf STATIC PERFORMANCE Full Scale Output Current 2 20 mA %JòFSFOUJBM/POMJOFBSJUZ -0.5 ±0.25 +0.5 LSB Integral Nonlinearity Best Fit Method -1 ±0.5 +1 LSB 0òTFU&SSPS -0.025 +0.025 % FSR 0òTFU5FNQDP 0.1 ppm FSR/°C Gain Error2 Internal Reference -10 ±0.8 +10 % FSR Gain Error2 External Reference -10 ±1.5 +10 % FSR Gain Tempco Internal Reference ±95 ppm FSR/°C Gain Tempco External Reference ±45 ppm FSR/°C Output Compliance Voltage -0.3 1.25 Volts DYNAMIC PERFORMANCE Conversion Rate 125 MHz Output Settling Time 0.1% FSR (±1/2 LSB) 34 ns Output Settling Time 0.2% FSR (±1 LSB) 22 ns Glitch Area 3- Ȱ 5 pV/s Output Rise Time Full Scale Step 1.1 ns Output Fall Time Full Scale Step 1.6 ns Output Noise Iout = 2mA 30 Q"ƃ)[ Output Noise Iout = 20mA 50 Q"ƃ)[ Total Harmonic Distortion5 Fout = 2.0MHz, Fclk = 100MHz Up to Nyquist -71 dBc Fout = 2.0MHz, Fclk = 50MHz Up to Nyquist -72 dBc Fout = 1.0MHz, Fclk = 50MHz, Up to Nyquist -76 dBc Spurious Free Dynamic Range5 (within a window) Fout = 33.1MHz, Fclk = 125MHz 10MHz Span 76 dBc Fout = 5.02MHz, Fclk = 100MHz 4MHz Span 76 dBc Fout = 10.1MHz, Fclk = 60MHz, 10MHz Span 75 dBc Fout = 5.01MHz, Fclk = 50MHz 2MHz Span 76 dBc Fout = 1.0MHz, Fclk = 50MHz 2MHz Span 78 dBc Spurious Free Dynamic Range5 (up to Nyquist) Fout = 33.1MHz, Fclk = 125MHz 55 dBc Fout = 10.1MHz, Fclk = 125MHz 65 dBc Fout = 40.2MHz, Fclk = 100MHz, 53 dBc Fout = 20.1MHz, Fclk = 100MHz 60 dBc Note: &YDFFEJOHTQFDJöDBUJPOTMJTUFEJO"CTPMVUF.BYJNVN3BUJOHTNBZDBVTFQFSNBOFOUEBNBHFUPUIFEFWJDF 2. ɁKBJTNFBTVSFEXJUIEFWJDFTPMEFSFEUPB1$#JOTUJMMBJS DYNAMIC PERFORMANCE ŷCont.) TEST CONDITION MIN. TYP . MAX. UNITS Spurious Free Dynamic Range5 (up to Nyquist) (cont.) Fout = 2.51MHz, Fclk = 100MHz 74 dBc Fout = 20.2MHz, Fclk = 60MHz 57 dBc Fout = 10.1MHz, Fclk = 60MHz 63 dBc Fout = 20.1MHz, Fclk = 50MHz 56 dBc Fout = 2.52MHz, Fclk = 50MHz 73 dBc Fout = 1.00MHz, Fclk = 50MHz 74 dBc Fout = 5.01MHz, Fclk = 50MHz 67 dBc Fout = 5.01MHz, Fclk = 25MHz 71 dBc REFERENCE Internal Reference Voltage 1.04 1.16 1.28 Volts Reference Voltage Drift ±58 ppm/°C Reference Current Sink/Source 0.1 µA Reference Input Impedance 1 .Ȱ Reference Input Mutiplying Bandwidth 1.4 MHz TIMING CHARACTERISTICS Data Setup Time7 (tsu) 3 ns Data Hold Time7 (thld) 3 ns Propagation Delay Time7 (tpd) 1 ns Clock (CLK) Pulse Width HI7 4 ns Clock (CLK) Pulse Width LO7 4 ns POWER REQUIREMENTS Power Supply Ranges AVDD3 2.7 5.0 5.5 Volts DVDD3 2.7 5.0 5.5 Volts Power Supply Currents AVDD4 (3V to 5V) IOUT = 20mA 22 30 mA AVDD4 (3V to 5V) IOUT = 2mA 5 mA DVDD4 5V 3 5 mA DVDD4 3V 1.5 mA AVDD Shut-Down Mode 3V or 5V 1.6 3 mA Power Dissipation 5V, IOUT = 2mA 4 70 mW 5V, IOUT = 20mA 6 164 mW 3V, IOUT = 2mA 4 28 mW 3V, IOUT = 20mA 6 86 mW Power Supply Rejection Ratio -0.2 +0.2 % FSR/V 4FF(MPTTBSZPG4QFDJöDBUJPOT (BJO&SSPSTQFDJöFEBTSBUJPPGPVUQVUDVSSFOUUPDVSSFOUUISPVHI3TFU QJO Ideal ratio = 31.969. 3. For optimal performance, when operating with supply voltages below 3V IOUT should be less than 12mA. 4. fclock = 100MHz, fout = 39MHz. 4QFDUSVN"OBMZTJTVTJOHEJòFSFOUJBMDPVQMFEUSBOTGPSNFS 6. fclock = 50MHz, fout = 2MHz 7. See Figure 4 %"5&- *OD$BCPU#PVMFWBSE .BOTöFME ."64" t 5FM t XXXEBUFMDPN t FNBJMIFMQ!EBUFMDPN DAC-1012 10-Bit, 125MSPS, Low-Power D/A Converters 01 Feb 2016 MDA_DAC-1012.C01.D1 Page 2 of 12
INPUT CODE (B1 - B10) IOUTA (mA) IOUTB (mA) 11 1111 1111 20 0 10 0000 0000 10 10 00 0000 0000 0 20 Output Current IOUTA and IOUTB provide complementary output current. The sum of IOUTA and IOUTB is always equal to the full scale output current minus one LSB. For single-ended applications, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be terminated with an equivalent value re- sistance or connected to AGND. The voltage developed at the output must not exceed UIFPVUQVUWPMUBHFDPNQMJBODFSBOHF TFFTQFDJöDBUJPOT 5IFUFSNJOBUJPOSFTJTUPSJT chosen to produce the desired output voltage: VOUT = IOUT X RLOAD 5IFTFPVUQVUTDBOCFVTFEJOBEJòFSFOUJBMUPTJOHMFFOEFEBSSBOHFNFOUUPBDIJFWF better harmonic rejection. The SFDR measurements in this data sheet were attained using a 1:1 transformer on the output of the DAC (see Figure 2). With the center tap grounded, the output swing of pins 21 and 22 will be biased at zero volts. It is impor- tant to note here that the negative voltage output compliance range limit is -300mV, JNQPTJOHBNBYJNVNPGN7QQBNQMJUVEFXJUIUIJTDPOöHVSBUJPO5IFMPBEJOHBT shown in Figure 2 will result in a 500mV signal at the output of the transformer if the full scale output current of the DAC is set to 20mA. 7PVU Y*PVUY3FRVJWBMFOU 3FRVJWBMFOU_Ȱ Ground Planes If separate DGND and AGND planes are used, then all of the digital functions of the device and the corresponding components should be located over the DGND plane and terminated to the DGND plane. The same is true for the analog components and the AGND. If proper grounding practices are implemented the converter will function properly with a single common ground plane. Supply Bypassing To minimize power supply noise, 0.1uF capacitors should be placed as close as possible to the converter’s power supply pins, AVDD and DVDD. Be assured that capacitors are bypassed to their proper AGND or DGND planes. Theory of Operation The DAC-1012 is a 10-bit, 20mA current output, CMOS, digital to analog converter. The maximum conversion rate is 125MSPS with an operating power supply range of +3V to +5V. The design topology incorporates segmented current source circuitry that reduces USBOTJFOUHMJUDIFT5IFöWFVQQFSCJUTBSFDPNQSJTFEPGNBKPSDVSSFOUTPVSDFTPG equivalent current. The remaining lower bits are comprised of binary weighted current sources. In the situation where an input waveform to the converter is ramped through BMMUIFDPEFTGSPNUP UIFöWFMPXFSCJUDVSSFOUTPVSDFTXPVMECFHJOUPDPVOUVQ When they reached the transition of code 31 to code 32, the lower bits would all turn PòBOEUIFöSTUNBKPSDVSSFOUTPVSDFXPVMEUVSOPO"TUIFJOQVUDPOUJOVFTUPSBNQ up, the 5 lower bits will count up another 31 codes until the next major current source UVSOTPOBOEUIFöWFMPXFSCJUTUVSOPò*OFBSMJFS%"BSDIJUFDUVSFTUIFDPOWFSUFSIBE BTVCTUBOUJBMMZMBSHFSBNPVOUPGDVSSFOUUVSOJOHPOBOEPòBUNBKPSDPEFUSBOTJUJPOT such as ¼, ½, and ¾ scale of the full scale range. The reduction of current switching at UIFTFNBKPSUSBOTJUJPOTTJHOJöDBOUMZSFEVDFTUIFPWFSBMMHMJUDIPGUIFDPOWFSUFSUIFSFCZ improving output settling times and transient spikes. Digital Inputs / Termination ThF%"$EJHJUBMJOQVUTBSFTQFDJöFEUP$.04MPHJDMFWFMT)PXFWFS MPXFSJOH the supply voltage to 3V will reduce the logic threshold level and thereby provide TTL compatible inputs. The internal CMOS register is updated on the rising edge of the DMPDL5PNJOJNJ[FSFøFDUJPOT QSPQFSUFSNJOBUJPOTIPVMECFJNQMFNFOUFE*GUIFJOQVUT BSFESJWFOGSPNȰESJWFSTUIFOȰUFSNJOBUJPOSFTJTUPSTTIPVMECFMPDBUFEBTDMPTFUP the inputs and DGND as possible. Voltage Reference ThFJOUFSOBM 7WPMUBHFSFGFSFODFPGUIFEFWJDFIBTBESJGUTQFDJöDBUJPOPG ppm/°C over the full temperature range. It is recommended that a bypass capacitor be placed as close as possible to the REFI/O pin, connected to AGND. The REFSEL (pin 16) selects whether an internal or external reference is used.. The internal reference can be selected if pin 16 is tied low (AGND). If an external reference is desired, then pin 16 should be tied high (AVDD) and the external reference driven into REFI/O, pin 17. The full scale output current of the converter is a function of both the reference voltage and the value of RSET. IOUT should be within the 2mA to 20mA range. Performance may degrade at 2mA FS Iout. If the internal reference is used, the voltage at GAINADJ (VGAINADJ) will equal approximately 1.16V (pin 18). If an external reference is used, the voltage at GAINADJ will equal the external reference. IOUT Full Scale can be calculated as: IOUT FS = (VGAINADJ/RSET)x 32 If the full scale output current is set to 20mA by using the internal voltage reference BOEBLƆ34&5SFTJTUPS UIFOUIFJOQVUDPEJOHUPPVUQVUDVSSFOUWTJOQVU coding will be as follows: Figure 2 %"5&- *OD$BCPU#PVMFWBSE .BOTöFME ."64" t 5FM t XXXEBUFMDPN t FNBJMIFMQ!EBUFMDPN DAC-1012 10-Bit, 125MSPS, Low-Power D/A Converters 01 Feb 2016 MDA_DAC-1012.C01.D1 Page 3 of 12
GLOSSARY OF SPECIFICATIONS INPUT / OUTPUT DESCRIPTIONS DIFFERENTIAL LINEARITY ERROR: The maximum deviation of any quantum (LSB change) in the transfer function of a data converter from its ideal size of FSR/2n. DIFFERENTIAL LINEARITY TEMPCO: 5IFDIBOHFJOEJòFSFOUJBMMJOFBSJUZFSSPS with temperature for a data converter, expressed in ppm/°C of FSR (Full Scale Range). GAIN ERROR: 5IFEJòFSFODFJOTMPQFCFUXFFOUIFBDUVBMBOEJEFBMUSBOTGFS functions for a data converter or other circuit. It is expressed as a percent of analog magnitude. GAIN TEMPCO: The change in gain (or scale factor) with temperature for a data converter or other circuit, generally expressed in ppm/°C. TOTAL HARMONIC DISTORTION:5IFSBUJPPGUIFSNTTVNPGUIFöSTUIBSNPOJDT to the rms of the fundamental signal, usually expressed in dB INTEGRAL LINEARITY ERROR: The maximum deviation of a data converter USBOTGFSGVODUJPOGSPNUIFJEFBMTUSBJHIUMJOFXJUIPòTFUBOEHBJOFSSPST[FSPFE*UJT generally expressed in LSB's or in percent of FSR. INTERNAL REFERENCE VOLTAGE DRIFT : The maximum deviation from the measured value at room temperature as compared with the value measured at either Tmin or Tmax. OUTPUT COMPLIANCE RANGE: The allowable Maximum Voltage at the output of a D/A. OFFSET ERROR: The deviation from the ideal at analog zero output OFFSET DRIFT: The change with temperature of analog zero for a data converter operating in the bipolar mode. It is generally expressed in ppm/°C of FSR. 108&34611-:3&+&$5*0/3"5*0ŷ1433Ÿ: The output change in a data converter caused by a change in power supply voltage. Power supply sensitivity is generally TQFDJöFEJO7PSJOTVQQMZDIBOHF REFERENCE INPUT MULTIPLYING BANDWIDTH: The -3dB reduction in the out- put when applying a sinusoidal voltage to the external reference (digital inputs are set to all 1s). The frequency is increased until the amplitude of the output waveform is -3dB of its original value. SETTLING TIME: The time elapsed from the application of a full scale step input to a DJSDVJUUPUIFUJNFXIFOUIFPVUQVUIBTFOUFSFEBOESFNBJOFEXJUIJOBTQFDJöFEFSSPS CBOEBSPVOEJUTöOBMWBMVF5IJTUFSNJTBOJNQPSUBOUTQFDJöDBUJPOGPSPQFSBUJPOBM BNQMJöFST BOBMPHNVMUJQMFYFST BOE%"DPOWFSUFST TOTAL HARMONIC DISTORTION:5IFSBUJPPGUIFSNTTVNPGUIFöSTUIBSNPOJDTUP the rms of the fundamental signal, usually expressed in dB GLITCH AREA: The transient appearing at the output when the input switches from one code to another. Typically the worst case is found at the MSB code transition. It is measured as the area under the overshoot portion of the curve and is expressed as a 7PMU5JNFTQFDJöDBUJPO SPURIOUS FREE DYNAMIC RANGE (SFDR): The largest harmonic, spurious frequency or noise component in a signal FFT. It is expressed in db with respect to the fundamental frequency. PIN DESCRIPTIONS PIN PIN NAME DESCRIPTION 1 -10 BIT 1 (MSB) through B10 (LSB) Digital Data input bits. B1 (MSB), B10 (LSB). 11-14 NC No Connection. For noise rejection may be tied to AGND. 15 SHTDWN Control pin to power-down the DAC. Sleep = HI, On = LO. Internal 20µA active pull-down current. 16 REFSEL Connect to AGND to enable internal 1.2V reference. Connect to AVDD to disable internal reference. 17 REFI/O Reference voltage output when using internal 1.2V reference Input pin when supplying external reference. 18 GAINADJ Full Scale current adjustment (gain). Use resistor to AGND to set current (see technical notes). 19 COMP External capacitor to AGND helps to reduce bandwidth.
20 AGND Analog Ground
21 IOUTB Complimentary output current. Full scale is attained when digital inputs are at all 0's. 22 IOUTA True output current. Full scale is attained when digital inputs are at all 1's. 23 NC Do not connect. Internal resistive connection to AGND. 24 AVDD Supply for analog circuitry (typically +3V to +5V). 25 NC No Connection. (12 and 14 bit devices in this series require pin 25 tied to AGND)
26 DGND Digital Ground
27 DVDD Supply for digital circuitry (typically +3V to +5V). 28 CLK Rising edge of clock latches data into input registers thereby updating converter. %"5&- *OD$BCPU#PVMFWBSE .BOTöFME ."64" t 5FM t XXXEBUFMDPN t FNBJMIFMQ!EBUFMDPN DAC-1012 10-Bit, 125MSPS, Low-Power D/A Converters 01 Feb 2016 MDA_DAC-1012.C01.D1 Page 11 of 12
7.50±0.10 17.90±0.20 10.33±0.33 Seating Plane 0.20±0.101.27 2.50±0.15 0.42±0.09 8°+0° -8° 0.27±0.05 45° 0.50±0.25 9 38 TYPICAL RECOMMENDED LAND PATTERN MECHANICAL DIMENSIONS - INCHES (mm)
ORDERING INFORMATION
5&.13"/(&ŷ¡$Ÿ PACKAGE SHIPPING DAC-1012SE -40 to +105 28 Pin TSSOP Tube DAC-1012SM -55 to +125 28 Pin TSSOP Tube DAC-1012-QL -55 to +125 Ceramic LCC Tray DAC-1012/883 -55 to +125 Ceramic LCC Tray %"5&- *OD$BCPU#PVMFWBSE .BOTöFME ."64" t 5FM t XXXEBUFMDPN t FNBJMIFMQ!EBUFMDPN DAC-1012 10-Bit, 125MSPS, Low-Power D/A Converters 01 Feb 2016 MDA_DAC-1012.C01.D1 Page 12 of 12