DA9292

DA9292 RENESAS | Alldatasheet

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High-Performance Multi-Phase DC-DC Buck Converter R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 1 © 2025 Renesas Electronics DA9292 is a high-performance Power Management IC suitable for supplying high-current rails in CPUs, GPUs, SOCs in multiple end-applications. The device is capable of supporting up to 52 A of peak current in a compact offering, with fully integrated power devices. DA9292 can be configured as either a 20 A quad- phase buck converter or two 10 A dual-phase buck converters. The input voltage range of 2.2 V to

5.5 V makes it suited for a wide range of low voltage

systems, including all single cell battery powered systems. The is optimized for a very small footprint – each phase will only need a 0.10 µH inductor. The output voltage is programmable from 0.3 V to 1.275 V in 5 mV steps. If higher output voltage is desired, the output voltage can be programmed from 0.6 V to 1.9 V in 10 mV steps. To guarantee the highest accuracy and support multiple PCB routing scenarios without loss of performance, a remote sensing capability is implemented in DA9292. The pass devices are fully integrated, so no external FETs or Schottky diodes are needed. A soft start-up is implemented, which limits the inrush current from the input node and secures a slope-controlled activation of the rail. The Dynamic Voltage Control (DVC) supports adaptive adjustment of the supply voltage dependent on the processor load, either via direct register write through the communication interface (I2C compatible) or via an external input pin (VSEL). DA9292 implements integrated over-temperature and over-current protections for increased system reliability, without the need for external sensing components. The configurable I2C slave ID selection via CONF allows multiple instances of DA9292 to be placed in the application sharing the same communication interface with different addresses. Key Features ▪ 2.2 V to 5.5 V input voltage ▪ Selectable output voltage range:

• 0.3 V to 1.275 V, 5 mV step
• 0.6 V to 1.9 V, 10 mV step ▪ 1x 20 A quad-phase converter (52 A peak output current) ▪ 2x 10 A dual-phase converters (26 A peak output current) ▪ 3 MHz nominal switching frequency ▪ ±1 % accuracy (static) ▪ Fast transient response ▪ Automatic phase shedding ▪ Integrated power switches ▪ Remote sensing at point of load ▪ I2C compatible interface ▪ Support 1.8 V level GPI input ▪ Adjustable soft-start ▪ -40 °C to +85 ºC Temperature range ▪ Package 6x9 WLCSP 2.48 mm x 3.68 mm (0.4 mm pitch) ▪ Dynamic voltage control (DVC)

Applications

▪ Game console ▪ Smartphones ▪ Tablet PCs ▪ Mobile computing

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 3

Contents

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 7 1. Terms and Definitions ATE Automated test equipment CPU Central processing unit DDR Dual data rate DVC Dynamic voltage control FET Field effect transistor FM+ Fast mode plus GBD Guaranteed by design GBQ Guaranteed by qualification GBSPC Guaranteed by statistical process characterization GPI General purpose input GPIO General purpose input/output GPU Graphics processing unit IC Integrated circuit HW Hardware Li-Ion Lithium-ion OTP One time programmable OV Over-voltage PCB Printed circuit board PRS Product requirements specification SCL Serial clock SDA Serial data SIPP Single in-line pin package SoC System on chip SW Software UV Under-voltage UVLO Under-voltage lockout

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 8 2. Pin Information

2.1 Pin Assignments

Noisy groundDigital signal Analog signalHigh power noisy signal High power signal Quiet ground 1 2 3 4 5 A B C D E F Top view FBN2 VDD1 GND2GND1 CE VDD1 LX1 FBP1 AVDD AGND LX1 LX1 EN1 PB_N VDD1 FBN1 GND1 GND2 GND2 GND1 VSEL1 LX2 VSEL2CONF TW_N FBP2 VDDIO EN2 SCL VDD2LX2 LX2 VDD2 VDD2 SDA DA9292 G H J VDD3 GND4GND3VDD3 LX3 LX3 LX3VDD3 GND3 GND4 GND4 GND3 LX4 VDD4LX4 LX4 VDD4 VDD4 INT_N Figure 3. DA9292 Pinout Diagram (Top View) Table 1. Pin Description

Description

A1, B1, C1 VDD1 PWR 5000 Power supply for phase1 A2, B2, C2 LX1 PWR 5000 LX node of phase1 A3, B3, C3 GND1 GND 5000 Power ground of phase1 A4, B4, C4 GND2 GND 5000 Power ground of phase2 A5, B5, C5 LX2 PWR 5000 LX node of phase2 A6, B6, C6 VDD2 PWR 5000 Power supply for phase2 D1 FBN1 AI 10 Negative remote sense input for CH1 D2 EN1 DI 10 Enable/disable input of CH1

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 9 Pin # Pin Name Type (Table 2) Drive (mA) D3 VSEL1 DI 10 External voltage control pin of CH1 D4 INT_N DOD 10 Interrupt output, active low D5 TW_N DOD 10 Thermal warning output, active low D6 VDDIO PWR 15 Power supply for IO E1 FBP1 AI 10 Positive remote sense input of CH1 E2 AGND GND 15 Ground of internal analog circuitry E3 SCL DI 15 I2C clock E4 SDA DIOD 15 I2C data E5 CE DI 10 Chip enable E6 FBP2 AI 10 Positive remote sense input of CH2 F1 AVDD PWR 10 Power supply for internal analog circuitry F2 PB_N DOD 10 Power-bad output, active low F3 CONF DI 10 Configuration mode select (1Ch-4Ph or 2Ch-2Ph+2Ph) F4 VSEL2 DI 10 External voltage control pin of CH2 F5 EN2 DI 10 Enable/disable input of CH2 F6 FBN2 AI 10 Negative remote sense input of CH2 G1, H1, J1 VDD3 PWR 5000 Power supply for phase3 G2, H2, J2 LX3 PWR 5000 LX node of phase3 G3, H3, J3 GND3 GND 5000 Power ground of phase3 G4, H4, J4 GND4 GND 5000 Power ground of phase4 G5, H5, J5 LX4 PWR 5000 LX node of phase4 G6, H6, J6 VDD4 PWR 5000 Power supply for phase4 Table 2. Pin Type Definition

3.1 Absolute Maximum Ratings

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Rating conditions for extended periods may affect device reliability. conditions can adversely impact product reliability and result in failures not covered by warranty. Table 3. Absolute Maximum Ratings

3.2 Electrostatic Discharge Ratings

Table 4. Electrostatic Discharge Ratings

3.3 Recommended Operating Conditions

Table 5. Recommended Operating Conditions conditions, please consult with Renesas Electronics. Note 2 VVDDIO is 3.3 V compatible as long as VIN is ≥ 3.3 V.

3.4 Thermal Specifications

Table 6. Thermal Characteristics

3.5 Buck Characteristics

Unless otherwise noted, the following is valid for -40 °C ≤ TA ≤ +85 °C, 2.2 V ≤ VIN ≤ 5.5 V, fsw = 3 MHz.

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 12 Parameter Description Conditions Min Typ Max Unit VOUT_ACC_DC Static voltage accuracy of output voltage (in PWM mode) VOUT < 1.0 V Including load and line regulation -10 10 mV VOUT_ACC_DC2 Static voltage accuracy of output voltage (in PWM mode) VOUT ≥ 1.0 V Including load and line regulation -1 1 % VTHR_OV Over-voltage threshold (no hysteresis) Delta from target VOUT 100 150 200 mV VTHR_UV_RISE Under-voltage threshold (rise) Delta from target VOUT -80 -50 -20 mV VTHR_UV_FALL Under-voltage threshold (fall) Delta from target VOUT -200 -150 -100 mV VOUT2 Output voltage Satisfy VDROPOUT2 spec 1 phase operation O =0x0) Programmable in 10 mV steps (CH<x>_VSTEP = 1) VIN ≥ 2.5 V Note 1 0.6 1.9 V VOUT2_LV Output voltage Satisfy VDROPOUT2_LV spec 1 phase operation O =0x0) Programmable in 10 mV steps (CH<x>_VSTEP = 1) Note 1 0.6 1.5 V VDROPOUT2 Dropout voltage (voltage difference between input and output) At IOUT_MAX For VOUT2 VIN ≥ 2.5 V 0.6 V VDROPOUT2_LV Dropout voltage (voltage difference between input and output) At IOUT_MAX For VOUT2_LV 0.7 V VOUT2_ACC_DC Static voltage accuracy of output voltage (in PWM mode) For VOUT2 Including load and line regulation -20 20 mV VTHR_OV2 Over-voltage threshold (no hysteresis) Delta from target VOUT2 200 300 400 mV VTHR_UV_RISE2 Under-voltage threshold (rise) Delta from target VOUT2 -160 -100 -40 mV VTHR_UV_FALL2 Under-voltage threshold (fall) Delta from target VOUT2 -400 -300 -200 mV IOUT_MAX Maximum output current Per phase 5 A IOUT_MAX_PK Maximum output current during transient Per phase 13 A

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 13 Parameter Description Conditions Min Typ Max Unit ILIM Current limit, programmable per phase Note 2 Adjustable with 2.5 A step 7.5 17.5 22.5 A ILIM_ACC Current limit accuracy Note 2 VIN ≥ 2.7 V -15 20 % ILIM_ACC2 Current limit accuracy Note 2 VIN < 2.7 V and CH<x>_ILIM = 0x0~0x4 -15 20 % ILIM_ACC3 Current limit accuracy Note 2 VIN < 2.7 V and CH<x>_ILIM = 0x5 17.5 * 85% 20 * 120% A ILIM_ACC4 Current limit accuracy Note 2 VIN < 2.7 V and CH<x>_ILIM = 0x6 17.5 * 85% 22.5 * 120% A fSW Switching frequency VIN ≥ 2.5 V 2.85 3 3.15 MHz fSW2 Switching frequency VIN < 2.5 V 2.7 3 3.3 MHz tON_MIN Minimum turn-on pulse 0 % duty is also supported 20 ns tBUCK_EN Turn-on time From EN<x> = 1 to switching start 50 μs RPD_LX Output pull-down resistance for each phase at LX node VIN = 3.7 V VLX = 0.5 V Per phase 70 100 130 Ω RON_PMOS On resistance of switching PMOS VIN = 3.7 V Per phase 19 mΩ RON_NMOS On resistance of switching NMOS VIN = 3.7 V Per phase 6 mΩ PFM Mode IQ_PFM_1PH Quiescent current in PFM VIN = 3.7 V No load AVDD current 500 μA IQ_PFM_1PH_25k Quiescent current in PFM with audible noise reduction VIN = 3.7 V No load AVDD current 500 μA Note 1 Multi-phase operation (CH<x>_MAXPH_VSEL_HI/LO =0x0) is not guaranteed. Note 2 tON > 40 ns

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 14

3.6 Performance and Supervision Characteristics

Unless otherwise noted, the following is valid for -40 °C ≤ TA ≤ +85 °C, 2.2 V ≤ VIN ≤ 5.5 V. Table 8: Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance VUVLO_RL UVLO release voltage 2.2 2.25 2.3 V VUVLO UVLO lock-out voltage 2.1 2.15 2.2 V TWARN Temperature warning threshold TEMP_WARN_SEL = 0x0 115 125 135 °C TCRIT Temperature shutdown threshold 130 140 150 °C IIN_OFF Supply current chip disable Off state TA = 27 °C CE = 0 0.2 2 μA IIN_STB Supply current stand-by mode On state TA = 27 °C CE = 1 Buck off 5 10 20 μA

3.7 Digital I/O Characteristics

Unless otherwise noted, the following is valid for -40 °C ≤ TA ≤ +85 °C, 2.2 V ≤ VIN ≤ 5.5 V Table 9: Digital I/O Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance VIH_CONF Input high voltage, CONF 0.75*A VDD AVDD V VIL_CONF Input low voltage, CONF 0.25*A VDD V tIC_EN IC enable time 1000 μs VIH Input high voltage, except CONF 0.75*V VDDIO VVDDI O V VIL Input low voltage, except CONF 0.25*V VDDIO V VOL Output low voltage SDA, INT_N, TW_N,PB_N Open drain IOUT = 1 mA 0.2*VV DDIO V IOD_LKG Output leak current SDA, INT_N, TW_N,PB_N Open drain Output is Hi-Z VOUT = VVDDIO 100 nA RPD Pull-down resistor, VSEL<x>, EN<x> 50 100 150 kΩ

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 15

3.8 Timing Characteristics

Unless otherwise noted, the following is valid for -40 °C ≤ TA ≤ +85 °C, 2.2 V ≤ VIN ≤ 5.5 V Table 10: I2C Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance tBUS Bus free time between a STOP and START condition 0.5 μs CBUS Bus line capacitive load 550 pF fSCL SCL clock frequency 0 1000 kHz tLO_SCL SCL low time 0.5 μs tHI_SCL SCL high time 0.26 μs tRISE_STD SCL and SDA rise time Requirement for input Standard mode 1000 ns tRISE_FAST SCL and SDA rise time Requirement for input Fast mode 300 ns tRISE_FPLUS SCL and SDA rise time Requirement for input Fast mode plus 120 ns tFALL_STD SCL and SDA fall time Requirement for input Standard mode 1000 ns tFALL_FAST SCL and SDA fall time Requirement for input Fast mode 20*VVD DIO/5.5 300 ns tFALL_FPLUS SCL and SDA fall time Requirement for input Fast mode plus 20*VVD DIO/5.5 120 ns tSETUP_START Start condition setup time 0.26 μs tHOLD_START Start condition hold time 0.26 μs tSETUP_STOP Stop condition setup time 0.26 μs tDATA Data valid time 0.45 μs tSETUP_DATA Data setup time 50 ns tDATA_ACK Data valid acknowledge time 0.45 μs tHOLD_DATA Data hold time 0 ns

5.1 DC-DC Buck Converter

two dual-phase buck converters when CONF is pulled up to AVDD or floating (HiZ). application sharing the same communication interface. processor status in the application. from S_CH<x>_UV and S_CH<x>_OV status bit, respectively. Table 11. An Example of Chip Configuration via CONF

1 AUTO AUTO AUTO

1 AUTO AUTO

5.1.1 Buck Enable and Disable

EN<x>_EN = 1 indicates that the functionality of external pin EN<x> to control buck enable/disable is enabled. The functionality of external pin EN<x> is disabled by writing 0 to EN<x>_EN register bit. Figure 37. CH1 Start-Up Diagram (EN1_EN = 1) The buck converter is disabled by writing 0 to CH<x>_EN or by toggling the external pin EN<x> from high to low.

Figure 38. CH1 Shutdown Diagram (EN1_EN = 1)

5.1.2 Output Voltage Selection

the external pin VSEL<x> or by changing the value of CH<x>_VSEL register bit. VSEL<x>_EN and CH<x>_VSEL in two different scenarios. Figure 39. VSEL1 Pin, VSEL1_EN and CH1_VSEL Diagram (Scenario 1) Figure 40. VSEL1 Pin, VSEL1_EN and CH1_VSEL Diagram (Scenario 2)

Figure 41. EN and VSEL Block Diagram

5.1.3 Switching Frequency

The buck switching frequency in PWM mode is selectable as an OTP option at typical 3.0 MHz . enabled by setting PFM_FREQ register bit to 1.

5.1.4 Operation Modes and Phase Selection

VSEL<x>_EN is set to 1 and external pin VSEL<x> is pulled high. External pin VSEL<x> can also be used to change buck operation mode when it is programmed to do so in OTP. depending on the load current. This improves the efficiency across the whole range of output load currents. configured by OTP and determined by external pin VSEL<x>. decrease) first before it can actually be operating in less number of active phases in full-phase mode.

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 27

5.1.5 Soft Start-Up and Shutdown

To limit in-rush current from VSYS, the buck converter performs a soft start-up after being enabled. The soft start-up and shutdown slew rates are selectable at (0.625, 1.25, 2.5, or 5.0) mV/ µs in CH<x>_SR_STARTUP and CH<x>_SR_SHUTDOWN, respectively. The buck converter follows shutdown slew-rate set in CH<x>_SR_SHUTDOWN when it is disabled by writing 0 to CH<x>_EN or by toggling the external pin EN<x> from high to low.

5.1.6 Dynamic Voltage Control

The buck converter is capable of supporting DVC transitions that occur when: ▪ the selected output voltage register is updated to a new target value ▪ the output voltage selection is changed using external pin VSEL<x> The DVC controller operates in pulse width modulation (PWM) mode with synchronous rectification. The slew rate of the DVC transition is programmable at (1.25, 2.5, 5.0, or 10.0) mV/µs in CH<x>_SR_UP for ramp-up and CH<x>_SR_DOWN for ramp-down.

5.1.7 Under-Voltage Lockout

The buck converter is shut down immediately if AVDD drops below the VUVLO threshold. In this case, output voltage ramp-down is determined by load and pull-down resistor at LX (CH<x>_DIS_PD = 0). DA9292 will re- start with the default registers setting when AVDD increases above the UVLO release voltage threshold.

5.1.8 Current Limit and Short Protection

The integrated cycle-by-cycle peak-current detection protects the power stages and external coil from excessive current. When the current limit is reached, the buck converter generates an event and an interrupt to the host processor unless the interrupt has been masked using M_CH<x>_OC in PMC_MASK_00 register. A short protection is implemented in DA9292 to protect the device from an output short condition. The buck converter stops switching immediately when short protection is triggered. Short protection is triggered when the current limit is hit more than 16 cycles consecutively and the output voltage drops below short detection threshold. Output voltage ramp-down in this case is determined by load and pull-down resistor at LX (CH<x>_DIS_PD = 0).

Figure 42. Current Limit and Short Protection

5.1.9 Thermal Protection

DA9292 is protected from internal overheating by thermal shutdown. EN<x> or writing 1 to CH<x>_EN register bit.

Figure 43. Buck Latch-Off Behavior by Temp Critical

5.2 Ports Description

CE is chip (IC) enable/disable control input. When CE = 0, all blocks except for low IQ POR are powered down. CE must never be left floating. the LX pull-down resistor (CH<x>_DIS_PD = 0), and not by the shutdown slew-rate.

5.2.2 CONF

pre-configure I2C Slave ID, CH<x>_VSTEP, EN<x>, VSEL<x>, TW_N and PB_N functionality (see Table 11).

5.2.3 EN1 and EN2

EN<x>_DEB_FALL and EN<x>_DEB_RISE at 10 µs, 100 µs, or 1 ms; it can also be disabled. In case of 1Ch-4Ph configuration, EN2 should be pulled down to AGND.

EN<x>_PD to 1. It is valid when CE is high and after initial OTP load.

5.2.4 VSEL1 and VSEL2

in full-phase mode, and operation mode of CH1 and CH2, respectively. VSEL<x> functionality is disabled when VSEL<x>_EN register bit is 0. VSEL<x>_DEB_FALL and VSEL<x>_DEB_RISE at 10 µs, 100 µs, or 1 ms; it can also be disabled. In case of 1Ch-4Ph configuration, VSEL2 should be pulled down to AGND. VSEL<x>_PD to 1. It is valid when CE is high and after initial OTP load. VSEL<x>_PIN2REG_DIS back to 0 updates CH<x>_VSEL to current VSEL<x> pin level.

5.2.5 TW_N

5.2.6 PB_N

Figure 44. PB_N at Under-Voltage and Over-Voltage Condition

Figure 45. PB_N at Short Circuit Condition

5.2.7 INT_N

Once asserted, INT_N will be kept low until the event registers are cleared. PMC_MASK_00 and PMC_MASK_01 registers.

5.3 I2C Communication

DA9292 supports I2C compatible interface based on the following signals. 400 kHz in fast-mode or 100 kHz in standard mode. protocol is the same whether operating in fast-mode plus, fast-mode or standard-mode.

5.3.1 I2C Protocol

brought high and then low. This pulse on SCL clocks the SDA bit into the receiver’s shift register. while the SCL is in the high state). Figure 46. I2C START (S) and STOP (P) following clock cycle (white blocks marked with A in Figure 47 and Figure 49). read/write bit, and the eight-bit register address followed by eight bits of data, terminated by a STOP condition. DA9292 responds to all bytes with acknowledge (A), see Figure 47. Figure 47. I2C Byte Write (SDA Line) written to consecutive addresses.

6.1 Register Map

Table 12. Register Map

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 35 Address Register 7 6 5 4 3 2 1 0 Reset 0x0014 PMC_CFG_06 I2C_TMR_EN VOUT_MAX_CFG PG_OV_MASK OC_DVC_MASK PB_CFG<1:0> PG_DVC_MASK<1:0> 0x00 0x0015 PMC_CFG_07 Reserved E_CLR_CFG PWM_FREQ PFM_FREQ SSPECTRUM TW_CFG TEMP_WARN_SEL<1:0> 0x00 0x0016 PMC_CFG_08 Reserved PB_SEL2 PB_SEL1 PB_SEL0 Reserved TW_SEL2 TW_SEL1 TW_SEL0 0x00 0x0018 PMC_CFG_0A I2C_SLAVE<6:0> I2C_FMP 0xD2 Device ID 0x0019 PMC_DEV_ID DEV_ID<7:0> 0xEA 0x001A PMC_REV_ID MRC_ID<3:0> VRC_ID<3:0> 0x10 0x001B PMC_CFG_REV CFG_REV<7:0> 0x00

6.2 Register Descriptions

The Type column in the register description tables maps to the Access shown in Table 13. Table 13. Register Access Type

6.2.1 Status and Event

Table 14. PMC_STATUS_00 (0x00) [7] RO S_CH2_OC CH2 current limit status. 0x0 CH2 output below current limit threshold. 0x1 CH2 output hitting current limit. [6] RO S_CH1_OC CH1 current limit status. 0x0 CH1 output below current limit threshold. 0x1 CH1 output hitting current limit. [5] RO S_CH2_OV CH2 output over-voltage status. 0x0 CH2 output below over-voltage threshold. 0x1 CH2 output above over-voltage threshold. [4] RO S_CH1_OV CH1 output over-voltage status. 0x0 CH1 output below over-voltage threshold. 0x1 CH1 output above over-voltage threshold. [3] RO S_CH2_UV CH2 output under-voltage status. 0x0 CH2 output above under-voltage threshold. 0x1 CH2 output below under-voltage threshold. [2] RO S_CH1_UV CH1 output under-voltage status. 0x0 CH1 output above under-voltage threshold. 0x1 CH1 output below under-voltage threshold.

0x0 CH2 output not at target voltage. 0x1 CH2 output at target voltage. 0x0 CH1 output not at target voltage. 0x1 CH1 output at target voltage. Table 15. PMC_STATUS_01 (0x01) [2] RO S_TEMP_WARN Device junction temperature at warning level. [1] RO S_TEMP_CRIT Device junction temperature at critical level. [0] RO S_VIN_UVLO Input supply voltage at low level. Table 16. PMC_EVENT_00 (0x02) [7] RWC1 E_CH2_OC CH2_OC event. Clear by write 1. [6] RWC1 E_CH1_OC CH1_OC event. Clear by write 1. [5] RWC1 E_CH2_OV CH2_OV event. Clear by write 1. [4] RWC1 E_CH1_OV CH1_OV event. Clear by write 1.

[3] RWC1 E_CH2_UV CH2_UV event. Clear by write 1. [2] RWC1 E_CH1_UV CH1_UV event. Clear by write 1. [1] RWC1 E_CH2_PG CH2_PG event. Clear by write 1. [0] RWC1 E_CH1_PG CH1_PG event. Clear by write 1. Table 17. PMC_EVENT_01 (0x03) [2] RWC1 E_TEMP_WARN TEMP_WARN event. Clear by write 1. [1] RWC1 E_TEMP_CRIT TEMP_CRIT event. Clear by write 1. [0] RWC1 E_VIN_UVLO VIN_UVLO event. Clear by write 1.

Table 18. PMC_MASK_00 (0x04) [7] RW M_CH2_OC INT_N mask for CH2_OC event. [6] RW M_CH1_OC INT_N mask for CH1_OC event. [5] RW M_CH2_OV INT_N mask for CH2_OV event. [4] RW M_CH1_OV INT_N mask for CH1_OV event. [3] RW M_CH2_UV INT_N mask for CH2_UV event. [2] RW M_CH1_UV INT_N mask for CH1_UV event. [1] RW M_CH2_PG INT_N mask for CH2_PG event. [0] RW M_CH1_PG INT_N mask for CH1_PG event.

Table 19. PMC_MASK_01 (0x05) [2] RW M_TEMP_WARN INT_N mask for TEMP_WARN event. [1] RW M_TEMP_CRIT INT_N mask for TEMP_CRIT event. [0] RW M_VIN_UVLO INT_N mask for VIN_UVLO event.

6.2.2 Control

Table 20. PMC_CTRL_00 (0x06) [2] RO CHSEL Channel operation mode. 0x1 One channel mode, up to 4 phase. [1:0] RO CONF Device configuration by CONF input pin. Table 21. PMC_CTRL_01 (0x07)

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 41 Bit Type Field Name Description Reset 0x1 10 [5] RW CH2_DIS_PD Disable pull-down of CH2 output while channel is not enabled. Value Description 0x0 Pull-down enabled when OFF. 0x1 Pull-down disabled. 0x0 [4] RW CH1_DIS_PD Disable pull-down of CH1 output while channel is not enabled. Value Description 0x0 Pull-down enabled when OFF. 0x1 Pull-down disabled. 0x0 [3] RW CH2_VSEL CH2 VOUT and operation select bit. Can be set/clear by VSEL2 input pin rise/fall. Value Description 0x0 low 0x1 high 0x0 [2] RW CH1_VSEL CH1 VOUT and operation select bit. Can be set/clear by VSEL1 input pin rise/fall. Value Description 0x0 low 0x1 high 0x0 [1] RW CH2_EN CH2 enable. Can be set/clear by EN2 pin rise/fall. Value Description 0x0 Disable 0x1 Enable 0x0 [0] RW CH1_EN CH1 enable. Can be set/clear by EN1 pin rise/fall. Value Description 0x0 Disable 0x1 Enable 0x0

Table 22. PMC_CTRL_02 (0x08) updated to VSEL2 pin level when this bit is cleared. updated to VSEL1 pin level when this bit is cleared.

Table 23. PMC_CTRL_03 (0x09) [7:6] RW CH2_MODE_VSEL_HI CH2 BUCK operation mode, when CH2_VSEL is 1. single/full-phase (phase-shedding). single, and full-phase transitions. [5:4] RW CH2_MODE_VSEL_LO CH2 BUCK operation mode, when CH2_VSEL is 0. single/full-phase (phase-shedding). single, and full-phase transitions. [3:2] RW CH1_MODE_VSEL_HI CH1 BUCK operation mode, when CH1_VSEL is 1. single/full-phase (phase-shedding). single, and full-phase transitions. [1:0] RW CH1_MODE_VSEL_LO CH1 BUCK operation mode, when CH1_VSEL is 0. single/full-phase (phase-shedding). single, and full-phase transitions.

6.2.3 Output Voltage

Table 24. PMC_VOUT_CH1_00 (0x0A) [7:0] RW CH1_VOUT_VSEL_LO CH1 output voltage setting (V), when CH1_VSEL is 0. Table 25. PMC_VOUT_CH1_01 (0x0B) [7:0] RW CH1_VOUT_VSEL_HI CH1 output voltage setting (V), when CH1_VSEL is 1.

Table 26. PMC_VOUT_CH2_00 (0x0C) [7:0] RW CH2_VOUT_VSEL_LO CH2 output voltage setting (V), when CH2_VSEL is 0. Table 27. PMC_VOUT_CH2_01 (0x0D) [7:0] RW CH2_VOUT_VSEL_HI CH2 output voltage setting (V), when CH2_VSEL is 1. Note 1 When CH1_VSTEP = 1, output voltage is doubled and limited to 1.90 V (0xBE~0xFF = 1.90 V). Note 2 When CH2_VSTEP = 1, output voltage is doubled and limited to 1.90 V (0xBE~0xFF = 1.90 V).

6.2.4 Others

Table 28. PMC_CFG_00 (0x0E) [7] RW VSEL2_PD Enable pull-down of VSEL2 pin. [6] RW VSEL1_PD Enable pull-down of VSEL1 pin. [5] RW EN2_PD Enable pull-down of EN2 pin. [4] RW EN1_PD Enable pull-down of EN1 pin. [3] RW VSEL2_EN Enable VSEL2 pin. [2] RW VSEL1_EN Enable VSEL1 pin. [1] RW EN2_EN Enable EN2 pin. [0] RW EN1_EN Enable EN1 pin.

Table 29. PMC_CFG_01 (0x0F) [6:4] RW CH2_ILIM CH2 current limit setting per phase (A). [2:0] RW CH1_ILIM CH1 current limit setting per phase (A). Table 30. PMC_CFG_02 (0x10) [7:6] RW VSEL2_DEB_FALL VSEL2 input pin debounce time on fall edge. [5:4] RW VSEL2_DEB_RISE VSEL2 input pin debounce time on rise edge. VSEL1 input pin debounce time on fall edge.

[1:0] RW VSEL1_DEB_RISE VSEL1 input pin debounce time on rise edge. Table 31. PMC_CFG_03 (0x11) [7:6] RW EN2_DEB_FALL EN2 input pin debounce time on fall edge. [5:4] RW EN2_DEB_RISE EN2 input pin debounce time on rise edge. [3:2] RW EN1_DEB_FALL EN1 input pin debounce time on fall edge. [1:0] RW EN1_DEB_RISE EN1 input pin debounce time on rise edge.

Table 32. PMC_CFG_04 (0x12) [5:4] RW CH2_SR_STARTUP CH2 soft-start output voltage slew-rate setting (mV/us). [1:0] RW CH1_SR_STARTUP CH1 soft-start output voltage slew-rate setting (mV/us). Note 1 Slew-rate is doubled when CH<x>_VSTEP = 1.

Table 33. PMC_CFG_05 (0x13) Note 1 Slew-rate is doubled when CH<x>_VSTEP = 1. Table 34. PMC_CFG_06 (0x14)

[5] RW PG_OV_MASK Exclude OV from power-good condition. [4] RW OC_DVC_MASK Over-current event mask during DVC. [3:2] RW PB_CFG Power-bad (PB) output configuration. [1:0] RW PG_DVC_MASK Power-good mask during DVC. Note 1 Counting starts after Slave ID is detected. SCL toggle is being monitored. Note 2 Invalid when VSTEP = 1. Table 35. PMC_CFG_07 (0x15) [5] RO PWM_FREQ BUCK PWM switching frequency option (MHz). [4] RW PFM_FREQ BUCK PFM switching frequency option.

Note 1 AVDD lost causes event flag clear. Table 36. PMC_CFG_08 (0x16) [6] RW PB_SEL2 PB_N pin output enable for CH2 power-bad. [5] RW PB_SEL1 PB_N pin output enable for CH1 power-bad. [4] RW PB_SEL0 PB_N pin output enable for S_TEMP_WARN. [2] RW TW_SEL2 TW_N pin output enable for CH2 power-bad. [1] RW TW_SEL1 TW_N pin output enable for CH1 power-bad.

[0] RW TW_SEL0 TW_N pin output enable for S_TEMP_WARN. Table 37. PMC_CFG_09 (0x17) [7:6] RW PB_N_FALL PB_N output pin debounce time on fall edge. [5:4] RW PB_N_RISE PB_N output pin debounce time on rise edge. [3:2] RW TW_N_FALL TW_N output pin debounce time on fall edge. [1:0] RW TW_N_RISE TW_N output pin debounce time on rise edge. Table 38. PMC_CFG_0A (0x18)

0 RW I2C_FMP I2C Fast-mode option

6.2.5 Device ID

Table 39. PMC_DEV_ID (0x19) Table 40. PMC_REV_ID (0x1A) Table 41. PMC_CFG_REV (0x1B)

7.1 Package Outlines

7.2 Moisture Sensitivity Level

MSL classification is defined in Table 42. The DA9292 package is qualified for MSL1. Table 42. MSL Classification

7.3 WLCSP Handling

tweezers are not acceptable, since contact may easily damage the silicon chip.

7.4 Soldering Information

downloaded from http://www.jedec.org.

and availability of OTP variants, please consult your Renesas local sales representative. Table 43. Ordering Information

requirements of a typical application.

9.1 Capacitor Selection

Table 44. Recommended Capacitor Types

9.2 Inductor Selection

Critical for the converter efficiency and should therefore be minimized. phase. Use of larger output inductance degrades the load transient performance of the buck converter. Table 45. Recommended Inductor Types

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 58 A ECAD Design Information This appendix contains information that supports the development of the PCB ECAD model for this device. It is intended to be used by PCB designers. A.1 Part Number Indexing Orderable Part Number Number of Pins Package Type Package Code/POD Number DA9292-xxOV2 54 WLCSP WB0054AC / PSC-5134-01 DA9292-xxOVC 54 WLCSP WB0054AC / PSC-5134-01 1. xx: OTP variant A.2 Symbol Pin Information A.2.1 54-WLCSP Pin Number Primary Pin Name Primary Electrical Type Alternate Pin Name(s) A1 VDD1 Power - A2 LX1 Power - A3 GND1 Power - A4 GND2 Power - A5 LX2 Power - A6 VDD2 Power - B1 VDD1 Power - B2 LX1 Power - B3 GND1 Power - B4 GND2 Power - B5 LX2 Power - B6 VDD2 Power - C1 VDD1 Power - C2 LX1 Power - C3 GND1 Power - C4 GND2 Power - C5 LX2 Power - C6 VDD2 Power - D1 FBN1 Input - D2 EN1 Input - D3 VSEL1 Input - D4 INT_N Output - D5 TW_N Output - D6 VDDIO Power - E1 FBP1 Input - E2 AGND Power - E3 SCL Input -

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 59 Pin Number Primary Pin Name Primary Electrical Type Alternate Pin Name(s) E4 SDA I/O - E5 CE Input - E6 FBP2 Input - F1 AVDD Power - F2 PB_N Output - F3 CONF Input - F4 VSEL2 Input - F5 EN2 Input - F6 FBN2 Input - G1 VDD3 Power - G2 LX3 Power - G3 GND3 Power - G4 GND4 Power - G5 LX4 Power - G6 VDD4 Power - H1 VDD3 Power - H2 LX3 Power - H3 GND3 Power - H4 GND4 Power - H5 LX4 Power - H6 VDD4 Power - J1 VDD3 Power - J2 LX3 Power - J3 GND3 Power - J4 GND4 Power - J5 LX4 Power - J6 VDD4 Power -

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 60 A.3 Symbol Parameters Orderable Part Number Interface Max Junction Temperature (Tj) Max Input Voltage Min Input Voltage Max Operating Temperature Min Operating Temperature Max Output Current Max Output Voltage Min Output Voltage Mounting Type Qualification RoHS Switching Frequency DA9292-xxOV2 I2C +150 °C 5.5 V 2.2 V +85 °C -40 °C 20 A 1.9 V 0.3 V SMD Industrial Compliant 3 MHz DA9292-xxOVC I2C +150 °C 5.5 V 2.2 V +85 °C -40 °C 20 A 1.9 V 0.3 V SMD Industrial Compliant 3 MHz

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 61 A.4 Footprint Design Information A.4.1 54-WLCSP IPC Footprint Type Package Code/ POD Number Number of Pins WLCSP WB0054AC / PSC-5134-01 54 Description Dimension Value (mm) Diagram Minimum body Length (vertical side) Dmin 3.66 Maximum body Length (vertical side) Dmax 3.70 Average length of grid (vertical side) D1ave 3.2 Minimum body Width (horizontal side) Emin 2.46 Maximum body Width (horizontal side) Emax 2.50 Average length of grid (horizontal side) E1ave 2 Minimum Standoff Height A1min 0.175 Maximum Height Amax 0.550 Average ball diameter Bnom 0.270 Distance between the center of any two adjacent balls (vertical side) PitchD 0.40 Distance between the center of any two adjacent balls (horizontal side) PitchE 0.40 P = Plain Grid, S = Staggered Grid GridType P F = Full Matrix, P = Perimeter, SD = Selectively Depopulated, TE = Thermally Enhanced MatrixType F Number of balls (vertical side) Rows 9 Number of balls (horizontal side) Columns 6 Maximum number of ball positions (Rows x Columns) Nmax 54 Number of actual balls present PinCount 54 Recommended Land Pattern Description Dimension Value (mm) Diagram Diameter of pad. If specified this overrides the calculated value. This can be used to specify a manufacturer's recommended pad size. X 0.221 Solder Mask Expansion. S 0.321

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 62

R16DS0518EJ0220 Rev. 2.2 Mar 24, 2025 CFR0011-120-00 Page 63 RoHS Compliance Renesas Electronics’ suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from our suppliers are available on request.

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