DA9217

Renesas Technology Corp

High-Performance Dual-Phase DC-DC Converter 10-Feb-2023

Manufacturer: Renesas Technology Corp

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DA9217 RENESAS | Alldatasheet

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Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 50

Technical content

Datasheet sections

1 Terms and Definitions
2 Pinout
3 Characteristics
3.1 Absolute Maximum Ratings
3.2 Recommended Operating Conditions
3.3 Thermal Characteristics
3.3.1 Thermal Ratings
3.3.2 Power Dissipation
3.4 ESD Characteristics
3.5 Buck Characteristics
3.6 Performance and Supervision Characteristics
3.7 Digital IO Characteristics
3.8 Timing Characteristics
3.9 Typical Performance
4 Functional Description
4.1 DC-DC Buck Converter
4.1.1 Switching Frequency
4.1.2 Operation Modes and Phase Selection
4.1.3 Output Voltage Selection
4.1.4 Soft Start-Up and Shutdown
4.1.5 Current Limit
4.1.6 Thermal Protection
4.2 Internal Circuits
4.2.1 IC_EN/Chip Enable/Disable
4.2.3 GPIO
4.3 Operating Modes
4.3.2 OFF
4.4 I2C Communication
4.4.1 I2C Protocol
5 Register Definitions
5.1 Register Map
5.1.1 System
5.1.2 Buck1
5.1.3 Serialization
6 Package Information
6.1 Package Outlines
6.2 Moisture Sensitivity Level
6.3 WLCSP Handling

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 1 of 49 © 2023 Renesas Electronics General Description DA9217 is a power management unit (PMU) suitable for supplying CPUs, GPUs, DDR memory rails in single in-line pin package (SIPP) modules, smartphones, tablets, and other handheld applications. DA9217 operates as a single-channel dual-phase buck converter, each phase requiring a small external 0.10 µH inductor. It is capable of delivering up to 6 A output current at a 0.3 V to 1.9 V output voltage range. The 2.5 V to 5.5 V input voltage range is suitable for a wide variety of low- voltage systems, including, but not limited to, all Li-Ion battery supplied applications. With remote sensing, the DA9217 guarantees the highest accuracy and supports multiple PCB routing scenarios without loss of performance. The pass devices are fully integrated, so no external FETs or Schottky diodes are needed. A programmable soft start-up can be enabled, which limits the inrush current from the input node and secures a slope-controlled rail activation. The dynamic voltage control (DVC) supports adaptive adjustment of the supply voltage dependent on the processor load, via either a direct register write using the communication interface (I2C- compatible) or with a programmable input pin. A configurable GPI allows multiple I2C address selection for multiple instances of DA9217 in the same application. DA9217 has integrated over-temperature and over-current protection for increased system reliability, without the need for external sensing components. Key Features ■ 2.5 V to 5.5 V input voltage ■ 0.3 V to 1.9 V output voltage ■ 4 MHz nominal switching frequency ■ ±1 % accuracy (static) ■ ±5 % accuracy (dynamic) ■ I2C-compatible interface (FM+) ■ Programmable GPIOs ■ Programmable soft-start ■ Voltage, current, and temperature supervision ■ -40 °C to +85 ºC ambient temperature range ■ Package: 24WLCSP 2.5 mm x 1.7 mm (0.4 mm pitch)

Applications

■ SIPP modules (SoC, DRAM) ■ Smartphones ■ Tablet PCs ■ Infotainment ■ Ultrabooks™ ■ Wi-Fi Modules ■ Game Consoles

1 Terms and Definitions

ATE Automated test equipment CPU Central processing unit DDR Dual data rate DVC Dynamic voltage control FET Field effect transistor FM+ Fast mode plus GBD Guaranteed by design GBQ Guaranteed by qualification GBSPC Guaranteed by statistical process characterization GPI General purpose input GPIO General purpose input/output GPU Graphics processing unit IC Integrated circuit HW Hardware Li-Ion Lithium-ion OTP One time programmable PCB Printed circuit board PRS Product requirements specification SCL Serial clock SDA Serial data SIPP Single in-line pin package SW Software

2 Pinout

Figure 4: DA9217 Pinout Diagram (Top View) Table 1: Pin Description Pin No. Pin Name Type (Table 2) Drive (mA) Reset State

Description

A1, B1 PVDD1 PWR 5000 Supply voltage for buck power stage, decouple with 10 µF and connect to same source as AVDD A2, B2 LX1 AIO 5000 Switch node of buck, connect a 100 nH inductor between LX1 and output capacitor A3, B3 PGND1 GND 5000 Buck power stage VSS rail A4, B4 PGND2 GND 5000 Buck power stage VSS rail A5, B5 LX2 AIO 5000 Switch node of buck, connect a 100 nH inductor between LX1 and output capacitor A6, B6 PVDD2 PWR 5000 Supply voltage for buck power stage, decouple with 10 µF and connect to same source as AVDD C1 SCL/GPIO3 DIO/DO 15 I2C clock or general purpose output C2 SDA/GPIO4 DIO/DO 15 I2C data or general purpose output C3 IC_EN AI 10 Powers up SW control interface and auxiliary circuitry (including bandgap, oscillator, and references). C4 CONF/GPIO0 AI/DIO 10 Chip configuration or general purpose I/O C5 GPIO1 DIO 10 General purpose I/O C6 GPIO2 DIO 10 General purpose I/O D1 FB1N AI 10 Buck negative node of differential voltage feedback, connect to VSS at point of load D2 FB1P AI 10 Buck positive node of differential voltage feedback, connect to VOUT1 at point of load D3 AVDD PWR 10 Supply rail for analog control circuitry, decouple with 1 µF and connect to same source as PVDD

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 7 of 49 © 2023 Renesas Electronics Pin No. Pin Name Type (Table 2) Drive (mA) Reset State D4 AGND GND 10 Analog control and auxiliary circuitry VSS D5 NC AI Not used D6 NC AI Not used Table 2: Pin Type Definition Pin Type Description Pin Type Description DI Digital input AI Analog input DO Digital output AO Analog output DIO Digital input/output AIO Analog input/output PWR Power GND Ground

3 Characteristics

3.1 Absolute Maximum Ratings

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Table 3: Absolute Maximum Ratings Parameter Description Conditions Min Max Unit TSTG Storage temperature -65 150 °C TJ Junction temperature -40 150 °C VSYS System supply voltage -0.3 6.0 V VPIN Voltage on pins -0.3 6.0 V

3.2 Recommended Operating Conditions

Table 4: Recommended Operating Conditions Parameter Description Conditions (Note 1) Min Typ Max Unit VSYS System supply voltage 2.5 5.5 V VPIN Voltage on pins -0.3 VSYS + 0.3 V TJ Junction temperature -40 125 °C TA Ambient temperature -40 85 °C Note 1 Within the specified limits, a lifetime of 10 years is guaranteed. If operating outside of these recommended conditions, please consult with Dialog Semiconductor.

3.3 Thermal Characteristics

3.3.1 Thermal Ratings

Table 5: Package Ratings Parameter Description Conditions Min Typ Max Unit JA Package thermal resistance Note 1 32.7 °C/W Note 1 Obtained from package thermal simulation, 2S2P4L board (JEDEC), influenced by PCB technology and layout.

3.3.2 Power Dissipation

Table 6: Power Dissipation Parameter Description Conditions Min Typ Max Unit PD Power dissipation Derating factor above TA = 70°C : 30.6 mW/°C (1/θJA) 2140 mW Figure 5: 24WLCSP Power Derating Curve

3.4 ESD Characteristics

Table 7: ESD Characteristics Parameter Description Conditions Min Typ Max Unit VESD_HBM ESD protection, human body model (HBM) 2 kV 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 20 30 40 50 60 70 80 90 100 110 120 130 140 PD (W) TA (°C) PD = (TJ - TA) / θJA θJA = 32.7 °C/W Still air (0 m/s) ▲TJ(WARN) = 125 °C ◆TJ(CRIT) = 140 °C

3.5 Buck Characteristics

Unless otherwise noted, the following is valid for TJ = -40 °C to +125 °C, VSYS = 2.5 V to 5.5 V. Table 8: Buck Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External Electrical Conditions VIN Input voltage VIN = VSYS 2.5 5.5 V COUT Output capacitance, per phase, including voltage and temperature coefficient -40 % 2 x 10 +30 % μF ESRCOUT Output capacitor series resistance, per phase f > 100 kHz 2 mΩ L Inductor value, per phase, including current and temperature dependence -50 % 0.1 +20 % μH DCRL Inductor DC resistance 30 50 mΩ Electrical Performance VOUT Output voltage, programmable in 10 mV steps IOUT = 0 mA to IMAX VIN = 2.5 V to 5.5 V 0.3 1.57 V VOUT_LIM Output voltage, programmable in 10 mV steps IOUT = 0 mA to IMAX VIN = 3.0 V to 5.5 V 0.3 1.9 V ILIM Current limit, programmable per phase Note 1 CHx_ILIM = 1010 -20 % 8 +20 % A VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT ≥ 1 V -1 1 % VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT < 1 V -10 10 mV VTHR_PG_RISE Power good voltage threshold for rising VOUT = VBUCK -80 -50 -20 mV VTHR_PG_DWN Power good voltage threshold for falling VOUT = VBUCK -160 -130 -100 mV VTHR_HV High VOUT voltage threshold VOUT = VBUCK 100 150 200 mV VOUT_TR_LINE Line transient response VIN = 3 V to 3.6 V IOUT = 0.5 * IMAX dt = 10 μs 15 mV fSW Switching frequency, post- trim 4 MHz

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 11 of 49 © 2023 Renesas Electronics Parameter Description Conditions Min Typ Max Unit tON_MIN Minimum turn-on pulse 0 % duty is also supported 20 ns tBUCK_EN Turn-on time CHx_EN = high 20 μs RPD Output pull-down resistance for each phase at the LX node, see BUCK<x>_PD_DIS VIN = 3.7 V VOUT = 0.5 V 100 150 200 Ω RON_PMOS On resistance of switching PMOS, per phase VIN = 3.7 V 36 mΩ RON_NMOS On resistance of switching NMOS, per phase VIN = 3.7 V 17 mΩ AUTO Mode VOUT_TR_LD_2 PH Load transient response, phase shedding enabled VOUT = 1 V IOUT = 0 A to 10 A dl/dt = 10 A/μs ±5 % PFM Mode IQ_PFM_2PH Quiescent current in PFM VIN = 3.7 V No load No switching 164 μA Note 1 tON > 40 ns

3.6 Performance and Supervision Characteristics

Table 9: Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical Performance VTHR_POR Power-on-reset threshold Threshold for AVDD falling 2.1 2.25 V VTHR_POR_HY S Power-on-reset hysteresis 200 mV TWARN Thermal warning temperature threshold 115 125 135 °C TCRIT Thermal shutdown temperature threshold 130 140 150 °C IIN_OFF Supply current OFF state TA = 27 °C IC_EN = 0 0.1 1 μA IIN_ON Supply current ON state TA = 27 °C IC_EN = 1 Buck off 5 10 20 μA

3.7 Digital IO Characteristics

Table 10: Digital I/O Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical Performance VIH_EN Input high voltage, IC enable 1.2 AVDD V VIL_EN Input low voltage, IC enable 0.4 V tIC_EN IC enable time 1000 μs VIH_GPIO_SCL _SDA Input high voltage GPIO, SCL, SDA 1.2 AVDD V VIL_GPIO_SCL_ SDA Input low voltage GPIO, SCL, SDA 0.4 V VOH_GPIO Output high voltage GPIO Push-pull mode IOUT = 1 mA 0.8*AV DD AVDD V VOL_GPIO Output low voltage GPIO Push-pull mode IOUT = 1 mA 0.2*AV DD V VOL_SDA Output low voltage SDA IOUT = 3 mA 0.24 V RPD GPIO pull-down resistor 2 10 120 kΩ RPU GPIO pull-up resistor 2 10 120 kΩ

3.8 Timing Characteristics

Table 11: I2C Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical Performance tBUS Bus free time between a STOP and START condition 0.5 μs CBUS Bus line capacitive load 150 pF fSCL SCL clock frequency 20 Note 1 1000 kHz tLO_SCL SCL low time 0.5 μs tHI_SCL SCL high time 0.26 μs tRISE SCL and SDA rise time Requirement for input 1000 ns tFALL SCL and SDA fall time Requirement for input 300 ns tSETUP_START Start condition setup time 0.26 μs tHOLD_START Start condition hold time 0.26 μs tSETUP_STOP Stop condition setup time 0.26 μs tDATA Data valid time 0.45 μs tDATA_ACK Data valid acknowledge time 0.45 μs tSETUP_DATA Data setup time 50 ns tHOLD_DATA Data hold time 0 ns Note 1 Minimum clock frequency is limited to 20 kHz if I2C_TIMEOUT is enabled

3.9 Typical Performance

output inductors (DCR = typ. 11.5 mΩ) and 4 x 10 μF output capacitors. Figure 6: Efficiency vs Load, VOUT = 0.7 V Figure 7: Efficiency vs Load, VOUT = 1.0 V

4 Functional Description

4.1 DC-DC Buck Converter

DA9217 operates as a single-channel dual-phase buck converter capable of delivering up to 6 A output current at a 0.3 V to 1.9 V output voltage range. The buck converter has two voltage registers. One defines the normal output voltage, while the other offers an alternative retention voltage. In this way, different application power modes can easily be supported. The voltage selection can be operated either via GPI or via control interface to guarantee the maximum flexibility according to the specific host processor status in the application. When a buck is enabled, its output voltage is monitored and a power good signal indicates that the buck output voltage has reached a level higher than the VTHR_PG_RISE threshold. The power good status is lost when the voltage drops below VTHR_PG_DWN or increases above VTHR_HV. The status of the power good indicator can be read back via I2C from the PG1 status bit. It can be also individually assigned to any of the GPIOs by setting the GPIO mode registers to PG1 output. The buck converter is capable of supporting DVC transitions that occur when:

the active and selected A- or B-voltage is updated to a new target value
the voltage selection is changed from the A- to B-voltage (or B- to A-voltage) using CH1_VSEL The DVC controller operates in pulse width modulation (PWM) mode with synchronous rectification. The slew rate of the DVC transition is programmed at 10 mV per 8 µs, 4 µs, 2 µs, 1 µs, or 0.5 µs in register bits CH1_SR_DVC. A pull-down resistor (typically 150 Ω) for each phase is always activated unless it is disabled by setting register bits CH1_PD_DIS to 1.

4.1.1 Switching Frequency

The buck switching frequency can be tuned using register bit OSC_TUNE. The internal 8 MHz oscillator frequency is tuned in ±160 kHz steps. This impacts the buck converter frequency in steps of 80 kHz and helps to mitigate possible disturbances to other high frequency systems in the application.

4.1.2 Operation Modes and Phase Selection

The buck converters can operate in PWM and PFM modes. The operating mode is selected using register bits CH1_<A or B>_MODE. Phase shedding automatically changes between 1- and 2-phase operation at a typical current of 2.0 A. If the automatic operation mode is selected on CH1_<A or B>_MODE, the buck converter automatically changes between synchronous PWM mode and PFM depending on the load current. This improves the efficiency across the whole range of output load currents.

4.1.3 Output Voltage Selection

The switching converter can be configured using the I2C interface. Two output voltages can be pre-configured in registers CH1_<A or B>_VOUT. The output voltage can be selected by either toggling register bit CH1_VSEL or by re-programming the selected voltage control register. Both changes will result in ramped voltage transitions. After being enabled, the buck converter will, by default, use the register settings in CH1_A_VOUT unless the output voltage selection is configured via the GPI port. Registers CH1_VMAX limit the output voltage that can be set for each of the respective buck converters. Figure 14: Buck Output Voltage Control Concept

4.1.4 Soft Start-Up and Shutdown

To limit in-rush current from VSYS, the buck converter can perform a soft-start after being enabled. The start-up behavior is a compromise between acceptable inrush current from the battery and turn- on time. Ramp times can be configured in register CH1_SR_STARTUP. Rates higher than 20 mV/µs may produce overshoot during the start-up phase, so it should be considered carefully. A ramped power down can be selected in register bits CH1_SR_SHDN. When no ramp is selected (immediate power down), the output node will be discharged only by the pull-down resistor, if enabled in register CH1_PD_DIS.

4.1.5 Current Limit

The integrated current limit protects the power stages and external coil from excessive current. The buck current limit should be configured to at least 40 % higher than the required maximum output current. When the current limit is reached, the buck converter generates an event and an interrupt to the host processor unless the interrupt has been masked using register M_OC1 in SYS_MASK_1. Register bit OC_DVC_MASK is used to mask over-current events during DVC transitions.

4.1.6 Thermal Protection

DA9217 is protected from internal overheating by thermal shutdown. There are two kinds of flags concerning thermal protection, thermal warning and thermal critical. The warning flag is asserted when TJ > TWARN and the critical flag is asserted when TJ > TCRIT. When the critical flag is asserted, Buck1 is shut down immediately. Table 12: Thermal Protection Control Registers Category Register name Description Status TEMP_WARN Asserted as long as the thermal warning threshold is reached TEMP_CRIT Asserted as long as the thermal shutdown threshold is reached IRQ event E_TEMP_WARN TEMP_WARN caused event E_TEMP_CRIT TEMP_CRIT caused event IRQ mask M_TEMP_WARN TEMP_WARN event IRQ mask M_TEMP_CRIT TEMP_CRIT event IRQ mask M_VR_HOT TEMP_WARN status IRQ mask Figure 15: Thermal Protection Operation Warning Flag TCRIT Junction Temperature TWARN Critical Flag IRQ IRQ Buck1 Shutdown Buck Enable I2C Bus Write to CH<x>_EN

4.2 Internal Circuits

4.2.1 IC_EN/Chip Enable/Disable

IC_EN is chip enable/disable control input. When IC_EN = 0, all blocks except for low IQ POR are powered-down and buck output is pulled-down. 4.2.2 nIRQ/Interrupt The interrupt triggers events. Trigger conditions and control registers for each interrupt event are listed in Table 13. Some of these events are categorized as fault events and affect device operation (for example, buck disable), see Section 4.1.6. Table 13: Interrupt List Name Polarity (Note 1) Trigger IRQ Status Register IRQ Mask Register Deglitch Period Thermal warning (event) N TJ rising above TWARN E_TEMP_WARN M_TEMP_WARN 0 s Thermal critical (event) N TJ rising above TCRIT E_TEMP_CRIT M_TEMP_CRIT 0 s Buck1 power-good (event) P Buck1 VOUT is in power-good voltage range (not under- or over-voltage) E_PG1 M_PG1 0 s Buck1 over-voltage (event) N Buck1 VOUT rising above over-voltage threshold (target voltage + 150 mV) E_OV1 M_OV1 Rise:8 µs Fall:8 µs Buck1 under- voltage (event) N Buck1 VOUT falling below under-voltage threshold (target voltage - VTH_PG) E_UV1 M_UV1 0 s Buck1 over-current (event) N Buck1 current rising above over-current threshold E_OC1 M_OC1 0 s Buck1 power-good (status) (Note 2) P Buck1 VOUT is in power-good voltage range (not under- or over-voltage) PG1 M_PG1_STAT (Note 3) 0 s Thermal warning (status) (Note 2) N TJ rising above TWARN TEMP_WARN M_VR_HOT (Note 3) 0 s GPIO0 change (event) N Detect GPIO0 change for active trigger selected GPIO0_TRIG register E_GPIO0 M_GPIO0 100 µs/ 1 ms/ 10 ms/ 100 ms GPIO1 change (event) N Detect GPIO1 change for active trigger selected GPIO1_TRIG register E_GPIO1 M_GPIO1

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 22 of 49 © 2023 Renesas Electronics Name Polarity (Note 1) Trigger IRQ Status Register IRQ Mask Register Deglitch Period GPIO2 change (event) N Detect GPIO2 change for active trigger selected GPIO2_TRIG register E_GPIO2 M_GPIO2 Note 1 Polarity at the source of the flag: P = active-high, N = active-low. General rule is: normal system state is high, and abnormal system state is low (for example, PG = high means power-good, TEMP_CRIT = low when TEMP critical state). Note 2 Interrupt outputs the status as is. I2C write is not required for interrupt clear. Note 3 OTP load value defined by CONF pin setting if CONF_EN = 1. Table 14: Interrupt Registers Except for Power Good Status Register Description E_<name> Read-only interrupt event register 0: No interrupt 1: Interrupt occurred Cleared after being written to I2C. Set until IRQ is removed. M_<name> Interrupt mask register 0: Not masked 1: Masked. No IRQ signal sent. Event register (E_<name>) is updated. Table 15: Interrupt Registers for Power Good and Temp Warning Status Register Description PG<x> Buck<x> power good status. Asserted as long as the buck<x> output voltage is in range (under-voltage threshold < buck output voltage < over-voltage threshold) 0: Not power good 1: Power good M_PG<x>_STAT Power good status interrupt mask register 0: Not masked 1: Masked. No IRQ signal sent. Power good status register (PG<x>) is updated TEMP_WARN Asserted as long as the thermal warning threshold (TWARN) is reached 0: Junction temperature is below TWARN 1: Junction temperature is above TWARN M_VR_HOT Temperature warning status (TEMP_WARN) interrupt mask register 0: Not masked 1: Masked. No IRQ signal sent. Temperature warning status register (TEMP_WARN) is updated

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 23 of 49 © 2023 Renesas Electronics Over-voltage Under-voltage PG# E_TEMP_WARN 0 VOUT IRQ Not Masked 1 0 TEMP_WARN TJ > TWARN TJ < TWARN I2C Write Clear Status Reg Event Reg Status Reg GPIO (nIRQ) Active-Low Setting (GPIO#_POL = 1) Active-High Setting (GPIO#_POL = 0) Target Voltage

GPIO is cofigured as nIRQ
M_TEMP_WARN = 0
M_PG#_STAT = 0 Condition Figure 16: Interrupt Operation Example

4.2.3 GPIO

4.2.3.1 GPIO Pin Assignment

The DA9217 provides up to five GPIO pins, three if the I2C is enabled, see Table 16. These registers are OTP programmable. When CONF_EN = 1 GPIO0 can be used for chip configuration. Any register settings for GPIO3 and GPIO4 are ignored and GPIO3 and GPIO4 function as SCL and SDA respectively if I2C_EN = 1. Note: GPIO3 and GPIO4 functions are limited only to output features if I2C_EN=0. Table 16: GPIO Pin Assignment OTP Option GPIO Pin Available GPIOs I2C_EN CONF_EN CONF/ GPIO0 GPIO1 GPIO2 SCL/ GPIO3 SDA/ GPIO4 1’b0 1’b0 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 5 1’b1 CONF GPIO1 GPIO2 GPIO3 GPIO4 4 1’b1 1’b0 GPIO0 GPIO1 GPIO2 SCL SDA 3 1’b1 CONF GPIO1 GPIO2 SCL SDA 2

4.2.3.2 GPIO Function

The GPIOs pins are configurable as the following functions in register GPIO<x>_MODE (x = 0 to 4): Note: When x = 3 and 4, GPIOs can be used as outputs only.

Buck1 enable input (EN1)
Buck1 DVC control input (DVC1)
Buck1 OTP setting reload input (RELOAD)
Buck1 power good output (PG1)
Interrupt output (nIRQ) Table 17: GPIO Function Configuration GPIO<x>_MODE[3:0] Function IO Condition 4’h0 GPIO disable HiZ 4’h1 EN1 In 4’h2 Reserved In 4’h3 Reserved In 4’h4 DVC1 In 4’h5 Reserved In 4’h6 Reserved In 4’h7 RELOAD In 4’h8 PG1 Out 4’h9 Reserved Out 4’hA Reserved Out 4’hB Reserved Out 4’hC nIRQ Out 4’hD Reserved HiZ

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 25 of 49 © 2023 Renesas Electronics GPIO<x>_MODE[3:0] Function IO Condition 4’hE Low level Out 4’hF High level Out

4.2.3.3 Chip Configuration Select (CONF)

GPIO0 functions as chip configuration select (CONF) input when CONF_EN = 1. Three different chip configurations can be selected according to the CONF pin level, whether it is HIGH, LOW, or Hi-Z. Table 18: GPIO0-Configurable Registers when CONF_EN = 1 Register Name Description IF_SLAVE_ADDR[6:0] I2C slave address CH1_A_MODE[1:0] CH1_A Operation mode select CH1_B_MODE[1:0] CH1_B Operation mode select CH1_VSEL CH1 output voltage and operation selection CH1_EN CH1 enable CH1_A_VOUT[7:0] CH1 output voltage setting A CH1_B_VOUT[7:0] CH1 output voltage setting B M_PG1_STAT IRQ mask setting for CH1 power good status M_VR_HOT IRQ mask setting for temp warning status GPIO1_MODE[3:0] GPIO1 mode setting GPIO2_MODE[3:0] GPIO2 mode setting GPIO1_OBUF GPIO1 output buffer select GPIO2_OBUF GPIO2 output buffer select GPIO1_TRIG[1:0] GPIO1 input trigger select GPIO1_POL GPIO1 polarity select GPIO1_PUPD GPIO1 pull-up/pull-down enable GPIO1_DEB[1:0] GPIO1 input debounce time setting GPIO1_DEB_RISE GPIO1 input debounce rising edge enable GPIO1_DEB_FALL GPIO1 input debounce falling edge enable GPIO2_TRIG[1:0] GPIO2 input trigger select GPIO2_POL GPIO2 polarity select GPIO2_PUPD GPIO2 pull-up/pull-down enable GPIO2_DEB[1:0] GPIO2 input debounce time setting GPIO2_DEB_RISE GPIO2 input debounce rising edge enable GPIO2_DEB_FALL GPIO2 input debounce falling edge enable

4.2.3.4 OTP Reload (RELOAD)

Buck settings listed in Table 19 are reloaded from CONF registers by triggering GPIO configured as RELOAD input. The OTP reload happens at the same time for Buck1 settings. During reloading, Buck1 keeps operating as configured without shut-down.

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 26 of 49 © 2023 Renesas Electronics Table 19: OTP Reload Registers Register Name Description CH#_VSEL CH# output voltage and operation selection. 0: A, 1: B CH#_A_VOUT[7:0] CH# output voltage setting A : CH#_A_VOUT * 10 mV Setting under 0.3V is clamped to 0.3V, and setting over 1.9V is clamped to 1.9 V CH#_B_VOUT[7:0] CH# output voltage setting B : CH#_A_VOUT * 10 mV Setting under 0.3 V is clamped to 0.3 V, and setting over 1.9V is clamped to 1.9 V CH#_A_MODE[1:0] Operation mode selection 0: Force PFM 1: Force PWM. full phase 2: Force PWM with phase shedding 3: Auto mode CH#_B_MODE[1:0] Operation mode selection 0: Force PFM 1: Force PWM. full phase 2: Force PWM with phase shedding 3: Auto mode

4.3 Operating Modes

4.3.1 ON DA9217 is ON when the IC_EN port is higher than VIH_EN and the supply voltage is higher than VTHR_POR. Once enabled, the host processor can start communicating with DA9217 using the control interface, after the tIC_EN delay.

4.3.2 OFF

DA9217 is OFF when the IC_EN port is lower than VIL_EN. In OFF, the bucks are always disabled and LX nodes are pulled down by (typically 150 Ω) internal pull-down resistors.

4.4 I2C Communication

All features of DA9217 can be controlled with the I2C interface which is enabled or disabled in register I2C_EN. I2C_EN Description

0 I2C disable: SCL/GPIO3 and SDA/GPIO4 pins can be used as GPIO

1 I2C enable: SCL/GPIO3 and SDA/GPIO4 pins are used as I2C clock input and I2C data

input/output. GPIO3 functions as the I2C clock and GPIO4 carries all the power manager bidirectional I2C data. The I2C interface is open-drain supporting multiple devices on a single line. The bus lines have to be pulled high by external pull-up resistors (2 kΩ to 20 kΩ). The standard frequency of the I2C bus is 1 MHz in fast-mode plus (FM+), 400 kHz in fast-mode, or 100 kHz in standard mode.

4.4.1 I2C Protocol

All data is transmitted across the I2C bus in eight-bit groups. To send a bit, the SDA line is driven towards the intended state while the SCL is low (a low SDA indicates a zero bit). Once the SDA has settled, the SCL line is brought high and then low. This pulse on SCL clocks the SDA bit into the receiver’s shift register.

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 28 of 49 © 2023 Renesas Electronics When the host reads data from a register it first has to write to DA9217 with the target register address and then read from DA9217 with a repeated START, or alternatively a second START, condition. After receiving the data, the host sends no acknowledge (A*) and terminates the transmission with a STOP condition, see Figure 19. S SLAVEadr W A REGadr A SLAVEadr A S = START condition A = Acknowledge (low) Sr = Repeated START condition A* = No Acknowledge P = STOP condition W = Write (low) R = Read (high) Master to Slave 7-bits 1-bit 8-bits 7-bits DATA A* Sr R 1-bit 8-bits SLAVEadr A 7-bits DATA P S R 1-bit 8-bits P Slave to Master S SLAVEadr W A REGadr P 7-bits 1-bit 8-bits A Figure 19: I2C Byte Read (SDA Line) Examples

5 Register Definitions

5.1 Register Map

Table 20: Register Map Addr Register 7 6 5 4 3 2 1 0 System Module System 0x0001 SYS_STATUS_0 Reserved Reserved Reserved Reserved Reserved Reserved TEMP_CRIT TEMP_W ARN 0x0002 SYS_STATUS_1 Reserved Reserved Reserved Reserved PG1 OV1 UV1 OC1 0x0003 SYS_STATUS_2 Reserved Reserved Reserved Reserved Reserved GPIO2 GPIO1 GPIO0 0x0004 SYS_EVENT_0 Reserved Reserved Reserved Reserved Reserved Reserved E_TEMP_C RIT E_TEMP_ WARN 0x0005 SYS_EVENT_1 Reserved Reserved Reserved Reserved E_PG1 E_OV1 E_UV1 E_OC1 0x0006 SYS_EVENT_2 Reserved Reserved Reserved Reserved Reserved E_GPIO2 E_GPIO1 E_GPIO0 0x0007 SYS_MASK_0 Reserved Reserved Reserved Reserved Reserved Reserved M_TEMP_C RIT M_TEMP_ WARN 0x0008 SYS_MASK_1 Reserved Reserved Reserved Reserved M_PG1 M_OV1 M_UV1 M_OC1 0x0009 SYS_MASK_2 Reserved Reserved Reserved Reserved Reserved M_GPIO2 M_GPIO1 M_GPIO0 0x000A SYS_MASK_3 Reserved Reserved Reserved Reserved M_VR_HO T Reserved Reserved M_PG1_S TAT 0x000B SYS_CONFIG_0 Reserved Reserved 0x000C SYS_CONFIG_1 Reserved Reserved 0x000D SYS_CONFIG_2 Reserved OC_LATCHOFF<1:0> OC_DVC_ MASK PG_DVC_MASK<1:0> Reserved Reserved 0x000E SYS_CONFIG_3 Reserved OSC_TUNE<2:0> Reserved Reserved I2C_TIMEO UT Reserved 0x0010 SYS_GPIO0_0 Reserved Reserved Reserved GPIO0_MODE<3:0> GPIO0_O BUF 0x0011 SYS_GPIO0_1 GPIO0_D EB_FALL GPIO0_D EB_RISE GPIO0_DEB<1:0> GPIO0_P UPD GPIO0_POL GPIO0_TRIG<1:0> 0x0012 SYS_GPIO1_0 Reserved Reserved Reserved GPIO1_MODE<3:0> GPIO1_O BUF 0x0013 SYS_GPIO1_1 GPIO1_D EB_FALL GPIO1_D EB_RISE GPIO1_DEB<1:0> GPIO1_P UPD GPIO1_POL GPIO1_TRIG<1:0> 0x0014 SYS_GPIO2_0 Reserved Reserved Reserved GPIO2_MODE<3:0> GPIO2_O BUF 0x0015 SYS_GPIO2_1 GPIO2_D EB_FALL GPIO2_D EB_RISE GPIO2_DEB<1:0> GPIO2_P UPD GPIO2_POL GPIO2_TRIG<1:0>

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 30 of 49 © 2023 Renesas Electronics Addr Register 7 6 5 4 3 2 1 0 Buck Control Buck1 0x0020 BUCK_BUCK1_0 Reserved CH1_SR_DVC_DWN<2:0> CH1_SR_DVC_UP<2:0> CH1_EN 0x0021 BUCK_BUCK1_1 Reserved CH1_SR_SHDN<2:0> CH1_SR_STARTUP<2:0> CH1_PD_ DIS 0x0022 BUCK_BUCK1_2 Reserved Reserved Reserved Reserved CH1_ILIM<3:0> 0x0023 BUCK_BUCK1_3 CH1_VMAX<7:0> 0x0024 BUCK_BUCK1_4 Reserved Reserved Reserved CH1_VSE L 0x0025 BUCK_BUCK1_5 CH1_A_VOUT<7:0> 0x0026 BUCK_BUCK1_6 CH1_B_VOUT<7:0> 0x0027 BUCK_BUCK1_7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Serialization 0x0048 OTP_DEVICE_ID DEV_ID<7:0> 0x0049 OTP_VARIANT_ID MRC<3:0> VRC<3:0> 0x004A OTP_CUSTOMER_ID CUST_ID<7:0> 0x004B OTP_CONFIG_ID CONFIG_REV<7:0>

5.1.1 System

Table 21: SYS_STATUS_0 (0x0001) Bit Symbol Description [1] TEMP_CRIT Asserted as long as the thermal shutdown threshold is reached [0] TEMP_WARN Asserted as long as the thermal warning threshold is reached Table 22: SYS_STATUS_1 (0x0002) Bit Symbol Description [3] PG1 Asserted as long as the Buck1 output voltage is in range [2] OV1 Asserted as long as Buck1 hitting over-voltage [1] UV1 Asserted as long as Buck1 hitting under-voltage [0] OC1 Asserted as long as Buck1 hitting over-current Table 23: SYS_STATUS_2 (0x0003) Bit Symbol Description [2] GPIO2 GPIO2 status [1] GPIO1 GPIO1 status [0] GPIO0 GPIO0 status Table 24: SYS_EVENT_0 (0x0004) Bit Symbol Description [1] E_TEMP_CRIT TEMP_CRIT caused event. Writing 1 action clear this bit into 0 if event source has been released. [0] E_TEMP_WARN TEMP_WARN caused event. Writing 1 action clear this bit into 0 if event source has been released. Table 25: SYS_EVENT_1 (0x0005) Bit Symbol Description [3] E_PG1 PG1 caused event. Writing 1 action clear this bit into 0 if event source has been released. [2] E_OV1 OV1 caused event. Writing 1 action clear this bit into 0 if event source has been released. [1] E_UV1 UV1 caused event. Writing 1 action clear this bit into 0 if event source has been released. [0] E_OC1 OC1 caused event. Writing 1 action clear this bit into 0 if event source has been released.

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 32 of 49 © 2023 Renesas Electronics Table 26: SYS_EVENT_2 (0x0006) Bit Symbol Description [2] E_GPIO2 GPIO2 event. Writing 1 action clear this bit into 0 if event source has been released. [1] E_GPIO1 GPIO1 event. Writing 1 action clear this bit into 0 if event source has been released. [0] E_GPIO0 GPIO0 event. Writing 1 action clear this bit into 0 if event source has been released. Table 27: SYS_MASK_0 (0x0007) Bit Symbol Description [1] M_TEMP_CRIT TEMP_CRIT IRQ mask [0] M_TEMP_WARN TEMP_WARN IRQ mask Table 28: SYS_MASK_1 (0x0008) Bit Symbol Description [3] M_PG1 PG1 event IRQ mask [2] M_OV1 OV1 event IRQ mask [1] M_UV1 UV1 event IRQ mask [0] M_OC1 OC1 event IRQ mask Table 29: SYS_MASK_2 (0x0009) Bit Symbol Description [2] M_GPIO2 GPIO2 IRQ mask [1] M_GPIO1 GPIO1 IRQ mask [0] M_GPIO0 GPIO0 IRQ mask Table 30: SYS_MASK_3 (0x000A) Bit Symbol Description [3] M_VR_HOT Temp warning status IRQ mask. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 [0] M_PG1_STAT PG1 status IRQ mask. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 33 of 49 © 2023 Renesas Electronics Table 31: SYS_CONFIG_2 (0x000D) Bit Symbol Description [6:5] OC_LATCHOFF Over-current latch-off setting. BUCK shut-down after OCP for 8 µs/1 ms/3 ms unless disable setting. IRQ is generated unless IRQ is masked. Value Description 0x0 Latch off disable 0x1 Latch off after 8 µs of OCP signal 0x2 Latch off after 1 ms of OCP signal 0x3 Latch off after 3 ms of OCP signal [4] OC_DVC_MASK Over-current event (IRQ and latch-off feature) mask during DVC ramp-up and ramp-down [3:2] PG_DVC_MASK Power-good mask during DVC Value Description 0x0 No mask 0x1 Mask as not power good during DVC 0x2 Mask as power good during DVC 0x3 Reserved Table 32: SYS_CONFIG_3 (0x000E) Bit Symbol Description [6:4] OSC_TUNE Tune oscillator frequency, tuned frequency = Current + OSC_TUNE * 160 kHz Value Description 0x3 3 0x2 2 0x1 1 0x0 0 0x7 -1 0x6 -2 0x5 -3 0x4 -4 [1] I2C_TIMEOUT Enable automatic reset of 2-wire interface (if SDA stays low for >50 ms).

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 34 of 49 © 2023 Renesas Electronics Table 33: SYS_GPIO0_0 (0x0010) Bit Symbol Description [4:1] GPIO0_MODE GPIO function mode select Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 Reserved 0x3 Reserved 0x4 DVC1 input 0x5 Reserved 0x6 Reserved 0x7 RELOAD input 0x8 PG1 output 0x9 Reserved 0xA Reserved 0xB Reserved 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] GPIO0_OBUF GPIO output buffer select Value Description 0x0 open-drain output 0x1 push-pull output Table 34: SYS_GPIO0_1 (0x0011) Bit Symbol Description [7] GPIO0_DEB_FALL GPI debouce falling edge [6] GPIO0_DEB_RISE GPI debounce rising edge [5:4] GPIO0_DEB GPI debounce time Value Description 0x0 100 µs debouce 0x1 1 ms debouce 0x2 10 ms debounce 0x3 100 ms debounce [3] GPIO0_PUPD GPIO pull-up/pull-down enable Value Description 0x0 GPI: pull-down disabled, GPO: pull-up to AVDD

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 35 of 49 © 2023 Renesas Electronics Bit Symbol Description disabled 0x1 GPI: pull-down enabled, GPO: pull-up to AVDD enabled [2] GPIO0_POL GPIO polarity Value Description 0x0 GPIO is active-high 0x1 GPIO is active-low [1:0] GPIO0_TRIG GPI trigger type Value Description 0x0 Dual-edge triggered 0x1 Pos-edge triggered 0x2 Neg-edge triggered 0x3 Reserved (No trigger) Table 35: SYS_GPIO1_0 (0x0012) Bit Symbol Description [4:1] GPIO1_MODE GPIO function mode select. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 Reserved 0x3 Reserved 0x4 DVC1 input 0x5 Reserved 0x6 Reserved 0x7 RELOAD input 0x8 PG1 output 0x9 Reserved 0xA Reserved 0xB Reserved 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] GPIO1_OBUF GPIO output buffer select. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 open-drain output

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 36 of 49 © 2023 Renesas Electronics Bit Symbol Description 0x1 push-pull output Table 36: SYS_GPIO1_1 (0x0013) Bit Symbol Description [7] GPIO1_DEB_FALL GPI debouce falling edge. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 [6] GPIO1_DEB_RISE GPI debounce rising edge. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 [5:4] GPIO1_DEB GPI debounce time. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 100 µs debouce 0x1 1 ms debouce 0x2 10 ms debounce 0x3 100 ms debounce [3] GPIO1_PUPD GPIO pull-up/pull-down enable. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 GPI: pull-down disabled, GPO: pull-up to AVDD disabled 0x1 GPI: pull-down enabled, GPO: pull-up to AVDD enabled [2] GPIO1_POL GPIO polarity. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 GPIO is active-high 0x1 GPIO is active-low [1:0] GPIO1_TRIG GPI trigger type. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 Dual-edge triggered 0x1 Pos-edge triggered 0x2 Neg-edge triggered 0x3 Reserved (No trigger) Table 37: SYS_GPIO2_0 (0x0014) Bit Symbol Description [4:1] GPIO2_MODE GPIO function mode select. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 GPIO disable 0x1 EN1 input

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 37 of 49 © 2023 Renesas Electronics Bit Symbol Description 0x2 Reserved 0x3 Reserved 0x4 DVC1 input 0x5 Reserved 0x6 Reserved 0x7 RELOAD input 0x8 PG1 output 0x9 Reserved 0xA Reserved 0xB Reserved 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] GPIO2_OBUF GPIO output buffer select. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 open-drain output 0x1 push-pull output Table 38: SYS_GPIO2_1 (0x0015) Bit Symbol Description [7] GPIO2_DEB_FALL GPI debouce falling edge. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 [6] GPIO2_DEB_RISE GPI debounce rising edge. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 [5:4] GPIO2_DEB GPI debounce time. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 100 µs debouce 0x1 1 ms debouce 0x2 10 ms debounce 0x3 100 ms debounce [3] GPIO2_PUPD GPIO pull-up/pull-down enable. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 GPI: pull-down disabled, GPO: pull-up to AVDD disabled 0x1 GPI: pull-down enabled, GPO: pull-up to AVDD enabled

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 38 of 49 © 2023 Renesas Electronics Bit Symbol Description [2] GPIO2_POL GPIO polarity. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 GPIO is active-high 0x1 GPIO is active-low [1:0] GPIO2_TRIG GPI trigger type. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 Dual-edge triggered 0x1 Pos-edge triggered 0x2 Neg-edge triggered 0x3 Reserved (No trigger)

5.1.2 Buck1

Table 39: BUCK_BUCK1_0 (0x0020) Bit Symbol Description [6:4] CH1_SR_DVC_DWN Voltage slew-rate for DVC ramp-down Value Description 0x0 10 mV/8 µs 0x1 10 mV/4 µs 0x2 10 mV/2 µs 0x3 10 mV/µs 0x4 20 mV/µs 0x5 Reserved 0x6 Reserved 0x7 Reserved [3:1] CH1_SR_DVC_UP Voltage slew-rate for DVC ramp-up Value Description 0x0 10 mV/8 µs 0x1 10 mV/4 µs 0x2 10 mV/2 µs 0x3 10 mV/µs 0x4 20 mV/µs 0x5 40 mV/µs 0x6 Reserved 0x7 Reserved [0] CH1_EN Channel enable. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Table 40: BUCK_BUCK1_1 (0x0021) Bit Symbol Description [6:4] CH1_SR_SHDN Voltage slew-rate during shut-down Value Description 0x0 10 mV/8 µs 0x1 10 mV/4 µs 0x2 10 mV/2 µs 0x3 10 mV/µs 0x4 20 mV/µs 0x5 Reserved 0x6 Reserved 0x7 Immediate power-down

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 40 of 49 © 2023 Renesas Electronics Bit Symbol Description [3:1] CH1_SR_STARTUP Voltage slew-rate during startup Value Description 0x0 10 mV/8 µs 0x1 10 mV/4 µs 0x2 10 mV/2 µs 0x3 10 mV/µs 0x4 20 mV/µs 0x5 40 mV/µs 0x6 Reserved 0x7 Reserved [0] CH1_PD_DIS Pull-down while buck is disabled. 0: enable, 1: disable Table 41: BUCK_BUCK1_2 (0x0022) Bit Symbol Description [3:0] CH1_ILIM Select OCP threshold (A) Value Description 0x0 Reserved 0x1 3.5 0x2 4.0 0x3 4.5 0x4 5.0 0x5 5.5 0x6 6.0 0x7 6.5 0x8 7.0 0x9 7.5 0xA 8.0 0xB 8.5 0xC 9.0 0xD 9.5 0xE 10.0 0xF Disable Table 42: BUCK_BUCK1_3 (0x0023) Bit Symbol Description [7:0] CH1_VMAX VOUT max setting (V): From 0.30 V (0x1E) to 1.90 V (0xBE) in 10 mV steps. This is a read-only register. Value Description

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 41 of 49 © 2023 Renesas Electronics Bit Symbol Description 0x1E 0.3 0x1F 0.31 0x20 0.32 Continuing through… 0x99 1.53 To… 0xBD 1.89 0xBE 1.9 Table 43: BUCK_BUCK1_4 (0x0024) Bit Symbol Description [4] CH1_VSEL Output voltage and operation selection: 0: A, 1: B. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 [3:2] CH1_B_MODE Operation mode selection. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 Force PFM operation 0x1 Force PWM operation (full phase) 0x2 Force PWM operation (with phase shedding) 0x3 Auto mode [1:0] CH1_A_MODE Operation mode selection. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 Force PFM operation 0x1 Force PWM operation (full phase) 0x2 Force PWM operation (with phase shedding) 0x3 Auto mode Table 44: BUCK_BUCK1_5 (0x0025) Bit Symbol Description [7:0] CH1_A_VOUT Output voltage setting A: Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 From 0.30 V (0x1E) to 1.90 V (0xBE) in steps of 10 mV (default 1.0 V) Write-protected when value is written below 0.30 V or above 1.90 V Value Description 0x1E 0.3 0x1F 0.31 0x20 0.32

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 42 of 49 © 2023 Renesas Electronics Bit Symbol Description Continuing through… 0x64 1 To… 0xBC 1.88 0xBD 1.89 0xBE 1.9 Table 45: BUCK_BUCK1_6 (0x0026) Bit Symbol Description [7:0] CH1_B_VOUT Output voltage setting B: Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 From 0.30 V (0x1E) to 1.90 V (0xBE) in steps of 10 mV (default 1.0 V) Write-protected when value is written below 0.30 V or above 1.90 V Value Description 0x1E 0.3 0x1F 0.31 0x20 0.32 Continuing through… 0x64 1 To… 0xBC 1.88 0xBD 1.89 0xBE 1.9

5.1.3 Serialization

Table 46: OTP_DEVICE_ID (0x0048) Bit Symbol Description [7:0] DEV_ID Device ID Table 47: OTP_VARIANT_ID (0x0049) Bit Symbol Description [7:4] MRC Mask Revision Code [3:0] VRC Chip Variant Code Table 48: OTP_CUSTOMER_ID (0x004A) Bit Symbol Description [7:0] CUST_ID Customer ID Table 49: OTP_CONFIG_ID (0x004B) Bit Symbol Description [7:0] CONFIG_REV OTP Variant

6 Package Information

6.1 Package Outlines

Figure 20: Package Outline Drawing

6.2 Moisture Sensitivity Level

The moisture sensitivity level (MSL) is an indicator for the maximum allowable time period (floor lifetime) in which a moisture sensitive plastic device, once removed from the dry bag, can be exposed to an environment with a specified maximum temperature and a maximum relative humidity before the solder reflow process. The MSL classification is defined in Table 50. For detailed information on MSL levels refer to the IPC/JEDEC standard J-STD-020, which can be downloaded from http://www.jedec.org. The DA9217 package is qualified for MSL1. Table 50: MSL Classification MSL Level Floor Lifetime Conditions MSL 1 Unlimited ≤30 °C / 85 % RH

6.3 WLCSP Handling

Manual handling of WLCSP packages should be reduced to the absolute minimum. In cases where it is still necessary, a vacuum pick-up tool should be used. In extreme cases plastic tweezers could be used, but metal tweezers are not acceptable, since contact may easily damage the silicon chip. Removal of a WLCSP package will cause damage to the solder balls. Therefore a removed sample cannot be reused. WLCSP packages are sensitive to visible and infrared light. Precautions should be taken to properly shield the chip in the final product.

6.4 Soldering Information

Refer to the IPC/JEDEC standard J-STD-020 for relevant soldering information. This document can be downloaded from http://www.jedec.org.

7 Ordering Information

The ordering number consists of the part number followed by a suffix indicating the packing method. For details and availability, please consult Dialog Semiconductor’s customer support portal or your local sales representative. Table 51: Ordering Information Part Number Package Size (mm) Shipment Form Pack Quantity DA9217-xxV72 24 WLCSP 2.5 x 1.7 T&R 4500 DA9217-xxV76 24 WLCSP 2.5 x 1.7 Waffle Tray 140 DA9217-20V72 Standard OTP Variant VOUT1 = 1.0 V 24 WLCSP 2.5 x 1.7 T&R 4500 DA9217-20V76 Standard OTP Variant VOUT1 = 1.0 V 24 WLCSP 2.5 x 1.7 Waffle Tray 140

8 Application Information

The following recommended components are examples selected from requirements of a typical application.

8.1 Capacitor Selection

Ceramic capacitors are used as bypass capacitors at all VDD and output rails. When selecting a capacitor, especially for types with high capacitance at smallest physical dimension, the DC bias characteristic has to be taken into account. Table 52: Recommended Capacitor Types Application Value Size Temp. Char. Tol. (%) V-Rate Type VOUT output bypass 10 µF 0402 X5R ±15 % ±20 6.3 V Murata GRM155R60J106ME15 PVDDx bypass 10 µF 0603 X5R ±15 % ±20 25 V Murata GRM188R61E106MA73 AVDD bypass 1 µF 0402 X5R ±15 % ±10 10 V Murata GRM155R61A105KE15

8.2 Inductor Selection

Inductors should be selected based on the following parameters:

Rated maximum current Usually a coil provides two current limits: ISAT specifies the maximum current at which the inductance drops by 30 % of the nominal value, and IMAX is defined by the maximum power dissipation and is applied to the effective current.
DC resistance Critical for the converter efficiency and should therefore be minimized. Table 53: Recommended Inductor Types Value (µH) Size (mm) IMAX (DC) (A) ISAT (A) Tol. (%) DC Resistance (mΩ) Type HTEN20161T-R10MDR MEKK1608TR10M MCHK1608TR10MJN MCHK2012TR11MKG MCEE1005TR10MHN 0.1 2.5 x 2.0 x 1.2 12 13 ±20 4 TDK TFM252012ALMAR10MT TFP160810M-R10N WE-PMMI 744 799 771 11

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 48 of 49 © 2023 Renesas Electronics Status Definitions Revision Datasheet Status Product Status Definition 1.<n> Target Development This datasheet contains the design specifications for product development. Specifications may be changed in any manner without notice. 2.<n> Preliminary Qualification This datasheet contains the specifications and preliminary characterization data for products in pre-production. Specifications may be changed at any time without notice in order to improve the design. 3.<n> Final Production This datasheet contains the final specifications for products in volume production. The specifications may be changed at any time in order to improve the design, manufacturing and supply. Major specification changes are communicated via Customer Product Notifications. Datasheet changes are communicated via http://www.renesas.com/. 4.<n> Obsolete Archived This datasheet contains the specifications for discontinued products. The information is provided for reference only. RoHS Compliance Renesas Electronics’ suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from our suppliers are available on request.

High-Performance Dual-Phase DC-DC Converter Datasheet Revision 2.3 10-Feb-2023 CFR0011-120-00 49 of 49 © 2023 Renesas Electronics Important Notice and Disclaimer RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. © 2023 Renesas Electronics Corporation. All rights reserved. Corporate Headquarters TOYOSU FORESIA, 3-2-24 Toyosu Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: https://www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. (Rev.1.0 Mar 2020)

TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) © 2021 Renesas Electronics Corporation. All rights reserved.

Product Information

DA9217 specifications and overview.

Summary

High-Performance Dual-Phase DC-DC Converter 10-Feb-2023

Description

High-Performance Dual-Phase DC-DC Converter 10-Feb-2023

Source title DA9217 Datasheet(PDF) - Renesas Technology Corp

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