DA9213_V01 RENESAS | Alldatasheet
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DA9213, DA9214, and DA9215 Multi-Phase 5 A/Phase DC-DC Buck Converter R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 1 © 2025 Renesas Electronics DA9213, DA9214, and DA9215 are PMUs optimized for the supply of CPUs, GPUs, and DDR memory rails in smartphones, tablets and other portable applications. The fast transient response (10 A/µs) and load regulation are optimized for the latest generation of multi core application processors. DA9213 operates as a single four-phase buck converter delivering up to 20 A output current. DA9214 integrates two dual-phase buck converters, capable of delivering 2 x 10 A output current. DA9215 integrates a three-phase buck converter capable of delivering 15 A and a single-phase buck converter delivering 5 A output current. Each buck regulates a programmable output voltage in the range 0.3 V to 1.57 V. With an external resistor divider, the output voltage can be set to any voltage between 1.57 V and 4.3 V. The input voltage range of 2.8 V to 5.5 V makes it suited for a wide variety of low voltage systems, including all Li-Ion battery powered applications. To guarantee the highest accuracy and to support multiple PCB routing scenarios without loss of performance, a remote sensing capability is implemented in DA9213, DA9214, and DA9215. The power devices are fully integrated, so no external FETs or Schottky diodes are needed. A programmable soft start-up can be enabled, which limits the inrush current from the input node and secures a slope-controlled activation of the rail. The Dynamic Voltage Control (DVC) supports adaptive adjustment of the supply voltage depending on the processor load, either via direct register writes through the communication interface (I2C or SPI compatible) or via an input pin. DA9213, DA9214, and DA9215 feature integrated over-temperature and over-current protection for increased system reliability without the need for external sensing components. The safety feature set is completed by a VDDIO under-voltage lockout. The configurable I2C address selection via GPI allows multiple instances of DA9213, DA9214, and DA9215 or both to be placed in the application sharing the same communication interface with different addresses. Key Features ▪ 2.8 V to 5.5 V input voltage ▪ 0.3 V to 1.57 V output voltage ▪ 1.57 V to 4.3 V with resistor divider ▪ 20 A DA9213 ▪ 2 x 10 A DA9214 ▪ 1 x 15 A + 1 x 5 A DA9215 ▪ 3 MHz nominal switching frequency (allows use of low profile [1 mm] inductors) ▪ ±1% accuracy (static) ▪ ±3% accuracy (dynamic) Feature ▪ Dynamic voltage control ▪ Automatic phase shedding ▪ Integrated power switches ▪ Remote sensing at point of load ▪ I2C/SPI compatible interface ▪ Adjustable soft start ▪ -40 ºC to +85 ºC temperature range ▪ Package 66 WL-CSP 0.4 mm pitch or 66 VFBGA 0.5 mm pitch
Applications
▪ TV/media players ▪ Smartphones ▪ Tablet PCs ▪ Ultrabooks ▪ Mobile computing
particular that the third phase of DA9215 BuckA is phase B2. Phase B1 is used for the single phase BuckB. Table 1. Buck Allocations for Each Phase per Device Figure 1. DA9213 System Diagram
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 4
Contents
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 7 1. Terms and Definitions CPU Central processing unit DDR Double data rate (type of SDRAM memory for PCs) DVC Dynamic voltage control GPU Graphic processing unit IC Integrated circuit OTP One-time programmable memory PCB Printed circuit board PMIC Power management integrated circuit POL Point of load SDRAM Synchronous dynamic random-access memory
2.1 Pin Assignments
Figure 4. DA9213/14/15 66 WL-CSP Ball Map
Figure 5. DA9213/14/15 66 VFBGA Ball Map
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 10
2.2 Pin Descriptions
Table 2. Pin Description
Description
B1, B2, B3, B4 LX_A1 AO Switching node for Buck A phase 1 E1, E2, E3, E4 LX_A2 AO Switching node for Buck A phase 2 B8, B9, B10, B11 LX_B1 AO Switching node for Buck B phase 1 E8, E9, E10, E11 LX_B2 AO Switching node for Buck B phase 2 A1, A2, A3, A4 VDD_A1 PS Supply voltage for Buck A phase 1 To be connected to VSYS F1, F2, F3, F4 VDD_A2 PS Supply voltage for Buck A phase 2 To be connected to VSYS A8, A9, A10, A11 VDD_B1 PS Supply voltage for Buck B phase 1 To be connected to VSYS F8, F9, F10, F11 VDD_B2 PS Supply voltage for Buck B phase 2 To be connected to VSYS F7 IC_EN DI Integrated Circuit (IC) Enable Signal F5 nIRQ DO Interrupt line towards the host E7 VDDIO PS I/O Voltage Rail C5 FBAP AI Positive sense node for Buck A D5 FBAN AI Negative sense node for Buck A C7 FBBP AI Positive sense node for Buck B of DA9214 or DA9215 NC AO Do not connect for DA9213 D7 FBBN AI Negative sense node for Buck B of DA9214 or DA9215 NC AO Do not connect for DA9213 A7 GPI0 TRK DI/AI General purpose input, input track B7 GPI1 DI General purpose input B6 GPIO2 DIO General purpose input/output A5 SDA SI DIO 2-WIRE data, 4-WIRE data input/output A6 SCL SK DI 2-WIRE clock, 4-WIRE clock D6 nCS GPI4 DI 4-WIRE chip select, general purpose input C6 SO GPIO3 DIO 4-WIRE data output, general purpose input/output B5 NC AO Do not connect and leave floating. This pin is used for the supply of internal circuits. VDDCORE AO Regulated supply (typical 2.5 V) for internal circuitry. On VFBGA package, decouple with 150 nF (or 220 nF). F6 VSYS PS Supply for IC and input for voltage supervision E5 VSS VSS E6 VSS_ANA VSS C1, C2, C3, C4, D1, D2, D3, D4, C8, C9, C10, C11, D8, D9, D10, D11 VSS_A1, VSS_A2 VSS_B1 VSS_B2 VSS Connect together
Table 3. Pin Type Definition
3.1 Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Rating conditions for extended periods may affect device reliability. conditions can adversely impact product reliability and result in failures not covered by warranty. Table 4. Absolute Maximum Ratings Note 1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. conditions for extended periods may affect device reliability.
3.2 Recommended Operating Conditions
Table 5. Recommended Operating Conditions (Note 1)
66 WL-CSP
66 VFBGA
Note 1 Within the specified limits, a lifetime of 10 years is guaranteed. Note 2 VDDIO is not allowed to be higher than VDD. Note 3 Obtained from simulation on a 2S2P 4L JEDEC Board (EIA/JESD51-2). Influenced by PCB technology and layout.
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 13
3.3 Electrical Specifications
Electrical characteristics table limits are guaranteed by production testing, design, or correlation using standard statistical quality control methods unless otherwise stated. Typical (Typ) specifications are mean or average values at TA = 25°C and are not guaranteed. Unless otherwise noted, the following is valid for TJ = -40 ºC to +125 ºC, VDD = 2.8 V to 5.5 V, COUT = 47 μF per phase, local sensing. Table 6. Buck Converters Characteristics
Electrical Characteristics
VDD Supply voltage VDD_x = VSYS 2.8 5.5 V VBUCK Buck output voltage Note 1 IO = 0 to IO_MAX 0.3 1.57 V VOACC Output voltage accuracy PWM mode Incl. static line/load reg and voltage ripple VBUCK ≥ 1 V -2.0 +2.0 % Incl. static line/load reg and voltage ripple VBUCK < 1 V ±20 mV VBUCK = 1 V VDD = 3.8 V no load -1.0 +1.0 % VBUCK = 1 V VDD = 3.8 V no load TA = 27 ºC -0.5 +0.5 % VTR_LOAD Load regulation transient voltage Note 2 DA9213 IO = 0 to 5 A, tR = 500 ns PWM 4-phase VBUCK ≥ 1 V VBUCK < 1 V -20 mV +20 mV DA9213 IO = 0 to 5 A, tR = 500 ns auto mode, ph shedding VBUCK = 1 V -3.5 +3.5 DA9214 IO = 0 to 5 A, tR = 500 ns PWM 2-phase VBUCK = 1 V ±3.5 % DA9215 Buck A ±2.5 %
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 14 Parameter Description Conditions Min Typ Max Unit IO = 0 to 5 A, tR = 500 ns PWM 3-phase VBUCK = 1 V DA9215 Buck B IO = 0 to 2.5 A, tR = 200 ns PWM, 2 x 47 µF VBUCK = 1 V ±2.5 % VTR_LINE Line regulation transient voltage VDD = 3.0 to 3.6 V dt =10 µs IO = IO(MAX)/2 15 mV IO_MAX Maximum output current Per phase 5000 mA ILIM_MIN Minimum current limit per phase (programmable) BUCKA_ILIM = 0000 BUCKB_ILIM = 0000 Note 3 -20% 4000 20% mA ILIM_MAX Maximum current limit per phase (programmable) BUCKA_ILIM = 1111 BUCKB_ILIM = 1111 Note 3 -20% 7000 20% mA IQ_PWM Quiescent current at synchronous rectification mode Per phase No load VDD = 3.7 V 17 mA fSW Switching frequency 3 MHz tSTUP Start-up time VOUT = 1.0 V BUCKA_UP_CTRL = 100 BUCKB_UP_CTRL = 100 Note 4 µs RO_PD Output pull-down resistance For each phase at the LX node at 0.5 V, (see BUCKx_PD_DIS) 150 200 Ω RON_PMOS PMOS on-resistance 66 WL-CSP incl. pin and routing VDD = 3.7 V per phase 26 mΩ incl. pin and routing VDD = 3.7 V per phase 27 mΩ RON_NMOS NMOS on-resistance 66 WL-CSP incl. pin and routing VDD = 3.7 V per phase 18 mΩ incl. pin and routing VDD = 3.7 V per phase 19 mΩ
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 15 Parameter Description Conditions Min Typ Max Unit PFM Mode VBUCK_PFM Buck output voltage in PFM IO = 0 mA to IO_MAX 0.3 1.57 V IMIN_PFM Minimum output current in PFM Static output voltage, no DVC 2 mA IQ_PFM_A2 DA9214 quiescent current Buck A enabled No switching VDD = 3.7 V Note 5 58 µA IQ_PFM_A4 DA9213 quiescent current Buck enabled No switching VDD = 3.7 V Note 5 72 µA IQ_PFM_A2B2 DA9214 quiescent current Buck A enabled Buck B enabled No switching VDD = 3.7 V Note 5 106 µA IQ_PFM_A3B1 DA9215 quiescent current Buck A enabled Buck B enabled No switching VDD = 3.7 V Note 5 130 µA Note 1 Programmable in 10 mV increments. Note 2 Additional to the dc accuracy. The value is intended to be measured directly at COUT(EXT). In case of remote sensing, parasitics of PCB and external components may affect this value. Note 3 On-time > 50 ns. Note 4 Time from beginning to end of the voltage ramp. Additional 10 µs typical delay, plus internal sync to the enable port. Note 5 For the total quiescent current of the IC, the IDD_ON should be added.
Table 7. IC Performance and Supervision Table 8. Digital I/O Characteristics
Table 9. 2-WIRE Control Bus Characteristics
Figure 6. 2-WIRE Bus Timing Table 10. 4-WIRE Control Bus Characteristics
Figure 7. 4-WIRE Bus Timing
A9215 the ideal single/dual buck companion ICs to expand the existing capabilities of a master PMIC. does not conflict with DA9063. host processor and improved power up sequencing. ▪ DA9213, DA9214, and DA9215 can share the same interrupt line with DA9063. parts and power applications. Figure 14. Interface of DA9213/14/15 with DA9063 and the Host Processor and DA9213, DA9214, and DA9215 used as companion IC for the high-power core supply. additionally controlled by means of hardware inputs.
Figure 17. Typical Application of DA9215 disables the CPU/GPU and the DDR individually via dedicated ports on DA9215. Table 11. Buck Allocations for each Phase per Device particular that the third phase of DA9215 BuckA is phase B2. Phase B1 is used for the single phase BuckB.
5.1 DC_DC Buck Converter
range 0.3 V to 1.57 V, with high accuracy in steps of 10 mV. DA9214 contains two buck converters, Buck A and Buck B, each capable of delivering 10 A.
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 25 DA9215 contains also two buck converters, Buck A capable of 15 A and Buck B capable of 5 A. To improve the accuracy of the delivered voltage, each buck converter is able to support a differential sensing of the configured voltage directly at the point of load via dedicated positive and negative sense pins. Both Buck A and Buck B have two voltage registers each. One defines the normal output voltage, while the other offers an alternative retention voltage. In this way different application power modes can easily be supported. The voltage selection can be operated either via GPI or via control interface to guarantee the maximum flexibility according to the specific host processor status in the application. When a buck is enabled, its output voltage is monitored, and a power good signal indicates that the buck output voltage has reached a level higher than the VTH(PG) threshold. The power good is lost when the voltage drops below VTH(PG) - VHYS(PG), which is the level at which the signal is de-asserted. The power good signaling should not be used in conjunction with fast start up rates, configured in BUCKx_UP_CTRL register fields and can be individually masked during DVC transitions using the PGA_DVC_MASK and PGB_DVC_MASK bits. For each of the buck converters the status of the power good indicator can be read back via I2C from the PWRGOOD_A and PWRGOOD_B status bits. It can be also individually assigned to either GPIO2 or GPIO3 using BUCKA_PG_SEL and BUCKB_PG_SEL. For correct functionality, the GPIO ports need to be configured as output. An I2C write in GPIOx_MODE can overwrite the internal configuration so that a new update will be automatically done only when the internal power good indicator changes status. The buck converters are capable of supporting DVC transitions that occur: ▪ When the active and selected A-voltage or B-voltage is updated to a new target value. ▪ When the voltage selection is changed from the A-voltage to the B-voltage (or B-voltage to the A voltage) using VBUCKA_SEL and VBUCKB_SEL. The DVC controller operates in Pulse Width Modulation (PWM) mode with synchronous rectification. When the host processor changes the output voltage, the voltage transition of each buck converter can be individually signaled with a READY signal routed to either GPIO2 or GPIO3. The port has to be configured as GPO and selected for the functionality via READYA_CONF or READYB_CONF. In contrast to the power good signal, the READY only informs the host processor about the completion of the digital DVC ramp without confirming that the target voltage has actually been reached. The slew rate of the DVC transition is individually programmed for each buck converter at 10 mV per (4, 2, 1, or 0.5) µs via control bit SLEW_RATE_A and SLEW_RATE_B. The typical supply current is in the order of 17 mA per phase (quiescent current and charge/discharge current) and drops to <1 µA when the buck is turned off. When the buck is disabled, a pull down resistor (typically 150 Ω) for each phase is activated depending of the value stored in register bits BUCKA_PD_DIS and BUCKB_PD_DIS. Phases disabled using PHASE_SEL_A and PHASE_SEL_B will not have any pull down. The pull-down resistor is always disabled at all phases when DA9213, DA9214, and DA9215 are OFF.
5.1.1 Switching Frequency
The switching frequency is chosen to be high enough to allow the use of a small 0.22 µH inductor (see a complete list of coils in the Application Information, section 6). The buck switching frequency can be tuned using register bit OSC_TUNE. The internal 6 MHz oscillator frequency is tuned in steps of 180 kHz. This impacts the buck converter frequency in steps of 90 kHz and helps to mitigate possible disturbances to other HF systems in the application.
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 26
5.1.2 Operation Modes and Phase Selection
The buck converters can operate in synchronous PWM mode and PFM mode. The operating mode is selected using register bits BUCKA_MODE and BUCKB_MODE. An automatic phase shedding can be enabled for each buck converter in PWM mode via PH_SH_EN_A, PH_SH_EN_B, thereby automatically reducing or increasing the number of active phases depending on the output load current. For DA9214 the phase shedding will automatically change between 1-phase and 2-phase operation at a typical current of 2.0 A. For DA9213 the phase shedding will automatically change between 1- phase and 4-phase operation at a typical current of 2.5 A. The PHASE_SEL_A and PHASE_SEL_B register fields limit the maximum number of active phases under any conditions. If the automatic operation mode is selected on BUCKA_MODE or BUCKB_MODE, the buck converters will automatically change between synchronous PWM mode and PFM depending on the load current. This improves the efficiency of the converters across the whole range of output load currents.
5.1.3 Output Voltage Selection
The switching converter can be configured using either a 2-WIRE or a 4-WIRE interface. For security reasons, the re-programming of registers that can cause damage when wrongly programmed (for example, the voltage settings) can be disabled by asserting the control V_LOCK. When V_LOCK is asserted, reprogramming the registers 0xD0 to 0x14F from control interfaces is disabled. For each buck converter two output voltages can be pre-configured inside registers VBUCKA_A and VBUCKB_A, and registers VBUCKA_B and VBUCKB_B. The output voltage can be selected by either toggling register bits VBUCKA_SEL and VBUCKB_SEL or by re-programming the selected voltage control register. Both changes will result into ramped voltage transitions, during which the READY signal is asserted. After being enabled, the buck converter will by default use the register settings in VBUCKA_A and VBUCKB_A unless the output voltage selection is configured via the GPI port. If “00” has been selected in BUCKA_MODE or BUCKB_MODE, A-/B- voltage selection registers VBUCKx_x control the operation of the PWM and PFM modes. Regardless of the values programmed in the VBUCKx_A and VBUCKx_B registers, the registers VBUCKA_MAX, VBUCKB_MAX will individually limit the output voltage that can be set for each of the buck converters. The buck converter provides an optional hardware enable/disable via selectable GPI, and configured via control register bits BUCKA_GPI and BUCKB_GPI. A change of the output voltage from the state of a GPI is enabled via control register bits VBUCKA_GPI and VBUCKB_GPI. After detecting a rising or falling edge at the related GPIs, DA9213, DA9214, and DA9215 will configure the buck converters according to their status. In addition to selecting between the A/B voltages, a track mode can be activated for Buck A to set the output voltage. In the DA9213, the track mode is applied to the 4-phase buck converter. This feature can be enabled on GPI0 via GPI0_PIN. The output voltage will be configured to follow the value applied at a selected GPI pin. The voltage applied at GPI0 must be in the same range as the nominal output voltage selectable for the buck rail (see VBUCKA_A and VBUCKA_B registers). In Track Mode, only single ended remote sensing is possible. In Track Mode, the content of the VBUCKA_SEL bit is ignored, as well as VBUCKA_A and VBUCKA_B bits. They will become active again once the voltage track mode is disabled. The GPI0 does not generate any event in this case.
Figure 18. Concept of Control of the Buck’s Output Voltage
5.1.4 Soft Start-Up
start-up phase, so they should be considered carefully. A ramped power down can be selected on register bits BUCKA_DOWN_CTRL and BUCKB_DOWN_CTRL. BUCKA_PD_DIS and BUCKB_PD_DIS.
5.1.5 Current Limit
required maximum continuous output current. order to ensure that the possible high current levels needed for DVC do not influence the event generation. VOUT to FBAN (or FBBN) can be used to set the output voltage higher than 1.57 V, see Figure 19. resistance of the divider resistors (R1+R2) should be less than 40 kΩ.
Figure 19. Resistive Divider from VOUT to FBAN
- Please contact your region's Renesas representative when adopting the resistive divider technique. Renesas need to
prepare a special OTP because incorrect OTP settings may result in a different output voltage than expected.
- The voltage difference between input voltage and output voltage needs to be:
- The total resistance (R1 + R2) is less than 40 kΩ.
- It is recommended that the device is operated in PWM mode only.
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 29
5.2 Ports Description
This section describes the functionality of each input / output port.
5.2.1 VDDIO
VDDIO is an independent IO supply rail input to DA9213, DA9214, and DA9215 that can be assigned to the power manager interface and to the GPIOs (see control PM_IF_V and GPI_V). The rail assignment determines the IO voltage levels and logical thresholds (see also the Digital I/O Characteristics in Table 8). An integrated under-voltage lockout circuit for the VDDIO prevents internal errors by disabling the I2C communication when the voltage drops below VULO_IO. In that case the buck converters are also disabled and cannot be re-enabled (even via input port) until the VDDIO under-voltage condition has been resolved. At the exit of the VDDIO under-voltage condition an event E_UVLO_IO is generated and the nIRQ line is driven active if the event is not masked. The VDDIO under-voltage circuit monitors voltages relative to a nominal voltage of 1.8 V. If a different rail voltage is being used, the under-voltage circuit can be disabled via UVLO_IO_DIS. Note that the maximum speed at 4-WIRE interface is only available if the selected supply rail is greater than 1.6 V.
5.2.2 IC_EN
IC_EN is a general enable signal for DA9213, DA9214, and DA9215, turning on and off the internal circuitry (for example, the reference, the digital core, and so on.). Correct control of this port has a direct impact on the quiescent current of the whole application. A low level of IC_EN allows the device to reach the minimum quiescent current. The voltage at this pin is continuously sensed by a dedicated analog circuit. The host processor will be allowed to start the communication with DA9213, DA9214, and DA9215 through the Control Interface and, for example to turn on the buck converters, a delay time of tEN after assertion of the IC_EN pin. If the bucks are enabled via OTP (see BUCKA_EN and BUCKB_EN controls), they will start up automatically after assertion of IC_EN. The IC_EN activation threshold is defined with a built-in hysteresis to avoid glitching transitions that take place with unstable rising or falling edges. 5.2.3 nIRQ The nIRQ port indicates that an interrupt causing event has occurred and that the event/status information is available in the related registers. The nIRQ is an output signal that can either be push pull or open drain (selected via IRQ_TYPE). If an active high IRQ signal is required, it can be achieved by asserting control IRQ_LEVEL (recommended for push-pull mode). Examples of this type of information can be critical temperature and voltage, fault conditions, status changes at GPI ports, and so forth. The event registers hold information about the events that have occurred. Events are triggered by a status change at the monitored signals. When an event bit is set, the nIRQ signal is asserted unless this interrupt is masked by a bit in the IRQ mask register. The nIRQ will not be released until all event registers with asserted bits have been read and cleared. New events that occur during reading an event register are held until the event register has been cleared, ensuring that the host processor does not miss them.
5.2.4 GPIO Extender
DA9213, DA9214, and DA9215 include a GPIO extender that offers up to five 5 V-tolerant general purpose input/output ports. Each port is controlled via registers from the host processor. The GPIO3 and GPI4 ports are pin-shared with the 4-WIRE Control Interface. For instance, if GPIO3_PIN = 01, GPI4_PIN = 01 (Interface selected), the GPIO3 and GPI4 ports will be exclusively dedicated to output and chip select signaling for 4-WIRE purposes. If the alternative function is selected, all GPIOs configuration as per registers 0x58 to 0x5A and 0x145 will be ignored. GPIs are supplied from the internal rail VDDCORE or VDDIO (selected via GPI_V) and can be configured to be active high or active low (selected via GPIOx_TYPE). The input signals can be debounced or directly change the state of the assigned status register GPIx to high or low, according to the setting of GPIOx_MODE. The debouncing time is configurable via control DEBOUNCE (10 ms default).
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 30 Whenever the status has changed to its configured active state (edge sensitive), the assigned event register is set and the nIRQ signal is asserted (unless this nIRQ is masked, see also Figure 20). Whenever DA9213, DA9214, and DA9215 is enabled and enters ON mode (also when enabled changing the setting of GPIOx_PIN) the GPI status bits are initiated towards their configured passive state. This ensures that already active signals are detected, and that they create an event immediately after the GPI comparators are enabled. The buck enable signal (BUCKx_EN) can be controlled directly via a GPI, if so configured in the BUCKA_GPI and BUCKB_GPI registers. If it is required that GPI ports do not generate an event when configured for the HW control of the switching regulator, the relative mask bit should be set. GPIs can alternatively be selected to toggle the VBUCKA_SEL and VBUCKB_SEL from rising and falling edges at these inputs. Apart from changing the regulator output voltage this also provides hardware control of the regulator mode (normal/low power mode) from the settings of BUCKA_SL_A, BUCKA_SL_B, BUCKB_SL_A, and BUCKB_SL_B (enabled if BUCKA_MODE or BUCKB_MODE = 00). All GPI ports have the additional option of activating a 100 kΩ pull-down resistor via GPIOx_PUPD, which ensures a well-defined level in case the input is not actively driven. If enabled via ADDR_SEL_CONF, the I2C address selection can be assigned to a specific GPI. An active voltage level at the selected GPI configures the slave address of DA9213, DA9214, and DA9215 to IF_BASE_ADDR1 while a passive voltage level configures the slave address to IF_BASE_ADDR2. If no GPI is selected then the IF_BASE_ADDR1 is automatically used. If defined as an output, GPIOs can be configured to be open-drain or push-pull. If configured as push pull, the supply rail is VDDIO. By disabling the internal 120 kΩ pull-up resistor in open-drain mode, the GPO can also be supplied from an external rail. The output state will be assigned as configured by the GPIO register bit GPIOx_MODE. A specific power good port for each of the buck converters can be configured via BUCKA_PG_SEL and BUCKB_PG_SEL. The respective port must be configured as GPO for correct operation. If assigned to the same GPO, it is necessary that the power good indicators for Buck A and Buck B are both active (supply voltages in range) to assert the overall power good. The signal will be released as soon as one of the single power good signals is not active (that is, at least one supply is out of range). The power good signaling should not be used in conjunction with fast start up rates, configured in BUCKx_UP_CTRL register fields. Once enabled via RELOAD_FUNC_EN the GPIO0 can be used as input port to operate a partial OTP download. When the input level is changed to active, the registers 0x5D, 0x5E, 0xD1 to 0xDA are updated to their OTP default. This allows a complete buck re-configuration that resets all the changes done to those registers previously (soft reset). If the buck should be kept on during the soft reset, the OTP values for the enable bits should be asserted because they are also part of the re-load. Whenever the GPIO unit is off (POR or OFF Mode) all ports are configured as open drain active high (pass device switched off, high impedance state). When leaving POR the pull-up or pull-down resistors will be configured from register GPIOx_PUPD.
Figure 20. GPIO Principle of Operation (Example Paths)
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 32
5.3 Operating Modes
5.3.1 ON Mode
DA9213, DA9214, and DA9215 are in ON Mode when the IC_EN port is higher than EN_ON and the supply voltage is higher than VTH(UVLO)(VDD). Once enabled, the host processor can start the communication with DA9213, DA9214, and DA9215 via Control Interface after the tEN delay needed for internal circuit start up. If BUCKA_EN or BUCKB_EN is asserted when DA9213, DA9214, and DA9215 is in ON Mode the power up of the related buck converter is initiated. If the bucks are controlled via GPI, the level of the controlling ports is checked when entering ON mode, so that an active level will immediately have effect on the buck. If BUCKA_EN or BUCKB_EN are not asserted and all controlling GPI ports are inactive, the buck converter will stay off with the output pull down resistor enabled/disabled according to the setting of BUCKA_PD_DIS and BUCKB_PD_DIS.
5.3.2 OFF Mode
DA9213, DA9214, and DA9215 are in OFF Mode when the IC_EN port is lower than EN_OFF. In OFF Mode, the bucks are always disabled and the output pull down resistors are disabled independently of BUCKA_PD_DIS and BUCKB_PD_DIS. All I/O ports of DA9213, DA9214, and DA9215 are configured as high impedance.
5.4 Control Interfaces
All the features of DA9213, DA9214, and DA9215 can be controlled by SW through a serial control interfaces. The communication is selectable to be either a 2-WIRE (I2C compliant) or a 4-WIRE connection (SPI compliant) via control IF_TYPE, which will be selected during the initial OTP read. If 4-WIRE is selected, the GPIO3 and GPI4 are automatically configured as interface pins. Data is shifted into or out of DA9213, DA9214, and DA9215 under the control of the host processor, which also provides the serial clock. In a normal application case, the interface is only configured once from OTP values, which are loaded during the initial start-up of DA9213, DA9214, and DA9215. DA9213, DA9214, and DA9215 reacts only on read/write commands where the transmitted register address (using the actual page bits as a MSB address range extensions) is within 0x50 to 0x67, 0xD0 to DF, 0x140 to 0x14F and (read only) 0x200 to 0x27F. Host access to registers outside these ranges will be ignored. This means there will be no acknowledge after receiving the register address in 2-WIRE Mode, and SO stays HI-Z in 4-WIRE Mode. During debug and production modes write access is available to page 4 (0x200 to 0x27F). DA9213, DA9214, and DA9215 will react only on write commands where the transmitted register address is 0x00, 0x80, 0x100 to0x106. The host processor must read the content of those registers before writing, thereby changing only the bit fields that are not marked as reserved (the content of the read back comes from the compatible PMIC, for example DA9063). If the STAND_ALONE bit is asserted (OTP bit), DA9213, DA9214, and DA9215 will also react to read commands. 5.4.1 4-WIRE Communication In 4-WIRE Mode the interface uses a chip-select line (nCS/nSS), a clock line (SK), data input (SI) and data output line (SO). The DA9213, DA9214, and DA9215 register map is split into four pages that each contain up to 128 registers. The register at address zero on each page is used as a page control register. The default active page after turn on includes registers 0x50 to 0x6F. Writing to the page control register changes the active page for all subsequent read/write operations unless an automatic return to page 0 was selected by asserting bit REVERT. Unless the REVERT bit was asserted after modifying the active page, it is recommended to read back the page control register to ensure that future data exchange is accessing the intended registers. All registers outside the DA9213, DA9214, and DA9215 range are write only, that is, the DA9213, DA9214, and DA9215 will not answer to a read command and the data bus is tristate (they are implicitly directed to DA9063). In particular the information contained in registers 0x105 and 0x106 is used by DA9213, DA9214, and DA9215 to configure the control interface. They must be the same as the main PMIC (DA9063), so that a write to those registers configures both the main PMIC and DA9213, DA9214, and DA9215 at the same time. The default OTP settings also need to be identical for a correct operation of the system. The 4-WIRE interface features a half-duplex operation, that is, data can be transmitted and received within a single 16-bit frame at enhanced clock speed (up to 14 MHz). It operates at the clock frequencies provided by the host.
Figure 21. Schematic of 4-WIRE and 2-WIRE Power Manager Bus bit nCS_POL. nCS resets the interface when inactive and it has to be released between successive cycles. signal can cause unintended current consumption inside other circuits. Table 12. 4-WIRE Clock Configurations DA9215 must be set to the same CPOL and CPHA states to communicate with each other.
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 36 Parameters Transmission Half-duplex MSB first 16-bit cycles 7-bit address, 1-bit read/write, 8-bit data Configuration CPOL Clock polarity CPHA Clock phase nCS_POL nCS is active low/high Note 1 Reading the same register at high clock rates directly after writing it does not guarantee a correct value. It is recommended to keep a delay of one frame until re-accessing a register that has just been written (for example, by writing/reading another register address in-between). 5.4.2 2-WIRE Communication The IF_TYPE bit in the INTERFACE2 register can be used to configure the DA9213, DA9214, and DA9215 control interface as a 2-WIRE serial data interface. In this case the GPIO3 and GPI4 are free for regular input/output functions. DA9213, DA9214, and DA9215 has a configurable device write address (default: 0xD0) and a configurable device read address (default: 0xD1). See control IF_BASE_ADDR1 for details of configurable addresses. The ADDR_SEL_CONF bit is used to configure the device address as IF_BASE_ADDR1 or IF_BASE_ADDR2 depending on the voltage level applied at a configurable GPI port (see section 5.2.4). The SK port functions as the 2-WIRE clock and the SI port carries all the power manager bidirectional 2-WIRE data. The 2-WIRE interface is open-drain supporting multiple devices on a single line. The bus lines have to be pulled HIGH by external pull-up resistors (in the 2 kΩ to 20 kΩ range). The attached devices only drive the bus lines LOW by connecting them to ground. As a result, two devices cannot conflict if they drive the bus simultaneously. In standard/fast mode the highest frequency of the bus is 400 kHz. The exact frequency can be determined by the application and does not have any relation to the DA9213, DA9214, and DA9215 internal clock signals. DA9213, DA9214, and DA9215 will follow the host clock speed within the described limitations, and does not initiate any clock arbitration or slow down. An automatic interface reset can be triggered using control 2WIRE_TO if the clock signal stops to toggle for more than 35 ms. The interface supports operation compatible to Standard, Fast, Fast-Plus and High-Speed mode of the I2C-bus specification Rev 4. Operation in high-speed mode at 3.4 MHz requires mode changing in order to set spike suppression and slope control characteristics to be compatible with the I2C-bus specification. The high-speed mode can be enabled on a transfer-by-transfer basis by sending the master code (0000 1XXX) at the beginning of the transfer. DA9213, DA9214, and DA9215 do not make use of clock stretching, and deliver read data without additional delay up to 3.4 MHz. Alternatively, PM_IF_HSM configures the interface to use high speed mode continuously. In this case, the master code is not required at the beginning of every transfer. This reduces the communication overhead on the bus but limits the slaves attachable to the bus to compatible devices. The communication on the 2-WIRE bus always takes place between two devices, one acting as the master and the other as the slave. The DA9213, DA9214, and DA9215 will only operate as a SLAVE. In contrast to the 4-WIRE mode, the 2-WIRE interface has direct access to two pages of the register map (up to 256 addresses). The register at address zero on each page is used as a page control register (with the 2-WIRE bus ignoring the LSB of control REG_PAGE). Writing to the page control register changes the active page for all subsequent read/write operations unless an automatic return to page 0 was selected by asserting control REVERT. Unless REVERT was asserted after modifying the active page, it is recommended to read back the page control register to ensure that future data exchange is accessing the intended registers. In 2-WIRE operation DA9213, DA9214, and DA9215 offer an alternative way to access register page 2 and page 3. It removes the need for preceding page selection writes by incrementing the device write/read address by one (default 0xD2/0xD3) for any direct access of page 2 and page 3 (page 0 and 1 access requires the basic write/read device address with the MSB of REG_PAGE to be 0).
5.4.3 Details of the 2-WIRE Control Bus Protocol
All data is transmitted across the 2-WIRE bus in groups of eight bits. To send a bit the SDA line is driven towards the intended state while the SCL is LOW (a low on SDA indicates a zero bit). Once the SDA has settled, the SCL line is brought HIGH and then LOW. This pulse on SCL clocks the SDA bit into the receiver’s shift register.
5.5 Internal Temperature Supervision
temperature is continuously monitored. There are three temperature thresholds, as shown in Table 14. Table 14. Over-Temperature Thresholds temperature remains higher than TEMP_WARN. immediately disable the buck converter, assert the bit TEMP_CRIT, and will generate the event E_TEMP_CRIT. permanent damage in the case of a rapid temperature increase.
The following recommended components are examples selected from requirements of a typical application.
6.1 Capacitor Selection
Table 15. Recommended Capacitor Types
6.2 Inductor Selection
dissipation and is applied to the effective current. ▪ DC resistance: critical for the converter efficiency and should therefore be minimized. the load transient performance of the buck converter. Table 16. Recommended Inductor Types
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 41 Value (µH) Size (mm) Imax(dc) (A) Isat (A) Tol (%) DC Res (mΩ) Type DFE252010P-H-R33M DFE252012P-H-R33M 0.47 4 x 4 x 1.0 9.0 10.5 ±20 17 Cyntec PIME041B-R47MS-11 0.47 4 x 4 x 1.2 8.7 6.7 ±20 14 Coilcraft XFL4012-471ME
7.1 Register Map
Table 17 displays the register map, where all bits loaded from OTP are marked in bold. Table 17. Register Map
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 43 Addr Function 7 6 5 4 3 2 1 0 0×D3 BUCK_CONF Reserved Reserved Reserved PH_SH_EN_B PH_SH_EN_A PHASE_SEL_B PHASE_SEL_A 0×D4 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0×D5 VBUCKA_MAX Reserved VBUCKA_MAX 0×D6 VBUCKB_MAX Reserved VBUCKB_MAX 0×D7 VBUCKA_A BUCKA_SL_A VBUCKA_A 0×D8 VBUCKA_B BUCKA_SL_B VBUCKA_B 0×D9 VBUCKB_A BUCKB_SL_A VBUCKB_A 0×DA VBUCKB_B BUCKB_SL_B VBUCKB_B Register Page 2 0×100 PAGE_CON REVERT WRITE_MODE Reserved Reserved Reserved REG_PAGE 0×101 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0×102 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0×103 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0×104 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0×105 INTERFACE IF_BASE_ADDR1 R/W_POL CPHA CPOL nCS_POL 0×106 INTERFACE2 IF_TYPE PM_IF_HSM PM_IF_FMP PM_IF_V Reserved Reserved Reserved Reserved 0×140 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0×141 Reserved Reserved 0×142 Reserved Reserved 0×143 CONFIG_A Reserved Reserved Reserved 2WIRE_TO GPI_V Reserved IRQ_TYPE IRQ_LEVEL 0×144 CONFIG_B UVLO_IO_DIS PGB_DVC_MASK PGA_DVC_MASK OCB_MASK OCA_MASK RELOAD_FUNC_EN 0×145 CONFIG_C Reserved Reserved Reserved GPI4_PUPD GPIO3_PUPD GPIO2_PUPD GPI1_PUPD GPIO_PUPD 0×146 CONFIG_D BUCKB_PG_SEL BUCKA_PG_SEL READYB_CONF READYA_CONF 0×147 CONFIG_E STAND_ALONE Reserved Reserved Reserved Reserved OSC_TUNE 0×148 CONFIG_F IF_BASE_ADDR2 Reserved Reserved ADDR_SEL_CONF
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 44
7.1.1 Register Page Control
Register Bit Type Label Description 0x00 PAGE_CON
7 R/W REVERT Resets REG_PAGE to 000 after read/write access has
6 R/W WRITE_MODE
2-WIRE multiple write mode (Note 1) 0: Page Write Mode 1: Repeated Write Mode 5:3 R/W (reserved) 2:0 R/W REG_PAGE I2C 00x: Selects Register 0x00 to 0xFF 01x: Selects Register 0x100 to 0x17F SPI 000: Selects Register 0x00 to 0x7F 001: Selects Register 0x80 to 0xFF 010: Selects Register 0x100 to 0x17F >010: Reserved for production and test Note 1 Not used for 4-WIRE-IF
7.1.2 Register Page 0
7.1.2.1 System Control and Event
The STATUS registers report the current value of the various signals at the time that it is read out. Register Bit Type Label Description 0x50 STATUS_A 7:5 R (reserved)
4 R GPI4 GPI4 level
3 R GPI3 GPI3 level
2 R GPI2 GPI2 level
1 R GPI1 GPI1 level
0 R GPI0 GPI0 level
Register Bit Type Label Description 0x51 STATUS_B
7 R RAMP_READY_B De-asserted during Buck A DVC, power up and power down
6 R RAMP_READY_A De-asserted during Buck B DVC, power up and power down
5 R OV_CURR_B Asserted as long as the current limit for Buck B is hit
4 R OV_CURR_A Asserted as long as the current limit for Buck A is hit
3 R TEMP_CRIT Asserted as long as the thermal shutdown threshold is
2 R TEMP_WARN Asserted as long as the thermal warning threshold is reached
1 R PWRGOOD_B Asserted as long as the Buck B output voltage is in range
0 R PWRGOOD_A Asserted as long as the Buck A output voltage is in range
The EVENT registers hold information about events that have occurred in DA9213, DA9214, and DA9215. Events are triggered by a change in the status register which contains the status of monitored signals. When an EVENT bit is set in the event register, the IRQ signal is asserted unless the event is masked by a bit in the mask
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 45 register. The IRQ triggering event register will be cleared from the host by writing back its read value. New events occurring during clearing will be delayed before they are passed to the event register, ensuring that the host controller does not miss them. Register Bit Type Label Description 0x52 EVENT_A
7 R (reserved)
6 R E_UVLO_IO UVLO_IO caused event
5 R (reserved)
4 R E_GPI4 GPI4 event according to active state setting
3 R E_GPI3 GPI3 event according to active state setting
2 R E_GPI2 GPI2 event according to active state setting
1 R E_GPI1 GPI1 event according to active state setting
0 R E_GPI0 GPI0 event according to active state setting
Register Bit Type Label Description 0x53 EVENT_B 7:6 R (reserved)
5 R E_OV_CURR_B OV_CURR Buck B caused event
4 R E_OV_CURR_A OV_CURR Buck A caused event
3 R E_TEMP_CRIT TEMP_CRIT caused event
2 R E_TEMP_WARN TEMP_WARN caused event
1 R E_PWRGOOD_B PWRGOOD loss at Buck B caused event
0 R E_PWRGOOD_A PWRGOOD loss at Buck A caused event
Register Bit Type Label Description 0x54 MASK_A
7 R/W (reserved)
6 R/W M_UVLO_IO Mask UVLO_IO caused nIRQ
5 R/W (reserved)
4 R/W M_GPI4 Mask nIRQ interrupt at GPI4
3 R/W M_GPI3 Mask nIRQ interrupt at GPI3
2 R/W M_GPI2 Mask nIRQ interrupt at GPI2
1 R/W M_GPI1 Mask nIRQ interrupt at GPI1
0 R/W M_GPI0 Mask nIRQ interrupt at GPI0
Register Bit Type Label Description 0x55 MASK_B 7:6 R/W (reserved)
5 R/W M_OV_CURR_B Mask OV_CURR Buck B caused nIRQ and event
4 R/W M_OV_CURR_A Mask OV_CURR Buck A caused nIRQ and event
3 R/W M_TEMP_CRIT Mask TEMP_CRIT caused nIRQ
2 R/W M_TEMP_WARN Mask TEMP_WARN caused nIRQ
1 R/W M_PWRGOOD_B Mask PWRGOOD Buck B caused nIRQ
0 R/W M_PWRGOOD_A Mask PWRGOOD Buck A caused nIRQ
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 46 Register Bit Type Label Description 0x56 CONTROL_A
7 R/W V_LOCK 0: Allows host writes into registers 0xD0 to 0x14F
1: Disables register 0xD0 to 0x14F re-programming from control interfaces 6:5 R/W SLEW_RATE_B Buck B DVC slewing is executed at 00: 10 mV every 4.0 µs 01: 10 mV every 2.0 µs 10: 10 mV every 1.0 µs 11: 10 mV every 0.5 µs 4:3 R/W SLEW_RATE_A Buck A DVC slewing is executed at 00: 10 mV every 4.0 µs 01: 10 mV every 2.0 µs 10: 10 mV every 1.0 µs 11: 10 mV every 0.5 µs 0:2 R/W DEBOUNCE Input signals debounce time: 000: no debounce time 001: 0.1 ms 010: 1.0 ms 011: 10 ms 100: 50 ms 101: 250 ms 110: 500 ms 111: 1000 ms
7.1.2.2 GPIO Control
Register Bit Type Label Description 0x58 GPI0-1 7 R/W GPI1_MODE 0: GPI: debouncing off 1: GPI: debouncing on
6 R/W GPI1_TYPE 0: GPI: active low
1: GPI: active high 5:4 R/W GPI1_PIN PIN assigned to: 00: GPI >00: Reserved
3 R/W GPI0_MODE 0: GPI: debouncing off
1: GPI: debouncing on
2 R/W GPI0_TYPE 0: GPI: active low
1: GPI: active high 1:0 R/W GPI0_PIN PIN assigned to: 00: GPI 01: Track enable 1x: Reserved Register Bit Type Label Description 0x59 GPIO2-3 7 R/W GPIO3_MODE 0: GPI: debouncing off GPO: Sets output to passive level 1: GPI: debouncing on GPO: Sets output to active level
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 47 Register Bit Type Label Description
6 R/W GPIO3_TYPE 0: GPI/GPO: active low
1: GPI/GPO: active high 5:4 R/W GPIO3_PIN PIN assigned to: 00: GPI 01: Reserved 10: GPO (Open drain) 11: GPO (Push-pull)
3 R/W GPIO2_MODE
0: GPI: debouncing off GPO: Sets output to passive level 1: GPI: debouncing on GPO: Sets output to active level
2 R/W GPIO2_TYPE 0: GPI/GPO: active low
1: GPI/GPO: active high 1:0 R/W GPIO2_PIN PIN assigned to: 00: GPI 01: Reserved 10: GPO (Open drain) 11: GPO (Push-pull) Register Bit Type Label Description 0x5A GPI4 7:4 R/W (reserved)
3 R/W GPI4_MODE 0: GPI: debouncing off
1: GPI: debouncing on
2 R/W GPI4_TYPE 0: GPI: active low
1: GPI: active high 1:0 R/W GPI4_PIN PIN assigned to: 00: GPI 01: Reserved 1x: Reserved
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 48
7.1.2.3 Regulators Control
Register Bit Type Label Description 0x5D BUCKA_CONT 6:5 R/W VBUCKA_GPI Selects the GPI that specifies the target voltage of VBUCKA. This is VBUCKA_A on active to passive transition, VBUCKA_B on passive to active transition. Active high/low is controlled by GPIx_TYPE. 00: Not controlled by GPIO 01: GPIO1 controlled 10: GPIO2 controlled 11: GPIO4 controlled
4 R/W VBUCKA_SEL
Buck A voltage is selected from (ramping): 0: VBUCKA_A 1: VBUCKA_B
3 R/W BUCKA_PD_DIS
0: Enable pull-down resistor of Buck A when the buck is disabled 1: Disable pull-down resistor of Buck A when the buck is disabled 2:1 R/W BUCKA_GPI GPIO enables the Buck A on passive to active state transition, disables the Buck A on active to passive state transition 00: Not controlled by GPIO 01: GPIO0 controlled 10: GPIO1 controlled 11: GPIO3 controlled
0 R/W BUCKA_EN 0: Buck A disabled
1: Buck A enabled Register Bit Type Label Description 0x5E BUCKB_CONT 6:5 R/W VBUCKB_GPI Selects the GPI that specifies the target voltage of VBUCKB. This is VBUCKB_A on active to passive transition, VBUCKB_B on passive to active transition. Active high/low is controlled by GPIx_TYPE. 00: Not controlled by GPIO 01: GPIO1 controlled 10: GPIO2 controlled 11: GPIO4 controlled
4 R/W VBUCKB_SEL
Buck A voltage is selected from (ramping): 0: VBUCKB_A 1: VBUCKB_B
3 R/W BUCKB_PD_DIS
0: Enable pull-down resistor of Buck B when the buck is disabled 1: Disable pull-down resistor of Buck B when the buck is disabled 2:1 R/W BUCKB_GPI GPIO enables the Buck B on passive to active state transition, disables the Buck B on active to passive state transition 00: Not controlled by GPIO 01: GPIO0 controlled
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 49 Register Bit Type Label Description 10: GPIO1 controlled 11: GPIO3 controlled
0 R/W BUCKB_EN 0: Buck B disabled
1: Buck B enabled
7.1.3 Register Page 1
Register Bit Type Label Description 0x80 PAGE_CON 2-WIRE multiple write mode 0: Page Write Mode 1: Repeated Write Mode 5:3 R/W (reserved) 2:0 R/W REG_PAGE I2C 00x: Selects Register 0x00 to 0xFF 01x: Selects Register 0x100 to 0x17F SPI 000: Selects Register 0x00 to 0x7F 001: Selects Register 0x80 to 0xFF 010: Selects Register 0x100 to 0x17F >010: Reserved for production and test
7.1.3.1 Regulators Settings
Register Bit Type Label Description 0xD0 BUCK_ILIM 7:4 R/W BUCKB_ILIM Current limit per phase: 0000: 4000 mA 0001: 4200 mA 0010: 4400 mA Continuing through… 1001: 5800 mA to… 1110: 6800 mA 1111: 7000 mA 3:0 R/W BUCKA_ILIM Current limit per phase: 0000: 4000 mA 0001: 4200 mA 0010: 4400 mA Continuing through… 1001: 5800 mA to… 1110: 6800 mA 1111: 7000 mA
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 50 Register Bit Type Label Description 0xD1 BUCKA_CONF 7:5 R/W BUCKA_DOWN_ CTRL Buck A voltage ramping during power down 000: 1.25 mV/µs 001: 2.5 mV/µs 010: 5 mV/µs 011: 10 mV/µs 100: 20 mV/µs 101: 30 mV/µs 110: 40 mV/µs 111: no ramped power down 4:2 R/W BUCKA_UP_CT RL Buck A voltage ramping during start up 000: 1.25 mV/µs 001: 2.5 mV/µs 010: 5 mV/µs 011: 10 mV/µs 100: 20 mV/µs (Note 1) 101: 30 mV/µs 110: 40 mV/µs 111: target voltage applied immediately (no soft start) 1:0 R/W BUCKA_MODE 00: PFM/PWM mode controlled via voltage A and B registers 01: Automatic mode (1-phase) 10: Buck A always operates in PWM mode 11: Automatic mode Note 1 Settings higher than 20 mV/µs may cause significant overshoot Register Bit Type Label Description 0xD2 BUCKB_CONF 7:5 R/W BUCKB_DOWN_ CTRL Buck B voltage ramping during power down 000: 1.25 mV/µs 001: 2.5 mV/µs 010: 5 mV/µs 011: 10 mV/µs 100: 20 mV/µs 101: 30 mV/µs 110: 40 mV/µs 111: no ramped power down 4:2 R/W BUCKB_UP_CT RL Buck B voltage ramping during start up 000: 1.25 mV/µs 001: 2.5 mV/µs 010: 5 mV/µs 011: 10 mV/µs 100: 20 mV/µs (Note 2) 101: 30 mV/µs 110: 40 mV/µs 111: target voltage applied immediately (no soft start) 1:0 R/W BUCKB_MODE 00: PFM/PWM mode controlled via voltage A and B registers 01: Automatic mode (1-phase) 10: Buck B always operates in PWM mode 11: Automatic mode
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 51 Note 2 Settings higher than 20 mV/µs may cause significant overshoot Register Bit Type Label Description 0xD3 BUCK_CONF 7:5 R/W (reserved)
4 R/W PH_SH_EN_B Enable current dependent phase shedding in PWM for
3 R/W PH_SH_EN_A Enable current dependent phase shedding in PWM for
2 R/W PHASE_SEL_B
Phase selection for Buck B in PWM 0: 1 phase is selected 1: 2 phases are selected 1:0 R/W PHASE_SEL_A Phase selection for Buck A in PWM mode. Settings >01 apply only for DA9213 otherwise the number of phases is limited to max 2 00: 1 phase is selected 01: 2 phases are selected 10: 3 phases are selected (uneven 0/90/180 phase shift) 11: 4 phases are selected Register Bit Type Label Description 0xD5 VBUCKA_MAX 6:0 R VBUCKA_MAX Sets the maximum voltage allowed for Buck A (OTP programmed, access only in test mode) 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V Continuing through… 1000110: 1.0 V to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Register Bit Type Label Description 0xD6 VBUCKB_MAX 6:0 R VBUCKB_MAX Sets the maximum voltage allowed for Buck B (OTP programmed, access only in test mode) 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V Continuing through… 1000110: 1.0 V to…
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 52 Register Bit Type Label Description 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Register Bit Type Label Description 0xD7 VBUCKA_A 7 R/W BUCKA_SL_A 0: Configures Buck A to PWM mode whenever selecting A voltage setting 1: Configures Buck A to automatic mode whenever selecting A voltage setting 6:0 R/W VBUCKA_A 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V Continuing through… 1000110: 1.0 V to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Register Bit Type Label Description 0xD8 VBUCKA_B 7 R/W BUCKA_SL_B 0: Configures Buck A to PWM mode, whenever selecting B voltage setting 1: Configures Buck A to automatic mode, whenever selecting B voltage setting 6:0 R/W VBUCKA_B 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V Continuing through… 1000110: 1.0 V to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Register Bit Type Label Description 0xD9 VBUCKB_A 7 R/W BUCKB_SL_A 0: Configures Buck B to PWM mode, whenever selecting A voltage setting 1: Configures Buck B to automatic mode, whenever selecting A voltage setting 6:0 R/W VBUCKB_A 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 53 Register Bit Type Label Description Continuing through… 1000110: 1.0 V to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V Register Bit Type Label Description 0xDA VBUCKB_B 7 R/W BUCKB_SL_B 0: Configures Buck B to PWM mode, whenever selecting B voltage setting 1: Configures Buck B to automatic mode, whenever selecting B voltage setting 6:0 R/W VBUCKB_B 0000000: 0.30 V 0000001: 0.31 V 0000010: 0.32 V Continuing through… 1000110: 1.0 V to… 1111101: 1.55 V 1111110: 1.56 V 1111111: 1.57 V
7.1.4 Register Page 2
Register Bit Type Label Description 0x100 PAGE_CON 2-WIRE multiple write mode 0: Page Write Mode 1: Repeated Write Mode 5:3 R/W (reserved) 2:0 R/W REG_PAGE I2C 00x: Selects Register 0x00 to 0xFF 01x: Selects Register 0x100 to 0x17F SPI 000: Selects Register 0x00 to 0x7F 001: Selects Register 0x80 to 0xFF 010: Selects Register 0x100 to 0x17F >010: Reserved for production and test
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 54
7.1.4.1 Interface and OTP Settings (shared with DA9063)
Register Bit Type Label Description 0x105 INTERFACE 7:4 R/W IF_BASE_ADDR
4 MSB of 2-WIRE control interfaces base address
11010000 = 0xD0 write address of PM 2-WIRE interface (page 0 and 1) 11010001 = 0xD1 read address of PM 2-WIRE interface (page 0 and 1) 11010010 = 0xD2 write address of PM-2-WIRE interface (page 2 and 3) 11010011 = 0xD3 read address of PM-2-WIRE interface (page 2 and 3) Code 0000 is reserved for unprogrammed OTP (triggers start-up with hardware default interface address)
3 R/W R/W_POL
4-WIRE: Read/Write bit polarity 0: Host indicates reading access via R/W bit = 0 1: Host indicates reading access via R/W bit = 1
2 R/W CPHA 4-WIRE interface clock phase (see Table 12)
1 R/W CPOL
4-WIRE interface clock polarity 0: SK is low during idle 1: SK is high during idle
0 R/W nCS_POL
4-WIRE chip select polarity 0: nCS is low active 1: nCS is high active Register Bit Type Label Description 0x106 INTERFACE2 7 R/W IF_TYPE 0: Power manager interface is 4-WIRE. Automatically configures GPIO3 and GPI4 as interface signals. The GPIO configuration is overruled. 1: Power manager interface is 2-WIRE
6 R/W PM_IF_HSM Enables continuous high speed mode on 2-WIRE interface if
asserted (no master code required)
5 R/W PM_IF_FMP Enables 2-WIRE interface operating with fast mode+ timings
4 R/W PM_IF_V
0: Power manager interface in 2-WIRE mode is supplied from VDDCORE (4-WIRE always from VDDIO) 1: Power manager interface in 2-WIRE mode is supplied from VDDIO (4-WIRE always from VDDIO) 0:3 R/W (reserved)
7.1.4.2 Application Configuration Settings
Register Bit Type Label Description 0x143 CONFIG_A 7:5 R/W (reserved)
4 R/W 2WIRE_TO
Enables automatic reset of 2-WIRE interface if the clock stays low for >35 ms 0: Disabled 1: Enabled
3 R/W GPI_V
GPIs are supplied from: 0: VDDCORE 1: VDDIO
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 55 Register Bit Type Label Description
2 R/W (reserved)
1 R/W IRQ_TYPE
nIRQ output port is: 0: Push-pull 1: Open drain (requires external pull-up resistor)
0 R/W IRQ_LEVEL
nIRQ output port is: 0: Active low 1: Active high Register Bit Type Label Description 0x144 CONFIG_B 7 R/W UVLO_IO_DIS Disable the UVLO for the VDDIO rail and its comparator (suggested for rail voltages different to
1.8 V and to save quiescent current)
6 R/W PGB_DVC_MASK
Power-good configuration for Buck B 0: Power-good signal not masked during DVC transitions 1: Power-good signal masked during DVC transitions (keep previous status)
5 R/W PGA_DVC_MASK
Power-good configuration for Buck A 0: Power-good signal not masked during DVC transitions 1: Power-good signal masked during DVC transitions (keep previous status) 4:3 R/W OCB_MASK Over Current configuration for Buck B 00: Event generation due to over current hit is always active during DVC transitions of the Buck converter 01: Event generation due to over current hit is masked during DVC transitions of the buck converter + 2 µs extra masking at the end 10: Event generation due to over current hit is masked during DVC transitions of the buck converter + 10 µs extra masking at the end 11: Event generation due to over current hit is masked during DVC transitions of the buck converter + 50 µs extra masking at the end 2:1 R/W OCA_MASK Over Current configuration for Buck A 00: Event generation due to over current hit is always active during DVC transitions of the buck converter 01: Event generation due to over current hit is masked during DVC transitions of the buck converter + 2 µs extra masking at the end 10: Event generation due to over current hit is masked during DVC transitions of the buck converter + 10 µs extra masking at the end 11: Event generation due to over current hit is masked during DVC transitions of the buck converter + 50 µs extra masking at the end
0 R/W RELOAD_FUNC_EN Enable the OTP re-load function for GPIO0 when
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 56 Register Bit Type Label Description 0x145 CONFIG_C 7:5 R/W (reserved)
4 R/W GPI4_PUPD 0: GPI: pull-down resistor disabled
1: GPI: pull-down resistor enabled
3 R/W GPIO3_PUPD
0: GPI: pull-down resistor disabled GPO (open drain): pull up resistor disabled (external pull-up resistor) 1: GPI: pull-down resistor enabled GPO (open drain): pull up resistor
2 R/W GPIO2_PUPD
0: GPI: pull-down resistor disabled GPO (open drain): pull up resistor disabled (external pull-up resistor) 1: GPI: pull-down resistor enabled GPO (open drain): pull up resistor enabled
1 R/W GPI1_PUPD 0: GPI: pull-down resistor disabled
1: GPI: pull-down resistor enabled
0 R/W GPI0_PUPD 0: GPI: pull-down resistor disabled
1: GPI: pull-down resistor enabled Register Bit Type Label Description 0x146 CONFIG_D 7:6 R/W BUCKB_PG_SEL Selection of the PG signal for Buck B 00: none 01: GPO2 10: GPO3 11: reserved 5:4 R/W BUCKA_PG_SEL Selection of the PG signal for Buck A 00: none 01: GPO2 10: GPO3 11: reserved 3:2 R/W READYB_CONF Selection of the READY signal for Buck B 00: none 01: GPO2 10: GPO3 11: reserved 1:0 R/W READYA_CONF Selection of the READY signal for Buck A 00: none 01: GPO2 10: GPO3 11: reserved Register Bit Type Label Description 0x147 CONFIG_E
7 R/W STAND_ALONE
0: DA9213, DA9214, and DA9215 is used as companion IC to DA9063 or DA9063-compliant 1: DA9213, DA9214, and DA9215 is standalone or as companion IC with another PMU not DA9063-compliant 6:5 R/W (reserved)
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 57 Register Bit Type Label Description 4:3 R/W (reserved) 2:0 R/W OSC_TUNE Tune the main 6 MHz oscillator frequency: 000: no tune 001: +180 kHz 010: +360 kHz 011: +540 kHz 100: +720 kHz 101: +900 kHz 110: +1080 kHz 111: +1260 kHz Register Bit Type Label Description 0x148 CONFIG_F 7:4 R/W IF_BASE_ADDR2 If a second I2C address is to be selected on ADR_SEL_CONF, this field configures the second address. 11010000 = 0xD0 write address of PM 2-WIRE interface (page 0 and 1) 11010001 = 0xD1 read address of PM 2-WIRE interface (page 0 and 1) 11010010 = 0xD2 write address of PM-2-WIRE interface (page 2 and 3) 11010011 = 0xD3 read address of PM-2-WIRE interface (page 2 and 3) Code 0000 is reserved for unprogrammed OTP (triggers start-up with hardware default interface address) 3:2 R (reserved)
1 R/W ADDR_SEL_CONF
Selects the GPI for the alternative I2C address selection: 00: none 01: GPI0 10: GPI1 11: GPI4
Figure 32. DA9213/14/15 66 WL-CSP Package Outline Drawing
Figure 33. DA9213/14/15 66 VFBGA Package Outline Drawing
8.1 Package Marking
Figure 34. Package Marking -A and -AT optionally indicate the Automotive and Automotive high temp test options. xx identifies the OTP Variant, vv may be used to show the silicon version.
and availability, please consult your Renesas local sales representative. Table 18. Ordering Information
DA9213, DA9214, DA9215 Datasheet R16DS0598EJ0361 Rev.03.61 Nov 03, 2025 CFR0011-120-00 Page 61 RoHS Compliance Renesas Electronics’ suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from our suppliers are available on request.
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