DA9142_V01 RENESAS | Alldatasheet
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High-Performance, 13 A/20 A Peak, DC-DC Converter R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 1 © 2025 Renesas Electronics The DA9142 is a high efficiency, 13 A continuous and 20 A peak, dual-phase, DC-DC stepdown converter (buck). It is also available as fully AEC- Q100 qualified. With remote sensing, the DA9142 improves output voltage regulation at the point of load. Fully integrated switching FETs means no external FETs or Schottky diodes are needed. A programmable soft startup can be enabled, which limits the inrush current from the input node and secures a slope-controlled rail activation. The dynamic voltage control (DVC) supports adaptive adjustment of the supply voltage dependent on the processor load, via either a direct register write using the communication interface (I2C compatible) or with a programmable input pin. A configurable GPI allows multiple I2C address selection for multiple instances of DA9142 in the same application. DA9142 has integrated over-temperature and over- current protection for increased system reliability, without the need for external sensing components. Key Features ▪ 2.8 V to 5.5 V input voltage ▪ 0.5 V to 1.3 V output voltage ▪ Up to 20 A peak output current, 13 A continuous output current ▪ 4 MHz nominal switching frequency ▪ Dual-phase operation ▪ 110 nH inductor per phase ▪ 110 µF output capacitor ▪ ±1% output voltage accuracy (static) ▪ ±5% load transient ▪ I2C-compatible interface (FM+) ▪ Programmable GPIOs ▪ Programmable soft startup ▪ Voltage, current, and temperature supervision ▪ 60 FC-BGA 4.5 mm x 7 mm (0.65 mm pitch) ▪ 130 mm2 total solution area ▪ Automotive AEC-Q100 qualified also available
Applications
▪ Navigation systems ▪ Telematics ▪ AI engines ▪ Automotive infotainment ▪ Advanced driver assistance systems (ADAS) ▪ SiPP modules
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 2
Contents
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 5 1. Terms and Definitions CPU Central processing unit DDR Dual data rate DVC Dynamic voltage control FET Field effect transistor FM+ Fast mode plus GPI General purpose input GPIO General purpose input/output GPU Graphics processing unit IC Integrated circuit OTP One time programmable PCB Printed circuit board SCL Serial clock SDA Serial data SIPP Single in-line pin package
2.1 Block Diagram
Figure 1. Block Diagram
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 7 3. Pin Information
3.1 Pin Assignments
Noisy groundDigital signal. Noisy Analog signal, Sensitive High Power, Noisy High Power Quiet ground Top view 1 2 3 4 5 A B C D E F G H J K PVDD1 LX1 PGND1 PGND2 LX2 PVDD2 PVDD1 LX1 PGND1 PGND2 LX2 PVDD2 PVDD1 LX1 PGND1 PGND2 LX2 PVDD2 PVDD1 LX1 PGND1 PGND2 LX2 PVDD2 GPIO1 GPIO2 AGND FBP AVDD SCL/ GPIO3 CONF/ GPIO0 AGND IC_EN FBN AVDD SDA/ GPIO4 PVDD3 LX3 PGND3 PGND4 LX4 PVDD4 PVDD3 LX3 PGND3 PGND4 LX4 PVDD4 PVDD3 LX3 PGND3 PGND4 LX4 PVDD4 PVDD3 LX3 PGND3 PGND4 LX4 PVDD4 Figure 2. Pinout Diagram (Top View)
3.2 Pin Descriptions
Table 1. Pin Description
Description
A1, B1, C1, D1 PVDD1 PWR 10000 Supply voltage for buck power stage, decouple with 10 µF and connect to same source as AVDD A2, B2, C2, D2 LX1 AIO 10000 Switch node of buck, connect a 100 nH inductor between LX1 and output capacitor
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 8 Pin Number Pin Name Type (Table 2) Drive (mA) A3, B3, C3, D3 PGND1 GND 10000 Buck power stage GND A4, B4, C4, D4 PGND2 GND 10000 Buck power stage GND A5, B5, C5, D5 LX2 AIO 10000 Switch node of buck, connect a 100 nH inductor between LX2 and output capacitor A6, B6, C6, D6 PVDD2 PWR 10000 Supply voltage for buck power stage, decouple with 10 µF and connect to same source as AVDD E1 GPIO1 DIO 10 General purpose I/O E2 GPIO2 DIO 10 General purpose I/O E3, F2 AGND GND 10 Analog control and auxiliary circuitry GND E4 FBP AI 10 Buck positive node of differential voltage feedback, connect to VOUT1 at point of load E5, F5 AVDD PWR 10 Supply rail for analog control circuitry, decouple with 1 µF and connect to same source as PVDD E6 SCL/GPIO3 DIO 15 I2C clock or general purpose I/O F1 CONF/GPIO0 AI/DIO 10 Chip configuration or general purpose I/O F3 IC_EN AI 10 Powers up I2C control interface and auxiliary circuitry (including bandgap, oscillator, and references) F4 FBN AI 10 Buck negative node of differential voltage feedback, connect to GND at point of load F6 SDA/GPIO4 DIO 15 I2C data or general purpose I/O G1, H1, J1, K1 PVDD3 PWR 10000 Supply voltage for buck power stage, connect to same source as AVDD G2, H2, J2, K2 LX3 AIO 0 Do Not Connect G3, H3, J3, K3 PGND3 GND 10000 Buck power stage VSS rail G4, H4, J4, K4 PGND4 GND 10000 Buck power stage VSS rail G5, H5, J5, K5 LX4 AIO 0 Do Not Connect G6, H6, J6, K6 PVDD4 PWR 10000 Supply voltage for buck power stage, connect to same source as AVDD Table 2. Pin Type Definition
4.1 Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Rating conditions for extended periods may affect device reliability. conditions can adversely impact product reliability and result in failures not covered by warranty. Table 3. Absolute Maximum Ratings
4.2 Electrostatic Discharge Ratings
Table 4. Electrostatic Discharge Ratings Note 1 Increased to 750 V for corner balls.
4.3 Recommended Operating Conditions
Table 5. Recommended Operating Conditions
4.4 Thermal Specifications
Table 6. Package Ratings Note 2 As per Note 1 with addition of aluminum heatsink, 114.3 mm x 101.6 mm x 1.0 mm representing the lid of a case.
4.4.1 Power Derating Curves
Figure 3. Power Derating Curve Table 7. Typical Temperatures
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 11
4.5 Buck1 Characteristics
Unless otherwise noted, the following is valid for TJ = -40 °C to +150 °C, VSYS = 2.8 V to 5.5 V. Table 8: Dual-Phase Buck Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External electrical conditions VIN Input voltage VIN = VSYS = VAVDD 2.8 5.5 V COUT Total output capacitance, including voltage and temperature coefficient Typ 8 x 22 μF -40% to +20% 106 176 211 μF ESRCOUT Output capacitor series resistance, per capacitor f > 100 kHz 3 mΩ L Inductor value, per phase, including current and temperature dependence 88 110 132 nH DCRL Inductor DC resistance 2 mΩ Electrical performance VOUT Output voltage, configurable in 10 mV steps IOUT = 0 mA to IOUT_MAX_PK VOUT_ACC Output voltage accuracy, including static line and load regulation -10 10 mV VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT ≥ 1 V -1 1 % IOUT_MAX_CONT Maximum continuous output current With suitable thermal design 13 A IOUT_MAX_PK Maximum peak output current With suitable thermal design 20 A ILIM Current limit, configureable per phase Note 1 Note 2 14.5 A ILIM_ACC Current limit accuracy Note 2 -20 20 % VTHR_PG_HYS Power-good voltage threshold hysteresis VOUT = VTHR_PG_DWN 70 80 90 mV VTHR_PG_DWN Power-good voltage threshold for falling VOUT = VBUCK -170 -140 -110 mV VTHR_HV High VOUT voltage threshold VOUT = VBUCK 130 160 195 mV VOUT_TR_LINE Line transient response VIN = 3.0 V to 3.6 V VOUT = 1.1 V IOUT = 0.5 * IOUT_MAX_PK dt = 10 μs 10 mV
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 12 Parameter Description Conditions Min Typ Max Unit fSW Switching frequency 4 MHz tON_MIN Minimum turn-on pulse 0% duty is also supported 10 ns tBUCK_EN Turn-on time CH1_EN = high VIN = 3.3 V VOUT = 0.85 V DVC slew rate: 10 mV/8 μs No load Recommended capacitance 600 μs RPD Output pull-down resistance for each phase at the LX node, see CH1_PD_DIS VIN = 3.3 V VOUT = 0.5 V 140 150 160 Ω RON_PMOS On resistance of switching PMOS, per phase VIN = 3.3 V 12 mΩ RON_NMOS On resistance of switching NMOS, per phase VIN = 3.3 V 6 mΩ PWM Mode ηPWM Efficiency, PWM VIN = 3.3 V VOUT = 1.1 V IOUT = 5% (IOUT_MAX_PK) to 80% (IOUT_MAX_PK) 80 % AUTO Mode VOUT_TR_LD_RISE Load transient response, phase shedding enabled VOUT = 1.1 V IOUT = 25% to 75% of IOUT_MAX_PK Load rise time = 1 μs -5 % VOUT_TR_LD_FALL Load transient response, phase shedding enabled VOUT = 1.1 V IOUT = 75% to 25% of IOUT_MAX_PK Load fall time = 1 μs 5 % PFM Mode IQ_PFM_1PH Quiescent current in PFM VIN = 3.3 V No load No switching 120 μA ηPFM Efficiency, PFM VIN = 3.3 V VOUT = 1.1 V IOUT = 100 mA 80 % Note 1 For applications requiring VOUT < 0.75 V contact Renesas applications support for configuration setting Note 2 tON > 40 ns
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4.6 Performance and Supervision Characteristics
Table 9: Performance and Supervision Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance VTHR_POR Power-on-reset threshold Threshold for AVDD falling 2.1 2.25 V VTHR_POR_HYS Power-on-reset hysteresis 200 mV TWARN Temperature warning threshold 120 130 140 °C TCRIT Temperature shutdown threshold 145 155 165 °C IIN_OFF Supply current OFF state TA = 27 °C IC_EN = 0 0.1 1 μA IIN_ON Supply current ON state TA = 27 °C IC_EN = 1 Buck off 5 10 20 μA
4.7 Digital IO Characteristics
Table 10: Digital I/O Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance VIH_EN Input high voltage, IC enable 1.2 AVDD V VIL_EN Input low voltage, IC enable 0.4 V tIC_EN IC enable time 1000 μs VIH_GPIO_SCL_SDA Input high voltage GPIO, SCL, SDA 1.2 AVDD V VIL_GPIO_SCL_SDA Input low voltage GPIO, SCL, SDA 0.4 V VOH_GPIO Output high voltage GPIO Push-pull mode IOUT = 1 mA 0.8*AVDD AVDD V VOL_GPIO Output low voltage GPIO Push-pull mode IOUT = 1 mA 0.2*AVDD V VOL_SDA Output low voltage SDA IOUT = 3 mA 0.24 V RPD GPIO pull-down resistor VSYS = 3.7 V Note 1 9 15 31 kΩ RPU GPIO pull-up resistor VSYS = 3.7 V Note 1 28 45 72 kΩ Note 1 Resistance may have greater variation, depending on voltage and temperature.
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4.8 Timing Characteristics
Table 11: I2C Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance tBUS Bus free time between a STOP and START condition 0.5 μs CBUS Bus line capacitive load 150 pF fSCL SCL clock frequency 20 Note 1 1000 kHz tLO_SCL SCL low time 0.5 μs tHI_SCL SCL high time 0.26 μs tRISE SCL and SDA rise time Requirement for input 1000 ns tFALL SCL and SDA fall time Requirement for input 300 ns tSETUP_START Start condition setup time 0.26 μs tHOLD_START Start condition hold time 0.26 μs tSETUP_STOP Stop condition setup time 0.26 μs tDATA Data valid time 0.45 μs tDATA_ACK Data valid acknowledge time 0.45 μs tSETUP_DATA Data setup time 50 ns tHOLD_DATA Data hold time 0 ns Note 1 Minimum clock frequency is limited to 20 kHz if I2C_TIMEOUT is enabled
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 16 6. Functional Description
6.1 Operating Modes
6.1.1 ON DA9142 is ON when the IC_EN pin is higher than VIH_EN and the supply voltage is higher than VTHR_POR. Once enabled, the host processor can start communicating with DA9142 using the control interface, after the tIC_EN delay.
6.1.2 OFF
DA9142 is OFF when the IC_EN pin is lower than VIL_EN. In OFF, the buck is always disabled and the LX nodes are pulled down by (typically 150 Ω) internal pull-down resistor.
6.2 DC-DC Buck Converter
DA9142 operates as a single-channel, dual-phase buck converter which delivers up to 20 A output current at a 0.5 V to 1.3 V output voltage range. The buck converter has two configurable output voltage settings. One is the normal output voltage (A), the other offers an alternative retention voltage (B). The bits used to configure the outputs are CH1_A_VOUT and CH1_B_VOUT. In this way, different application power modes are supported. The target output voltage (either A or B) is toggled by either GPI or I2C control interface, providing maximum flexibility for the application's host processor. When the buck is enabled, its output voltage is monitored and a power-good signal indicates that the buck output voltage has reached a level higher than the power-good rise threshold. The power-good status is lost when the voltage drops below VTHR_PG_DWN or increases above VTHR_HV. VTHR_PG_HYS is the value that defines the hysteresis between a power-good rise and VTHR_PG_DWN. The status of the power-good indicator is read back via I2C from the PG1 status bit. Alternatively, it can be assigned to any of the GPIOs by setting the GPIO<x>_MODE bits to PG1 output. The buck converter is capable of supporting DVC transitions that occur when: ▪ the active and selected A- or B-voltage is updated to a new target value, using bits CH1_A_VOUT and CH1_B_VOUT ▪ the voltage selection is toggled from the A- to B-voltage (or B- to A-voltage), using bit CH1_VSEL or via GPI control The DVC operates in pulse-width-modulation (PWM) mode with synchronous rectification. The slew rate of the DVC ramp up and ramp down transitions is programmed at 10 mV per (8, 4, 2, 1, or 0.5) µs in register bits CH1_SR_DVC_DWN and CH1_SR_DVC_UP. A pull-down resistor (typically 150 Ω) for each phase is always activated when the buck is disabled, unless it is disabled by setting register bits CH1_PD_DIS to 0x1.
6.2.1 Switching Frequency
The buck switching frequency is tuned using register bit OSC_TUNE. The internal 8 MHz oscillator frequency is tuned in ±160 kHz steps. This impacts the buck converter frequency in steps of 80 kHz and helps to mitigate possible disturbances to other high frequency systems in the application.
6.2.2 Operation Modes and Phase Selection
The buck converter operates in PWM or PFM modes. The operating mode is selected using register bits CH1_A_MODE and CH1_B_MODE. Phase shedding automatically changes between 1- and 2-phase operation at a typical current of 4 A. If the automatic operation mode (Auto mode) is selected, the buck converter automatically changes between synchronous PWM mode and PFM mode depending on the load current. This improves the efficiency across the range of output load currents.
6.2.3 Output Voltage Selection
The switching converter is configured using the I2C interface. options will result in ramped voltage transitions. the output voltage selection is configured via the GPI port to be CH1_B_VOUT. Register bits CH1_VMAX limit the output voltage that can be set. Figure 6. Buck Output Voltage Control Concept
6.2.4 Soft Startup and Shutdown
configured in register CH1_SR_STARTUP. Note: Rates higher than 5 mV/µs may produce overshoot during the startup phase. down), the output node is discharged only by the pull-down resistor, if enabled, in register CH1_PD_DIS.
6.2.5 Current Limit
configured to at least 40% higher than the required maximum per phase output current. Note: This value is loaded from the OTP. over-current events during DVC transitions.
6.2.6 Temperature Protection
DA9142 is protected from internal overheating by temperature-triggered shutdown. thermal limits, an IRQ is raised and an event is set, although the chip continues working. below TWARN and the event flags need to be cleared before starting the bucks.
Table 12. Temperature Protection Control Registers Figure 7. Temperature Protection Operation
6.3 Control Circuits
6.3.1 Chip Enable and Disable
and the buck output is pulled down.
6.3.2 GPIO
6.3.2.1 GPIO Pin Assignment
the GPIO pin assignments are OTP programmable. GPIO4 function as SCL and SDA respectively. Note: GPIO3 and GPIO4 functions are limited only to output features if I2C_EN = 0. Table 13. GPIO Pin Assignment
6.3.2.2 GPIO Function
6.3.2.3 Chip Configuration Select
GPIO0 functions as chip configuration select (CONF) input when enabled as an OTP setting. Three different chip configurations can be selected according to the CONF pin level. ▪ GPIO0 floating: CONF2 - not recommended. Table 14. GPIO0 Configurable Registers when CONF Enabled
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 20 Register Name Description CH1_EN CH1 enable CH1_A_VOUT[7:0] CH1 output voltage setting A CH1_B_VOUT[7:0] CH1 output voltage setting B M_PG1_STAT IRQ mask setting for CH1 power-good status M_VR_HOT IRQ mask setting for temp warning status GPIO1_MODE[3:0] GPIO1 mode setting GPIO2_MODE[3:0] GPIO2 mode setting GPIO1_OBUF GPIO1 output buffer select GPIO2_OBUF GPIO2 output buffer select GPIO1_TRIG[1:0] GPIO1 input trigger select GPIO1_POL GPIO1 polarity select GPIO1_PUPD GPIO1 pull-up/pull-down enable GPIO1_DEB[1:0] GPIO1 input debounce time setting GPIO1_DEB_RISE GPIO1 input debounce rising edge enable GPIO1_DEB_FALL GPIO1 input debounce falling edge enable GPIO2_TRIG[1:0] GPIO2 input trigger select GPIO2_POL GPIO2 polarity select GPIO2_PUPD GPIO2 pull-up/pull-down enable GPIO2_DEB[1:0] GPIO2 input debounce time setting GPIO2_DEB_RISE GPIO2 input debounce rising edge enable GPIO2_DEB_FALL GPIO2 input debounce falling edge enable
6.3.3 Interrupt
interrupt event are listed in Table 15. Table 15. Interrupt List Note 2 Note 2 OTP load value defined by CONF pin setting (if CONF pin enabled).
Table 16. Interrupt Registers Except for Power-Good Status Cleared after being written to I2C. Set until IRQ is removed. 1: Masked. No IRQ signal sent. Event register (E_<name>) is updated. Table 17. Interrupt Registers for Power-Good and Temperature Warning Status It is possible to route interrupts to a GPIO by setting the bitfield GPIO<x>_MODE = 0xC on the relevant GPIO. system-good status is high, and pulled low if an event listed in Table 15 occurs.
- GPIO is cofigured as nIRQ
- M_TEMP_WARN = 0
- M_PG1_STAT = 0 Conditions
Figure 8. Interrupt Operation Example
6.4 I2C Communication
All features of DA9142 can be controlled with the I2C interface, which is enabled or disabled as an OTP setting. Enabled SCL/GPIO3 and SDA/GPIO4 pins are used as I2C clock input and I2C data input/output. GPIO3 functions as the I2C clock (SCL) and GPIO4 carries all the power manager bidirectional I2C data (SDA). (FM+), 400 kHz in fast-mode, or 100 kHz in standard mode.
6.4.1 I2C Protocol
brought high and then low. This pulse on SCL clocks the SDA bit into the receiver’s shift register. SDA line while the SCL is in the high state). Figure 9. I2C START and STOP Condition Timing following clock cycle (white blocks marked with A in Figure 10 and Figure 11). read/write bit, and the eight-bit register address followed by eight bits of data, terminated by a STOP condition. DA9142 responds to all bytes with acknowledge (A), see Figure 10. Figure 10. I2C Byte Write (SDA Line) the host sends no acknowledge (A*) and terminates the transmission with a STOP condition, see Figure 11. address to the register SYS_CFG_SLVADDR, see Table 41.
Figure 11. I2C Byte Read (SDA Line) Examples
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 25 7. Register Definitions
7.1 Register Map
Table 18: Register Map Addr Register 7 6 5 4 3 2 1 0 System Module 0x01 SYS_STATUS_0 Reserved Reserved Reserved Reserved Reserved Reserved 0 TEMP_CRIT TEMP_WARN 0x02 SYS_STATUS_1 Reserved Reserved Reserved Reserved PG1 OV1 UV1 OC1 0x03 SYS_STATUS_2 Reserved Reserved Reserved Reserved Reserved GPIO2 GPIO1 GPIO0 0x04 SYS_EVENT_0 Reserved Reserved Reserved Reserved Reserved Reserved 0 E_TEMP_CRIT E_TEMP_WARN 0x05 SYS_EVENT_1 Reserved Reserved Reserved Reserved E_PG1 E_OV1 E_UV1 E_OC1 0x06 SYS_EVENT_2 Reserved Reserved Reserved Reserved Reserved E_GPIO2 E_GPIO1 E_GPIO0 0x07 SYS_MASK_0 Reserved Reserved Reserved Reserved Reserved Reserved 1 M_TEMP_CRIT M_TEMP_WARN 0x08 SYS_MASK_1 Reserved Reserved Reserved Reserved M_PG1 M_OV1 M_UV1 M_OC1 0x09 SYS_MASK_2 Reserved Reserved Reserved Reserved Reserved M_GPIO2 M_GPIO1 M_GPIO0 0x0A SYS_MASK_3 Reserved Reserved Reserved Reserved M_VR_HOT Reserved 1 Reserved M_PG1_STAT 0x0B SYS_CONFIG_0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x0D SYS_CONFIG_2 Reserved OC_LATCHOFF<1:0> OC_DVC_MASK PG_DVC_MASK<1:0> Reserved Reserved 0x0E SYS_CONFIG_3 Reserved OSC_TUNE<2:0> Reserved Reserved I2C_TIMEOUT Reserved 0 0x10 SYS_GPIO0_0 Reserved Reserved Reserved GPIO0_MODE<3:0> GPIO0_OBUF 0x11 SYS_GPIO0_1 GPIO0_DEB_FALL GPIO0_DEB_RISE GPIO0_DEB<1:0> GPIO0_PUPD GPIO0_POL GPIO0_TRIG<1:0> 0x12 SYS_GPIO1_0 Reserved Reserved Reserved GPIO1_MODE<3:0> GPIO1_OBUF 0x13 SYS_GPIO1_1 GPIO1_DEB_FALL GPIO1_DEB_RISE GPIO1_DEB<1:0> GPIO1_PUPD GPIO1_POL GPIO1_TRIG<1:0> 0x14 SYS_GPIO2_0 Reserved Reserved Reserved GPIO2_MODE<3:0> GPIO2_OBUF 0x15 SYS_GPIO2_1 GPIO2_DEB_FALL GPIO2_DEB_RISE GPIO2_DEB<1:0> GPIO2_PUPD GPIO2_POL GPIO2_TRIG<1:0> 0x16 SYS_GPIO3_0 Reserved Reserved Reserved GPIO3_MODE<3:0> GPIO3_OBUF 0x17 SYS_GPIO3_1 GPIO3_DEB_FALL GPIO3_DEB_RISE GPIO3_DEB<1:0> GPIO3_PUPD GPIO3_POL GPIO3_TRIG<1:0> 0x18 SYS_GPIO4_0 Reserved Reserved Reserved GPIO4_MODE<3:0> GPIO4_OBUF 0x19 SYS_GPIO4_1 GPIO4_DEB_FALL GPIO4_DEB_RISE GPIO4_DEB<1:0> GPIO4_PUPD GPIO4_POL GPIO4_TRIG<1:0>
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 26 Addr Register 7 6 5 4 3 2 1 0 Buck Control Buck1 0x20 BUCK_BUCK1_0 Reserved CH1_SR_DVC_DWN<2:0> CH1_SR_DVC_UP<2:0> CH1_EN 0x21 BUCK_BUCK1_1 Reserved CH1_SR_SHDN<2:0> CH1_SR_STARTUP<2:0> CH1_PD_DIS 0x22 BUCK_BUCK1_2 Reserved Reserved Reserved Reserved CH1_ILIM<3:0> 0x23 BUCK_BUCK1_3 CH1_VMAX<7:0> 0x24 BUCK_BUCK1_4 Reserved Reserved Reserved CH1_VSEL CH1_B_MODE<1:0> CH1_A_MODE<1:0> 0x25 BUCK_BUCK1_5 CH1_A_VOUT<7:0> 0x26 BUCK_BUCK1_6 CH1_B_VOUT<7:0> 0x27 BUCK_BUCK1_7 Reserved Reserved Reserved Reserved Reserved Reserved CH1_RIPPLE_CANCEL<1:0> OTP Control Serialization 0x48 OTP_DEVICE_ID DEV_ID<7:0> 0x49 OTP_VARIANT_ID MRC<3:0> VRC<3:0> 0x4A OTP_CUSTOMER_ID CUST_ID<7:0> 0x4B OTP_CONFIG_ID CONFIG_REV<7:0>
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7.2 Register Descriptions
7.2.1 System
Table 19: SYS_STATUS_0 (0x01) Bit Type Field Name Description [1] R TEMP_CRIT Asserted when the thermal shutdown threshold is reached [0] R TEMP_WARN Asserted when the thermal warning threshold is reached Table 20: SYS_STATUS_1 (0x02) Bit Type Field Name Description [3] R PG1 Asserted when the buck output voltage is in range [2] R OV1 Asserted when the buck exceeds the over-voltage threshold [1] R UV1 Asserted when the buck exceeds the under-voltage threshold [0] R OC1 Asserted when the buck exceeds the over-current threshold Table 21: SYS_STATUS_2 (0x03) Bit Type Field Name Description [2] R GPIO2 GPIO2 input readback status - asserted if the input on GPIO is seen as logic high [1] R GPIO1 GPIO1 input readback status - asserted if the input on GPIO is seen as logic high [0] R GPIO0 GPIO0 input readback status - asserted if the input on GPIO is seen as logic high Table 22: SYS_EVENT_0 (0x04) Bit Type Field Name Description [1] RW1C E_TEMP_CRIT An over-temperature event has occurred. Write 0x1 to reset this bit to 0x0 when the event source has been released. [0] RW1C E_TEMP_WARN A temperature warning event has occurred. Write 0x1 to reset this bit to 0x0 when the event source has been released. Table 23: SYS_EVENT_1 (0x05) Bit Type Field Name Description [3] RW1C E_PG1 PG1 caused event. Write 0x1 to reset this bit to 0x0 when the event source has been released. [2] RW1C E_OV1 OV1 caused event. Write 0x1 to reset this bit to 0x0 when the event source has been released. [1] RW1C E_UV1 UV1 caused event. Write 0x1 to reset this bit to 0x0 when the event source has been released. [0] RW1C E_OC1 OC1 caused event. Write 0x1 to reset this bit to 0x0 when the event source has been released. Table 24: SYS_EVENT_2 (0x06) Bit Type Field Name Description [2] RW1C E_GPIO2 GPIO2 caused event. Write 0x1 to reset this bit to 0x0 when the event source has been released.
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 28 Bit Type Field Name Description [1] RW1C E_GPIO1 GPIO1 caused event. Write 0x1 to reset this bit to 0x0 when the event source has been released. [0] RW1C E_GPIO0 GPIO0 caused event. Write 0x1 to reset this bit to 0x0 when the event source has been released. Table 25: SYS_MASK_0 (0x07) Bit Type Field Name Description [1] RW M_TEMP_CRIT Thermal shutdown can cause an interrupt. Write 0x1 to mask this cause of interrupt. [0] RW M_TEMP_WARN Temperature warning can cause an interrupt. Write 0x1 to mask this cause of interrupt. Table 26: SYS_MASK_1 (0x08) Bit Type Field Name Description [3] RW M_PG1 PG1 event can cause an interrupt. Write 0x1 to mask this cause of interrupt. [2] RW M_OV1 OV1 event can cause an interrupt. Write 0x1 to mask this cause of interrupt. [1] RW M_UV1 UV1 event can cause an interrupt. Write 0x1 to mask this cause of interrupt. [0] RW M_OC1 OC1 event can cause an interrupt. Write 0x1 to mask this cause of interrupt. Table 27: SYS_MASK_2 (0x09) Bit Type Field Name Description [2] RW M_GPIO2 GPIO2 event can cause an interrupt. Write 0x1 to mask this cause of interrupt. [1] RW M_GPIO1 GPIO1 event can cause an interrupt. Write 0x1 to mask this cause of interrupt. [0] RW M_GPIO0 GPIO0 event can cause an interrupt. Write 0x1 to mask this cause of interrupt. Table 28: SYS_MASK_3 (0x0A) Bit Type Field Name Description [3] RW M_VR_HOT Temperature warning status IRQ mask. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) [0] RW M_PG1_STAT PG1 status IRQ mask. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Table 29: SYS_CONFIG_2 (0x0D) Bit Type Field Name Description [6:5] RW OC_LATCHOFF Over-current latch-off time (Debounce duration). Buck shuts down after over-current persists for 8 µs, 1 ms or 3 ms unless setting is disabled setting. An IRQ is generated unless masked. Value Description 0x0 Latch off disable 0x1 Latch off after 8 µs
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 29 Bit Type Field Name Description 0x2 Latch off after 1 ms 0x3 Latch off after 3 ms [4] RW OC_DVC_MASK Over-current event mask during DVC ramp-up and ramp-down. Write 0x1 to mask over-current during DVC causing IRQ and LATCHOFF. [3:2] RW PG_DVC_MASK Power good mask during DVC Value Description 0x0 No mask 0x1 Mask as not power good 0x2 Mask as power good 0x3 Reserved Table 30: SYS_CONFIG_3 (0x0E) Bit Type Field Name Description [6:4] RW OSC_TUNE Tune oscillator frequency, tuned frequency = current frequency + OSC_TUNE * 160 kHz Value Description 0x3 3 0x2 2 0x1 1 0x0 0 0x7 -1 0x6 -2 0x5 -3 0x4 -4 [1] RW I2C_TIMEOUT Enable automatic reset of 2 wire interface (if SDA stays low for > 50 ms). Table 31: SYS_GPIO0_0 (0x10) Bit Type Field Name Description [4:1] RW GPIO0_MODE GPIO function mode select Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 Reserved 0x3 EN1 input 0x4 DVC1 input 0x5 Reserved 0x6 DVC1 input 0x7 RELOAD input 0x8 PG1 output 0x9 Low output
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 30 Bit Type Field Name Description 0xA Low output 0xB PG1 output 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] RW GPIO0_OBUF GPIO output buffer select Value Description 0x0 open-drain output 0x1 push-pull output Table 32: SYS_GPIO0_1 (0x11) Bit Type Field Name Description [7] RW GPIO0_DEB_FALL GPI debounce falling edge [6] RW GPIO0_DEB_RISE GPI debounce rising edge [5:4] RW GPIO0_DEB GPI debounce time Value Description 0x0 100 µs debounce 0x1 1 ms debounce 0x2 10 ms debounce 0x3 100 ms debounce [3] RW GPIO0_PUPD GPIO pull-up/pull-down enable Value Description 0x0 GPI: pull-down disabled, GPO: pull-up to AVDD disabled 0x1 GPI: pull-down enabled, GPO: pull-up to AVDD enabled [2] RW GPIO0_POL GPIO polarity Value Description 0x0 GPIO is active-high 0x1 GPIO is active-low [1:0] RW GPIO0_TRIG GPI trigger type Value Description 0x0 Dual-edge triggered 0x1 Positive-edge triggered 0x2 Negative-edge triggered 0x3 Reserved (No trigger)
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 31 Table 33: SYS_GPIO1_0 (0x12) Bit Type Field Name Description [4:1] RW GPIO1_MODE GPIO function mode select. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 Reserved 0x3 EN1 input 0x4 DVC1 input 0x5 Reserved 0x6 DVC1 input 0x7 RELOAD input 0x8 PG1 output 0x9 Low output 0xA Low output 0xB PG1 output 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] RW GPIO1_OBUF GPIO output buffer select. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting). Value Description 0x0 open-drain output 0x1 push-pull output Table 34: SYS_GPIO1_1 (0x13) Bit Type Field Name Description [7] RW GPIO1_DEB_FALL GPI debounce falling edge. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) [6] RW GPIO1_DEB_RISE GPI debounce rising edge. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) [5:4] RW GPIO1_DEB GPI debounce time. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 100 µs debounce 0x1 1 ms debounce 0x2 10 ms debounce 0x3 100 ms debounce [3] RW GPIO1_PUPD GPIO pull-up/pull-down enable. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting)
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 32 Bit Type Field Name Description Value Description 0x0 GPI: pull-down disabled, GPO: pull-up to AVDD disabled 0x1 GPI: pull-down enabled, GPO: pull-up to AVDD enabled [2] RW GPIO1_POL GPIO polarity. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 GPIO is active-high 0x1 GPIO is active-low [1:0] RW GPIO1_TRIG GPI trigger type. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 Dual-edge triggered 0x1 Positive-edge triggered 0x2 Negative-edge triggered 0x3 Reserved (No trigger) Table 35: SYS_GPIO2_0 (0x14) Bit Type Field Name Description [4:1] RW GPIO2_MODE GPIO function mode select. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 Reserved 0x3 EN1 input 0x4 DVC1 input 0x5 Reserved 0x6 DVC1 input 0x7 RELOAD input 0x8 PG1 output 0x9 Low output 0xA Low output 0xB PG1 output 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] RW GPIO2_OBUF GPIO output buffer select. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting)
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 33 Bit Type Field Name Description Value Description 0x0 open-drain output 0x1 push-pull output Table 36: SYS_GPIO2_1 (0x15) Bit Type Field Name Description [7] RW GPIO2_DEB_FALL GPI debounce falling edge. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) [6] RW GPIO2_DEB_RISE GPI debounce rising edge. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) [5:4] RW GPIO2_DEB GPI debounce time. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 100 µs debounce 0x1 1 ms debounce 0x2 10 ms debounce 0x3 100 ms debounce [3] RW GPIO2_PUPD GPIO pull-up/pull-down enable. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 GPI: pull-down disabled, GPO: pull-up to AVDD disabled 0x1 GPI: pull-down enabled, GPO: pull-up to AVDD enabled [2] RW GPIO2_POL GPIO polarity. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 GPIO is active-high 0x1 GPIO is active-low [1:0] RW GPIO2_TRIG GPI trigger type. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 Dual-edge triggered 0x1 Positive-edge triggered 0x2 Negative-edge triggered 0x3 Reserved (No trigger) Table 37: SYS_GPIO3_0 (0x16) Bit Type Field Name Description [4:1] R GPIO3_MODE GPIO function mode select Value Description 0x0 GPIO disable
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 34 Bit Type Field Name Description 0x1 EN1 input 0x2 Reserved 0x3 EN1 input 0x4 DVC1 input 0x5 Reserved 0x6 DVC1 input 0x7 RELOAD input 0x8 PG1 output 0x9 Low output 0xA Low output 0xB PG1 output 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] R GPIO3_OBUF GPIO output buffer select Value Description 0x0 open-drain output 0x1 push-pull output Table 38: SYS_GPIO3_1 (0x17) Bit Type Field Name Description [7] R GPIO3_DEB_FALL GPI debounce falling edge [6] R GPIO3_DEB_RISE GPI debounce rising edge [5:4] R GPIO3_DEB GPI debounce time Value Description 0x0 100 µs debounce 0x1 1 ms debounce 0x2 10 ms debounce 0x3 100 ms debounce [3] R GPIO3_PUPD GPIO pull-up/pull-down enable Value Description 0x0 GPI: pull-down disabled, GPO: pull-up to AVDD disabled 0x1 GPI: pull-down enabled, GPO: pull-up to AVDD enabled [2] R GPIO3_POL GPIO polarity Value Description 0x0 GPIO is active-high 0x1 GPIO is active-low
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 35 Bit Type Field Name Description [1:0] R GPIO3_TRIG GPI trigger type Value Description 0x0 Dual-edge triggered 0x1 Positive-edge triggered 0x2 Negative-edge triggered 0x3 Reserved (No trigger) Table 39: SYS_GPIO4_0 (0x18) Bit Type Field Name Description [4:1] R GPIO4_MODE GPIO function mode select Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 Reserved 0x3 EN1 input 0x4 DVC1 input 0x5 Reserved 0x6 DVC1 input 0x7 RELOAD input 0x8 PG1 output 0x9 Low output 0xA Low output 0xB PG1 output 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] R GPIO4_OBUF GPIO output buffer select Value Description 0x0 open-drain output 0x1 push-pull output Table 40: SYS_GPIO4_1 (0x19) Bit Type Field Name Description [7] R GPIO4_DEB_FALL GPI debounce falling edge [6] R GPIO4_DEB_RISE GPI debounce rising edge [5:4] R GPIO4_DEB GPI debounce time Value Description 0x0 100 µs debounce 0x1 1 ms debounce
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 36 Bit Type Field Name Description 0x2 10 ms debounce 0x3 100 ms debounce [3] R GPIO4_PUPD GPIO pull-up/pull-down enable Value Description 0x0 GPI: pull-down disabled, GPO: pull-up to AVDD disabled 0x1 GPI: pull-down enabled, GPO: pull-up to AVDD enabled [2] R GPIO4_POL GPIO polarity Value Description 0x0 GPIO is active-high 0x1 GPIO is active-low [1:0] R GPIO4_TRIG GPI trigger type Value Description 0x0 Dual-edge triggered 0x1 Positive-edge triggered 0x2 Negative-edge triggered 0x3 Reserved (No trigger) Table 41: SYS_CFG_SLVADDR (0xA1) Bit Type Symbol Description [6:0] RW I2C_SLAVE_ADDR Slave address of the device.
7.2.2 Buck1
Table 42: BUCK_BUCK1_0 (0x20) Bit Type Field Name Description [6:4] RW CH1_SR_DVC_DWN Voltage slew-rate for DVC ramp-down Value Description 0x0 10 mV / 8 µs 0x1 10 mV / 4 µs 0x2 10 mV / 2 µs 0x3 10 mV / 1 µs 0x4 20 mV / 1 µs 0x5 Reserved 0x6 Reserved 0x7 Reserved [3:1] RW CH1_SR_DVC_UP Voltage slew-rate for DVC ramp-up Value Description 0x0 10 mV / 8 µs 0x1 10 mV / 4 µs 0x2 10 mV / 2 µs
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 37 Bit Type Field Name Description 0x3 10 mV / 1 µs 0x4 20 mV / 1 µs 0x5 40 mV / 1 µs 0x6 Reserved 0x7 Reserved [0] RW CH1_EN Channel enable. Write 0x1 to enable the buck. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Table 43: BUCK_BUCK1_1 (0x21) Bit Type Field Name Description [6:4] RW CH1_SR_SHDN Voltage slew-rate during shut-down Value Description 0x0 10 mV / 8 µs 0x1 10 mV / 4 µs 0x2 10 mV / 2 µs 0x3 10 mV / 1 µs 0x4 20 mV / 1 µs 0x5 Reserved 0x6 Reserved 0x7 Immediate power-down [3:1] RW CH1_SR_STARTUP Voltage slew-rate during start-up Value Description 0x0 10 mV / 8 µs 0x1 10 mV / 4 µs 0x2 10 mV / 2 µs 0x3 10 mV / 1 µs 0x4 20 mV / 1 µs 0x5 40 mV / 1 µs 0x6 Reserved 0x7 Reserved [0] RW CH1_PD_DIS LX Pull down while BUCK is off. Write 0x1 to disable this function. Table 44: BUCK_BUCK1_2 (0x22) Bit Type Field Name Description [3:0] RW CH1_ILIM Select OCP threshold (A) Value Description 0x0 Reserved 0x1 6.5 0x2 7.5
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 38 Bit Type Field Name Description 0x3 8.5 0x4 9.5 0x5 10.5 0x6 11.5 0x7 12.5 0x8 13.5 0x9 14.5 0xA 15.5 0xB 16.5 0xC 17.5 0xD 18.5 0xE 19.5 0xF Disable Table 45: BUCK_BUCK1_3 (0x23) Bit Type Field Name Description [7:0] R CH1_VMAX VOUT max setting (V): From 0.50 V (0x32) to 1.30 V (0x82) in steps of 10 mV This is a read-only register. Value Description 0x00 Reserved 0x31 Reserved 0x32 0.5 0x33 0.51 ... +0.01 steps 0x63 0.99 0x64 1 0x65 1.01 ... +0.01 steps 0x81 1.29 0x82 1.3 0x83 Reserved 0xFF Reserved Table 46: BUCK_BUCK1_4 (0x24) Bit Type Field Name Description [4] RW CH1_VSEL Output voltage and operation selection: 0: A, 1: B. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) [3:2] RW CH1_B_MODE Operation mode selection. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting)
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 39 Bit Type Field Name Description Value Description 0x0 Force PFM operation 0x1 Force PWM operation (full phase) 0x2 Force PWM operation (with phase shedding) 0x3 Auto mode [1:0] RW CH1_A_MODE Operation mode selection. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 Force PFM operation 0x1 Force PWM operation (full phase) 0x2 Force PWM operation (with phase shedding) 0x3 Auto mode Table 47: BUCK_BUCK1_5 (0x25) Bit Type Field Name Description [7:0] RW CH1_A_VOUT Output voltage setting A: Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) From 0.50 V (0x32) to 1.30 V (0x82) in steps of 10 mV Value Description 0x00 Reserved 0x31 Reserved 0x32 0.5 0x33 0.51 ... +0.01 steps 0x63 0.99 0x64 1 0x65 1.01 ... +0.01 steps 0x81 1.29 0x82 1.3 0x83 Reserved 0xFF Reserved Table 48: BUCK_BUCK1_6 (0x26) Bit Type Field Name Description [7:0] RW CH1_B_VOUT Output voltage setting B: Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) From 0.50 V (0x32) to 1.30 V (0x82) in steps of 10 mV Value Description 0x00 Reserved 0x31 Reserved
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 40 Bit Type Field Name Description 0x32 0.5 0x33 0.51 ... +0.01 steps 0x63 0.99 0x64 1 0x65 1.01 ... +0.01 steps 0x81 1.29 0x82 1.3 0x83 Reserved 0xFF Reserved Table 49: BUCK_BUCK1_7 (0x27) Bit Type Field Name Description [1:0] RW CH1_RIPPLE_CANCEL Ripple cancel control Value Description 0x0 No ripple cancel 0x1 Small ripple cancel 0x2 Mid ripple cancel 0x3 Large ripple cancel
7.2.3 OTP Control
7.2.3.1 Serialization
Table 50: OTP_DEVICE_ID (0x48) Bit Type Field Name Description [7:0] R DEV_ID Device ID; hard-coded or metal-programmed Table 51: OTP_VARIANT_ID (0x49) Bit Type Field Name Description [7:4] R MRC Mask Revision Code [3:0] R VRC Chip Variant Code; e.g. package variants. Table 52: OTP_CUSTOMER_ID (0x4A) Bit Type Field Name Description [7:0] R CUST_ID Customer ID Table 53: OTP_CONFIG_ID (0x4B) Bit Type Field Name Description [7:0] R CONFIG_REV OTP settings revision
- Moisture Sensitivity Level
MSL classification is defined in Table 54. The DA9142 package is qualified for MSL 3. Table 54. MSL Classification
8.1 Soldering Information
downloaded from http://www.jedec.org.
9.1 Package Outline
Figure 12. Package Outline Drawing
9.2 Package Marking
Figure 13. Chip Marking Details -A optionally indicate the Automotive test options.
and availability, please consult your Renesas local sales representative. Table 55. Ordering Information for Consumer/Industrial Applications Table 56. Ordering Information for Automotive Applications
10.1 Variants Ordering Information
actual variant number. Please contact your Renesas local sales representative to discuss requirements.
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 45 11. Application Information
11.1 Capacitor Selection
Ceramic capacitors are used as bypass capacitors at all VDD and output rails. When selecting a capacitor, especially for types with high capacitance at smallest physical dimension, the DC bias characteristic has to be taken into account. Table 57: Recommended Non-Automotive-Grade Capacitor Types Application Value (µF) Size Temp. Char. Note 1 Tol. (%) V-Rate (V) Type VOUT output bypass 22 1206 X7R ±20 6.3 Murata GRM31CR70J226ME19L 22 0805 X7T ±20 6.3 Murata GRM21BD70J226ME44L PVDDx bypass 10 0805 X7S ±10 16 Murata GRM21BC71C106KE11L 10 0603 X6S ±20 16 Murata GRM188C81C106MA73D PVDDx bypass for VSYS < 4V 10 0603 X7T ±20 6.3 Murata GRM188D70J106MA73D 10 0402 X6S ±20 6.3 Murata GRM155C80J106ME18D AVDD bypass 1 0805 X7R ±10 50 Murata GRM21BR71H105KA12L 1 0603 X7T ±10 50 Murata GRM188D71H105KE01D Note 1 Select suitable Temperature Characteristics for the expected operating conditions. Table 58: Recommended Automotive-Grade Capacitor Types Application Value (µF) Size Temp. Char. Tol. (%) V-Rate (V) Type VOUT output bypass 22 1206 X7R ±20 6.3 Murata GCM31CR70J226ME23L PVDDx bypass 10 0805 X7S ±10 16 Murata GCM21BC71C106KE36L PVDDx bypass for VSYS < 4V 10 0603 X7T ±20 6.3 Murata GCM188D70J106ME36L AVDD bypass 1 0805 X7R ±10 50 Murata GCM21BR71H105KA03L
11.2 Inductor Selection
Inductors should be selected based on the following parameters: ▪ Rated maximum current and ISAT ISAT specifies the maximum current at which the inductance drops by 30% of the nominal value, and IMAX is defined by the maximum power dissipation and is applied to the effective current at 40 °C temperature rise. ▪ DC resistance Critical for the converter efficiency and should therefore be minimized. Table 59: Recommended Inductor Types Value (nH) Size (mm) IMAX (DC) (A) ISAT (A) Tol. (%) DC Resistance (mΩ) Type 112 3.2 x 2.5 x 2.5 20 31 20 1.9 TDK CLT3225AR11MI3 110 4.0 x 4.0 x 2.1 29 29 20 1.4 Coilcraft XGL4020-111MEC
Figure 14. DA9142 Footprint
R16DS0592EG0301 Rev.03.01 Oct 17, 2025 CFR0011-120-00 Page 47 RoHS Compliance Renesas Electronics’ suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from our suppliers are available on request.
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