DA9142

Renesas Technology Corp

High-Performance, 13 A/20 A Peak, DC-DC Converter 28-Jan-2022

Manufacturer: Renesas Technology Corp

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DA9142 RENESAS | Alldatasheet

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High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 1 of 51 © 2022 Renesas Electronics General Description The DA9142 is a high efficiency, 13 A continuous and 20 A peak, dual-phase, DC-DC stepdown converter (buck). It is also available as fully AEC-Q100 qualified. With remote sensing, the DA9142 improves output voltage regulation at the point of load. Fully integrated switching FETs means no external FETs or Schottky diodes are n eeded. A programmable soft startup can be enabled, which limits the inrush current from the input node and secures a slope-controlled rail activation. The dynamic voltage control (DVC) supports adaptive adjustment of the supply voltage dependent on the processor load, via either a direct register write using the communication interface (I 2C compatible) or with a programmable input pin. A configurable GPI allows multiple I2C address selection for multiple instances of DA9142 in the same application. DA9142 has integrated over-temperature and over-current protection for increased system reliability, without the need for external sensing components. Key Features ■ 2.8 V to 5.5 V input voltage ■ 0.5 V to 1.3 V output voltage ■ Up to 20 A peak output current, 13 A continuous output current ■ 4 MHz nominal switching frequency ■ Dual-phase operation ■ 110 nH inductor per phase ■ 110 µF output capacitor ■ ±1 % output voltage accuracy (static) ■ ±5 % load transient ■ I2C-compatible interface (FM+) ■ Programmable GPIOs ■ Programmable soft startup ■ Voltage, current, and temperature supervision ■ 60 FC-BGA 4.5 mm x 7 mm (0.65 mm pitch) ■ 130 mm2 total solution area ■ Automotive AEC-Q100 qualified also available

Applications

■ Navigation systems ■ Telematics ■ AI engines ■ Automotive infotainment ■ Advanced driver assistance systems (ADAS) ■ SiPP modules

1 Terms and Definitions

CPU Central processing unit DDR Dual data rate DVC Dynamic voltage control FET Field effect transistor FM+ Fast mode plus GPI General purpose input GPIO General purpose input/output GPU Graphics processing unit IC Integrated circuit OTP One time programmable PCB Printed circuit board SCL Serial clock SDA Serial data SIPP Single in-line pin package

2 Block Diagram

Register MapIC_EN CONF/GPIO0 GPIO1 GPIO2 SCL/GPIO3 SDA/GPIO4 FB1P 5 x 22 µF 110 nH PGND1-2 FB1N 110 nH AGND VOUT1 = 0.3 V to 1.3 V 1 µF 2x 10 µF VDD = 2.8 V to 5.5 V Bias Supervision Oscillator I2C GPIO PVDD1-2AVDD Figure 1: Block Diagram

3 Pinout

Noisy groundDigital signal. Noisy Analog signal, Sensitive High Power, Noisy High Power Quiet ground Top view 1 2 3 4 5 A B C D E F G H J K PVDD1 LX1 PGND1 PGND2 LX2 PVDD2 PVDD1 LX1 PGND1 PGND2 LX2 PVDD2 PVDD1 LX1 PGND1 PGND2 LX2 PVDD2 PVDD1 LX1 PGND1 PGND2 LX2 PVDD2 GPIO1 GPIO2 AGND FBP AVDD SCL/ GPIO3 CONF/ GPIO0 AGND IC_EN FBN AVDD SDA/ GPIO4 PVDD3 LX3 PGND3 PGND4 LX4 PVDD4 PVDD3 LX3 PGND3 PGND4 LX4 PVDD4 PVDD3 LX3 PGND3 PGND4 LX4 PVDD4 PVDD3 LX3 PGND3 PGND4 LX4 PVDD4 Figure 2: Pinout Diagram (Top View) Table 1: Pin Description Pin # Pin Name Type (Table 2) Drive (mA)

Description

A1, B1, C1, D1 PVDD1 PWR 10000 Supply voltage for buck power stage, decouple with 10 µF and connect to same source as AVDD A2, B2, C2, D2 LX1 AIO 10000 Switch node of buck, connect a 100 nH inductor between LX1 and output capacitor A3, B3, C3, D3 PGND1 GND 10000 Buck power stage GND

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 8 of 51 © 2022 Renesas Electronics Pin # Pin Name Type (Table 2) Drive (mA) A4, B4, C4, D4 PGND2 GND 10000 Buck power stage GND A5, B5, C5, D5 LX2 AIO 10000 Switch node of buck, connect a 100 nH inductor between LX2 and output capacitor A6, B6, C6, D6 PVDD2 PWR 10000 Supply voltage for buck power stage, decouple with 10 µF and connect to same source as AVDD E1 GPIO1 DIO 10 General purpose I/O E2 GPIO2 DIO 10 General purpose I/O E3, F2 AGND GND 10 Analog control and auxiliary circuitry GND E4 FBP AI 10 Buck positive node of differential voltage feedback, connect to VOUT1 at point of load E5, F5 AVDD PWR 10 Supply rail for analog control circuitry, decouple with 1 µF and connect to same source as PVDD E6 SCL/GPIO3 DIO 15 I2C clock or general purpose I/O F1 CONF/GPIO0 AI/DIO 10 Chip configuration or general purpose I/O F3 IC_EN AI 10 Powers up I2C control interface and auxiliary circuitry (including bandgap, oscillator, and references) F4 FBN AI 10 Buck negative node of differential voltage feedback, connect to GND at point of load F6 SDA/GPIO4 DIO 15 I2C data or general purpose I/O G1, H1, J1, K1 PVDD3 PWR 10000 Supply voltage for buck power stage, connect to same source as AVDD G2, H2, J2, K2 LX3 AIO 0 Do Not Connect G3, H3, J3, K3 PGND3 GND 10000 Buck power stage VSS rail G4, H4, J4, K4 PGND4 GND 10000 Buck power stage VSS rail G5, H5, J5, K5 LX4 AIO 0 Do Not Connect G6, H6, J6, K6 PVDD4 PWR 10000 Supply voltage for buck power stage, connect to same source as AVDD Table 2: Pin Type Definition Pin Type Description Pin Type Description DI Digital input AI Analog input DO Digital output AO Analog output DIO Digital input/output AIO Analog input/output PWR Power GND Ground

4 Characteristics

4.1 Absolute Maximum Ratings

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Note: Values are preliminary, pending final silicon characterization results. Table 3: Absolute Maximum Ratings Parameter Description Conditions Min Max Unit TSTG Storage temperature -65 150 °C TJ Junction temperature -40 150 °C VSYS System supply voltage -0.3 6.0 V VPIN Voltage on pins -0.3 6.0 V

4.2 Electrostatic Discharge Ratings

Note: Values are preliminary, pending final silicon characterization results. Table 4: Electrostatic Discharge Ratings Parameter Description Conditions Value Unit ESDHBM Maximum ESD protection Human body model (HBM) All exposed pins 2 kV ESDCDM Maximum ESD protection Charged device model (CDM) 500 (Note 1) V Note 1 Increased to 750 V for corner balls.

4.3 Recommended Operating Conditions

Note: Values are preliminary, pending final silicon characterization results. Table 5: Recommended Operating Conditions Parameter Description Conditions Min Typ Max Unit VSYS System supply voltage 2.8 5.5 V VPIN Voltage on pins -0.3 VSYS + 0.3 V TJ Junction temperature -40 150 °C TA Ambient temperature -40 125 °C

4.4 Thermal Characteristics

Note: Values are preliminary, pending final silicon characterization results. Table 6: Package Ratings Parameter Description Conditions Min Typ Max Unit JA Thermal resistance junction to ambient No heatsink Note 1 16.4 °C/W With heatsink Note 2 9.6 °C/W JB Thermal resistance junction to board Note 1 9.2 °C/W JC Thermal resistance junction to case Note 1 7.0 °C/W PD Maximum power dissipation No heatsink Derating factor above TA = 85°C: 60.9 mW/°C (1/JA) 3660 4270 mW With heatsink Derating factor above TA = 85°C:104.1 mW/°C (1/JA) 6250 7290 mW Note 1 Obtained from package thermal simulations, JEDEC 2S2P four-layer board (114.3 mm x 101.6 mm x 1.6 mm), 70 μm (2 oz) copper thickness power planes, 35 μm (1 oz) copper thickness signal layer traces, natural convection (still air) Note 2 As per Note 1 with addition of aluminium heatsink, 114.3 mm x 101.6 mm x 1.0 mm representing the lid of a case.

4.4.1 Power Derating Curves

Figure 3: Power Derating Curve Table 7: Typical Temperatures TA = 85 °C TA = 105 °C TA = 125 °C TJ_WARN PD = 2.74 W PD = 1.52 W PD = 0.30 W TJ_CRIT_WC PD = 3.66 W PD = 2.44 W PD = 1.22 W

4.5 Buck1 Characteristics

Unless otherwise noted, the following is valid for TJ = -40 °C to +150 °C, VSYS = 2.8 V to 5.5 V. Note: Values are preliminary, pending final silicon characterization results. Table 8: Dual-Phase Buck Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External Electrical Conditions VIN Input voltage VIN = VSYS = VAVDD 2.8 5.5 V COUT Total output capacitance, including voltage and temperature coefficient Typ 8 x 22 μF -40 % to +20 % 106 176 211 μF

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 12 of 51 © 2022 Renesas Electronics Parameter Description Conditions Min Typ Max Unit ESRCOUT Output capacitor series resistance, per capacitor f > 100 kHz 3 mΩ L Inductor value, per phase, including current and temperature dependence 88 110 132 nH DCRL Inductor DC resistance 2 mΩ Electrical Performance VOUT Output voltage, configurable in 10 mV steps IOUT = 0 mA to IOUT_MAX_PK VOUT_ACC Output voltage accuracy, including static line and load regulation -10 10 mV VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT ≥ 1 V -1 1 % IOUT_MAX_CONT Maximum continuous output current With suitable thermal design 13 A IOUT_MAX_PK Maximum peak output current With suitable thermal design 20 A ILIM Current limit, configureable per phase Note 1 Note 2 14.5 A ILIM_ACC Current limit accuracy Note 2 -20 20 % VTHR_PG_HYS Power-good voltage threshold hysteresis VOUT = VTHR_PG_DWN 70 80 90 mV VTHR_PG_DWN Power-good voltage threshold for falling VOUT = VBUCK -170 -140 -110 mV

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 13 of 51 © 2022 Renesas Electronics Parameter Description Conditions Min Typ Max Unit VTHR_HV High VOUT voltage threshold VOUT = VBUCK 130 160 195 mV VOUT_TR_LINE Line transient response VIN = 3.0 V to 3.6 V VOUT = 1.1 V IOUT = 0.5 * IOUT_MAX_PK dt = 10 μs 10 mV fSW Switching frequency 4 MHz tON_MIN Minimum turn-on pulse 0 % duty is also supported 10 ns tBUCK_EN Turn-on time CH1_EN = high VIN = 3.3 V VOUT = 0.85 V DVC slew rate: 10 mV/8 μs No load Recommended capacitance 600 μs RPD Output pull-down resistance for each phase at the LX node, see CH1_PD_DIS VIN = 3.3 V VOUT = 0.5 V 140 150 160 Ω RON_PMOS On resistance of switching PMOS, per phase VIN = 3.3 V 12 mΩ RON_NMOS On resistance of switching NMOS, per phase VIN = 3.3 V 6 mΩ PWM Mode ηPWM Efficiency, PWM VIN = 3.3 V VOUT = 1.1 V IOUT = 5 % (IOUT_MAX_PK) to 80 % (IOUT_MAX_PK) 80 % AUTO Mode VOUT_TR_LD_RISE Load transient response, phase shedding enabled VOUT = 1.1 V IOUT = 25 % to 75 % of IOUT_MAX_PK Load rise time = 1 μs -5 % VOUT_TR_LD_FALL Load transient response, phase shedding enabled VOUT = 1.1 V IOUT = 75 % to 25 % of IOUT_MAX_PK Load fall time = 1 μs 5 %

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 14 of 51 © 2022 Renesas Electronics Parameter Description Conditions Min Typ Max Unit PFM Mode IQ_PFM_1PH Quiescent current in PFM VIN = 3.3 V No load No switching 120 μA ηPFM Efficiency, PFM VIN = 3.3 V VOUT = 1.1 V IOUT = 100 mA 80 % Note 1 For applications requiring VOUT < 0.75 V contact Renesas applications support for configuration setting Note 2 tON > 40 ns

4.6 Performance and Supervision Characteristics

Note: Values are preliminary, pending final silicon characterization results. Table 9: Performance and Supervision Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical Performance VTHR_POR Power-on-reset threshold Threshold for AVDD falling 2.1 2.25 V VTHR_POR_HYS Power-on-reset hysteresis 200 mV TWARN Temperature warning threshold 120 130 140 °C TCRIT Temperature shutdown threshold 145 155 165 °C IIN_OFF Supply current OFF state TA = 27 °C IC_EN = 0 0.1 1 μA IIN_ON Supply current ON state TA = 27 °C IC_EN = 1 Buck off 5 10 20 μA

4.7 Digital IO Characteristics

Note: Values are preliminary, pending final silicon characterization results. Table 10: Digital I/O Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical Performance VIH_EN Input high voltage, IC enable 1.2 AVDD V VIL_EN Input low voltage, IC enable 0.4 V tIC_EN IC enable time 1000 μs VIH_GPIO_SCL_SDA Input high voltage GPIO, SCL, SDA 1.2 AVDD V VIL_GPIO_SCL_SDA Input low voltage GPIO, SCL, SDA 0.4 V VOH_GPIO Output high voltage GPIO Push-pull mode IOUT = 1 mA 0.8*AV DD AVDD V VOL_GPIO Output low voltage GPIO Push-pull mode IOUT = 1 mA 0.2*AV DD V

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 16 of 51 © 2022 Renesas Electronics Parameter Description Conditions Min Typ Max Unit VOL_SDA Output low voltage SDA IOUT = 3 mA 0.24 V RPD GPIO pull-down resistor 2 10 120 kΩ RPU GPIO pull-up resistor 2 10 120 kΩ

4.8 Timing Characteristics

Note: Values are preliminary, pending final silicon characterization results. Table 11: I2C Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical Performance tBUS Bus free time between a STOP and START condition 0.5 μs CBUS Bus line capacitive load 150 pF fSCL SCL clock frequency 20 Note 1 1000 kHz tLO_SCL SCL low time 0.5 μs tHI_SCL SCL high time 0.26 μs tRISE SCL and SDA rise time Requirement for input 1000 ns tFALL SCL and SDA fall time Requirement for input 300 ns tSETUP_START Start condition setup time 0.26 μs tHOLD_START Start condition hold time 0.26 μs tSETUP_STOP Stop condition setup time 0.26 μs tDATA Data valid time 0.45 μs tDATA_ACK Data valid acknowledge time 0.45 μs tSETUP_DATA Data setup time 50 ns tHOLD_DATA Data hold time 0 ns Note 1 Minimum clock frequency is limited to 20 kHz if I2C_TIMEOUT is enabled

4.9 Typical Performance

The static efficiency measurement plots depicted in Figure 4 and Figure 5 are performed at 25°C in a temperature-controlled environment. A continuous load was used for the measurements. Figure 4: DA9142 Efficiency, PWM Mode without Phase Shedding Figure 5: DA9142 Efficiency, Auto Mode with Phase Shedding

5 Functional Description

5.1 Operating Modes

5.1.1 ON DA9142 is ON when the IC_EN pin is higher than VIH_EN and the supply voltage is higher than VTHR_POR. Once enabled, the host processor can start communicating with DA9142 using the control interface, after the tIC_EN delay.

5.1.2 OFF

DA9142 is OFF when the IC_EN pin is lower than VIL_EN. In OFF, the buck is always disabled and the LX nodes are pulled down by a (typically 150 Ω) internal pull-down resistor.

5.2 DC-DC Buck Converter

DA9142 operates as a single-channel, dual-phase buck converter which delivers up to 20 A output current at a 0.5 V to 1.3 V output voltage range. The buck converter has two configurable output voltage settings. One is the normal output voltage (A), the other offers an alternative retention voltage (B). The bits used to configure the outputs are CH1_A_VOUT and CH1_B_VOUT. In this way, different application power modes are supported. The target output voltage (either A or B) is toggled by either GPI or I2C control interface, providing maximum flexibility for the application's host processor. When the buck is enabled, its output voltage is monitored and a power-good signal indicates that the buck output voltage has reached a level higher than the power-good rise threshold. The power-good status is lost when the voltage drops below VTHR_PG_DWN or increases above VTHR_HV. VTHR_PG_HYS is the value that defines the hysteresis between a power-good rise and VTHR_PG_DWN. The status of the power-good indicator is read back via I2C from the PG1 status bit. Alternatively, it can be assigned to any of the GPIOs by setting the GPIO<x>_MODE bits to PG1 output. The buck converter is capable of supporting DVC transitions that occur when:

the active and selected A- or B-voltage is updated to a new target value, using bits CH1_A_VOUT and CH1_B_VOUT
the voltage selection is toggled from the A- to B-voltage (or B- to A-voltage), using bit CH1_VSEL or via GPI control The DVC operates in pulse-width-modulation (PWM) mode with synchronous rectification. The slew rate of the DVC ramp up and ramp down transitions is programmed at 10 mV per (8, 4, 2, 1, or 0.5) µs in register bits CH1_SR_DVC_DWN and CH1_SR_DVC_UP. A pull-down resistor (typically 150 Ω) for each phase is always activated when the buck is disabled, unless it is disabled by setting register bits CH1_PD_DIS to 0x1.

5.2.1 Switching Frequency

The buck switching frequency is tuned using register bit OSC_TUNE. The internal 8 MHz oscillator frequency is tuned in ±160 kHz steps. This impacts the buck converter frequency in steps of 80 kHz and helps to mitigate possible disturbances to other high frequency systems in the application .

5.2.2 Operation Modes and Phase Selection

The buck converter operates in PWM or PFM modes. The operating mode is selected using register bits CH1_A_MODE and CH1_B_MODE. Phase shedding automatically changes between 1- and 2-phase operation at a typical current of 4 A.

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 19 of 51 © 2022 Renesas Electronics If the automatic operation mode (Auto mode) is selected , the buck converter automatically changes between synchronous PWM mode and PFM mode depending on the load current. This improves the efficiency across the range of output load currents.

5.2.3 Output Voltage Selection

The switching converter is configured using the I2C interface. Two output voltages (Value A and Value B in Figure 6) are pre-configured in registers CH1_A_VOUT and CH1_B_VOUT. The output voltage (VBUCK in Figure 6) is selected by toggling register bit CH1_VSEL, by re-programming the selected voltage control register, or by toggling a GPI if configured to do so. Any of these options will result in ramped voltage transitions. After being enabled, the buck converter uses, by default, the register settings in CH1_A_VOUT (Value A) unless the output voltage selection is configured via the GPI port to be CH1_B_VOUT. Register bits CH1_VMAX limit the output voltage that can be set. Value A Value B A/B SEL VBUCK GPIO Host write Figure 6: Buck Output Voltage Control Concept

5.2.4 Soft Startup and Shutdown

To limit in-rush current from VSYS, the buck converter performs a soft-start after being enabled. The startup behavior is a compromise between acceptable inrush current from the battery and turn -on time. Ramp times are configured in register CH1_SR_STARTUP. Note: rates higher than 5 mV/µs may produce overshoot during the startup phase. A ramped power down is selected in register bits CH1_SR_SHDN. When no ramp is selected (immediate power down), the output node is discharged only by the pull-down resistor, if enabled, in register CH1_PD_DIS.

5.2.5 Current Limit

The integrated current limit protects the power stages and external coil from excessive current. It should be configured to at least 40 % higher than the required maximum per phase output current. Note: this value is loaded from the OTP. When the current limit is reached, the buck converter generates an event and an interrupt to the host processor unless the interrupt has been masked using bit M_OC1 in SYS_MASK_1. Register bit OC_DVC_MASK masks over-current events during DVC transitions.

5.2.6 Temperature Protection

DA9142 is protected from internal overheating by temperature-triggered shutdown. There are two kinds of flags concerning temperature protection: temperature warning and temperature critical. The warning flag asserts when TJ > TWARN and the critical flag asserts when TJ > TCRIT. When the critical flag asserts, Buck1 shuts down immediately. Table 12: Temperature Protection Control Registers Category Register name Description Status TEMP_WARN Asserts when the temperature warning threshold is reached TEMP_CRIT Asserts when the temperature shutdown threshold is reached IRQ event E_TEMP_WARN TEMP_WARN caused event E_TEMP_CRIT TEMP_CRIT caused event IRQ mask M_TEMP_WARN TEMP_WARN event IRQ mask M_TEMP_CRIT TEMP_CRIT event IRQ mask M_VR_HOT TEMP_WARN status IRQ mask Figure 7: Temperature Protection Operation

5.3 Control Circuits

5.3.1 Chip Enable and Disable

The IC_EN pin enables and disables the IC. When IC_EN = 0 all blocks, except for low IQ POR, powerdown and the buck output is pulled down. Warning Flag TCRIT Junction Temperature TWARN Critical Flag IRQ IRQ Buck1 Shutdown Buck Enable I2C Bus Write to CH<x>_EN

5.3.2 GPIO

5.3.2.1 GPIO Pin Assignment

The DA9142 provides up to five GPIO pins, three if the I2C is enabled, see Table 13. The registers that configure the GPIO pin assignments are OTP programmable. GPIO0 can be programmed (OTP option) to function as chip configuration (CONF), see Section 5.3.2.3. When the I2C interface is enabled (OTP option) any register settings for GPIO3 and GPIO4 are ignored and GPIO3 and GPIO4 function as SCL and SDA respectively. Table 13: GPIO Pin Assignment OTP Option GPIO Pin Available GPIOs I2C CONF CONF/ GPIO0 GPIO1 GPIO2 SCL/ GPIO3 SDA/ GPIO4 Disabled Disabled GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 5 Enabled CONF GPIO1 GPIO2 GPIO3 GPIO4 4 Enabled Disabled GPIO0 GPIO1 GPIO2 SCL SDA 3 Enabled CONF GPIO1 GPIO2 SCL SDA 2

5.3.2.2 GPIO Function

The GPIO pins are configurable as the following functions in register GPIO<x>_MODE (x = 0 to 4):

Buck1 enable input (EN1)
Buck1 DVC control input (DVC1)
Buck1 OTP setting reload input (RELOAD)
Buck1 power-good output (PG1)
Interrupt output (nIRQ)

5.3.2.3 Chip Configuration Select

GPIO0 functions as chip configuration select (CONF) input when enabled as an OTP setting. Three different chip configurations can be selected according to the CONF pin level (high, low, or Hi - Z). Table 14: GPIO0 Configurable Registers when CONF Enabled Register Name Description IF_SLAVE_ADDR[6:0] I2C slave address CH1_A_MODE[1:0] CH1_A Operation mode select CH1_B_MODE[1:0] CH1_B Operation mode select CH1_VSEL CH1 output voltage and operation selection CH1_EN CH1 enable CH1_A_VOUT[7:0] CH1 output voltage setting A CH1_B_VOUT[7:0] CH1 output voltage setting B M_PG1_STAT IRQ mask setting for CH1 power-good status M_VR_HOT IRQ mask setting for temp warning status GPIO1_MODE[3:0] GPIO1 mode setting GPIO2_MODE[3:0] GPIO2 mode setting

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 22 of 51 © 2022 Renesas Electronics Register Name Description GPIO1_OBUF GPIO1 output buffer select GPIO2_OBUF GPIO2 output buffer select GPIO1_TRIG[1:0] GPIO1 input trigger select GPIO1_POL GPIO1 polarity select GPIO1_PUPD GPIO1 pull-up/pull-down enable GPIO1_DEB[1:0] GPIO1 input debounce time setting GPIO1_DEB_RISE GPIO1 input debounce rising edge enable GPIO1_DEB_FALL GPIO1 input debounce falling edge enable GPIO2_TRIG[1:0] GPIO2 input trigger select GPIO2_POL GPIO2 polarity select GPIO2_PUPD GPIO2 pull-up/pull-down enable GPIO2_DEB[1:0] GPIO2 input debounce time setting GPIO2_DEB_RISE GPIO2 input debounce rising edge enable GPIO2_DEB_FALL GPIO2 input debounce falling edge enable

5.3.3 Interrupt

When an event is triggered, the nIRQ interrupt flag is asserted. Trigger conditions and control registers for each interrupt event are listed in Table 15. Some of these events are categorized as fault events and affect device operation (for example, buck disable), see Section 5.2.6. Table 15: Interrupt List Name Polarity (Note 1) Trigger IRQ Status Register IRQ Mask Register Deglitch Period Temperature warning (event) N TJ rising above TWARN E_TEMP_WARN M_TEMP_WARN 0 s Temperature critical (event) N TJ rising above TCRIT E_TEMP_CRIT M_TEMP_CRIT 0 s Buck1 power-good (event) P Buck1 VOUT is in power- good voltage range (not under- or over-voltage) E_PG1 M_PG1 0 s Buck1 over-voltage (event) N Buck1 VOUT rising above over-voltage threshold (target voltage + 150 mV) E_OV1 M_OV1 Rise: 8 µs Fall: 8 µs Buck1 under- voltage (event) N Buck1 VOUT falling below under-voltage threshold (target voltage - VTH_PG_FALL) E_UV1 M_UV1 0 s Buck1 over-current (event) N Buck1 current rising above over-current threshold E_OC1 M_OC1 0 s Buck1 power-good (status) (Note 2) P Buck1 VOUT is in power- good voltage range (not under- or over-voltage) PG1 M_PG1_STAT (Note 3) 0 s Temperature warning (status) (Note 2) N TJ rising above TWARN TEMP_WARN M_VR_HOT (Note 3) 0 s GPIO0 change (event) N Detect GPIO0 change for active trigger selected by GPIO0_TRIG register E_GPIO0 M_GPIO0 100 µs, 1 ms, or 10 ms 100 ms GPIO1 change (event) N Detect GPIO1 change for active trigger selected by GPIO1_TRIG register E_GPIO1 M_GPIO1 GPIO2 change (event) N Detect GPIO2 change for active trigger selected by GPIO2_TRIG register E_GPIO2 M_GPIO2 Note 1 Polarity at the source of the flag: P = active high, N = active low. General rule is: normal system state is high, and abnormal system state is low (for example, PG = high means power-good, TEMP_CRIT = low when in temperature critical state). Note 2 Interrupt outputs the status as is. I2C write is not required for interrupt clear. Note 3 OTP load value defined by CONF pin setting (if CONF pin enabled).

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 24 of 51 © 2022 Renesas Electronics Table 16: Interrupt Registers Except for Power-Good Status Register Description E_<name> Read-only interrupt event register 0: No interrupt 1: Interrupt occurred Cleared after being written to I2C. Set until IRQ is removed. M_<name> Interrupt mask register 0: Not masked 1: Masked. No IRQ signal sent. Event register (E_<name>) is updated. Table 17: Interrupt Registers for Power-Good and Temperature Warning Status Register Description PG1 Buck1 power-good status. Asserted as long as Buck1 output voltage is in range (under-voltage threshold < buck output voltage < over-voltage threshold) 0: Not power-good 1: Power-good M_PG1_STAT Power-good status interrupt mask register 0: Not masked 1: Masked. No IRQ signal sent. Power-good status register (PG1) is updated TEMP_WARN Asserted as long as the temperature warning threshold (TWARN) is reached 0: Junction temperature is below TWARN 1: Junction temperature is above TWARN M_VR_HOT Temperature warning status (TEMP_WARN) interrupt mask register 0: Not masked 1: Masked. No IRQ signal sent. Temperature warning status register (TEMP_WARN) is updated Over-voltage Under-voltage PG1 E_TEMP_WARN 0 VOUT IRQ Not Masked 1 0 TEMP_WARN TJ > TWARN TJ < TWARN I2C Write Clear Status Reg Event Reg Status Reg GPIO (nIRQ) Active-Low Setting (GPIO<x>_POL = 1) Active-High Setting (GPIO<x>_POL = 0) Target voltage

GPIO is cofigured as nIRQ
M_TEMP_WARN = 0
M_PG1_STAT = 0 Conditions Figure 8: Interrupt Operation Example

5.4 I2C Communication

All features of DA9142 can be controlled with the I2C interface, which is enabled or disabled as an OTP setting. I2C Description Disabled SCL/GPIO3 and SDA/GPIO4 pins can be used as GPIO Enabled SCL/GPIO3 and SDA/GPIO4 pins are used as I2C clock input and I2C data input/output. GPIO3 functions as the I2C clock (SCL) and GPIO4 carries all the power manager bidirectional I2C data (SDA). The I2C interface is open drain supporting multiple devices on a single line. The bus lines have to be pulled high by external pull-up resistors (2 kΩ to 20 kΩ). The standard frequency of the I2C bus is 1 MHz in fast-mode plus (FM+), 400 kHz in fast-mode, or 100 kHz in standard mode.

5.4.1 I2C Protocol

All data is transmitted across the I2C bus in eight-bit groups. To send a bit, the SDA line is driven towards the intended state while the SCL is low (a low SDA indicates a zero bit). Once the SDA has settled, the SCL line is brought high and then low. This pulse on SCL clocks the SDA bit into the receiver’s shift register. A two-byte serial protocol is used containing one byte for address and one byte for data. Data and address transfer are transmitted MSB first for both read and write operations. All transmissions begin with the START condition from the master while the bus is in idle state (the bus is free). It is i nitiated by a high to low transition on the SDA line while the SCL is in the high state (a STOP condition is indicated by a low to high transition on the SDA line while the SCL is in the high state). SCL SDA Figure 9: I2C START and STOP Condition Timing The I2C bus is monitored for a valid slave address whenever the interface is enabled. It responds immediately when it receives its own slave address. The acknowledge is done by pulling the SDA line low during the following clock cycle (white blocks marked with A in Figure 10 and Figure 11). The protocol for a register write from master to slave consists of a START condition, a slave address with read/write bit, and the eight-bit register address followed by eight bits of data, terminated by a STOP condition. DA9142 responds to all bytes with acknowledge (A), see Figure 10. SLAVEadr W REGadr A DATA A P S = START condition A = Acknowledge (low) P = STOP condition W = Write (low) Master to Slave Slave to Master 7-bits 1-bit 8-bits 8-bits A S Figure 10: I2C Byte Write (SDA Line)

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 26 of 51 © 2022 Renesas Electronics When the host reads data from a register it first has to write to DA9142 with the target register address and then read from DA9142 with a repeated START, or alternatively a second START, condition. After receiving the data, the host sends no acknowledge (A*) and terminates the transmission with a STOP condition, see Figure 11. S SLAVEadr W A REGadr A SLAVEadr A S = START condition A = Acknowledge (low) Sr = Repeated START condition A* = No Acknowledge P = STOP condition W = Write (low) R = Read (high) Master to Slave 7-bits 1-bit 8-bits 7-bits DATA A* Sr R 1-bit 8-bits SLAVEadr A 7-bits DATA P S R 1-bit 8-bits P Slave to Master S SLAVEadr W A REGadr P 7-bits 1-bit 8-bits A Figure 11: I2C Byte Read (SDA Line) Examples

6 Register Definitions

6.1 Register Map

Table 18: Register Map Addr Register 7 6 5 4 3 2 1 0 System Module 0x0001 SYS_STATUS_0 Reserved Reserved Reserved Reserved Reserved Reserved 0 TEMP_CRIT TEMP_WARN 0x0002 SYS_STATUS_1 Reserved Reserved Reserved Reserved PG1 OV1 UV1 OC1 0x0003 SYS_STATUS_2 Reserved Reserved Reserved Reserved Reserved GPIO2 GPIO1 GPIO0 0x0004 SYS_EVENT_0 Reserved Reserved Reserved Reserved Reserved Reserved 0 E_TEMP_CRIT E_TEMP_WARN 0x0005 SYS_EVENT_1 Reserved Reserved Reserved Reserved E_PG1 E_OV1 E_UV1 E_OC1 0x0006 SYS_EVENT_2 Reserved Reserved Reserved Reserved Reserved E_GPIO2 E_GPIO1 E_GPIO0 0x0007 SYS_MASK_0 Reserved Reserved Reserved Reserved Reserved Reserved 1 M_TEMP_CRIT M_TEMP_WARN 0x0008 SYS_MASK_1 Reserved Reserved Reserved Reserved M_PG1 M_OV1 M_UV1 M_OC1 0x0009 SYS_MASK_2 Reserved Reserved Reserved Reserved Reserved M_GPIO2 M_GPIO1 M_GPIO0 0x000A SYS_MASK_3 Reserved Reserved Reserved Reserved M_VR_HOT Reserved 1 Reserved M_PG1_STAT 0x000B SYS_CONFIG_0 CH1_DIS_DLY<3:0> CH1_EN_DLY<3:0> 0x000D SYS_CONFIG_2 Reserved OC_LATCHOFF<1:0> OC_DVC_MASK PG_DVC_MASK<1:0> Reserved Reserved 0x000E SYS_CONFIG_3 Reserved OSC_TUNE<2:0> Reserved Reserved I2C_TIMEOUT Reserved 0 0x0010 SYS_GPIO0_0 Reserved Reserved Reserved GPIO0_MODE<3:0> GPIO0_OBUF 0x0011 SYS_GPIO0_1 GPIO0_DEB_FALL GPIO0_DEB_RISE GPIO0_DEB<1:0> GPIO0_PUPD GPIO0_POL GPIO0_TRIG<1:0> 0x0012 SYS_GPIO1_0 Reserved Reserved Reserved GPIO1_MODE<3:0> GPIO1_OBUF 0x0013 SYS_GPIO1_1 GPIO1_DEB_FALL GPIO1_DEB_RISE GPIO1_DEB<1:0> GPIO1_PUPD GPIO1_POL GPIO1_TRIG<1:0> 0x0014 SYS_GPIO2_0 Reserved Reserved Reserved GPIO2_MODE<3:0> GPIO2_OBUF 0x0015 SYS_GPIO2_1 GPIO2_DEB_FALL GPIO2_DEB_RISE GPIO2_DEB<1:0> GPIO2_PUPD GPIO2_POL GPIO2_TRIG<1:0> 0x0016 SYS_GPIO3_0 Reserved Reserved Reserved GPIO3_MODE<3:0> GPIO3_OBUF 0x0017 SYS_GPIO3_1 GPIO3_DEB_FALL GPIO3_DEB_RISE GPIO3_DEB<1:0> GPIO3_PUPD GPIO3_POL GPIO3_TRIG<1:0> 0x0018 SYS_GPIO4_0 Reserved Reserved Reserved GPIO4_MODE<3:0> GPIO4_OBUF 0x0019 SYS_GPIO4_1 GPIO4_DEB_FALL GPIO4_DEB_RISE GPIO4_DEB<1:0> GPIO4_PUPD GPIO4_POL GPIO4_TRIG<1:0>

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 28 of 51 © 2022 Renesas Electronics Addr Register 7 6 5 4 3 2 1 0 Buck Control Buck1 0x0020 BUCK_BUCK1_0 Reserved CH1_SR_DVC_DWN<2:0> CH1_SR_DVC_UP<2:0> CH1_EN 0x0021 BUCK_BUCK1_1 Reserved CH1_SR_SHDN<2:0> CH1_SR_STARTUP<2:0> CH1_PD_DIS 0x0022 BUCK_BUCK1_2 Reserved Reserved Reserved Reserved CH1_ILIM<3:0> 0x0023 BUCK_BUCK1_3 CH1_VMAX<7:0> 0x0024 BUCK_BUCK1_4 Reserved Reserved Reserved CH1_VSEL CH1_B_MODE<1:0> CH1_A_MODE<1:0> 0x0025 BUCK_BUCK1_5 CH1_A_VOUT<7:0> 0x0026 BUCK_BUCK1_6 CH1_B_VOUT<7:0> 0x0027 BUCK_BUCK1_7 Reserved Reserved Reserved Reserved Reserved Reserved CH1_RIPPLE_CANCEL<1:0> OTP Control Serialization 0x0048 OTP_DEVICE_ID DEV_ID<7:0> 0x0049 OTP_VARIANT_ID MRC<3:0> VRC<3:0> 0x004A OTP_CUSTOMER_ID CUST_ID<7:0> 0x004B OTP_CONFIG_ID CONFIG_REV<7:0>

6.2 Register Descriptions

Table 19: SYS_STATUS_0 (0x0001) Bit Type Field Name Description [1] R TEMP_CRIT Asserted when the thermal shutdown threshold is reached [0] R TEMP_WARN Asserted when the thermal warning threshold is reached Table 20: SYS_STATUS_1 (0x0002) Bit Type Field Name Description [3] R PG1 Asserted when the buck output voltage is in range [2] R OV1 Asserted when the buck exceeds the over-voltage threshold [1] R UV1 Asserted when the buck exceeds the under-voltage threshold [0] R OC1 Asserted when the buck exceeds the over-current threshold Table 21: SYS_STATUS_2 (0x0003) Bit Type Field Name Description [2] R GPIO2 GPIO2 input readback status - asserted if the input on GPIO is seen as logic high [1] R GPIO1 GPIO1 input readback status - asserted if the input on GPIO is seen as logic high [0] R GPIO0 GPIO0 input readback status - asserted if the input on GPIO is seen as logic high Table 22: SYS_EVENT_0 (0x0004) Bit Type Field Name Description [1] RW1C E_TEMP_CRIT An over-temperature event has occurred. Write 0x1 to reset this bit to 0x0 when the event source has been released. [0] RW1C E_TEMP_WARN A temperature warning event has occurred. Write 0x1 to reset this bit to 0x0 when the event source has been released. Table 23: SYS_EVENT_1 (0x0005) Bit Type Field Name Description [3] RW1C E_PG1 PG1 caused event. Write 0x1 to reset this bit to 0x0 when the event source has been released. [2] RW1C E_OV1 OV1 caused event. Write 0x1 to reset this bit to 0x0 when the event source has been released. [1] RW1C E_UV1 UV1 caused event. Write 0x1 to reset this bit to 0x0 when the event source has been released. [0] RW1C E_OC1 OC1 caused event. Write 0x1 to reset this bit to 0x0 when the event source has been released.

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 30 of 51 © 2022 Renesas Electronics Table 24: SYS_EVENT_2 (0x0006) Bit Type Field Name Description [2] RW1C E_GPIO2 GPIO2 caused event. Write 0x1 to reset this bit to 0x0 when the event source has been released. [1] RW1C E_GPIO1 GPIO1 caused event. Write 0x1 to reset this bit to 0x0 when the event source has been released. [0] RW1C E_GPIO0 GPIO0 caused event. Write 0x1 to reset this bit to 0x0 when the event source has been released. Table 25: SYS_MASK_0 (0x0007) Bit Type Field Name Description [1] RW M_TEMP_CRIT Thermal shutdown can cause an interrupt. Write 0x1 to mask this cause of interrupt. [0] RW M_TEMP_WARN Temperature warning can cause an interrupt. Write 0x1 to mask this cause of interrupt. Table 26: SYS_MASK_1 (0x0008) Bit Type Field Name Description [3] RW M_PG1 PG1 event can cause an interrupt. Write 0x1 to mask this cause of interrupt. [2] RW M_OV1 OV1 event can cause an interrupt. Write 0x1 to mask this cause of interrupt. [1] RW M_UV1 UV1 event can cause an interrupt. Write 0x1 to mask this cause of interrupt. [0] RW M_OC1 OC1 event can cause an interrupt. Write 0x1 to mask this cause of interrupt. Table 27: SYS_MASK_2 (0x0009) Bit Type Field Name Description [2] RW M_GPIO2 GPIO2 event can cause an interrupt. Write 0x1 to mask this cause of interrupt. [1] RW M_GPIO1 GPIO1 event can cause an interrupt. Write 0x1 to mask this cause of interrupt. [0] RW M_GPIO0 GPIO0 event can cause an interrupt. Write 0x1 to mask this cause of interrupt. Table 28: SYS_MASK_3 (0x000A) Bit Type Field Name Description [3] RW M_VR_HOT Temperature warning status IRQ mask. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) [0] RW M_PG1_STAT PG1 status IRQ mask. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting)

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 31 of 51 © 2022 Renesas Electronics Table 29: SYS_CONFIG_0 (0x000B) Bit Type Field Name Description [7:4] RW CH1_DIS_DLY Delay time (ms) until CH1 is disabled. Active when GPIO is configured as EN1 or IC_EN control. Initial value is determined by CONF pin setting during start up if the CONF pin is enabled (OTP setting) Value Description 0x0 0 0x1 1 0x2 2 0x3 3 0x4 4 0x5 5 0x6 6 0x7 7 0x8 8 0x9 9 0xA 10 0xB 11 0xC 12 0xD 13 0xE 14 0xF 15 [3:0] RW CH1_EN_DLY Delay time (ms) until CH1 is enabled. Active when GPIO is configured as EN1 control or IC_EN control. Initial value is determined by CONF pin setting during start up if the CONF pin is enabled (OTP setting) Value Description 0x0 0 0x1 0.5 0x2 1 0x3 1.5 0x4 2 0x5 2.5 0x6 3 0x7 3.5 0x8 4 0x9 4.5 0xA 5

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 32 of 51 © 2022 Renesas Electronics Bit Type Field Name Description 0xB 5.5 0xC 6 0xD 6.5 0xE 7 0xF 7.5 Table 30: SYS_CONFIG_2 (0x000D) Bit Type Field Name Description [6:5] RW OC_LATCHOFF Over-current latch-off time (Debounce duration). Buck shuts down after over-current persists for 8 us, 1 ms or 3 ms unless setting is disabled setting. An IRQ is generated unless masked. Value Description 0x0 Latch off disable 0x1 Latch off after 8 us 0x2 Latch off after 1 ms 0x3 Latch off after 3 ms [4] RW OC_DVC_MASK Over-current event mask during DVC ramp-up and ramp- down. Write 0x1 to mask over-current during DVC causing IRQ and LATCHOFF. [3:2] RW PG_DVC_MASK Power good mask during DVC Value Description 0x0 No mask 0x1 Mask as not power good 0x2 Mask as power good 0x3 Reserved Table 31: SYS_CONFIG_3 (0x000E) Bit Type Field Name Description [6:4] RW OSC_TUNE Tune oscillator frequency, tuned frequency = current frequency + OSC_TUNE * 160 kHz Value Description 0x3 3 0x2 2 0x1 1 0x0 0 0x7 -1 0x6 -2 0x5 -3

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 33 of 51 © 2022 Renesas Electronics Bit Type Field Name Description 0x4 -4 [1] RW I2C_TIMEOUT Enable automatic reset of 2 wire interface (if SDA stays low for > 50 ms). Table 32: SYS_GPIO0_0 (0x0010) Bit Type Field Name Description [4:1] RW GPIO0_MODE GPIO function mode select Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 Reserved 0x3 EN1 input 0x4 DVC1 input 0x5 Reserved 0x6 DVC1 input 0x7 RELOAD input 0x8 PG1 output 0x9 Low output 0xA Low output 0xB PG1 output 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] RW GPIO0_OBUF GPIO output buffer select Value Description 0x0 open-drain output 0x1 push-pull output Table 33: SYS_GPIO0_1 (0x0011) Bit Type Field Name Description [7] RW GPIO0_DEB_FALL GPI debounce falling edge [6] RW GPIO0_DEB_RISE GPI debounce rising edge [5:4] RW GPIO0_DEB GPI debounce time Value Description 0x0 100 us debounce 0x1 1 ms debounce

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 34 of 51 © 2022 Renesas Electronics Bit Type Field Name Description 0x2 10 ms debounce 0x3 100 ms debounce [3] RW GPIO0_PUPD GPIO pull-up/pull-down enable Value Description 0x0 GPI: pull-down disabled, GPO: pull-up to AVDD disabled 0x1 GPI: pull-down enabled, GPO: pull-up to AVDD enabled [2] RW GPIO0_POL GPIO polarity Value Description 0x0 GPIO is active-high 0x1 GPIO is active-low [1:0] RW GPIO0_TRIG GPI trigger type Value Description 0x0 Dual-edge triggered 0x1 Positive-edge triggered 0x2 Negative-edge triggered 0x3 Reserved (No trigger) Table 34: SYS_GPIO1_0 (0x0012) Bit Type Field Name Description [4:1] RW GPIO1_MODE GPIO function mode select. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 Reserved 0x3 EN1 input 0x4 DVC1 input 0x5 Reserved 0x6 DVC1 input 0x7 RELOAD input 0x8 PG1 output 0x9 Low output 0xA Low output 0xB PG1 output 0xC nIRQ output

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 35 of 51 © 2022 Renesas Electronics Bit Type Field Name Description 0xD Reserved 0xE Low output 0xF High output [0] RW GPIO1_OBUF GPIO output buffer select. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting). Value Description 0x0 open-drain output 0x1 push-pull output Table 35: SYS_GPIO1_1 (0x0013) Bit Type Field Name Description [7] RW GPIO1_DEB_FALL GPI debounce falling edge. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) [6] RW GPIO1_DEB_RISE GPI debounce rising edge. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) [5:4] RW GPIO1_DEB GPI debounce time. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 100 us debounce 0x1 1 ms debounce 0x2 10 ms debounce 0x3 100 ms debounce [3] RW GPIO1_PUPD GPIO pull-up/pull-down enable. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 GPI: pull-down disabled, GPO: pull-up to AVDD disabled 0x1 GPI: pull-down enabled, GPO: pull-up to AVDD enabled [2] RW GPIO1_POL GPIO polarity. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 GPIO is active-high 0x1 GPIO is active-low [1:0] RW GPIO1_TRIG GPI trigger type. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 36 of 51 © 2022 Renesas Electronics Bit Type Field Name Description 0x0 Dual-edge triggered 0x1 Positive-edge triggered 0x2 Negative-edge triggered 0x3 Reserved (No trigger) Table 36: SYS_GPIO2_0 (0x0014) Bit Type Field Name Description [4:1] RW GPIO2_MODE GPIO function mode select. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 Reserved 0x3 EN1 input 0x4 DVC1 input 0x5 Reserved 0x6 DVC1 input 0x7 RELOAD input 0x8 PG1 output 0x9 Low output 0xA Low output 0xB PG1 output 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] RW GPIO2_OBUF GPIO output buffer select. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 open-drain output 0x1 push-pull output Table 37: SYS_GPIO2_1 (0x0015) Bit Type Field Name Description [7] RW GPIO2_DEB_FALL GPI debounce falling edge. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting)

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 37 of 51 © 2022 Renesas Electronics Bit Type Field Name Description [6] RW GPIO2_DEB_RISE GPI debounce rising edge. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) [5:4] RW GPIO2_DEB GPI debounce time. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 100 us debounce 0x1 1 ms debounce 0x2 10 ms debounce 0x3 100 ms debounce [3] RW GPIO2_PUPD GPIO pull-up/pull-down enable. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 GPI: pull-down disabled, GPO: pull-up to AVDD disabled 0x1 GPI: pull-down enabled, GPO: pull-up to AVDD enabled [2] RW GPIO2_POL GPIO polarity. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 GPIO is active-high 0x1 GPIO is active-low [1:0] RW GPIO2_TRIG GPI trigger type. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 Dual-edge triggered 0x1 Positive-edge triggered 0x2 Negative-edge triggered 0x3 Reserved (No trigger) Table 38: SYS_GPIO3_0 (0x0016) Bit Type Field Name Description [4:1] R GPIO3_MODE GPIO function mode select Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 Reserved 0x3 EN1 input

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 38 of 51 © 2022 Renesas Electronics Bit Type Field Name Description 0x4 DVC1 input 0x5 Reserved 0x6 DVC1 input 0x7 RELOAD input 0x8 PG1 output 0x9 Low output 0xA Low output 0xB PG1 output 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] R GPIO3_OBUF GPIO output buffer select Value Description 0x0 open-drain output 0x1 push-pull output Table 39: SYS_GPIO3_1 (0x0017) Bit Type Field Name Description [7] R GPIO3_DEB_FALL GPI debounce falling edge [6] R GPIO3_DEB_RISE GPI debounce rising edge [5:4] R GPIO3_DEB GPI debounce time Value Description 0x0 100 us debounce 0x1 1 ms debounce 0x2 10 ms debounce 0x3 100 ms debounce [3] R GPIO3_PUPD GPIO pull-up/pull-down enable Value Description 0x0 GPI: pull-down disabled, GPO: pull-up to AVDD disabled 0x1 GPI: pull-down enabled, GPO: pull-up to AVDD enabled [2] R GPIO3_POL GPIO polarity Value Description 0x0 GPIO is active-high 0x1 GPIO is active-low

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 39 of 51 © 2022 Renesas Electronics Bit Type Field Name Description [1:0] R GPIO3_TRIG GPI trigger type Value Description 0x0 Dual-edge triggered 0x1 Positive-edge triggered 0x2 Negative-edge triggered 0x3 Reserved (No trigger) Table 40: SYS_GPIO4_0 (0x0018) Bit Type Field Name Description [4:1] R GPIO4_MODE GPIO function mode select Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 Reserved 0x3 EN1 input 0x4 DVC1 input 0x5 Reserved 0x6 DVC1 input 0x7 RELOAD input 0x8 PG1 output 0x9 Low output 0xA Low output 0xB PG1 output 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] R GPIO4_OBUF GPIO output buffer select Value Description 0x0 open-drain output 0x1 push-pull output Table 41: SYS_GPIO4_1 (0x0019) Bit Type Field Name Description [7] R GPIO4_DEB_FALL GPI debounce falling edge [6] R GPIO4_DEB_RISE GPI debounce rising edge [5:4] R GPIO4_DEB GPI debounce time

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 40 of 51 © 2022 Renesas Electronics Bit Type Field Name Description Value Description 0x0 100 us debounce 0x1 1 ms debounce 0x2 10 ms debounce 0x3 100 ms debounce [3] R GPIO4_PUPD GPIO pull-up/pull-down enable Value Description 0x0 GPI: pull-down disabled, GPO: pull-up to AVDD disabled 0x1 GPI: pull-down enabled, GPO: pull-up to AVDD enabled [2] R GPIO4_POL GPIO polarity Value Description 0x0 GPIO is active-high 0x1 GPIO is active-low [1:0] R GPIO4_TRIG GPI trigger type Value Description 0x0 Dual-edge triggered 0x1 Positive-edge triggered 0x2 Negative-edge triggered 0x3 Reserved (No trigger)

6.2.1 Buck1

Table 42: BUCK_BUCK1_0 (0x0020) Bit Type Field Name Description [6:4] RW CH1_SR_DVC_DWN Voltage slew-rate for DVC ramp-down Value Description 0x0 10 mV / 8 us 0x1 10 mV / 4 us 0x2 10 mV / 2 us 0x3 10 mV / 1 us 0x4 20 mV / 1 us 0x5 Reserved 0x6 Reserved 0x7 Reserved [3:1] RW CH1_SR_DVC_UP Voltage slew-rate for DVC ramp-up Value Description

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 41 of 51 © 2022 Renesas Electronics Bit Type Field Name Description 0x0 10 mV / 8 us 0x1 10 mV / 4 us 0x2 10 mV / 2 us 0x3 10 mV / 1 us 0x4 20 mV / 1 us 0x5 40 mV / 1 us 0x6 Reserved 0x7 Reserved [0] RW CH1_EN Channel enable. Write 0x1 to enable the buck. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Table 43: BUCK_BUCK1_1 (0x0021) Bit Type Field Name Description [6:4] RW CH1_SR_SHDN Voltage slew-rate during shut-down Value Description 0x0 10 mV / 8 us 0x1 10 mV / 4 us 0x2 10 mV / 2 us 0x3 10 mV / 1 us 0x4 20 mV / 1 us 0x5 Reserved 0x6 Reserved 0x7 Immediate power-down [3:1] RW CH1_SR_STARTUP Voltage slew-rate during start-up Value Description 0x0 10 mV / 8 us 0x1 10 mV / 4 us 0x2 10 mV / 2 us 0x3 10 mV / 1 us 0x4 20 mV / 1 us 0x5 40 mV / 1 us 0x6 Reserved 0x7 Reserved [0] RW CH1_PD_DIS LX Pull down while BUCK is off. Write 0x1 to disable this function.

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 42 of 51 © 2022 Renesas Electronics Table 44: BUCK_BUCK1_2 (0x0022) Bit Type Field Name Description [3:0] RW CH1_ILIM Select OCP threshold (A) Value Description 0x0 Reserved 0x1 6.5 0x2 7.5 0x3 8.5 0x4 9.5 0x5 10.5 0x6 11.5 0x7 12.5 0x8 13.5 0x9 14.5 0xA 15.5 0xB 16.5 0xC 17.5 0xD 18.5 0xE 19.5 0xF Disable Table 45: BUCK_BUCK1_3 (0x0023) Bit Type Field Name Description [7:0] R CH1_VMAX VOUT max setting (V): From 0.50 V (0x32) to 1.30 V (0x82) in steps of 10 mV This is a read-only register. Value Description 0x00 Reserved 0x31 Reserved 0x32 0.5 0x33 0.51 ... +0.01 steps 0x63 0.99 0x64 1 0x65 1.01 ... +0.01 steps 0x81 1.29 0x82 1.3

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 43 of 51 © 2022 Renesas Electronics Bit Type Field Name Description 0x83 Reserved 0xFF Reserved Table 46: BUCK_BUCK1_4 (0x0024) Bit Type Field Name Description [4] RW CH1_VSEL Output voltage and operation selection: 0: A, 1: B. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) [3:2] RW CH1_B_MODE Operation mode selection. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 Force PFM operation 0x1 Force PWM operation (full phase) 0x2 Force PWM operation (with phase shedding) 0x3 Auto mode [1:0] RW CH1_A_MODE Operation mode selection. Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) Value Description 0x0 Force PFM operation 0x1 Force PWM operation (full phase) 0x2 Force PWM operation (with phase shedding) 0x3 Auto mode Table 47: BUCK_BUCK1_5 (0x0025) Bit Type Field Name Description [7:0] RW CH1_A_VOUT Output voltage setting A: Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) From 0.50 V (0x32) to 1.30 V (0x82) in steps of 10 mV Value Description 0x00 Reserved 0x31 Reserved 0x32 0.5 0x33 0.51 ... +0.01 steps 0x63 0.99 0x64 1 0x65 1.01

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 44 of 51 © 2022 Renesas Electronics Bit Type Field Name Description ... +0.01 steps 0x81 1.29 0x82 1.3 0x83 Reserved 0xFF Reserved Table 48: BUCK_BUCK1_6 (0x0026) Bit Type Field Name Description [7:0] RW CH1_B_VOUT Output voltage setting B: Initial value is determined by CONF pin setting during start-up and if the CONF pin is enabled (OTP setting) From 0.50 V (0x32) to 1.30 V (0x82) in steps of 10 mV Value Description 0x00 Reserved 0x31 Reserved 0x32 0.5 0x33 0.51 ... +0.01 steps 0x63 0.99 0x64 1 0x65 1.01 ... +0.01 steps 0x81 1.29 0x82 1.3 0x83 Reserved 0xFF Reserved Table 49: BUCK_BUCK1_7 (0x0027) Bit Type Field Name Description [1:0] RW CH1_RIPPLE_CANCEL Ripple cancel control Value Description 0x0 No ripple cancel 0x1 Small ripple cancel 0x2 Mid ripple cancel 0x3 Large ripple cancel

6.2.2 OTP Control

6.2.2.1 Serialization

Table 50: OTP_DEVICE_ID (0x0048) Bit Type Field Name Description [7:0] R DEV_ID Device ID; hard-coded or metal-programmed Table 51: OTP_VARIANT_ID (0x0049) Bit Type Field Name Description [7:4] R MRC Mask Revision Code [3:0] R VRC Chip Variant Code; e.g. package variants. Table 52: OTP_CUSTOMER_ID (0x004A) Bit Type Field Name Description [7:0] R CUST_ID Customer ID Table 53: OTP_CONFIG_ID (0x004B) Bit Type Field Name Description [7:0] R CONFIG_REV OTP settings revision

7 Package Information

7.1 Package Outlines

Figure 12: Package Outline Drawing

7.2 Moisture Sensitivity Level

The Moisture Sensitivity Level (MSL) is an indicator for the maximum allowable time period (floor lifetime) in which a moisture sensitive plastic device, once removed from the dry bag, can be exposed to an environment with a specified maximum temperature and a maximum relative hu midity before the solder reflow process. The MSL classification is defined in Table 54. For detailed information on MSL levels refer to the IPC/JEDEC standard J-STD-020, which can be downloaded from http://www.jedec.org. The DA9142 package is qualified for MSL 3. Table 54: MSL Classification MSL Level Floor Lifetime Conditions MSL 4 72 hours 30 °C / 60 % RH MSL 3 168 hours 30 °C / 60 % RH MSL 2A 4 weeks 30 °C / 60 % RH MSL 2 1 year 30 °C / 60 % RH MSL 1 Unlimited 30 °C / 85 % RH

7.3 Soldering Information

Refer to the IPC/JEDEC standard J-STD-020 for relevant soldering information. This document can be downloaded from http://www.jedec.org.

8 Ordering Information

The ordering number consists of the part number followed by a suffix indicating the packing method. For details and availability, please consult your Renesas local sales representative. Table 55: Ordering Information for Consumer / Industrial Applications Part Number Package Size (mm) Shipment Form Pack Quantity DA9142-xxF71 60 FCBGA 4.5 x 7 x 1.01 0.65 mm pitch Tray 364 DA9142-xxF72 60 FCBGA 4.5 x 7 x 1.01 0.65 mm pitch Reel 2600 Table 56: Ordering Information for Automotive Applications Part Number Package Size (mm) Shipment Form Pack Quantity DA9142-xxF71-A 60 FCBGA 4.5 x 7 x 1.01 0.65 mm pitch Tray 364 DA9142-xxF72-A 60 FCBGA 4.5 x 7 x 1.01 0.65 mm pitch Reel 2600

9 Application Information

The following recommended components are examples selected from requirements of a typical application.

9.1 Capacitor Selection

Ceramic capacitors are used as bypass capacitors at all VDD and output rails. When selecting a capacitor, especially for types with high capacitance at smallest physical dimension, the DC bias characteristic has to be taken into account. Table 57: Recommended Automotive Grade Capacitor Types Application Value (µF) Size Temp. Char. Tol. (%) V-Rate (V) Type VOUT output bypass 22 1206 X7R ±15% ±20 6.3 Murata GCM31CR70J226ME23L PVDDx bypass 10 0805 X7R ±15% ±10 16 Murata GCM21BC71C106KE36L PVDDx bypass for VSYS < 4V 10 0603 X7R ±15% ±10 6.3 Murata GCM188D70J106ME36L AVDD bypass 1 0805 X7R ±15% ±10 50 Murata GCM21BR71H105KA03L

9.2 Inductor Selection

Inductors should be selected based on the following parameters:

Rated maximum current and ISAT ISAT specifies the maximum current at which the inductance drops by 30 % of the nominal value, and IMAX is defined by the maximum power dissipation and is applied to the effective current at 40°C temperature rise.
DC resistance Critical for the converter efficiency and should therefore be minimized. Table 58: Recommended Inductor Types Value (nH) Size (mm) IMAX (DC) (A) ISAT (A) Tol. (%) DC Resistance (mΩ) Type 112 3.2 x 2.5 x 2.5 20 31 20 1.9 TDK CLT3225AR11MI3 110 4.0 x 4.0 x 2.1 29 29 20 1.4 Coilcraft XGL4020-111MEC

10 Layout Guidelines

Figure 13: DA9142 Footprint

High-Performance, 13 A/20 A Peak, DC-DC Converter Datasheet Revision 2.0 28-Jan-2022 CFR0011-120-00 51 of 51 © 2022 Renesas Electronics Status Definitions Revision Datasheet Status Product Status Definition 1.<n> Target Development This datasheet contains the design specifications for product development. Specifications may be changed in any manner without notice. 2.<n> Preliminary Qualification This datasheet contains the specifications and preliminary characterization data for products in pre-production. Specifications may be changed at any time without notice in order to improve the design. 3.<n> Final Production This datasheet contains the final specifications for products in volume production. The specifications may be changed at any time in order to improve the design, manufacturing and supply. Major specification changes are communicated via Customer Product Notifications. Datasheet changes are communicated via www.dialog-semiconductor.com. 4.<n> Obsolete Archived This datasheet contains the specifications for discontinued products. The information is provided for reference only. RoHS Compliance Dialog Semiconductor’s suppliers certify that its products are in compliance with the requirements of Directive 2011/65/ EU of the European Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certifi cates from our suppliers are available on request.

TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) © 2021 Renesas Electronics Corporation. All rights reserved.

Product Information

DA9142 specifications and overview.

Summary

High-Performance, 13 A/20 A Peak, DC-DC Converter 28-Jan-2022

Description

High-Performance, 13 A/20 A Peak, DC-DC Converter 28-Jan-2022

Source title DA9142 Datasheet(PDF) - Renesas Technology Corp

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DA9142 RENESAS | Alldatasheet

Document overview

Technical content

Applications

Contents

1 Terms and Definitions

2 Block Diagram

3 Pinout

Description

4 Characteristics

4.1 Absolute Maximum Ratings

4.2 Electrostatic Discharge Ratings

4.3 Recommended Operating Conditions

4.4 Thermal Characteristics

4.4.1 Power Derating Curves

4.5 Buck1 Characteristics

4.6 Performance and Supervision Characteristics

4.7 Digital IO Characteristics

4.8 Timing Characteristics

4.9 Typical Performance

5 Functional Description

5.1 Operating Modes

5.1.2 OFF

5.2 DC-DC Buck Converter

5.2.1 Switching Frequency

5.2.2 Operation Modes and Phase Selection

5.2.3 Output Voltage Selection

5.2.4 Soft Startup and Shutdown

5.2.5 Current Limit

5.2.6 Temperature Protection

5.3 Control Circuits

5.3.1 Chip Enable and Disable

5.3.2 GPIO

5.3.2.1 GPIO Pin Assignment

5.3.2.2 GPIO Function

5.3.2.3 Chip Configuration Select

5.3.3 Interrupt

5.4 I2C Communication

5.4.1 I2C Protocol

6 Register Definitions

6.1 Register Map

6.2 Register Descriptions

6.2.1 Buck1

6.2.2 OTP Control

6.2.2.1 Serialization

7 Package Information

7.1 Package Outlines

7.2 Moisture Sensitivity Level

7.3 Soldering Information

8 Ordering Information

9 Application Information

9.1 Capacitor Selection

9.2 Inductor Selection

10 Layout Guidelines

DA9142 specifications and overview.

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