DA9132-A_V01 RENESAS | Alldatasheet
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High-Performance, Dual-Channel DC-DC Converter for Automotive Applications R16DS0579EJ0300 Rev.03.00 Sep 04, 2025 CFR0011-120-00 Page 1 © 2025 Renesas Electronics DA9132-A is a power management IC (PMIC) suitable for supplying CPUs, GPUs, DDR memory rails in single in-line pin package (SIPP) modules, vehicle infotainment systems, ADAS, automotive navigation, center console and telematics. DA9132-A integrates two single-phase buck converters, each phase requiring a small external 0.22 µH inductor. Each buck is capable of delivering up to 3 A output current at a 0.3 V to 1.9 V output voltage range. The 2.8 V to 5.5 V input voltage range is suitable for a wide variety of low-voltage systems. With remote sensing, the DA9132-A guarantees the highest accuracy and supports multiple PCB routing scenarios without loss of performance. The pass devices are fully integrated, so no external FETs or Schottky diodes are needed. A programmable soft start-up can be enabled, which limits the inrush current from the input node and secures a slope-controlled rail activation. The dynamic voltage control (DVC) supports adaptive adjustment of the supply voltage dependent on the processor load, via either a direct register write using the communication interface (I2C-compatible) or with a programmable input pin. A configurable GPI allows multiple I2C address selection for multiple instances of DA9132-A in the same application. DA9132-A has integrated over-temperature and over-current protection for increased system reliability, without the need for external sensing components. Key Features ▪ 2.8 V to 5.5 V input voltage ▪ 0.3 V to 1.9 V output voltage ▪ Up to 3 A output current per channel ▪ 4 MHz nominal switching frequency ▪ Dual-channel ▪ 220 nH inductor per channel ▪ 20 µF output capacitor ▪ ±1 % output voltage accuracy (static) ▪ ±5 % load transient (dynamic) ▪ Programmable GPIOs ▪ Programmable soft startup ▪ I2C-compatible interface (FM+) ▪ Voltage, current, and temperature supervision ▪ 24-pin FCQFN package, wettable flanks (nom. 3.3 mm x 4.8 mm) ▪ 218 mm² total solution area ▪ -40 °C to +105 ºC ambient temperature range
- AEC-Q100 Grade 2 qualified for Automotive
applications
▪ Vehicle infotainment systems ▪ ADAS ▪ Automotive navigation ▪ Automotive center console ▪ Automotive cluster ▪ Telematics ▪ SIPP modules (SoC, DRAM) ▪ SoC/FPGA based, high performance, automotive Electronic Control unit (ECUI) requiring efficient, high current, power delivery
R16DS0579EJ0300 Rev.03.00 Sep 04, 2025 CFR0011-120-00 Page 2 Benefits ▪ High Efficiency buck converters deliver outstanding thermal performance ▪ Fully integrated switching FET’s means no external FETs or Schottky diodes are required ▪ Remote sensing guarantees the highest accuracy and supports multiple PCB routing scenarios without loss of performance. ▪ Fully programmable soft-start limits the inrush current from the input to give a slope-controlled output voltage. ▪ Dynamic voltage control (DVC) enables adaptive adjustment of the device output voltage depending on the load. This increases efficiency when the downstream circuitry enters low power or idle mode, resulting in power savings. ▪ Configurable GPIOs support a range of features including I2C, DVC and Power-Good indicator. ▪ Optimized BoM cost and footprint: Each output requires a very small inductor and capacitor delivering parts and cost savings ▪ Cycle by cycle current limiting for superior over-current protection
R16DS0579EJ0300 Rev.03.00 Sep 04, 2025 CFR0011-120-00 Page 4
Contents
R16DS0579EJ0300 Rev.03.00 Sep 04, 2025 CFR0011-120-00 Page 8 1. Terms and Definitions ATE Automated test equipment CPU Central processing unit DDR Dual data rate DVC Dynamic voltage control FET Field effect transistor FM+ Fast mode plus GBD Guaranteed by design GBQ Guaranteed by qualification GBSPC Guaranteed by statistical process characterization GPI General purpose input GPIO General purpose input/output GPU Graphics processing unit IC Integrated circuit HW Hardware OTP One time programmable PCB Printed circuit board PRS Product requirements specification SCL Serial clock SDA Serial data SIPP Single in-line pin package SW Software
R16DS0579EJ0300 Rev.03.00 Sep 04, 2025 CFR0011-120-00 Page 9 2. Pin Information
2.1 Pin Assignments
IC_ENAVDDAGNDCONF/ GPIO0GPIO1FB2P FB2N GPIO2 PVDD2 PVDD2 LX2 LX2 PGND PGND PGND PGND LX1 LX1 Figure 4. DA9132-A Pinout Diagram (Bottom View)
2.2 Pin Descriptions
Table 1. Pin Description
Description
1, 2 PVDD1 PS 5000 Supply for Ch1
3 SCL/GPIO3 DIO 15 SCL
4 FB1N AI 10 Negative feedback for Ch1
5 FB1P AI 10 Positive feedback for Ch1
6 SDA/GPIO4 DIO 15 SDA
7 IC_EN DI 10 IC enable.
8 AVDD PS 10 Analog supply
9 AGND PS 10 Analog ground
10 CONF/GPIO0 DIO 10 GPIO
11 GPIO1 DIO 10 GPIO
12 FB2P AI 10 Positive feedback for Ch2
13 FB2N AI 10 Negative feedback for Ch2
14 GPIO2 DIO 10 GPIO
15, 16 PVDD2 PS 5000 Supply for Ch2 17, 18 LX2 AO 5000 Buck output of Ch2
R16DS0579EJ0300 Rev.03.00 Sep 04, 2025 CFR0011-120-00 Page 10 Pin # Pin Name Type (Table 2) Drive (mA) 19, 20, 21, 22 PGND PS 5000 Power ground 23, 24 LX1 AO 5000 Buck output of Ch1 Table 2. Pin Type Definition
3.1 Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Rating conditions for extended periods may affect device reliability. conditions can adversely impact product reliability and result in failures not covered by warranty. Table 3. Absolute Maximum Ratings
3.2 Electrostatic Discharge Ratings
Table 4. Electrostatic Discharge Ratings
3.3 Recommended Operating Conditions
Table 5. Recommended Operating Conditions conditions, please consult with Renesas Electronics. Note 2 VSYS, VIN, PVDD, AVDD should be connected together. The pin names are different for routing purposes.
3.4 Thermal Specifications
Table 6. Package Ratings
3.4.1 Power Dissipation
Table 7. Power Dissipation Figure 5. Power Derating Curve
R16DS0579EJ0300 Rev.03.00 Sep 04, 2025 CFR0011-120-00 Page 13
3.5 Electrical Specifications
Electrical characteristics table limits are guaranteed by production testing, design, or correlation using standard statistical quality control methods unless otherwise stated. Typical (Typ) specifications are mean or average values at TA = 25°C and are not guaranteed. Recommended operating conditions unless otherwise noted. VIN = 4.5 V to 80 V, or VDD = 8 V ±10%, C_VCC5V = 4.7 µF, TA = -40°C to +125°C, Typical values are at TA = +25°C, unless otherwise specified. Table 8: Single-Phase Buck Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External electrical conditions VIN Input voltage VIN = VSYS 2.8 5.5 V COUT Output capacitance, including voltage and temperature coefficient -40 % 20 +30 % μF ESRCOUT Output capacitor series resistance f > 100 kHz 1 mΩ L Inductor value, including current and temperature dependence -50 % 220 +20 % nH DCRL Inductor DC resistance 8 13 mΩ Electrical performance VOUT Output voltage, configurable in 10 mV steps IOUT = 0 mA to IMAX at 25 °C ambient
2.8 V < VOUT + 1 V < VIN ≤
5.5 V 0.3 1.9 V ILIM Current limit, configurable per phase Note 1 Note 2 CHx_ILIM = 0100 -20 % 5 +20 % A IMAX Output current Note 3 VIN ≥ VOUT + 1.0 V 3 A VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT < 1 V -10 10 mV VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT ≥ 1 V -1 1 % VTHR_PG_HYS Power-good voltage threshold hysteresis VOUT = VTHR_PG_DWN 60 80 100 mV VTHR_PG_DWN Power-good voltage threshold for falling VOUT = VBUCK -160 -130 -80 mV VTHR_HV High VOUT voltage threshold VOUT = VBUCK 100 150 200 mV VOUT_TR_LINE Line transient response VIN = 3 V to 3.6 V IOUT = 0.5 * IMAX dt = 10 μs 15 mV fSW Switching frequency 4 MHz
R16DS0579EJ0300 Rev.03.00 Sep 04, 2025 CFR0011-120-00 Page 14 Parameter Description Conditions Min Typ Max Unit tON_MIN Minimum turn-on pulse 0 % duty is also supported 5 7 11 ns tBUCK_EN Turn-on time CHx_EN = high 20 μs RPD Output pull-down resistance at the LX node, see CHx_PD_DIS VIN = 3.7 V VOUT = 0.5 V 145 150 161 Ω RON_PMOS On resistance of switching PMOS VIN = 3.7 V 17 25 37 mΩ RON_NMOS On resistance of switching NMOS VIN = 3.7 V 6 10 16 mΩ PWM Mode IQ_PWM Quiescent current VIN = 3.7 V No load 16 mA ηPWM Efficiency VIN = 3.6 V VOUT = 1 V IOUT = 10 % (IMAX) to 80 % (IMAX) 85 % AUTO Mode VOUT_TR_LD Load transient response VOUT = 1 V IOUT = 1.25 to 3.75 A at 25 °C ambient dl/dt = 2.5 A/μs -30 55 mV PFM Mode IQ_PFM Quiescent current in PFM 1-phase VIN = 3.7 V No load No switching 88 μA ηPFM Efficiency VIN = 3.6 V VOUT = 1 V IOUT = 10 mA 80 % Note 1 tON > 40 ns Note 2 The value is configured by OTP and should not be modified while the buck is active. Note 3 For short durations to meet peak current requirements, IOUT can be operated at up to 10 % higher than the specified maximum operating condition. The part should not be operated in this mode for extended periods and is not guaranteed for continuous operation.
R16DS0579EJ0300 Rev.03.00 Sep 04, 2025 CFR0011-120-00 Page 15
3.6 Performance and Supervision Characteristics
Table 9: Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance VTHR_POR Power-on-reset threshold Threshold for AVDD falling 2.1 2.25 V VTHR_POR_HYS Power-on-reset hysteresis 200 mV TWARN Thermal warning temperature threshold 115 125 135 °C TCRIT Thermal shutdown temperature threshold 130 140 150 °C IIN_OFF Supply current OFF state TA = 27 °C IC_EN = 0 0.1 1 μA IIN_ON Supply current ON state TA = 27 °C IC_EN = 1 Buck off 5 10 20 μA
3.7 Timing Specifications
Table 10: I2C Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance tBUS Bus free time between a STOP and START condition 0.5 μs CBUS Bus line capacitive load 150 pF fSCL SCL clock frequency 20 Note 1 1000 kHz tLO_SCL SCL low time 0.5 μs tHI_SCL SCL high time 0.26 μs tRISE SCL and SDA rise time Requirement for input 1000 ns tFALL SCL and SDA fall time Requirement for input 300 ns tSETUP_START Start condition setup time 0.26 μs tHOLD_START Start condition hold time 0.26 μs tSETUP_STOP Stop condition setup time 0.26 μs tDATA Data valid time 0.45 μs tDATA_ACK Data valid acknowledge time 0.45 μs tSETUP_DATA Data setup time 50 ns
R16DS0579EJ0300 Rev.03.00 Sep 04, 2025 CFR0011-120-00 Page 16 Parameter Description Conditions Min Typ Max Unit tHOLD_DATA Data hold time 0 ns Note 1 Minimum clock frequency is limited to 20 kHz if I2C_TIMEOUT is enabled
3.8 Digital I/O Characteristics
Table 11: Digital I/O Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance VIH_EN Input high voltage, IC enable 1.2 AVDD V VIL_EN Input low voltage, IC enable 0.4 V tIC_EN IC enable time 1000 μs VIH_GPIO_SCL_SDA Input high voltage GPIO, SCL, SDA 1.2 AVDD V VIL_GPIO_SCL_SDA Input low voltage GPIO, SCL, SDA 0.4 V VOH_GPIO Output high voltage GPIO Push-pull mode IOUT = 1 mA 0.8*AV DD AVDD V VOL_GPIO Output low voltage GPIO Push-pull mode IOUT = 1 mA 0.2*AV DD V VOL_SDA Output low voltage SDA IOUT = 3 mA 0.24 V RPD GPIO pull-down resistor VSYS = 3.7 V Note 1 9 15 24 kΩ RPU GPIO pull-up resistor VSYS = 3.7 V Note 1 28 45 70 kΩ Note 1 Resistance may have greater variation, depending on voltage and temperature.
R16DS0579EJ0300 Rev.03.00 Sep 04, 2025 CFR0011-120-00 Page 18 5. Functional Description
5.1 DC-DC Buck Converter
DA9132-A contains two buck converters, Buck1 and Buck2, each capable of delivering up to 3 A output current at a 0.3 V to 1.9 V output voltage range. Buck1 and Buck2 have two voltage registers each. One defines the normal output voltage, while the other offers an alternative retention voltage. In this way, different application power modes can easily be supported. The voltage selection can be operated either via GPI or via control interface to guarantee the maximum flexibility according to the specific host processor status in the application. When a buck is enabled, its output voltage is monitored and a power-good signal indicates that the buck output voltage has reached a level higher than the VTHR_PG_HYS threshold. The power-good status is lost when the voltage drops below VTHR_PG_DWN or increases above VTHR_HV. For each of the buck converters the status of the power-good indicator can be read back via I2C from the PG1 and PG2 status bits. It can be also individually assigned to any of the GPIOs by setting the GPIO mode registers to either PG1 or PG2 output. The buck converters are capable of supporting DVC transitions that occur when: ▪ the active and selected A- or B-voltage is updated to a new target value ▪ the voltage selection is changed from the A- to B-voltage (or B- to A-voltage) using CH<x>_VSEL The DVC controller operates in pulse width modulation (PWM) mode with synchronous rectification. The slew rate of the DVC transition is individually programmed for each buck converter at 10 mV per (8, 4, 2, 1, or 0.5)µs in register bits CH1_SR_DVC and CH2_SR_DVC. A pull-down resistor (typically 150 Ω) for each phase is always activated unless it is disabled by setting register bits CH<x>_PD_DIS to 1.
5.1.1 Switching Frequency
The buck switching frequency, nominally 4 MHz, can be tuned using register bit OSC_TUNE. The internal 8 MHz oscillator frequency is tuned in ±160 kHz steps. This impacts the buck converter frequency in steps of 80 kHz and helps to mitigate possible disturbances to other high frequency systems in the application.
5.1.2 Operation Modes and Phase Selection
The buck converters can operate in PWM and PFM modes. The operating mode is selected using register bits CH1_<A or B>_MODE and CH2_<A or B>_MODE. If the automatic operation mode is selected on CH1_<A or B>_MODE or CH2_<A or B>_MODE, the buck converters automatically change between synchronous PWM mode and PFM depending on the load current. This improves the efficiency across the whole range of output load currents.
5.1.3 Output Voltage Selection
The switching converter can be configured using the I2C interface. For each buck converter two output voltages can be pre-configured in registers CH<x>_<A or B>_VOUT. The output voltage can be selected by either toggling register bit CH<x>_VSEL or by re-programming the selected voltage control register. Both changes will result in ramped voltage transitions. After being enabled, the buck converter will, by default, use the register settings in CH<x>_A_VOUT unless the output voltage selection is configured via the GPI port. Registers CH<1 and 2>_VMAX limit the output voltage that can be set for each of the respective buck converters.
Figure 8. Buck Output Voltage Control Concept
5.1.4 Soft Start-Up and Shutdown
higher than 20 mV/µs may produce overshoot during the start-up phase, so they should be considered carefully. registers CH<1 and 2>_PD_DIS.
5.1.5 Current Limit
limit should be configured to at least 40% higher than the required maximum output current. OC_DVC_MASK is used to mask over-current events during DVC transitions.
5.1.6 Resistive Divider
DA9132-A can support output voltages higher than 1.9 V using an external resistive divider shown in Figure 9. VSEL is the device buck output voltage setting.
Figure 9. Resistive Divider resistors. The voltage across FB1P and FB1N (VSEL) is guaranteed, but not the output voltage accuracy.
- Please contact your region's Renesas representative when adopting the resistive divider technique. Renesas need to
prepare a special OTP because incorrect OTP settings may result in a different output voltage than expected.
- The total resistance (R1+R2) is less than 40 kΩ.
It is recommended that the device is operated in PWM mode only.
5.1.7 Thermal Protection
DA9132-A is protected from internal overheating by thermal shutdown. thermal limits, an IRQ is raised and an event is set, although the chip continues working. below TWARN and the event flags need to be cleared before starting the bucks. Table 12. Thermal Protection Control Registers
Figure 10. Thermal Protection Operation
5.2 Internal Circuits
5.2.1 IC_EN/Chip Enable/Disable
down and the buck output is pulled-down. Table 13. Interrupt List
Note 1 Interrupt outputs the status as is. I2C write is not required for interrupt clear. Note 2 OTP load value defined by CONF pin setting if CONF_EN = 1, see section 5.2.3.3. Table 14 and Table 15 show the interrupt registers structure. See section 5.1.1 for bitfield descriptions. Table 14. Interrupt Registers Except for Power-Good Status
Cleared after being written to I2C. Set until IRQ is removed. 1: Masked. No IRQ signal sent. Event register (E_<name>) is updated. Table 15. Interrupt Registers for Power-Good, System Good, and Temp Warning Status It is possible to route interrupts to a GPIO by setting the bitfield GPIO<x>_MODE = 0xC on the relevant GPIO. system-good status is high, and pulled low if an event listed in the Table 13 occurs.
- GPIO is configured as nIRQ
- M_SG_STAT = 0 Condition IRQ Not Masked System NOT Good
Figure 14. Interrupt Operation Example 4
5.2.3 GPIO
5.2.3.1 GPIO Pin Assignment
programmable. When CONF_EN = 1 GPIO0 can be used for chip configuration. Note: GPIO3 and GPIO4 functions are limited only to output features if I2C_EN = 0. Table 16. GPIO Pin Assignment
5.2.3.2 GPIO Function
Table 17. GPIO Function Configuration
Figure 15. Power-Good (PG) and System Good (SG)
5.2.3.3 Chip Configuration Select (CONF)
GPIO0 functions as chip configuration select (CONF) input when CONF_EN = 1. Three different chip configurations can be selected according to the CONF pin level. ▪ GPIO0 floating: CONF2 - not recommended. lists the device configurations can be modified if CONF_EN = 1. Table 18. GPIO0-Configurable Registers when CONF_EN = 1
R16DS0579EJ0300 Rev.03.00 Sep 04, 2025 CFR0011-120-00 Page 28 Register Name Description CH1_A_VOUT[7:0] CH1 output voltage setting A CH1_B_VOUT[7:0] CH1 output voltage setting B CH2_A_MODE[1:0] CH2_A Operation mode select CH2_B_MODE[1:0] CH2_B Operation mode select CH2_VSEL CH2 output voltage and operation selection CH2_EN CH2 enable CH2_A_VOUT[7:0] CH2 output voltage setting A CH2_B_VOUT[7:0] CH2 output voltage setting B M_PG1_STAT IRQ mask setting for CH1 power-good status M_PG2_STAT IRQ mask setting for CH2 power-good status M_SG_STAT IRQ mask setting for system good status M_VR_HOT IRQ mask setting for temp warning status CH1_EN_DLY[3:0] Delay setting for CH1 enable CH1_DIS_DLY[3:0] Delay setting for CH1 disable CH2_EN_DLY[3:0] Delay setting for CH2 enable CH2_DIS_DLY[3:0] Delay setting for CH2 disable GPIO1_MODE[3:0] GPIO1 mode setting GPIO2_MODE[3:0] GPIO2 mode setting GPIO1_OBUF GPIO1 output buffer select GPIO2_OBUF GPIO2 output buffer select GPIO1_TRIG[1:0] GPIO1 input trigger select GPIO1_POL GPIO1 polarity select GPIO1_PUPD GPIO1 pull-up/pull-down enable GPIO1_DEB[1:0] GPIO1 input debounce time setting GPIO1_DEB_RISE GPIO1 input debounce rising edge enable GPIO1_DEB_FALL GPIO1 input debounce falling edge enable GPIO2_TRIG[1:0] GPIO2 input trigger select GPIO2_POL GPIO2 polarity select GPIO2_PUPD GPIO2 pull-up/pull-down enable GPIO2_DEB[1:0] GPIO2 input debounce time setting GPIO2_DEB_RISE GPIO2 input debounce rising edge enable GPIO2_DEB_FALL GPIO2 input debounce falling edge enable
5.3 Operating Modes
5.3.1 ON DA9132-A is ON when the IC_EN port is higher than VIH_EN and the supply voltage is higher than VTHR_POR. Once enabled, the host processor can start communicating with DA9132-A using the control interface, after the tIC_EN delay.
5.3.2 OFF
DA9132-A is OFF when the IC_EN port is lower than VIL_EN. In OFF, the bucks are always disabled and LX nodes are pulled down by (typically 150 Ω) internal pull-down resistors.
5.4 I2C Communication
0 I2C disable: SCL/GPIO3 and SDA/GPIO4 pins should be used as GPO
1 I2C enable: SCL/GPIO3 and SDA/GPIO4 pins are used as I2C clock input and I2C data input/output. (FM+), 400 kHz in fast-mode, or 100 kHz in standard mode.
5.4.1 I2C Protocol
brought high and then low. This pulse on SCL clocks the SDA bit into the receiver’s shift register. while the SCL is in the high state). Figure 16. I2C START and STOP Condition Timing following clock cycle (white blocks marked with A in Figure 17 and Figure 18). read/write bit, and the eight-bit register address followed by eight bits of data, terminated by a STOP condition. DA9132-A responds to all bytes with acknowledge (A), see Figure 17. Figure 17. I2C Byte Write (SDA Line) the host sends no acknowledge (A*) and terminates the transmission with a STOP condition, see Figure 18. address to the register SYS_CFG_SLVADDR, see section 7.1.1.
Figure 18. I2C Byte Read (SDA Line) Examples
The following recommended components are examples selected from requirements of a typical application.
6.1 Capacitor Selection
Table 19. Recommended Automotive Grade Capacitor Types
6.2 Inductor Selection
Critical for the converter efficiency and should therefore be minimized. Table 20. Recommended Inductor Types
7.1 Register Map
Table 21. Register Map
R16DS0579EJ0300 Rev.03.00 Sep 04, 2025 CFR0011-120-00 Page 33 Addr Register 7 6 5 4 3 2 1 0 Buck Control Buck1 0x20 BUCK_BUCK1_0 Reserved CH1_SR_DVC_DWN<2:0> CH1_SR_DVC_UP<2:0> CH1_EN 0x21 BUCK_BUCK1_1 Reserved CH1_SR_SHDN<2:0> CH1_SR_STARTUP<2:0> CH1_PD_DIS 0x22 BUCK_BUCK1_2 Reserved Reserved Reserved Reserved CH1_ILIM<3:0> 0x23 BUCK_BUCK1_3 CH1_VMAX<7:0> 0x24 BUCK_BUCK1_4 Reserved Reserved Reserved CH1_VSEL CH1_B_MODE<1:0> CH1_A_MODE<1:0> 0x25 BUCK_BUCK1_5 CH1_A_VOUT<7:0> 0x26 BUCK_BUCK1_6 CH1_B_VOUT<7:0> Buck2 0x28 BUCK_BUCK2_0 Reserved CH2_SR_DVC_DWN<2:0> CH2_SR_DVC_UP<2:0> CH2_EN 0x29 BUCK_BUCK2_1 Reserved CH2_SR_SHDN<2:0> CH2_SR_STARTUP<2:0> CH2_PD_DIS 0x2A BUCK_BUCK2_2 Reserved Reserved Reserved Reserved CH2_ILIM<3:0> 0x2B BUCK_BUCK2_3 CH2_VMAX<7:0> 0x2C BUCK_BUCK2_4 Reserved Reserved Reserved CH2_VSEL CH2_B_MODE<1:0> CH2_A_MODE<1:0> 0x2D BUCK_BUCK1_5 CH2_A_VOUT<7:0> 0x2E BUCK_BUCK1_6 CH2_B_VOUT<7:0> Serialization 0x48 OTP_DEVICE_ID DEV_ID<7:0> 0x49 OTP_VARIANT_ID MRC<3:0> VRC<3:0> 0x4A OTP_CUSTOMER_ID CUST_ID<7:0> 0x4B OTP_CONFIG_ID CONFIG_REV<7:0>
7.1.1 System
Table 22. SYS_STATUS_0 (0x01) Table 23. SYS_STATUS_1 (0x02) Table 24. SYS_STATUS_2 (0x03) Table 25. SYS_EVENT_0 (0x04) Table 26. SYS_EVENT_1 (0x05)
Table 27. SYS_EVENT_2 (0x06) Table 28. SYS_MASK_0 (0x07) Table 29. SYS_MASK_1 (0x08) Table 30. SYS_MASK_2 (0x09) Table 31. SYS_MASK_3 (0x0A) setting at the start-up if CONF_EN = 1, see section 5.2.3.3. the start-up if CONF_EN = 1, see section 5.2.3.3.
the start-up if CONF_EN = 1, see section 5.2.3.3. the start-up if CONF_EN = 1, see section 5.2.3.3. Table 32. SYS_CONFIG_0 (0x0B)
R16DS0579EJ0300 Rev.03.00 Sep 04, 2025 CFR0011-120-00 Page 37 Bit Type Symbol Description [3:0] RW CH1_EN_DLY Delay for CH1 enable. Active with GPIO configured as EN1&EN2 control and IC_EN control. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 0 0x1 0.5 ms 0x2 1.0 ms 0x3 1.5 ms 0x4 2.0 ms 0x5 2.5 ms 0x6 3.0 ms 0x7 3.5 ms 0x8 4.0 ms 0x9 4.5 ms 0xA 5.0 ms 0xB 5.5 ms 0xC 6.0 ms 0xD 6.5 ms 0xE 7.0 ms 0xF 7.5 ms
Table 33. SYS_CONFIG_1 (0x0C)
Table 34. SYS_CONFIG_2 (0x0D)
Table 35. SYS_CONFIG_3 (0x0E) [1] RW I2C_TIMEOUT Enable automatic reset of 2-wire interface (if SDA stays low for >50 ms). Table 36. SYS_GPIO0_0 (0x10)
Table 37. SYS_GPIO0_1 (0x11)
Table 38. SYS_GPIO1_0 (0x12) Table 39. SYS_GPIO1_1 (0x13)
Table 40. SYS_GPIO2_0 (0x14)
Table 41. SYS_GPIO2_1 (0x15) Table 42. SYS_CFG_SLVADDR (0xA1)
7.1.2 Buck1
Table 43. BUCK_BUCK1_0 (0x20) Table 44. BUCK_BUCK1_1 (0x21)
Table 45. BUCK_BUCK1_2 (0x22) should not be modified while the buck is active.
Table 46. BUCK_BUCK1_3 (0x23) This is a read-only register. Table 47. BUCK_BUCK1_4 (0x24) Output voltage and operation selection: 0: A, 1: B.
Table 48. BUCK_BUCK1_5 (0x25) Table 49. BUCK_BUCK1_6 (0x26)
7.1.3 Buck2
Table 50. BUCK_BUCK2_0 (0x28) Table 51. BUCK_BUCK2_1 (0x29)
Table 52. BUCK_BUCK2_2 (0x2A)
Table 53. BUCK_BUCK2_3 (0x2B) This is a read-only register. Table 54. BUCK_BUCK2_4 (0x2C)
Table 55. BUCK_BUCK2_5 (0x2D) Table 56. BUCK_BUCK2_6 (0x2E)
7.1.4 Serialization
Table 57. OTP_DEVICE_ID (0x48) Table 58. OTP_VARIANT_ID (0x49) Table 59. OTP_CUSTOMER_ID (0x4A) Table 60. OTP_CONFIG_ID (0x4B)
- Moisture Sensitivity Level
MSL classification is defined in Table 61. The FCQFN package is qualified for MSL 3. Table 61. MSL Classification
8.1 Soldering Information
downloaded from http://www.jedec.org.
9.1 Package Outlines
Figure 19. Package Outline Drawing
9.2 Package Marking
2nd D A 9 1 3 2 Orientation/Part No. A or AT optionally indicate the Automotive and Automotive high temp test options.
R16DS0579EJ0300 Rev.03.00 Sep 04, 2025 CFR0011-120-00 Page 56 10. Ordering Information The ordering number consists of the part number followed by a suffix indicating the packing method. For details and availability, please consult your Renesas local sales representative. Table 62. Ordering Information
24 FCQFN
wettable flanks, 3.3 x 4.8 T&R, 4800 pcs 3 Reels - 14400 AEC-Q100 Grade 2 DA9132-AxxRT1-A wettable flanks, 3.3 x 4.8 Tray, 490 pcs 30 Trays - 14700 pcs AEC-Q100 Grade 2 DA9132-AxxRT2-AT wettable flanks, 3.3 x 4.8 T&R, 4800 pcs 3 Reels - 14400 AEC-Q100 Grade 2 DA9132-AxxRT1-AT wettable flanks, 3.3 x 4.8 Tray, 490 pcs 30 Trays - 14700 pcs AEC-Q100 Grade 2
10.1 Variants Ordering Information
DA9132 supports delivery of variants indicated by xx in the part number above, where xx is replaced with the actual variant number. Please contact your Renesas local sales representative to discuss requirements.
Figure 20. DA9132-A Footprint ▪ Standard pads are 0.85 mm x 0.3 mm with 0.05 mm radius corners. ▪ Solder paste on custom pads is split into multiple apertures meeting standard area coverage of 30 to 70%.
11.1 Custom Pads Details
Figure 21. DA9132-A Footprint Details
R16DS0579EJ0300 Rev.03.00 Sep 04, 2025 CFR0011-120-00 Page 58 RoHS Compliance Renesas Electronics’ suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from our suppliers are available on request.
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