DA9131

Renesas Technology Corp

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications July 18, 2025

Manufacturer: Renesas Technology Corp

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High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 1 of 57 © 2022 Renesas Electronics General Description DA9131 is an power management IC (PMIC) suitable for supplying CPUs, GPUs, DDR memory rails in single in-line pin package (SIPP) modules, mobile, portable and consumer applications. DA9131 integrates two single-phase buck converters, each phase requiring a small external 0.22 µH inductor. Each buck is capable of delivering up to 5 A output current at a 0.3 V to 1.9 V output voltage range. The 2.8 V to 5.5 V input voltage range is suitable for a wide variety of low-voltage systems. With remote sensing, the DA9131 guarantees the highest accuracy and supports multiple PCB routing scenarios without loss of performance. The pass devices are fully integrated, so no external FETs or Schottky diodes are needed. A programmable soft start-up can be enabled, which limits the inrush current from the input node and secures a slope-controlled rail activation. The dynamic voltage control (DVC) supports adaptive adjustment of the supply voltage dependent on the processor load, via either a direct register write using the communication interface (I 2C- compatible) or with a programmable input pin. A configurable GPI allows multiple I2C address selection for multiple instances of DA9131 in the same application. DA9131 has integrated over-temperature and over-current protection for increased system reliability, without the need for external sensing components. Key Features ■ 2.8 V to 5.5 V input voltage ■ 0.3 V to 1.9 V output voltage ■ Up to 5 A output current per channel ■ 4 MHz nominal switching frequency ■ Dual-channel ■ 220 nH inductor per channel ■ 20 µF output capacitor ■ ±1 % output voltage accuracy (static) ■ ±5 % load transient (dynamic) ■ Programmable GPIOs ■ Programmable soft startup ■ I2C-compatible interface (FM+) ■ Voltage, current, and temperature supervision ■ 24-pin FCQFN package, wettable flanks (nom. 3.3 mm x 4.8 mm) ■ 218 mm² total solution area ■ -40 °C to +105 ºC ambient temperature range ■ AEC-Q100 Grade 2 qualified version also available for Automotive applications (DA9131-A) Benefits ■ High Efficiency buck converters deliver outstanding thermal performance ■ Fully integrated switching FET’s means no external FETs or Schottky diodes are required ■ Remote sensing guarantees the highest accuracy and supports multiple PCB routing scenarios without loss of performance. ■ Fully programmable soft-start limits the inrush current from the input to give a slope-controlled output voltage. ■ Dynamic voltage control (DVC) enables adaptive adjustment of the device output voltage depending on the load. This increases efficiency when the downstream circuitry enters low power or idle mode, resulting in power savings. ■ Configurable GPIOs support a range of features including I2C, DVC and Power-Good indicator.

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 2 of 57 © 2022 Renesas Electronics ■ Optimized BoM cost and footprint: Each output requires a very small inductor and capacitor delivering parts and cost savings ■ Cycle by cycle current limiting for superior over-current protection

Applications

■ Switches and routers ■ Smart metering ■ Industrial automation ■ Wireless ■ Consumer products ■ SoC/FPGA based, high performance, automotive Electronic Control unit (ECUI) requiring efficient, high current, power delivery ■ SIPP modules (SoC, DRAM)

1 Terms and Definitions

ATE Automated Test Equipment CPU Central Processing Unit DDR Dual Data Rate DVC Dynamic Voltage Control FET Field Effect Transistor FM+ Fast Mode Plus GBD Guaranteed By Design GBQ Guaranteed By Qualification GBSPC Guaranteed By Statistical Process Characterization GPI General Purpose Input GPIO General Purpose Input/Output GPU Graphics Processing Unit IC Integrated Circuit HW Hardware OTP One Time Programmable PCB Printed Circuit Board PRS Product Requirements Specification SCL Serial Clock SDA Serial Data SIPP Single In-Line Pin Package SW Software

2 Pinout

IC_ENAVDDAGNDCONF/ GPIO0GPIO1FB2P FB2N GPIO2 PVDD2 PVDD2 LX2 LX2 PGND PGND PGND PGND LX1 LX1 Figure 4: DA9131 Pinout Diagram (Bottom View) Table 1: Pin Description Pin # Pin Name Type (Table 2) Drive (mA)

Description

1, 2 PVDD1 PS 5000 Supply for Ch1

3 SCL/GPIO3 DIO 15 SCL

4 FB1N AI 10 Negative feedback for Ch 1

5 FB1P AI 10 Positive feedback for Ch 1

6 SDA/GPIO4 DIO 15 SDA

7 IC_EN DI 10 IC enable.

8 AVDD PS 10 Analog supply

9 AGND PS 10 Analog ground

10 GPIO0 DIO 10 GPIO

11 CONF/GPIO1 DIO 10 GPIO

12 FB2P AI 10 Positive feedback for Ch 2

13 FB2N AI 10 Negative feedback for Ch 2

14 GPIO2 DIO 10 GPIO

15, 16 PVDD2 PS 5000 Supply for Ch2 17, 18 LX2 AO 5000 Buck output of Ch 2 19, 20, 21, 22 PGND PS 5000 Power ground 23, 24 LX1 AO 5000 Buck output of Ch 1

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 9 of 57 © 2022 Renesas Electronics Table 2: Pin Type Definition Pin Type Description Pin Type Description DI Digital input AI Analog input DIO Digital input/output AO Analog output PS Power supply

3 Characteristics

3.1 Absolute Maximum Ratings

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Table 3: Absolute Maximum Ratings Parameter Description Conditions Min Max Unit TSTG Storage temperature -65 150 °C TJ Junction temperature -40 150 °C VSYS System supply voltage -0.3 6.0 V VPIN Voltage on pins -0.3 6.0 V

3.2 Recommended Operating Conditions

Table 4: Recommended Operating Conditions Parameter Description (Note 2) Conditions (Note 1) Min Typ Max Unit VSYS System supply voltage 2.8 5.5 V VPIN Voltage on pins -0.3 VSYS + 0.3 V TJ Junction temperature -40 125 °C TA Ambient temperature -40 105 °C Note 1 Within the specified limits, a lifetime of 10 years is guaranteed. If operating outside of these recommended conditions, please consult with Dialog Semiconductor. Note 2 VSYS, VIN, PVDD, AVDD should be connected together. The pin names are different for routing purposes.

3.3 Thermal Characteristics

3.3.1 Thermal Ratings

Table 5: Package Ratings Parameter Description Conditions Min Typ Max Unit JA Package thermal resistance Note 1 21.21 °C/W JB Thermal resistance junction to board Note 1 12.37 °C/W JC Thermal resistance junction to case Without PCB 32 °C/W Note 1 Obtained from package thermal simulations, JEDEC 2S2P four layer board (76.2 mm x 114 mm x 1.6 mm), 70 μm (2 oz) copper thickness power planes, 35 μm (1 oz) copper thickness signal layer traces, natural convection (still air), see Section 6.1.

3.3.2 Power Dissipation

Table 6: Power Dissipation Parameter Description Conditions Min Typ Max Unit PD_Twarn Power dissipation @105 °C ambient, TJ_WARN 0.94 W PD_Tcrit Power dissipation @105 °C ambient, TCRIT 1.41 1.65 W PD_70 Power dissipation @70°C ambient 2.43 W Figure 5: Power Derating Curve

3.3.3 ESD Characteristics

Table 7: ESD Characteristics Parameter Description Conditions Value Unit VESD_HBM ESD protection, human body model (HBM) 2 kV VESD_CDM Maximum ESD protection Charged device model (CDM) 500 V

3.4 Buck Characteristics

Unless otherwise noted, the following is valid for TJ = -40 °C to +125 °C, VSYS = 2.8 V to 5.5 V. Table 8: Buck Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External Electrical Conditions VIN Input voltage VIN = VSYS 2.8 5.5 V COUT Output capacitance, including voltage and temperature coefficient -40 % 20 +30 % μF ESRCOUT Output capacitor series resistance f > 100 kHz 1 mΩ L Inductor value, including current and temperature dependence -50 % 220 +20 % nH DCRL Inductor DC resistance 8 13 mΩ Electrical Performance VOUT Output voltage, configurable in 10 mV steps IOUT = 0 mA to IMAX at 25 °C ambient

2.8 V < VOUT + 1 V < VIN ≤

5.5 V 0.3 1.9 V ILIM Current limit, configurable per phase Note 1 Note 2 CHx_ILIM = 1010 -20 % 8 +20 % A IMAX_0V7 Output current Note 3 VIN ≥ VOUT + 0.7 V 2 A IMAX_1V0 Output current Note 3 VIN ≥ VOUT + 1.0 V 5.6 A VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT < 1 V -10 10 mV VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT ≥ 1 V -1 1 % VTHR_PG_HYS Power-good voltage threshold hysteresis VOUT = VTHR_PG_DWN 60 80 100 mV VTHR_PG_DWN Power-good voltage threshold for falling VOUT = VBUCK -160 -130 -80 mV VTHR_HV High VOUT voltage threshold VOUT = VBUCK 100 150 200 mV VOUT_TR_LINE Line transient response VIN = 3 V to 3.6 V IOUT = 0.5 * IMAX dt = 10 μs 15 mV

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 13 of 57 © 2022 Renesas Electronics Parameter Description Conditions Min Typ Max Unit fSW Switching frequency 4 MHz tON_MIN Minimum turn-on pulse 0 % duty is also supported 5 7 11 ns tBUCK_EN Turn-on time CHx_EN = high 20 μs RPD Output pull-down resistance at the LX node, see CHx_PD_DIS VIN = 3.7 V VOUT = 0.5 V 145 150 161 Ω RON_PMOS On resistance of switching PMOS VIN = 3.7 V 17 25 37 mΩ RON_NMOS On resistance of switching NMOS VIN = 3.7 V 6 10 16 mΩ PWM Mode IQ_PWM Quiescent current VIN = 3.7 V No load 16 mA ηPWM Efficiency VIN = 3.6 V VOUT = 1 V IOUT = 10 % (IMAX) to 80 % (IMAX) 85 % AUTO Mode VOUT_TR_LD Load transient response VOUT = 1 V IOUT = 1.25 to 3.75 A at 25 °C ambient dl/dt = 2.5 A/μs -30 55 mV PFM Mode IQ_PFM Quiescent current in PFM 1-phase VIN = 3.7 V No load No switching 88 μA ηPFM Efficiency VIN = 3.6 V VOUT = 1 V IOUT = 10 mA 80 % Note 1 tON > 40 ns Note 2 The value is configured by OTP and should not be modified while the buck is active. Note 3 For short durations to meet peak current requirements, IOUT can be operated at up to 10 % higher than the specified maximum operating condition. The part should not be operated in this mode for extended periods and is not guaranteed for continuous operation.

3.5 Performance and Supervision Characteristics

Table 9: Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical Performance VTHR_POR Power-on-reset threshold Threshold for AVDD falling 2.1 2.25 V VTHR_POR_HYS Power-on-reset hysteresis 200 mV TWARN Thermal warning temperature threshold 115 125 135 °C TCRIT Thermal shutdown temperature threshold 130 140 150 °C IIN_OFF Supply current OFF state TA = 27 °C IC_EN = 0 0.1 1 μA IIN_ON Supply current ON state TA = 27 °C IC_EN = 1 Buck off 5 10 20 μA

3.6 Digital I/O Characteristics

Table 10: Digital I/O Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical Performance VIH_EN Input high voltage, IC enable 1.2 AVDD V VIL_EN Input low voltage, IC enable 0.4 V tIC_EN IC enable time 1000 μs VIH_GPIO_SCL_SDA Input high voltage GPIO, SCL, SDA 1.2 AVDD V VIL_GPIO_SCL_SDA Input low voltage GPIO, SCL, SDA 0.4 V VOH_GPIO Output high voltage GPIO Push-pull mode IOUT = 1 mA 0.8*AV DD AVDD V VOL_GPIO Output low voltage GPIO Push-pull mode IOUT = 1 mA 0.2*AV DD V VOL_SDA Output low voltage SDA IOUT = 3 mA 0.24 V RPD GPIO pull-down resistor VSYS = 3.7 V Note 1 9 15 24 kΩ RPU GPIO pull-up resistor VSYS = 3.7 V Note 1 28 45 70 kΩ Note 1 Resistance may have greater variation, depending on voltage and temperature.

3.7 Timing Characteristics

Table 11: I2C Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical Performance tBUS Bus free time between a STOP and START condition 0.5 μs CBUS Bus line capacitive load 150 pF fSCL SCL clock frequency 20 Note 1 1000 kHz tLO_SCL SCL low time 0.5 μs tHI_SCL SCL high time 0.26 μs tRISE SCL and SDA rise time Requirement for input 1000 ns tFALL SCL and SDA fall time Requirement for input 300 ns tSETUP_START Start condition setup time 0.26 μs tHOLD_START Start condition hold time 0.26 μs tSETUP_STOP Stop condition setup time 0.26 μs tDATA Data valid time 0.45 μs tDATA_ACK Data valid acknowledge time 0.45 μs tSETUP_DATA Data setup time 50 ns tHOLD_DATA Data hold time 0 ns Note 1 Minimum clock frequency is limited to 20 kHz if I2C_TIMEOUT is enabled

3.8 Typical Performance

Figure 6: DA9131 Efficiency at VOUT = 1.0 V, PWM Mode Figure 7: DA9131 Efficiency at VOUT = 1.0 V, Auto Mode

4 Functional Description

4.1 DC-DC Buck Converter

DA9131 contains two buck converters, Buck1 and Buck2, each capable of delivering up to 5 A output current at a 0.3 V to 1.9 V output voltage range. Buck1 and Buck2 have two voltage registers each. One defines the normal output voltage, while the other offers an alternative retention voltage. In this way, different application power modes can easily be supported. The voltage selection can be operated either via GPI or via control interface to guarantee the maximum flexibility according to the specific host processor status in the application. When a buck is enabled, its output voltage is monitored and a power-good signal indicates that the buck output voltage has reached a level higher than the VTHR_PG_HYS threshold. The power-good status is lost when the voltage drops below VTHR_PG_DWN or increases above VTHR_HV. For each of the buck converters the status of the power-good indicator can be read back via I2C from the PG1 and PG2 status bits. It can be also individually assigned to any of the GPIOs by setting the GPIO mode registers to either PG1 or PG2 output. The buck converters are capable of supporting DVC transitions that occur when:

the active and selected A- or B-voltage is updated to a new target value
the voltage selection is changed from the A- to B-voltage (or B- to A-voltage) using CH<x>_VSEL The DVC controller operates in pulse width modulation (PWM) mode with synchronous rectification. The slew rate of the DVC transition is individually programmed for each buck converter at 10 mV per 8 µs, 4 µs, 2 µs, 1 µs, or 0.5 µs in register bits CH1_SR_DVC and CH2_SR_DVC. A pull-down resistor (typically 150 Ω) for each phase is always activated unless it is disabled by setting register bits CH<x>_PD_DIS to 1.

4.1.1 Switching Frequency

The buck switching frequency, nominally 4 MHz, can be tuned using register bit OSC_TUNE. The internal 8 MHz oscillator frequency is tuned in ±160 kHz steps. This impacts the buck converter frequency in steps of 80 kHz and helps to mitigate possible disturbances to other high frequency systems in the application.

4.1.2 Operation Modes and Phase Selection

The buck converters can operate in PWM and PFM modes. The operating mode is selected using register bits CH1_<A or B>_MODE and CH2_<A or B>_MODE. If the automatic operation mode is selected on CH1_<A or B>_MODE or CH2_<A or B>_MODE, the buck converters automatically change between synchronous PWM mode and PFM depending on the load current. This improves the efficiency across the whole range of output load currents.

4.1.3 Output Voltage Selection

The switching converter can be configured using the I2C interface. For each buck converter two output voltages can be pre-configured in registers CH<x>_<A or B>_VOUT. The output voltage can be selected by either toggling register bit CH <x>_VSEL or by re- programming the selected voltage control register. Both changes will result in ramped voltage transitions. After being enabled, the buck converter will, by default, use the register settings in CH<x>_A_VOUT unless the output voltage selection is configured via the GPI port. Registers CH<1 and 2>_VMAX limit the output voltage that can be set for each of the respective buck converters. Figure 8: Buck Output Voltage Control Concept

4.1.4 Soft Start-Up and Shutdown

To limit in-rush current from VSYS, the buck converters can perform a soft-start after being enabled. The start-up behavior is a compromise between acceptable inrush current from the battery and turn - on time. Individual ramp times can be configured for each buck converter in registers CH<1 and 2>_SR_STARTUP respectively. Rates higher than 20 mV/µs may produce overshoot during the start-up phase, so they should be considered carefully. A ramped power down can be selected in register bits CH<1 and 2>_SR_SHDN. When no ramp is selected (immediate power down), the output node will be discharged on ly by the pull-down resistor, if enabled in registers CH<1 and 2>_PD_DIS.

4.1.5 Current Limit

The integrated current limit protects the power stages and external coil from excessive current. The buck current limit should be configured to at least 40 % higher than the required maximum output current. When the current limit is reached, each buck converter generates an event and an interrupt to the host processor unless the interrupt has been masked using register M_OC<x> in SYS_MASK_1. Register bits OC_DVC_MASK is used to mask over-current events during DVC transitions.

4.1.6 Resistive Divider

DA9131 can support output voltages higher than 1.9 V using an external resistive divider shown in Figure 9. To calculate the output voltage with an external divider, use the following equation 𝑉𝑂𝑈𝑇 = 𝑉𝑆𝐸𝐿 × (1 + 𝑅1 𝑅2) Equation 1 VSEL is the device buck output voltage setting. Figure 9: Resistive Divider For example, to program the output voltage to 3.3 V, set VSEL to 1.65 V, and use a 2.2 kΩ resistor for both R1 and R2, with Cff = 1 nF. NOTE The resistors need to be properly selected since the output voltage accuracy will be directly affected by any errors on the resistors. The voltage across FB1P and FB1N (VSEL) is guaranteed, but not the output voltage accuracy. CAUTION The followings are important notes that need to be considered before using resistive divider on DA9131: 1. Please contact your region's Dialog representative when adopting the resistive divider technique. Dialog need to prepare a special OTP because incorrect OTP settings may result in a different output voltage than expected. 2. The total resistance (R1+R2) is less than 40 kΩ. 3. It is recommended that the device is operated in PWM mode only.

4.1.7 Thermal Protection

DA9131 is protected from internal overheating by thermal shutdown. There are two kinds of flags concerning thermal protection, thermal warning and thermal critical. The warning flag is asserted when TJ > TWARN and the critical flag is asserted when TJ > TCRIT. When the critical flag is asserted, Buck1 and Buck2 are shut down immediately. Table 12: Thermal Protection Control Registers Category Register Name Description Status TEMP_WARN Asserted as long as the thermal warning threshold is reached TEMP_CRIT Asserted as long as the thermal shutdown threshold is reached IRQ event E_TEMP_WARN TEMP_WARN caused event E_TEMP_CRIT TEMP_CRIT caused event IRQ mask M_TEMP_WARN TEMP_WARN event IRQ mask M_TEMP_CRIT TEMP_CRIT event IRQ mask M_VR_HOT TEMP_WARN status IRQ mask Figure 10: Thermal Protection Operation Warning Flag TCRIT Junction Temperature TWARN Critical Flag IRQ IRQ Buck1 and Buck2 Shutdown Buck Enable I2C Bus Write to CH<x>_EN

4.2 Internal Circuits

4.2.1 IC_EN/Chip Enable/Disable

IC_EN is chip enable/disable control input. When IC_EN = 0, all blocks except for low I Q POR are powered-down and buck output is pulled-down. 4.2.2 nIRQ/Interrupt The interrupt triggers events. Trigger conditions and control registers for each interrupt event are listed in Table 13. Some of these events are categorized as fault events and affect device operation (for example, buck disable), see Section 4.1.7. Table 13: Interrupt List Name Polarity (Note 1) Trigger IRQ Status Register IRQ Mask Register Deglitch Period Thermal warning (event) N TJ rising above TWARN E_TEMP_WARN M_TEMP_WARN 0 s Thermal critical (event) N TJ rising above TCRIT E_TEMP_CRIT M_TEMP_CRIT 0 s System good (event) P Buck1 PG or Buck2 PG event E_SG M_SG 0 s Buck1 power-good (event) P Buck1 VOUT is in power- good voltage range (not under- or over-voltage) E_PG1 M_PG1 0 s Buck2 power-good (event) P Buck2 VOUT is in power- good voltage range (not under- or over-voltage) E_PG2 M_PG2 0 s Buck1 over-voltage (event) N Buck1 VOUT rising above over-voltage threshold (target voltage + 150 mV) E_OV1 M_OV1 Rise:8 µs Fall:8 µs Buck2 over-voltage (event) N Buck2 VOUT rising above over-voltage threshold (target voltage + 150 mV) E_OV2 M_OV2 Rise:8 µs Fall:8 µs Buck1 under- voltage (event) N Buck1 VOUT falling below under-voltage threshold (target voltage - VTH_PG) E_UV1 M_UV1 0 s Buck2 under- voltage (event) N Buck2 VOUT falling below under-voltage threshold (target voltage - VTH_PG) E_UV2 M_UV2 0 s Buck1 over-current (event) N Buck1 current rising above over-current threshold E_OC1 M_OC1 0 s

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 23 of 57 © 2022 Renesas Electronics Name Polarity (Note 1) Trigger IRQ Status Register IRQ Mask Register Deglitch Period Buck2 over-current (event) N Buck2 current rising above over-current threshold E_OC2 M_OC2 0 s Buck1 power-good (status) (Note 2) P Buck1 VOUT is in power- good voltage range (not under- or over-voltage) PG1 M_PG1_STAT (Note 3) 0 s Buck2 power-good (status) (Note 2) P Buck2 VOUT is in power- good voltage range (not under- or over-voltage) PG2 M_PG2_STAT (Note 3) 0 s System good (status) (Note 2) P Buck1 PG or Buck2 PG is active SG M_SG_STAT (Note 3) 0 s Thermal warning (status) (Note 2) N TJ rising above TWARN TEMP_WARN M_VR_HOT (Note 3) 0 s GPIO0 change (event) N Detect GPIO0 change for active trigger selected GPIO0_TRIG register E_GPIO0 M_GPIO0 100 µs/ 1 ms/ 10 ms/ 100 ms GPIO1 change (event) N Detect GPIO1 change for active trigger selected GPIO1_TRIG register E_GPIO1 M_GPIO1 GPIO2 change (event) N Detect GPIO2 change for active trigger selected GPIO2_TRIG register E_GPIO2 M_GPIO2 Note 1 Polarity at the source of the flag: P = active-high, N = active-low. General rule is: normal system state is high, and abnormal system state is low (for example, PG = high means power-good, TEMP_CRIT = low when TEMP critical state). Note 2 Interrupt outputs the status as is. I2C write is not required for interrupt clear. Note 3 OTP load value defined by CONF pin setting if CONF_EN = 1. Table 14: Interrupt Registers Except for Power-Good Status Register Description E_<name> Read-only interrupt event register 0: No interrupt 1: Interrupt occurred Cleared after being written to I2C. Set until IRQ is removed. M_<name> Interrupt mask register 0: Not masked 1: Masked. No IRQ signal sent. Event register (E_<name>) is updated.

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 24 of 57 © 2022 Renesas Electronics Table 15: Interrupt Registers for Power-Good, System Good, and Temp Warning Status Register Description PG<x> Buck<x> power-good status. Asserted as long as the buck<x> output voltage is in range (under-voltage threshold < buck output voltage < over-voltage threshold) 0: Not power-good 1: Power-good M_PG<x>_STAT Power-good status interrupt mask register 0: Not masked 1: Masked. No IRQ signal sent. Power-good status register (PG<x>) is updated SG System good status 0: Not system good 1: System good M_SG_STAT System good status (SG) interrupt mask register 0: Not masked 1: Masked. No IRQ signal sent. System good status register (SG) is updated TEMP_WARN Asserted as long as the thermal warning threshold (TWARN) is reached 0: Junction temperature is below TWARN 1: Junction temperature is above TWARN M_VR_HOT Temperature warning status (TEMP_WARN) interrupt mask register 0: Not masked 1: Masked. No IRQ signal sent. Temperature warning status register (TEMP_WARN) is updated Over-voltage Under-voltage PG# E_TEMP_WARN 0 VOUT IRQ Not Masked 1 0 TEMP_WARN TJ > TWARN TJ < TWARN I2C Write Clear Status Reg Event Reg Status Reg GPIO (nIRQ) Active-Low Setting (GPIO#_POL = 1) Active-High Setting (GPIO#_POL = 0) Target Voltage

GPIO is cofigured as nIRQ
M_TEMP_WARN = 0
M_PG#_STAT = 0 Condition Figure 11: Interrupt Operation Example

4.2.3 GPIO

4.2.3.1 GPIO Pin Assignment

The DA9131 provides up to five GPIO pins, three if the I2C is enabled, see Table 16. These registers are OTP programmable. When CONF_EN = 1 GPIO0 can be used for chip configuration. Any register settings for GPIO3 and GPIO4 are ignored and GPIO3 and GPIO4 function as SCL and SDA respectively if I2C_EN = 1. Table 16: GPIO Pin Assignment OTP Option GPIO Pin Available GPIOs I2C_EN CONF_EN CONF/ GPIO0 GPIO1 GPIO2 SCL/ GPIO3 SDA/ GPIO4 1’b0 1’b0 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 5 1’b1 CONF GPIO1 GPIO2 GPIO3 GPIO4 4 1’b1 1’b0 GPIO0 GPIO1 GPIO2 SCL SDA 3 1’b1 CONF GPIO1 GPIO2 SCL SDA 2

4.2.3.2 GPIO Function

The GPIOs pins are configurable as the following functions in register GPIO<x>_MODE (x = 0 to 4):

Buck1 enable input (EN1)
Buck2 enable input (EN2)
Buck1 and Buck2 enable input (EN1 & EN2)
Buck1 DVC control input (DVC1)
Buck2 DVC control input (DVC2)
Buck1 and Buck2 DVC control input (DVC1 & DVC2)
Buck1 and Buck2 OTP setting reload input (RELOAD)
Buck1 power-good output (PG1)
Buck2 power-good output (PG2)
Buck1 and Buck2 power-good output (PG1 & PG2)
System good output (SG)
Interrupt output (nIRQ) Table 17: GPIO Function Configuration GPIO<x>_MODE[3:0] Function IO Condition 4’h0 GPIO disable HiZ 4’h1 EN1 In 4’h2 EN2 In 4’h3 EN1 & EN2 In 4’h4 DVC1 In 4’h5 DVC2 In 4’h6 DVC1 & DVC2 In 4’h7 RELOAD In 4’h8 PG1 Out 4’h9 PG2 Out

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 27 of 57 © 2022 Renesas Electronics GPIO<x>_MODE[3:0] Function IO Condition 4’hA PG1 & PG2 Out 4’hB SG Out 4’hC nIRQ Out 4’hD Reserved HiZ 4’hE Low level Out 4’hF High level Out CH1_VOUT Over Voltage Under Voltage Target Voltage CH2_VOUT Over Voltage Under Voltage Target Voltage CH1_EN CH2_EN CH1_PG CH2_PG SG CH1_EN & CH1_PG (CH1_EN & CH1_PG) & (CH2_EN & CH2_PG) CH2_EN & CH2_PG Figure 15: Power-Good (PG) and System Good (SG)

4.2.3.3 Chip Configuration Select (CONF)

GPIO0 functions as chip configuration select (CONF) input when CONF_EN = 1. Three different chip configurations can be selected according to the CONF pin level, whether it is HIGH, LOW, or Hi-Z. Table 18 lists the device configurations can be modified if CONF_EN = 1. Table 18: GPIO0-Configurable Registers when CONF_EN = 1 Register Name Description IF_SLAVE_ADDR[6:0] I2C slave address CH1_A_MODE[1:0] CH1_A Operation mode select CH1_B_MODE[1:0] CH1_B Operation mode select CH1_VSEL CH1 output voltage and operation selection CH1_EN CH1 enable CH1_A_VOUT[7:0] CH1 output voltage setting A CH1_B_VOUT[7:0] CH1 output voltage setting B CH2_A_MODE[1:0] CH2_A Operation mode select CH2_B_MODE[1:0] CH2_B Operation mode select CH2_VSEL CH2 output voltage and operation selection CH2_EN CH2 enable CH2_A_VOUT[7:0] CH2 output voltage setting A CH2_B_VOUT[7:0] CH2 output voltage setting B M_PG1_STAT IRQ mask setting for CH1 power-good status M_PG2_STAT IRQ mask setting for CH2 power-good status M_SG_STAT IRQ mask setting for system good status M_VR_HOT IRQ mask setting for temp warning status CH1_EN_DLY[3:0] Delay setting for CH1 enable CH1_DIS_DLY[3:0] Delay setting for CH1 disable CH2_EN_DLY[3:0] Delay setting for CH2 enable CH2_DIS_DLY[3:0] Delay setting for CH2 disable GPIO1_MODE[3:0] GPIO1 mode setting GPIO2_MODE[3:0] GPIO2 mode setting GPIO1_OBUF GPIO1 output buffer select GPIO2_OBUF GPIO2 output buffer select GPIO1_TRIG[1:0] GPIO1 input trigger select GPIO1_POL GPIO1 polarity select GPIO1_PUPD GPIO1 pull-up/pull-down enable GPIO1_DEB[1:0] GPIO1 input debounce time setting GPIO1_DEB_RISE GPIO1 input debounce rising edge enable GPIO1_DEB_FALL GPIO1 input debounce falling edge enable GPIO2_TRIG[1:0] GPIO2 input trigger select GPIO2_POL GPIO2 polarity select GPIO2_PUPD GPIO2 pull-up/pull-down enable

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 29 of 57 © 2022 Renesas Electronics Register Name Description GPIO2_DEB[1:0] GPIO2 input debounce time setting GPIO2_DEB_RISE GPIO2 input debounce rising edge enable GPIO2_DEB_FALL GPIO2 input debounce falling edge enable

4.3 Operating Modes

4.3.1 ON DA9131 is ON when the IC_EN port is higher than VIH_EN and the supply voltage is higher than VTHR_POR. Once enabled, the host processor can start communicating with DA9131 using the control interface, after the tIC_EN delay.

4.3.2 OFF

DA9131 is OFF when the IC_EN port is lower than VIL_EN. In OFF, the bucks are always disabled and LX nodes are pulled down by (typically 150 Ω) internal pull-down resistors.

4.4 I2C Communication

All features of DA9131 can be controlled with the I2C interface which is enabled or disabled in register I2C_EN. I2C_EN Description

0 I2C disable: SCL/GPIO3 and SDA/GPIO4 pins can be used as GPIO

1 I2C enable: SCL/GPIO3 and SDA/GPIO4 pins are used as I2C clock input and I2C data

input/output. GPIO3 functions as the I2C clock and GPIO4 carries all the power manager bidirectional I2C data. The I2C interface is open-drain supporting multiple devices on a single line. The bus lines have to be pulled high by external pull-up resistors (2 kΩ to 20 kΩ). The standard frequency of the I2C bus is 1 MHz in fast-mode plus (FM+), 400 kHz in fast-mode, or 100 kHz in standard mode.

4.4.1 I2C Protocol

All data is transmitted across the I2C bus in eight-bit groups. To send a bit, the SDA line is driven towards the intended state while the SCL is low (a low SDA indicates a zero bit). Once the SDA has settled, the SCL line is brought high and then low. This pulse on SCL clocks the SDA bit into the receiver’s shift register. A two-byte serial protocol is used containing one byte for address and one byte data. Data and address transfer are transmitted MSB first for both read and write operations. All transmissions begin with the START condition from the master while the bus is in idle state (the bus is free). It is initiated by a high to low transition on the SDA line while the SCL is in the high state (a STOP condition is indicated by a low to high transition on the SDA line while the SCL is in the high state).

5 Register Definitions

5.1 Register Map

Table 19: Register Map Addr Register 7 6 5 4 3 2 1 0 System Module System 0x0001 SYS_STATUS_0 Reserve d Reserve d Reserve d Reserve d Reserve d SG TEMP_CRI T TEMP_WA RN 0x0002 SYS_STATUS_1 PG2 OV2 UV2 OC2 PG1 OV1 UV1 OC1 0x0003 SYS_STATUS_2 Reserve d Reserve d Reserve d Reserve d Reserve d GPIO2 GPIO1 GPIO0 0x0004 SYS_EVENT_0 Reserve d Reserve d Reserve d Reserve d Reserve d E_SG E_TEMP_C RIT E_TEMP_W ARN 0x0005 SYS_EVENT_1 E_PG2 E_OV2 E_UV2 E_OC2 E_PG1 E_OV1 E_UV1 E_OC1 0x0006 SYS_EVENT_2 Reserve d Reserve d Reserve d Reserve d Reserve d E_GPIO2 E_GPIO1 E_GPIO0 0x0007 SYS_MASK_0 Reserve d Reserve d Reserve d Reserve d Reserve d M_SG M_TEMP_C RIT M_TEMP_ WARN 0x0008 SYS_MASK_1 M_PG2 M_OV2 M_UV2 M_OC2 M_PG1 M_OV1 M_UV1 M_OC1 0x0009 SYS_MASK_2 Reserve d Reserve d Reserve d Reserve d Reserve d M_GPIO2 M_GPIO1 M_GPIO0 0x000A SYS_MASK_3 Reserve d Reserve d Reserve d Reserve d M_VR_H OT M_SG_ST AT M_PG2_ST AT M_PG1_ST AT 0x000B SYS_CONFIG_0 CH1_DIS_DLY<3:0> CH1_EN_DLY<3:0> 0x000C SYS_CONFIG_1 CH2_DIS_DLY<3:0> CH2_EN_DLY<3:0> 0x000D SYS_CONFIG_2 Reserve d OC_LATCHOFF<1:0 OC_DV C_MASK PG_DVC_MASK<1:0> Reserved Reserved 0x000E SYS_CONFIG_3 Reserve d OSC_TUNE<2:0> Reserve d Reserved I2C_TIMEO UT Reserved 0x0010 SYS_GPIO0_0 Reserve d Reserve d Reserve d GPIO0_MODE<3:0> GPIO0_OB UF 0x0011 SYS_GPIO0_1 GPIO0_ DEB_FA LL GPIO0_ DEB_RI SE GPIO0_DEB<1:0> GPIO0_ PUPD GPIO0_P OL GPIO0_TRIG<1:0> 0x0012 SYS_GPIO1_0 Reserve d Reserve d Reserve d GPIO1_MODE<3:0> GPIO1_OB UF 0x0013 SYS_GPIO1_1 GPIO1_ DEB_FA LL GPIO1_ DEB_RI SE GPIO1_DEB<1:0> GPIO1_ PUPD GPIO1_P OL GPIO1_TRIG<1:0> 0x0014 SYS_GPIO2_0 Reserve d Reserve d Reserve d GPIO2_MODE<3:0> GPIO2_OB UF 0x0015 SYS_GPIO2_1 GPIO2_ DEB_FA LL GPIO2_ DEB_RI SE GPIO2_DEB<1:0> GPIO2_ PUPD GPIO2_P OL GPIO2_TRIG<1:0> Buck Control Buck1 0x0020 BUCK_BUCK1_0 Reserve d 0x0021 BUCK_BUCK1_1 Reserve d S 0x0022 BUCK_BUCK1_2 Reserve d Reserve d Reserve d Reserve d CH1_ILIM<3:0> 0x0023 BUCK_BUCK1_3 CH1_VMAX<7:0>

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 32 of 57 © 2022 Renesas Electronics Addr Register 7 6 5 4 3 2 1 0 0x0024 BUCK_BUCK1_4 Reserve d Reserve d Reserve d CH1_VS EL 0x0025 BUCK_BUCK1_5 CH1_A_VOUT<7:0> 0x0026 BUCK_BUCK1_6 CH1_B_VOUT<7:0> 0x0027 BUCK_BUCK1_7 Reserved Reserved Reserved Reserved Reserved Reserved CH1_RIPPLE_CANCEL< 1:0> Buck2 0x0028 BUCK_BUCK2_0 Reserve d 0x0029 BUCK_BUCK2_1 Reserve d S 0x002A BUCK_BUCK2_2 Reserve d Reserve d Reserve d Reserve d CH2_ILIM<3:0> 0x002B BUCK_BUCK2_3 CH2_VMAX<7:0> 0x002C BUCK_BUCK2_4 Reserve d Reserve d Reserve d CH2_VS EL 0x002D BUCK_BUCK1_5 CH2_A_VOUT<7:0> 0x002E BUCK_BUCK1_6 CH2_B_VOUT<7:0> 0x002F BUCK_BUCK2_7 Reserved Reserved Reserved Reserved Reserved Reserved CH2_RIPPLE_CANCEL< 1:0> Serialization 0x0048 OTP_DEVICE_ID DEV_ID<7:0> 0x0049 OTP_VARIANT_I D MRC<3:0> VRC<3:0> 0x004A OTP_CUSTOME R_ID CUST_ID<7:0> 0x004B OTP_CONFIG_ID CONFIG_REV<7:0>

5.1.1 System

Table 20: SYS_STATUS_0 (0x0001) Bit Type Symbol Description [2] R SG Asserted as long as the output voltage of the enabled buck is in range [1] R TEMP_CRIT Asserted whilst the thermal shutdown threshold is exceeded [0] R TEMP_WARN Asserted whilst the thermal warning threshold is exceeded Table 21: SYS_STATUS_1 (0x0002) Bit Type Symbol Description [7] R PG2 Asserted whilst Buck2 output voltage is in range [6] R OV2 Asserted whilst Buck2 output is over-voltage [5] R UV2 Asserted whilst Buck2 output is under-voltage [4] R OC2 Asserted whilst Buck2 output is over-current [3] R PG1 Asserted whilst Buck1 output voltage is in range [2] R OV1 Asserted whilst Buck1 output is over-voltage [1] R UV1 Asserted whilst Buck1 output is under-voltage [0] R OC1 Asserted whilst Buck1 output is over-current Table 22: SYS_STATUS_2 (0x0003) Bit Type Symbol Description [2] R GPIO2 GPIO2 status [1] R GPIO1 GPIO1 status [0] R GPIO0 GPIO0 status Table 23: SYS_EVENT_0 (0x0004) Bit Type Symbol Description [2] R E_SG SG caused event. Write 1 to clear this bit after the event source has been released. [1] R E_TEMP_CRIT TEMP_CRIT event. Write 1 to clear this bit after the event source has been released. [0] R E_TEMP_WARN TEMP_WARN event. Write 1 to clear this bit after the event source has been released. Table 24: SYS_EVENT_1 (0x0005) Bit Type Symbol Description [7] RW E_PG2 PG2 caused event. Write 1 to clear this bit after the event source has been released. [6] RW E_OV2 OV2 caused event. Write 1 to clear this bit after the event source has been released. [5] RW E_UV2 UV2 caused event. Write 1 to clear this bit after the event source has been released. [4] RW E_OC2 OC2 caused event. Write 1 to clear this bit after the event source has been released.

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 34 of 57 © 2022 Renesas Electronics Bit Type Symbol Description [3] RW E_PG1 PG1 caused event. Write 1 to clear this bit after the event source has been released. [2] RW E_OV1 OV1 caused event. Write 1 to clear this bit after the event source has been released. [1] RW E_UV1 UV1 caused event. Write 1 to clear this bit after the event source has been released. [0] RW E_OC1 OC1 caused event. Write 1 to clear this bit after the event source has been released. Table 25: SYS_EVENT_2 (0x0006) Bit Type Symbol Description [2] RW E_GPIO2 GPIO2 event. Write 1 to clear this bit after the event source has been released. [1] RW E_GPIO1 GPIO1 event. Write 1 to clear this bit after the event source has been released. [0] RW E_GPIO0 GPIO0 event. Write 1 to clear this bit after the event source has been released. Table 26: SYS_MASK_0 (0x0007) Bit Type Symbol Description [2] RW M_SG SG IRQ mask [1] RW M_TEMP_CRIT TEMP_CRIT IRQ mask [0] RW M_TEMP_WARN TEMP_WARN IRQ mask Table 27: SYS_MASK_1 (0x0008) Bit Type Symbol Description [7] RW M_PG2 PG2 event IRQ mask [6] RW M_OV2 OV2 event IRQ mask [5] RW M_UV2 UV2 event IRQ mask [4] RW M_OC2 OC2 event IRQ mask [3] RW M_PG1 PG1 event IRQ mask [2] RW M_OV1 OV1 event IRQ mask [1] RW M_UV1 UV1 event IRQ mask [0] RW M_OC1 OC1 event IRQ mask Table 28: SYS_MASK_2 (0x0009) Bit Type Symbol Description [2] RW M_GPIO2 GPIO2 IRQ mask [1] RW M_GPIO1 GPIO1 IRQ mask [0] RW M_GPIO0 GPIO0 IRQ mask

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 35 of 57 © 2022 Renesas Electronics Table 29: SYS_MASK_3 (0x000A) Bit Type Symbol Description [3] RW M_VR_HOT Temp warning status IRQ mask. Initial value is determined by CONF pin setting at the start-up if CONF_EN = 1, see Section 4.2.3.3 [2] RW M_SG_STAT SG status IRQ mask. Initial value is determined by CONF pin setting at the start-up if CONF_EN = 1, see Section 4.2.3.3 [1] RW M_PG2_STAT PG2 status IRQ mask. Initial value is determined by CONF pin setting at the start-up if CONF_EN = 1, see Section 4.2.3.3 [0] RW M_PG1_STAT PG1 status IRQ mask. Initial value is determined by CONF pin setting at the start-up if CONF_EN = 1, see Section 4.2.3.3 Table 30: SYS_CONFIG_0 (0x000B) Bit Type Symbol Description [7:4] RW CH1_DIS_DLY Delay for CH1 disable. Active with GPIO configured as EN1&EN2 control and IC_EN control. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 0 0x1 1.0 ms 0x2 2.0 ms 0x3 3.0 ms 0x4 4.0 ms 0x5 5.0 ms 0x6 6.0 ms 0x7 7.0 ms 0x8 8.0 ms 0x9 9.0 ms 0xA 10.0 ms 0xB 11.0 ms 0xC 12.0 ms 0xD 13.0 ms 0xE 14.0 ms 0xF 15.0 ms [3:0] RW CH1_EN_DLY Delay for CH1 enable. Active with GPIO configured as EN1&EN2 control and IC_EN control. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 0 0x1 0.5 ms 0x2 1.0 ms 0x3 1.5 ms

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 36 of 57 © 2022 Renesas Electronics Bit Type Symbol Description 0x4 2.0 ms 0x5 2.5 ms 0x6 3.0 ms 0x7 3.5 ms 0x8 4.0 ms 0x9 4.5 ms 0xA 5.0 ms 0xB 5.5 ms 0xC 6.0 ms 0xD 6.5 ms 0xE 7.0 ms 0xF 7.5 ms Table 31: SYS_CONFIG_1 (0x000C) Bit Type Symbol Description [7:4] RW CH2_DIS_DLY Delay for CH2 disable. Active with GPIO configured as EN1&EN2 control and IC_EN control. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 0 0x1 1.0 ms 0x2 2.0 ms 0x3 3.0 ms 0x4 4.0 ms 0x5 5.0 ms 0x6 6.0 ms 0x7 7.0 ms 0x8 8.0 ms 0x9 9.0 ms 0xA 10.0 ms 0xB 11.0 ms 0xC 12.0 ms 0xD 13.0 ms 0xE 14.0 ms 0xF 15.0 ms [3:0] RW CH2_EN_DLY Delay for CH2 enable. Active with GPIO configured as EN1&EN2 control and IC_EN control. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 37 of 57 © 2022 Renesas Electronics Bit Type Symbol Description 0x0 0 0x1 0.5 ms 0x2 1.0 ms 0x3 1.5 ms 0x4 2.0 ms 0x5 2.5 ms 0x6 3.0 ms 0x7 3.5 ms 0x8 4.0 ms 0x9 4.5 ms 0xA 5.0 ms 0xB 5.5 ms 0xC 6.0 ms 0xD 6.5 ms 0xE 7.0 ms 0xF 7.5 ms Table 32: SYS_CONFIG_2 (0x000D) Bit Type Symbol Description [6:5] RW OC_LATCHOFF Over-current latch-off setting. BUCK shut-down after OCP for 8 µs/1 ms/3 ms unless disable setting. IRQ is generated unless IRQ is masked. Value Description 0x0 Latch off disable 0x1 Latch off after 8 µs of OCP signal 0x2 Latch off after 1 ms of OCP signal 0x3 Latch off after 3 ms of OCP signal [4] RW OC_DVC_MASK Over-current event (IRQ and latch-off feature) mask during DVC ramp-up and ramp-down for both CH1 and CH2 [3:2] RW PG_DVC_MASK Power-good mask during DVC for both CH1 and CH2 Value Description 0x0 No mask 0x1 Mask as not power-good during DVC 0x2 Mask as power-good during DVC 0x3 Reserved

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 38 of 57 © 2022 Renesas Electronics Table 33: SYS_CONFIG_3 (0x000E) Bit Type Symbol Description [6:4] RW OSC_TUNE Tune oscillator frequency, tuned frequency = Current + OSC_TUNE * 160 kHz Value Description 0x3 3 0x2 2 0x1 1 0x0 0 0x7 -1 0x6 -2 0x5 -3 0x4 -4 [1] RW I2C_TIMEOUT Enable automatic reset of 2-wire interface (if SDA stays low for >50 ms). Table 34: SYS_GPIO0_0 (0x0010) Bit Type Symbol Description [4:1] RW GPIO0_MODE GPIO function mode select Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 EN2 input 0x3 EN1 & EN2 input 0x4 DVC1 input 0x5 DVC2 input 0x6 DVC1 & DVC2 input 0x7 RELOAD input 0x8 PG1 output 0x9 PG2 output 0xA PG1 & PG2 output 0xB SG output 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] RW GPIO0_OBUF GPIO output buffer select Value Description 0x0 open-drain output

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 39 of 57 © 2022 Renesas Electronics Bit Type Symbol Description 0x1 push-pull output Table 35: SYS_GPIO0_1 (0x0011) Bit Type Symbol Description [7] RW GPIO0_DEB_FALL GPI debouce falling edge [6] RW GPIO0_DEB_RISE GPI debounce rising edge [5:4] RW GPIO0_DEB GPI debounce time Value Description 0x0 100 µs debouce 0x1 1 ms debouce 0x2 10 ms debounce 0x3 100 ms debounce [3] RW GPIO0_PUPD GPIO pull-up/pull-down enable Value Description 0x0 GPI: pull-down disabled, GPO: pull-up to AVDD disabled 0x1 GPI: pull-down enabled, GPO: pull-up to AVDD enabled [2] RW GPIO0_POL GPIO polarity Value Description 0x0 GPIO is active-high 0x1 GPIO is active-low [1:0] RW GPIO0_TRIG GPI trigger type Value Description 0x0 Dual-edge triggered 0x1 Pos-edge triggered 0x2 Neg-edge triggered 0x3 Reserved (No trigger) Table 36: SYS_GPIO1_0 (0x0012) Bit Type Symbol Description [4:1] RW GPIO1_MODE GPIO function mode select. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 EN2 input 0x3 EN1 & EN2 input 0x4 DVC1 input

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 40 of 57 © 2022 Renesas Electronics Bit Type Symbol Description 0x5 DVC2 input 0x6 DVC1 & DVC2 input 0x7 RELOAD input 0x8 PG1 output 0x9 PG2 output 0xA PG1 & PG2 output 0xB SG output 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] RW GPIO1_OBUF GPIO output buffer select. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 open-drain output 0x1 push-pull output Table 37: SYS_GPIO1_1 (0x0013) Bit Type Symbol Description [7] RW GPIO1_DEB_FALL GPI debouce falling edge. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 [6] RW GPIO1_DEB_RISE GPI debounce rising edge. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 [5:4] RW GPIO1_DEB GPI debounce time. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 100 µs debouce 0x1 1 ms debouce 0x2 10 ms debounce 0x3 100 ms debounce [3] RW GPIO1_PUPD GPIO pull-up/pull-down enable. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 GPI: pull-down disabled, GPO: pull-up to AVDD disabled 0x1 GPI: pull-down enabled, GPO: pull-up to AVDD enabled [2] RW GPIO1_POL GPIO polarity. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 GPIO is active-high

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 41 of 57 © 2022 Renesas Electronics Bit Type Symbol Description 0x1 GPIO is active-low [1:0] RW GPIO1_TRIG GPI trigger type. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 Dual-edge triggered 0x1 Pos-edge triggered 0x2 Neg-edge triggered 0x3 Reserved (No trigger) Table 38: SYS_GPIO2_0 (0x0014) Bit Type Symbol Description [4:1] RW GPIO2_MODE GPIO function mode select. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 EN2 input 0x3 EN1 & EN2 input 0x4 DVC1 input 0x5 DVC2 input 0x6 DVC1 & DVC2 input 0x7 RELOAD input 0x8 PG1 output 0x9 PG2 output 0xA PG1 & PG2 output 0xB SG output 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] RW GPIO2_OBUF GPIO output buffer select. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 open-drain output 0x1 push-pull output

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 42 of 57 © 2022 Renesas Electronics Table 39: SYS_GPIO2_1 (0x0015) Bit Type Symbol Description [7] RW GPIO2_DEB_FALL GPI debouce falling edge. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 [6] RW GPIO2_DEB_RISE GPI debounce rising edge. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 [5:4] RW GPIO2_DEB GPI debounce time. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 100 µs debouce 0x1 1 ms debouce 0x2 10 ms debounce 0x3 100 ms debounce [3] RW GPIO2_PUPD GPIO pull-up/pull-down enable. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 GPI: pull-down disabled, GPO: pull-up to AVDD disabled 0x1 GPI: pull-down enabled, GPO: pull-up to AVDD enabled [2] RW GPIO2_POL GPIO polarity. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 GPIO is active-high 0x1 GPIO is active-low [1:0] RW GPIO2_TRIG GPI trigger type. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 Dual-edge triggered 0x1 Pos-edge triggered 0x2 Neg-edge triggered 0x3 Reserved (No trigger)

5.1.2 Buck1

Table 40: BUCK_BUCK1_0 (0x0020) Bit Type Symbol Description [6:4] RW CH1_SR_DVC_DWN Voltage slew-rate for DVC ramp-down Value Description 0x0 10 mV/8 µs 0x1 10 mV/4 µs 0x2 10 mV/2 µs 0x3 10 mV/µs 0x4 20 mV/µs 0x5 Reserved 0x6 Reserved 0x7 Reserved [3:1] RW CH1_SR_DVC_UP Voltage slew-rate for DVC ramp-up Value Description 0x0 10 mV/8 µs 0x1 10 mV/4 µs 0x2 10 mV/2 µs 0x3 10 mV/µs 0x4 20 mV/µs 0x5 40 mV/µs 0x6 Reserved 0x7 Reserved [0] RW CH1_EN Channel enable. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Table 41: BUCK_BUCK1_1 (0x0021) Bit Type Symbol Description [6:4] RW CH1_SR_SHDN Voltage slew-rate during shut-down Value Description 0x0 10 mV/8 µs 0x1 10 mV/4 µs 0x2 10 mV/2 µs 0x3 10 mV/µs 0x4 20 mV/µs 0x5 Reserved 0x6 Reserved 0x7 Immediate power-down

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 44 of 57 © 2022 Renesas Electronics Bit Type Symbol Description [3:1] RW CH1_SR_STARTUP Voltage slew-rate during startup Value Description 0x0 10 mV/8 µs 0x1 10 mV/4 µs 0x2 10 mV/2 µs 0x3 10 mV/µs 0x4 20 mV/µs 0x5 40 mV/µs 0x6 Reserved 0x7 Reserved [0] RW CH1_PD_DIS Pull-down while buck is disabled. 0: enable, 1: disable Table 42: BUCK_BUCK1_2 (0x0022) Bit Type Symbol Description [3:0] RW CH1_ILIM Select OCP threshold (A). The value is configured by OTP and should not be modified while the buck is active. Value Description 0x0 Reserved 0x1 3.5 0x2 4.0 0x3 4.5 0x4 5.0 0x5 5.5 0x6 6.0 0x7 6.5 0x8 7.0 0x9 7.5 0xA 8.0 0xB 8.5 0xC 9.0 0xD 9.5 0xE 10.0 0xF Disable

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 45 of 57 © 2022 Renesas Electronics Table 43: BUCK_BUCK1_3 (0x0023) Bit Type Symbol Description [7:0] RW CH1_VMAX VOUT max setting (V): From 0.30 V (0x1E) to 1.90 V (0xBE) in 10 mV steps. This is a read-only register. Value Description 0x1E 0.3 0x1F 0.31 0x20 0.32 Continuing through… 0x99 1.53 To… 0xBD 1.89 0xBE 1.9 Table 44: BUCK_BUCK1_4 (0x0024) Bit Type Symbol Description [4] RW CH1_VSEL Output voltage and operation selection: 0: A, 1: B. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 [3:2] RW CH1_B_MODE Operation mode selection. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 Force PFM operation 0x1 Force PWM operation 0x2 Force PWM operation 0x3 Auto mode [1:0] RW CH1_A_MODE Operation mode selection. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 Force PFM operation 0x1 Force PWM operation 0x2 Force PWM operation 0x3 Auto mode

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 46 of 57 © 2022 Renesas Electronics Table 45: BUCK_BUCK1_5 (0x0025) Bit Type Symbol Description [7:0] RW CH1_A_VOUT Output voltage setting A: Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 From 0.30 V (0x1E) to 1.90 V (0xBE) in steps of 10 mV (default 1.0 V) Write-protected when value is written below 0.30 V or above 1.90 V Value Description 0x1E 0.3 0x1F 0.31 0x20 0.32 Continuing through… 0x64 1 To… 0xBC 1.88 0xBD 1.89 0xBE 1.9 Table 46: BUCK_BUCK1_6 (0x0026) Bit Type Symbol Description [7:0] RW CH1_B_VOUT Output voltage setting B: Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 From 0.30 V (0x1E) to 1.90 V (0xBE) in steps of 10 mV (default 1.0 V) Write-protected when value is written below 0.30 V or above 1.90 V Value Description 0x1E 0.3 0x1F 0.31 0x20 0.32 Continuing through… 0x64 1 To… 0xBC 1.88 0xBD 1.89 0xBE 1.9

5.1.3 Buck2

Table 47: BUCK_BUCK2_0 (0x0028) Bit Type Symbol Description [6:4] RW CH2_SR_DVC_DWN Voltage slew-rate for DVC ramp-down Value Description 0x0 10 mV/8 µs 0x1 10 mV/4 µs 0x2 10 mV/2 µs 0x3 10 mV/µs 0x4 20 mV/µs 0x5 Reserved 0x6 Reserved 0x7 Reserved [3:1] RW CH2_SR_DVC_UP Voltage slew-rate for DVC ramp-up Value Description 0x0 10 mV/8 µs 0x1 10 mV/4 µs 0x2 10 mV/2 µs 0x3 10 mV/µs 0x4 20 mV/µs 0x5 40 mV/µs 0x6 Reserved 0x7 Reserved [0] RW CH2_EN Channel enable. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Table 48: BUCK_BUCK2_1 (0x0029) Bit Type Symbol Description [6:4] RW CH2_SR_SHDN Voltage slew-rate during power-down Value Description 0x0 10 mV/8 µs 0x1 10 mV/4 µs 0x2 10 mV/2 µs 0x3 10 mV/µs 0x4 20 mV/µs 0x5 Reserved 0x6 Reserved 0x7 Immediate power-down [3:1] RW CH2_SR_STARTUP Voltage slew-rate during startup

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 48 of 57 © 2022 Renesas Electronics Bit Type Symbol Description Value Description 0x0 10 mV/8 µs 0x1 10 mV/4 µs 0x2 10 mV/2 µs 0x3 10 mV/µs 0x4 20 mV/µs 0x5 40 mV/µs 0x6 Reserved 0x7 Reserved [0] RW CH2_PD_DIS Pull-down while BUCK is disabled. 0: enable, 1: disable Table 49: BUCK_BUCK2_2 (0x002A) Bit Type Symbol Description [3:0] RW CH2_ILIM Select OCP threshold Value Description 0x0 Reserved 0x1 3.5 0x2 4.0 0x3 4.5 0x4 5.0 0x5 5.5 0x6 6.0 0x7 6.5 0x8 7.0 0x9 7.5 0xA 8.0 0xB 8.5 0xC 9.0 0xD 9.5 0xE 10.0 0xF Disable

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 49 of 57 © 2022 Renesas Electronics Table 50: BUCK_BUCK2_3 (0x002B) Bit Type Symbol Description [7:0] RW CH2_VMAX VOUT max setting (V): From 0.30 V (0x1E) to 1.90 V (0xBE) in steps of 10 mV This is a read-only register. Value Description 0x1E 0.3 0x1F 0.31 0x20 0.32 Continuing through… 0x64 1 To… 0xBC 1.88 0xBD 1.89 0xBE 1.9 Table 51: BUCK_BUCK2_4 (0x002C) Bit Type Symbol Description [4] RW CH2_VSEL Output voltage and operation selection: 0: A, 1: B. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 [3:2] RW CH2_B_MODE Operation mode selection. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 Force PFM operation 0x1 Force PWM operation 0x2 Force PWM operation 0x3 Auto mode [1:0] RW CH2_A_MODE Operation mode selection. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 Force PFM operation 0x1 Force PWM operation 0x2 Force PWM operation 0x3 Auto mode

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 50 of 57 © 2022 Renesas Electronics Table 52: BUCK_BUCK2_5 (0x002D) Bit Type Symbol Description [7:0] RW CH2_A_VOUT Output voltage setting A: Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 From 0.30 V (0x1E) to 1.90 V (0xBE) in steps of 10 mV (default 1.0 V) Write-protected when value is written below 0.30 V or above 1.90 V Value Description 0x1E 0.3 0x1F 0.31 0x20 0.32 Continuing through… 0x64 1 To… 0xBC 1.88 0xBD 1.89 0xBE 1.9 Table 53: BUCK_BUCK2_6 (0x002E) Bit Type Symbol Description [7:0] RW CH2_B_VOUT Output voltage setting B: Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 From 0.30 V (0x1E) to 1.90 V (0xBE) in steps of 10 mV (default 1.0 V) Write-protected when value is written below 0.30 V or above 1.90 V Value Description 0x1E 0.3 0x1F 0.31 0x20 0.32 Continuing through… 0x64 1 To… 0xBC 1.88 0xBD 1.89 0xBE 1.9

5.1.4 Serialization

Table 54: OTP_DEVICE_ID (0x0048) Bit Type Symbol Description [7:0] R DEV_ID Device ID Table 55: OTP_VARIANT_ID (0x0049) Bit Type Symbol Description [7:4] R MRC Mask Revision Code [3:0] R VRC Chip Variant Code Table 56: OTP_CUSTOMER_ID (0x004A) Bit Type Symbol Description [7:0] R CUST_ID Customer ID Table 57: OTP_CONFIG_ID (0x004B) Bit Type Symbol Description [7:0] R CONFIG_REV OTP Variant

6 Package Information

6.1 Package Outlines

Figure 19: Package Outline Drawing

6.2 Package Marking

6.3 Moisture Sensitivity Level

The moisture sensitivity level (MSL) is an indicator for the maximum allowable time period (floor lifetime) in which a moisture sensitive plastic device, once removed from the dry bag, can be exposed to an environment with a specified maximum temperature and a maximum relative humidity before the solder reflow process. The MSL classification is defined in Table 58. For detailed information on MSL levels refer to the IPC/JEDEC standard J -STD-020, which can be downloaded from http://www.jedec.org. The FCQFN package is qualified for MSL 3. Table 58: MSL Classification MSL Level Floor Lifetime Conditions MSL 4 72 hours 30 °C / 60 % RH MSL 3 168 hours 30 °C / 60 % RH MSL 2A 4 weeks 30 °C / 60 % RH MSL 2 1 year 30 °C / 60 % RH MSL 1 Unlimited 30 °C / 60 % RH

6.4 Soldering Information

Refer to the IPC/JEDEC standard J-STD-020 for relevant soldering information. This document can be downloaded from http://www.jedec.org. A1 Corner > Format 1st ● Pin 1 ID 2nd D A 9 1 3 1 Orientation/Part No. 3rd x x A T y y OTP/Option/Year 4th w w z z z z Date Code A or AT optionally indicate the Automotive and Automotive high temp test options. Package Marking Marking Content Date Code Format: yy = Year, ww = Week, zzzz = Traceability xx identifies the OTP Variant

7 Ordering Information

The ordering number consists of the part number followed by a suffix indicating the packing method. For details and availability, please consult your Dialog Semiconductor local sales representative. Table 59: Ordering Information Part Number Package Package Description MOQ DA9131-xxRT2 24 FCQFN wettable flanks, 3.3 x 4.8 T&R, 4800 pcs 3 Reels - 14400 DA9131-xxRT1 24 FCQFN wettable flanks Tray, 490 pcs 30 Trays - 14700 pcs

8 Application Information

The following recommended components are examples selected from requirements of a typical application.

8.1 Capacitor Selection

Ceramic capacitors are used as bypass capacitors at all VDD and output rails. When selecting a capacitor, especially for types with high capacitance at smallest physical dimension, the DC bias characteristic has to be taken into account. Table 60: Recommended Consumer Grade Capacitor Types Application Value (µF) Size Temp. Char. Tol. (%) V-Rate (V) Type VOUT output bypass 10 0402 X5R 20 6.3 Murata GRM155R60J106ME15 PVDDx bypass 10 0603 X5R 20 25 Murata GRM188R61E106MA73 AVDD bypass 1 0402 X5R 10 10 Murata GRM155R61A105KE15 Table 61: Recommended Automotive Grade Capacitor Types Application Value (µF) Size Temp. Char. Tol. (%) V-Rate (V) Type VOUT output bypass 10 0805 X7R ±15% ±10 6.3 TDK CGA4J1X7R0J106K125AC PVDDx bypass 10 3216 X7R ±15% ±10 16 Murata GCM31CR71C106KA64L AVDD bypass 1 0805 X7R ±15% ±10 50 Murata GCM21BR71H105KA03L

8.2 Inductor Selection

Inductors should be selected based on the following parameters:

Rated maximum current Usually a coil provides two current limits: ISAT specifies the maximum current at which the inductance drops by 30 % of the nominal value, and IMAX is defined by the maximum power dissipation and is applied to the effective current.
DC resistance Critical for the converter efficiency and should therefore be minimized. Table 62: Recommended Inductor Types Value (µH) Size (mm) IMAX (DC) (A) ISAT (A) Tol. (%) DC Resistance (mΩ) Type

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 56 of 57 © 2022 Renesas Electronics Status Definitions Revision Datasheet Status Product Status Definition 1.<n> Target Development This datasheet contains the design specifications for product development. Specifications may be changed in any manner without notice. 2.<n> Preliminary Qualification This datasheet contains the specifications and preliminary characterization data for products in pre-production. Specifications may be changed at any time without notice in order to improve the design. 3.<n> Final Production This datasheet contains the final specifications for products in volume production. The specifications may be changed at any time in order to improve the design, manufacturing and supply. Major specification changes are communicated via Customer Product Notifications. Datasheet changes are communicated via www.dialog-semiconductor.com. 4.<n> Obsolete Archived This datasheet contains the specifications for discontinued products. The information is provided for reference only. RoHS Compliance Dialog Semiconductor’s suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from our suppliers are available on request.

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications Datasheet Revision 2.1 25-May-2022 CFR0011-120-00 57 of 57 © 2022 Renesas Electronics Important Notice and Disclaimer RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHO UT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your app lication meets applicable standards, and any other safety, security, or other require ments. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reprodu ction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damag es, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditio ns of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicab le warranties or warranty disclaimers for these products. © 2022 Renesas Electronics Corporation. All rights reserved. Corporate Headquarters TOYOSU FORESIA, 3-2-24 Toyosu Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: https://www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. (Rev.1.0 Mar 2020)

TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) © 2021 Renesas Electronics Corporation. All rights reserved.

Product Information

DA9131 specifications and overview.

Summary

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications July 18, 2025

Description

High-Performance, Dual-Channel DC-DC Converter for Mobile and Portable Applications July 18, 2025

Source title DA9131_V01 Datasheet(PDF) - Renesas Technology Corp

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DA9131 RENESAS | Alldatasheet

Document overview

Technical content

Applications

Contents

1 Terms and Definitions

2 Pinout

Description

3 SCL/GPIO3 DIO 15 SCL

4 FB1N AI 10 Negative feedback for Ch 1

5 FB1P AI 10 Positive feedback for Ch 1

6 SDA/GPIO4 DIO 15 SDA

8 AVDD PS 10 Analog supply

9 AGND PS 10 Analog ground

10 GPIO0 DIO 10 GPIO

11 CONF/GPIO1 DIO 10 GPIO

12 FB2P AI 10 Positive feedback for Ch 2

13 FB2N AI 10 Negative feedback for Ch 2

14 GPIO2 DIO 10 GPIO

3 Characteristics

3.1 Absolute Maximum Ratings

3.2 Recommended Operating Conditions

3.3 Thermal Characteristics

3.3.1 Thermal Ratings

3.3.2 Power Dissipation

3.3.3 ESD Characteristics

3.4 Buck Characteristics

2.8 V < VOUT + 1 V < VIN ≤

3.5 Performance and Supervision Characteristics

3.6 Digital I/O Characteristics

3.7 Timing Characteristics

3.8 Typical Performance

4 Functional Description

4.1 DC-DC Buck Converter

4.1.1 Switching Frequency

4.1.2 Operation Modes and Phase Selection

4.1.3 Output Voltage Selection

4.1.4 Soft Start-Up and Shutdown

4.1.5 Current Limit

4.1.6 Resistive Divider

4.1.7 Thermal Protection

4.2 Internal Circuits

4.2.1 IC_EN/Chip Enable/Disable

4.2.3 GPIO

4.2.3.1 GPIO Pin Assignment

4.2.3.2 GPIO Function

4.2.3.3 Chip Configuration Select (CONF)

4.3 Operating Modes

4.3.2 OFF

4.4 I2C Communication

0 I2C disable: SCL/GPIO3 and SDA/GPIO4 pins can be used as GPIO

1 I2C enable: SCL/GPIO3 and SDA/GPIO4 pins are used as I2C clock input and I2C data

4.4.1 I2C Protocol

5 Register Definitions

5.1 Register Map

5.1.1 System

5.1.2 Buck1

5.1.3 Buck2

5.1.4 Serialization

6 Package Information

6.1 Package Outlines

6.2 Package Marking

6.3 Moisture Sensitivity Level

6.4 Soldering Information

7 Ordering Information

8 Application Information

8.1 Capacitor Selection

8.2 Inductor Selection

DA9131 specifications and overview.

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