DA9130_V01 RENESAS | Alldatasheet
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High-Performance, 10 A, Dual -Phase DC-DC Converter for Mobile and Portable Applications R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 1 © 2025 Renesas Electronics DA9130 is a power management IC (PMIC) suitable for supplying CPUs, GPUs, DDR memory rails in single in-line pin package (SIPP) modules, mobile, portable and consumer applications. DA9130 operates as a single -channel dual-phase buck converter, each phase requiring a small external 0.22 µH inductor. It is capable of delivering up to 10 A output current at a 0.3 V to 1.9 V output voltage range. The 2.8 V to 5.5 V input voltage range is suitable for a wide variety of low -voltage systems. With remote sensing, the DA9130 guarantees the highest accuracy and supports multiple PCB routing scenarios without loss of performance. The pass devices are fully integrated, so no external FETs or Schottky diodes are needed. A programmable soft start -up can be enabled, which limits the inrush current from the input node and secures a slope -controlled rail activation. The dynamic voltage control (DVC) supports adaptive adjustment of the supply voltage dependent on the processor load, via either a direct register write using the communication interface (I2C-compatible) or with a programmable input pin. A configurable GPI allows multiple I 2C address selection for multiple instances of DA9130 in the same application. DA9130 has integrated over-temperature and over- current protection for increased system reliability, without the need for external sensing components. Key Features ▪ 2.8 V to 5.5 V input voltage ▪ 0.3 V to 1.9 V output voltage ▪ Up to 10 A output current ▪ 4 MHz nominal switching frequency ▪ Dual-phase operation ▪ 220 nH inductor per phase ▪ 20 µF output capacitor ▪ ±1 % output voltage accuracy (static) ▪ ±5 % load transient (dynamic) ▪ Programmable GPIO s ▪ Programmable soft startup ▪ I2C-compatible interface (FM+) ▪ Voltage, current, and temperature supervision ▪ 24-pin FCQFN package, wettable flanks (nom. 3.3 mm x 4.8 mm) ▪ 218 mm² total solution area ▪ -40 °C to +105 ºC ambient temperature range ▪ AEC-Q100 Grade 2 qualified version also available for Automotive applications (DA9130-A)
Applications
▪ Switches and routers ▪ Smart metering ▪ Industrial automation ▪ Wireless ▪ Consumer products ▪ SoC/FPGA high performance processing system requiring efficient, high current, power delivery ▪ SIPP modules (SoC, DRAM)
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 2 Benefits ▪ High Efficiency buck converters deliver outstanding thermal performance ▪ Fully integrated switching FET’s means no external FETs or Schottky diodes are required ▪ Remote sensing guarantees the highest accuracy and supports multiple PCB routing scenarios without loss of performance. ▪ Fully programmable soft-start limits the inrush current from the input to give a slope-controlled output voltage. ▪ Dynamic voltage control (DVC) enables adaptive adjustment of the device output voltage depending on the load. This increases efficiency when the downstream circuitry enters low power or idle mode, resulting in power savings. ▪ Configurable GPIOs support a range of features including I 2C, DVC and Power -Good indicator. ▪ Optimized BoM cost and footprint: Each output requires a very small inductor and capacitor delivering parts and cost savings ▪ Cycle by cycle current limiting for superior over -current protection
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Contents
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R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 7 1. Terms and Definitions ATE Automated test equipment CPU Central processing unit DDR Dual data rate DVC Dynamic voltage control FET Field effect transistor FM+ Fast mode plus GBD Guaranteed by design GBQ Guaranteed by qualification GBSPC Guaranteed by statistical process characterization GPI General purpose input GPIO General purpose input/output GPU Graphics processing unit IC Integrated circuit HW Hardware OTP One time programmable PCB Printed circuit board PRS Product requirements specification SCL Serial clock SDA Serial data SIPP Single in-line pin package SW Software
2.1 Pin Assignments
Figure 4. DA9130 Pinout Diagram (Bottom View)
2.2 Pin Descriptions
3 SCL/GPIO3 DIO 15 SCL
4 FB1N AI 10 Negative feedback for Ch 1
5 FB1P AI 10 Positive feedback for Ch 1
6 SDA/GPIO4 DIO 15 SDA
8 AVDD PS 10 Analog supply
9 AGND PS 10 Analog ground
10 CONF/GPIO0 DIO 10 GPIO
11 GPIO1 DIO 10 GPIO
12 FB2P AI 10 Positive feedback for Ch 2
13 FB2N AI 10 Negative feedback for Ch 2
14 GPIO2 DIO 10 GPIO
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 9 Table 2: Pin Type Definition Pin type Description Pin type Description DI Digital input AI Analog input DO Digital output AO Analog output PS Power supply
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 10 3. Specifications
3.1 Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. Table 3: Absolute Maximum Ratings Parameter Description Conditions Min Max Unit TSTG Storage temperature -65 150 °C TJ Junction temperature -40 150 °C VSYS System supply voltage -0.3 6.0 V VPIN Voltage on pins -0.3 6.0 V
3.2 Electrostatic Discharge Ratings
Table 4: Electrostatic Discharge Ratings Parameter Description Conditions Rating Unit VESD_HBM ESD protection, human body model (HBM) 2 kV VESD_CDM Maximum ESD protection Charged device model (CDM) 500 V
3.3 Recommended Operating Conditions
Table 5: Recommended Operating Conditions Parameter Description Conditions (Note 1) Min Typ Max Unit VSYS System supply voltage 2.8 5.5 V VPIN Voltage on pins -0.3 VSYS + 0.3 V TJ Junction temperature -40 125 °C TA Ambient temperature -40 105 °C Note 1 Within the specified limits, a lifetime of 10 years is guaranteed. If operating outside of these recommended conditions, please consult with Renesas . Note 2 VSYS, VIN, PVDD and AVDD should be connected together. The pin names are different for routing purposes.
3.4 Thermal Specifications
3.4.1 Power Dissipation
Figure 5. Power Derating Curve
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3.5 Buck Characteristics
Unless otherwise noted, the following is valid for T J = -40 °C to +125 °C, V SYS = 2.8 V to 5.5 V. Table 8: Dual-Phase Buck Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External electrical conditions VIN Input voltage VIN = VSYS 2.8 5.5 V COUT Output capacitance, per phase, including voltage and temperature coefficient -40 % 20 +30 % μF ESRCOUT Output capacitor series resistance, per phase f > 100 kHz 1 mΩ L Inductor value, per phase, including current and temperature dependence -50 % 220 +20 % nH DCRL Inductor DC resistance 8 13 mΩ Electrical performance VOUT Output voltage, configurable in 10 mV steps IOUT = 0 mA to IMAX at 25 °C ambient
2.8 V < VOUT + 1 V < VIN ≤
5.5 V 0.3 1.9 V ILIM Current limit, configurable per phase Note 1 Note 2 CHx_ILIM = 1010 -20 % 8 +20 % A IMAX Output current Note 3 VIN ≥ VOUT + 1 V
5 A per phase
VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT ≥ 1 V -1 1 % VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT < 1 V -10 10 mV VTHR_PG_HYS Power-good voltage threshold hysteresis VOUT = VTHR_PG_DWN 60 80 100 mV VTHR_PG_DWN Power-good voltage threshold for falling VOUT = VBUCK -160 -130 -80 mV VTHR_HV High V OUT voltage threshold VOUT = VBUCK 100 150 200 mV VOUT_TR_LINE Line transient response VIN = 3 V to 3.6 V IOUT = 0.5 * IMAX dt = 10 μs 15 mV fSW Switching frequency 4 MHz
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 13 Parameter Description Conditions Min Typ Max Unit tON_MIN Minimum turn -on pulse 0 % duty is also supported 5 7 11 ns tBUCK_EN Turn-on time CHx_EN = high 20 μs RPD Output pull -down resistance for each phase at the LX node, see BUCK<x>_PD_DIS VIN = 3.7 V VOUT = 0.5 V 145 150 161 Ω RON_PMOS On resistance of switching PMOS, per phase VIN = 3.7 V 17 25 37 mΩ RON_NMOS On resistance of switching NMOS, per phase VIN = 3.7 V 6 10 16 mΩ PWM Mode ITHR_1PH_TO_2PH Current threshold for automatic phase shedding 1 -phase to 2 - phase 2.25 A ITHR_2PH_TO_1PH Current threshold for automatic phase shedding 2 -phase to 1 - phase 1.7 A IQ_PWM_2PH Quiescent current, per phase VIN = 3.7 V No load 16 mA ηPWM Efficiency, phase shedding VIN = 3.6 V VOUT = 1 V IOUT = 5 % (IMAX) to 80 % (IMAX) 85 % AUTO Mode VOUT_TR_LD_2PH Load transient response, phase shedding enabled VOUT = 1 V IOUT = 2.5 to 7.5 A at 25 °C ambient dl/dt = 5 A/μs -25 45 mV PFM Mode IQ_PFM_2PH Quiescent current in PFM VIN = 3.7 V No load No switching 164 μA ηPFM Efficiency VIN = 3.6 V VOUT = 1 V IOUT = 10 mA 83 % Note 1 tON > 40 ns Note 2 The value is configured by OTP and should not be modified while the buck is active. Note 3 For short durations to meet peak current requirements, I OUT can be operated at up to 10 % higher than the specified maximum operating condition. The part should not be operated in this mode for extended periods and is not guaranteed for continuous operation.
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3.6 Performance and Supervision Characteristics
Table 9: Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance VTHR_POR Power-on -reset threshold Threshold for AVDD falling 2.1 2.25 V VTHR_POR_HYS Power-on -reset hysteresis 200 mV TWARN Thermal warning temperature threshold 115 125 135 °C TCRIT Thermal shutdown temperature threshold 130 140 150 °C IIN_OFF Supply current OFF state TA = 27 °C IC_EN = 0 0.1 1 μA IIN_ON Supply current ON state TA = 27 °C IC_EN = 1 Buck off 5 10 20 μA
3.7 Digital IO Characteristics
Table 10: Digital I/O Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance VIH_EN Input high voltage, IC enable 1.2 AVDD V VIL_EN Input low voltage, IC enable 0.4 V tIC_EN IC enable time 1000 μs VIH_GPIO_SCL_SDA Input high voltage GPIO, SCL, SDA 1.2 AVDD V VIL_GPIO_SCL_SDA Input low voltage GPIO, SCL, SDA 0.4 V VOH_GPIO Output high voltage GPIO Push-pull mode IOUT = 1 mA 0.8*AV DD AVDD V VOL_GPIO Output low voltage GPIO Push-pull mode IOUT = 1 mA 0.2*AV DD V VOL_SDA Output low voltage SDA IOUT = 3 mA 0.24 V RPD GPIO pull -down resistor VSYS = 3.7 V Note 1 9 15 24 kΩ
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 15 Parameter Description Conditions Min Typ Max Unit RPU GPIO pull -up resistor VSYS = 3.7 V Note 1 28 45 70 kΩ Note 1 Resistance may have greater variation, depending on voltage and temperature.
3.8 Timing Specifications
Table 11: I2C Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance tBUS Bus free time between a STOP and START condition 0.5 μs CBUS Bus line capacitive load 150 pF fSCL SCL clock frequency Note 1 1000 kHz tLO_SCL SCL low time 0.5 μs tHI_SCL SCL high time 0.26 μs tRISE SCL and SDA rise time Requirement for input 1000 ns tFALL SCL and SDA fall time Requirement for input 300 ns tSETUP_START Start condition setup time 0.26 μs tHOLD_START Start condition hold time 0.26 μs tSETUP_STOP Stop condition setup time 0.26 μs tDATA Data valid time 0.45 μs tDATA_ACK Data valid acknowledge time 0.45 μs tSETUP_DATA Data setup time 50 ns tHOLD_DATA Data hold time 0 ns Note 1 Minimum clock frequency is limited to 20 kHz if I2C_TIMEOUT is enabled
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 17 5. Functional Description
5.1 DC-DC Buck Converter
DA9130 operates as a single-channel dual-phase buck converter capable of delivering up to 10 A output current at a 0.3 V to 1.9 V output voltage range. The buck converter has two voltage registers. One defines the normal output voltage, while the other offers an alternative retention voltage. In this way, different application power modes can easily be supported. The voltage selection can be operated either via GPI or via control interface to guarantee the maximum flexibility according to the specific host processor status in the application. When a buck is enabled, its output voltage is monitored and a power good signal indicates that the buck output voltage has reached a level higher than the V THR_PG_HYS threshold. The power good status is lost when the voltage drops below VTHR_PG_DWN or increases above VTHR_HV. The status of the power good indicator can be read back via I2C from the PG1 status bit. It can be also individually assigned to any of the GPIOs by setting the GPIO mode registers to PG1 output. The buck converter is capable of supporting DVC transitions that occur when: ▪ the active and selected A - or B-voltage is updated to a new target value ▪ the voltage selection is changed from the A - to B -voltage (or B - to A -voltage) using CH1_VSEL The DVC controller operates in pulse width modulation (PWM) mode with synchronous rectification. The slew rate of the DVC transition is programmed at 10 mV per (8, 4, 2, 1)µs, or 0.5 µs in register bits CH1_SR_DVC. A pull-down resistor (typically 150 Ω) for each phase is always activated unless it is disabled by setting register bits CH1_PD_DIS to 1.
5.1.1 Switching Frequency
The buck switching frequency, nominally 4 MHz, can be tuned using register bit OSC_TUNE. The internal 8 MHz oscillator frequency is tuned in ±160 kHz steps. This impacts the buck converter frequency in steps of 80 kHz and helps to mitigate possible disturb ances to other high frequency systems in the application.
5.1.2 Operation Modes and Phase Selection
The buck converters can operate in PWM and PFM modes. The operating mode is selected using register bits CH1_<A or B>_MODE. Phase shedding automatically changes between 1 - and 2-phase operation at a typical current of 2.0 A. If the automatic operation mode is selected on CH1_<A or B>_MODE, the buck converter automatically changes between synchronous PWM mode and PFM depending on the load current. This improves the efficiency across the whole range of output load currents.
5.1.3 Output Voltage Selection
The switching converter can be configured using the I2C interface. Two output voltages can be pre -configured in registers CH1_<A or B>_VOUT. The output voltage can be selected by either toggling register bit CH1_VSEL or by re-programming the selected voltage control register. Both changes will result in ramped voltage transitions. After being enabled, the buck converter will, by default, use the register settings in CH1_A_VOUT unless the output voltage selection is configured via the GPI port. Registers CH1_VMAX limit the output voltage that can be set for each of the respective buck converters.
Figure 8. Buck Output Voltage Control Concept
5.1.4 Soft Start-Up and Shutdown
start-up phase, so it should be considered carefully.
5.1.5 Current Limit
limit should be configured to at least 40 % higher than the required maximum output current. used to mask over -current events during DVC transitions.
5.1.6 Thermal Protection
DA9130 is protected from internal overheating by thermal shutdown. thermal limits, an IRQ is is raised and an event is set, although the chip continues working. below TWARN and the event flags need to be cleared before starting the bucks.
Figure 9. Thermal Protection Operation
5.2 Internal Circuits
5.2.1 IC_EN/Chip Enable/Disable
down and the buck output is pulled -down.
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 20 Name Trigger IRQ Status Register IRQ Mask Register Deglitch Period Buck1 under - voltage (event) Buck1 VOUT falling below under - voltage threshold (target voltage - VTH_PG) E_UV1 M_UV1 0 s Buck1 over -current (event) Buck1 current rising above over - current threshold E_OC1 M_OC1 0 s Buck1 power - good (status) (Note 1) Buck1 VOUT is in power -good voltage range (not under - or over -voltage) PG1 M_PG1_STAT (Note 2) 0 s System good (status) (Note 1) Buck1 power -good is active SG S_PG_STAT (Note 2) 0 s Thermal warning (status) (Note 1) TJ above TWARN TEMP_WARN M_VR_HOT (Note 2) 0 s GPIO0 change (event) Detect GPIO0 change for active trigger selected GPIO0_TRIG register E_GPIO0 M_GPIO0 100 µs/ 1 ms/ 10 ms/ 100 ms GPIO1 change (event) Detect GPIO1 change for active trigger selected GPIO1_TRIG register E_GPIO1 M_GPIO1 GPIO2 change (event) Detect GPIO2 change for active trigger selected GPIO2_TRIG register E_GPIO2 M_GPIO2 Note 1 Interrupt outputs the status as is. I 2C write is not required for interrupt clear. Note 2 OTP load value defined by CONF pin setting if CONF_EN = 1 , see section 5.2.3.3. Table 14 and Table 15 show the interrupt registers structure. See section 7.1.1 for bitfield descriptions . Table 14: Interrupt Registers Except for Power Good Status Register Description E_<name> Read-only interrupt event register 0: No interrupt 1: Interrupt occurred Cleared after being written to I2C. Set until IRQ is removed. M_<name> Interrupt mask register 0: Not masked 1: Masked. No IRQ signal sent. Event register (E_<name>) is updated . Table 15: Interrupt Registers for Power Good and Temp Warning Status Register Description PG<x> Buck<x> power good status. Asserted as long as the buck<x> output voltage is in range (under -voltage threshold < buck output voltage < over -voltage threshold) 0: Not power good
It is possible to route interrupts to a GPIO by setting the bitfield GPIO<x>_MODE = 0xC on the relevant GPIO. system -good status is high, and pulled low if an event listed in the Table 13 occurs.
- GPIO is cofigured as nIRQ
- M_TEMP_WARN = 0
- M_PG#_STAT = 0 Condition
Figure 10. Interrupt Operation Example
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5.2.3 GPIO
5.2.3.1 GPIO Pin Assignment
The DA9130 provides up to five GPIO pins, three if the I2C is enabled, see Table 16. These registers are OTP programmable. When CONF_EN = 1 GPIO0 can be used for chip configuration. Any register settings for GPIO3 and GPIO4 are ignored and GPIO3 and GPIO4 function as SCL and SDA respectively if I2C_EN = 1. Note: GPIO3 and GPIO4 functions are limited only to output features if I2C_EN = 0. Table 16: GPIO Pin Assignment OTP Option GPIO Pin Available GPIOs I2C_EN CONF_EN CONF/ GPIO0 GPIO1 GPIO2 SCL/ GPIO3 SDA/ GPIO4 1’b0 1’b0 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 5 1’b1 CONF GPIO1 GPIO2 GPIO3 GPIO4 4 1’b1 1’b0 GPIO0 GPIO1 GPIO2 SCL SDA 3 1’b1 CONF GPIO1 GPIO2 SCL SDA 2
5.2.3.2 GPIO Function
The GPIOs pins are configurable as the following functions in register GPIO<x>_MODE (x = 0 to 4): ▪ Buck1 enable input (EN1) ▪ Buck1 DVC control input (DVC1) ▪ Buck1 OTP setting reload input (RELOAD) ▪ Buck1 power good output (PG1) ▪ System good output (SG) ▪ Interrupt output (nIRQ) Table 17: GPIO Function Configuration GPIO<x>_MODE[3:0] Function IO Condition 4’h0 GPIO disable HiZ 4’h1 EN1 In 4’h2 Reserved In 4’h3 Reserved In 4’h4 DVC1 In 4’h5 Reserved In 4’h6 Reserved In 4’h7 RELOAD In 4’h8 PG1 Out 4’h9 Reserved Out 4’hA Reserved Out 4’hB SG Out 4’hC nIRQ Out 4’hD Reserved HiZ 4’hE Low level Out 4’hF High level Out
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5.2.3.3 Chip Configuration Select (CONF)
GPIO0 functions as chip configuration select (CONF) input when CONF_EN = 1. Three different chip configurations can be selected according to the CONF pin level. ▪ GPIO0 low: OTP default or CONF0 on reload ▪ GPIO0 high: CONF1 ▪ GPIO0 floating: CONF2 - not recommended. Table 18 lists the device configurations that can be modified if CONF_EN = 1. Register CONF_EN is set by OTP, see section 10.1. Table 18: GPIO0-Configurable Registers when CONF_EN = 1 Register Name Description IF_SLAVE_ADDR[6:0] I2C slave address CH1_A_MODE[1:0] CH1_A Operation mode select CH1_B_MODE[1:0] CH1_B Operation mode select CH1_VSEL CH1 output voltage and operation selection CH1_EN CH1 enable CH1_A_VOUT[7:0] CH1 output voltage setting A CH1_B_VOUT[7:0] CH1 output voltage setting B M_PG1_STAT IRQ mask setting for CH1 power good status M_VR_HOT IRQ mask setting for temp warning status GPIO1_MODE[3:0] GPIO1 mode setting GPIO2_MODE[3:0] GPIO2 mode setting GPIO1_OBUF GPIO1 output buffer select GPIO2_OBUF GPIO2 output buffer select GPIO1_TRIG[1:0] GPIO1 input trigger select GPIO1_POL GPIO1 polarity select GPIO1_PUPD GPIO1 pull -up/pull -down enable GPIO1_DEB[1:0] GPIO1 input debounce time setting GPIO1_DEB_RISE GPIO1 input debounce rising edge enable GPIO1_DEB_FALL GPIO1 input debounce falling edge enable GPIO2_TRIG[1:0] GPIO2 input trigger select GPIO2_POL GPIO2 polarity select GPIO2_PUPD GPIO2 pull -up/pull -down enable GPIO2_DEB[1:0] GPIO2 input debounce time setting GPIO2_DEB_RISE GPIO2 input debounce rising edge enable GPIO2_DEB_FALL GPIO2 input debounce falling edge enable
5.3 Operating Modes
5.3.1 ON DA9130 is ON when the IC_EN port is higher than VIH_EN and the supply voltage is higher than V THR_POR. Once enabled, the host processor can start communicating with DA9130 using the control interface, after the t IC_EN delay.
5.3.2 OFF
are pulled down by (typically 150 Ω) internal pull -down resistors.
5.4 I2C Communication
All features of DA9130 can be controlled with the I2C interface which is enabled or disabled in register I2C_EN.
0 I2C disable: SCL/GPIO3 and SDA/GPIO4 pins should be used as GPO
1 I2C enable: SCL/GPIO3 and SDA/GPIO4 pins are used as I 2C clock input and I 2C data input/output. (FM+), 400 kHz in fast -mode, or 100 kHz in standard mode.
5.4.1 I2C Protocol
brought high and then low. This pulse on SCL clocks the SDA bit into the receiver’s shift register. while the SCL is in the high state). Figure 11. I2C START and STOP Condition Timing following clock cycle (white blocks marked with A in Figure 12 and Figure 13). read/write bit, and the eight-bit register address followed by eight bits of data, terminated by a STOP condition. DA9130 responds to all bytes with acknowledge (A), see Figure 12. Figure 12. I2C Byte Write (SDA Line) the host sends no acknowledge (A*) and terminates the transmission with a STOP condition, see Figure 13.
address to the register SYS_CFG_SLVADDR, see section 7.1.1. Figure 13. I2C Byte Read (SDA Line) Examples
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 26 6. Application Information The following recommended components are examples selected from requirements of a typical application .
6.1 Capacitor Selection
Ceramic capacitors are used as bypass capacitors at all VDD and output rails. When selecting a capacitor, especially for types with high capacitance at smallest physical dimension, the DC bias characteristic has to be taken into account. Table 19: Recommended Consumer Grade Capacitor Types Application Value (µF) Size Temp. Char. Tol. (%) V-Rate (V) Type VOUT output bypass 10 0402 X5R 20 6.3 Murata GRM155R60J106ME15 PVDDx bypass 10 0603 X5R 20 25 Murata GRM188R61E106MA73 AVDD bypass 1 0402 X5R 10 10 Murata GRM155R61A105KE15 Table 20: Recommended Automotive Grade Capacitor Types Application Value (µF) Size Temp. Char. Tol. (%) V-Rate (V) Type VOUT output bypass 10 0805 X7R ±15 % ±10 6.3 TDK CGA4J1X7R0J106K125AC VOUT output bypass 10 0603 X7R ±22 % ±33 6.3 Murata GCM188D70J106ME36D PVDDx bypass 10 3216 X7R ±15 % ±10 16 Murata GCM31CR71C106KA64L AVDD bypass 1 0805 X7R ±15 % ±10 50 Murata GCM21BR71H105KA03L
6.2 Inductor Selection
Inductors should be selected based on the following parameters: ▪ Rated maximum current Usually a coil provides two current limits: ISAT specifies the maximum current at which the inductance drops by 30 % of the nominal value, and IMAX is defined by the maximum power dissipation and is applied to the effective current. ▪ DC resistance Critical for the converter efficiency and should therefore be minimized. Table 21: Recommended Inductor Types Value (µH) Size (mm) IMAX (DC) (A) ISAT (A) Tol. (%) DC Resistance (mΩ) Type
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7.1 Register Map
Table 22: Register Map Addr Register 7 6 5 4 3 2 1 0 System Module System 0x01 SYS_STATUS_0 Reserved Reserved Reserved Reserved Reserved SG TEMP_CRIT TEMP_WARN 0x02 SYS_STATUS_1 Reserved Reserved Reserved Reserved PG1 OV1 UV1 OC1 0x03 SYS_STATUS_2 Reserved Reserved Reserved Reserved Reserved GPIO2 GPIO1 GPIO0 0x04 SYS_EVENT_0 Reserved Reserved Reserved Reserved Reserved E_SG E_TEMP_CRIT E_TEMP_WAR N 0x05 SYS_EVENT_1 Reserved Reserved Reserved Reserved E_PG1 E_OV1 E_UV1 E_OC1 0x06 SYS_EVENT_2 Reserved Reserved Reserved Reserved Reserved E_GPIO2 E_GPIO1 E_GPIO0 0x07 SYS_MASK_0 Reserved Reserved Reserved Reserved Reserved Reserved M_TEMP_CRIT M_TEMP_WAR N 0x08 SYS_MASK_1 Reserved Reserved Reserved Reserved M_PG1 M_OV1 M_UV1 M_OC1 0x09 SYS_MASK_2 Reserved Reserved Reserved Reserved Reserved M_GPIO2 M_GPIO1 M_GPIO0 0x0A SYS_MASK_3 Reserved Reserved Reserved Reserved M_VR_HO T Reserved Reserved M_PG1_STAT 0x0B SYS_CONFIG_0 Reserved Reserved 0x0C SYS_CONFIG_1 Reserved Reserved 0x0D SYS_CONFIG_2 Reserved OC_LATCHOFF<1:0> OC_DVC_ M ASK PG_DVC_MASK<1:0> Reserved Reserved 0x0E SYS_CONFIG_3 Reserved OSC_TUNE<2:0> Reserved Reserved I2C_TIMEOUT Reserved 0x10 SYS_GPIO0_0 Reserved Reserved Reserved GPIO0_MODE<3:0> GPIO0_OBUF 0x11 SYS_GPIO0_1 GPIO0_DE B_FALL GPIO0_DE B_RISE GPIO0_DEB<1:0> GPIO0_PU PD GPIO0_POL GPIO0_TRIG<1:0> 0x12 SYS_GPIO1_0 Reserved Reserved Reserved GPIO1_MODE<3:0> GPIO1_OBUF 0x13 SYS_GPIO1_1 GPIO1_DE B_FALL GPIO1_DE B_RISE GPIO1_DEB<1:0> GPIO1_PU PD GPIO1_POL GPIO1_TRIG<1:0> 0x14 SYS_GPIO2_0 Reserved Reserved Reserved GPIO2_MODE<3:0> GPIO2_OBUF 0x15 SYS_GPIO2_1 GPIO2_DE B_FALL GPIO2_DE B_RISE GPIO2_DEB<1:0> GPIO2_PU PD GPIO2_POL GPIO2_TRIG<1:0>
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 28 Addr Register 7 6 5 4 3 2 1 0 Buck Control Buck1 0x20 BUCK_BUCK1_0 Reserved CH1_SR_DVC_DWN<2:0> CH1_SR_DVC_UP<2:0> CH1_EN 0x21 BUCK_BUCK1_1 Reserved CH1_SR_SHDN<2:0> CH1_SR_STARTUP<2:0> CH1_PD_DIS 0x22 BUCK_BUCK1_2 Reserved Reserved Reserved Reserved CH1_ILIM<3:0> 0x23 BUCK_BUCK1_3 CH1_VMAX<7:0> 0x24 BUCK_BUCK1_4 Reserved Reserved Reserved CH1_VSEL CH1_B_MODE<1:0> CH1_A_MODE<1:0> 0x25 BUCK_BUCK1_5 CH1_A_VOUT<7:0> 0x26 BUCK_BUCK1_6 CH1_B_VOUT<7:0> 0x27 BUCK_BUCK1_7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Serialization 0x48 OTP_DEVICE_ID DEV_ID<7:0> 0x49 OTP_VARIANT_ID MRC<3:0> VRC<3:0> 0x4A OTP_CUSTOMER_ID CUST_ID<7:0> 0x4B OTP_CONFIG_ID CONFIG_REV<7:0>
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7.1.1 System
Table 23: SYS_STATUS_0 (0x01) Bit Type Symbol Description [2] R SG Asserted whilst PG1 is asserted [1] R TEMP_CRIT Asserted whilst the thermal shutdown threshold is exceeded [0] R TEMP_WARN Asserted whilst the thermal warning threshold is exceeded Table 24: SYS_STATUS_1 (0x02) Bit Type Symbol Description [3] R PG1 Asserted whilst Buck1 output voltage is in range [2] R OV1 Asserted whilst Buck1 output is over -voltage [1] R UV1 Asserted whilst Buck1 output is under -voltage [0] R OC1 Asserted whilst Buck1 output is over -current Table 25: SYS_STATUS_2 (0x03) Bit Type Symbol Description [2] R GPIO2 GPIO2 status [1] R GPIO1 GPIO1 status [0] R GPIO0 GPIO0 status Table 26: SYS_EVENT_0 (0x04) Bit Type Symbol Description [2] R E_SG SG event. Similar to PG1 . Write 1 to clear this bit after the event source has been released. [1] R E_TEMP_CRIT TEMP_CRIT event. Write 1 to clear this bit after the event source has been released. [0] R E_TEMP_WARN TEMP_WARN event. Write 1 to clear this bit after the event source has been released. Table 27: SYS_EVENT_1 (0x05) Bit Type Symbol Description [3] RW E_PG1 PG1 caused event. Write 1 to clear this bit after the event source has been released. [2] RW E_OV1 OV1 caused event. Write 1 to clear this bit after the event source has been released. [1] RW E_UV1 UV1 caused event. Write 1 to clear this bit after the event source has been released. [0] RW E_OC1 OC1 caused event. Write 1 to clear this bit after the event source has been released.
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 30 Table 28: SYS_EVENT_2 (0x06) Bit Type Symbol Description [2] RW E_GPIO2 GPIO2 event. Write 1 to clear this bit after the event source has been released. [1] RW E_GPIO1 GPIO1 event. Write 1 to clear this bit after the event source has been released. [0] RW E_GPIO0 GPIO0 event. Write 1 to clear this bit after the event source has been released. Table 29: SYS_MASK_0 (0x07) Bit Type Symbol Description [2] RW M_SG SG IRQ mask [1] RW M_TEMP_CRIT TEMP_CRIT IRQ mask [0] RW M_TEMP_WARN TEMP_WARN IRQ mask Table 30: SYS_MASK_1 (0x08) Bit Type Symbol Description [3] RW M_PG1 PG1 event IRQ mask [2] RW M_OV1 OV1 event IRQ mask [1] RW M_UV1 UV1 event IRQ mask [0] RW M_OC1 OC1 event IRQ mask Table 31: SYS_MASK_2 (0x09) Bit Type Symbol Description [2] RW M_GPIO2 GPIO2 IRQ mask [1] RW M_GPIO1 GPIO1 IRQ mask [0] RW M_GPIO0 GPIO0 IRQ mask Table 32: SYS_MASK_3 (0x0A) Bit Type Symbol Description [3] RW M_VR_HOT Temp warning status IRQ mask. Initial value is determined by CONF pin setting at the start -up if CONF_EN = 1, see Section 5.2.3.3 [0] RW M_PG1_STAT PG1 status IRQ mask. Initial value is determined by CONF pin setting at the start-up if CONF_EN = 1, see Section 5.2.3.3
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 31 Table 33: SYS_CONFIG_2 (0x0D) Bit Type Symbol Description [6:5] RW OC_LATCHOFF Over-current latch -off setting. BUCK shut -down after OCP for 8 µs/1 ms/3 ms unless disable setting. IRQ is generated unless IRQ is masked. Value Description 0x0 Latch off disable 0x1 Latch off after 8 µs of OCP signal 0x2 Latch off after 1 ms of OCP signal 0x3 Latch off after 3 ms of OCP signal [4] RW OC_DVC_MASK Over-current event (IRQ and latch -off feature) mask during DVC ramp -up and ramp -down [3:2] RW PG_DVC_MASK Power-good mask during DVC Value Description 0x0 No mask 0x1 Mask as not power good during DVC 0x2 Mask as power good during DVC 0x3 Reserved Table 34: SYS_CONFIG_3 (0x0E) Bit Type Symbol Description [6:4] RW OSC_TUNE Tune oscillator frequency, tuned frequency = Current + OSC_TUNE * 160 kHz Value Description 0x3 3 0x2 2 0x1 1 0x0 0 0x7 -1 0x6 -2 0x5 -3 0x4 -4 [1] RW I2C_TIMEOUT Enable automatic reset of 2 -wire interface (if SDA stays low for >50 ms).
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 32 Table 35: SYS_GPIO0_0 (0x10) Bit Type Symbol Description [4:1] RW GPIO0_MODE GPIO function mode select Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 Reserved 0x3 Reserved 0x4 DVC1 input 0x5 Reserved 0x6 Reserved 0x7 RELOAD input 0x8 PG1 output 0x9 Reserved 0xA Reserved 0xB Reserved 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] RW GPIO0_OBUF GPIO output buffer select Value Description 0x0 open -drain output 0x1 push -pull output Table 36: SYS_GPIO0_1 (0x11) Bit Type Symbol Description [7] RW GPIO0_DEB_FALL GPI debou nce falling edge [6] RW GPIO0_DEB_RISE GPI debounce rising edge [5:4] RW GPIO0_DEB GPI debounce time Value Description 0x0 100 µs debou nce 0x1 1 ms debou nce 0x2 10 ms debounce 0x3 100 ms debounce [3] RW GPIO0_PUPD GPIO pull -up/pull -down enable Value Description 0x0 GPI: pull -down disabled, GPO: pull -up to AVDD disabled 0x1 GPI: pull -down enabled, GPO: pull -up to AVDD enabled
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 33 Bit Type Symbol Description [2] RW GPIO0_POL GPIO polarity Value Description 0x0 GPIO is active -high 0x1 GPIO is active -low [1:0] RW GPIO0_TRIG GPI trigger type Value Description 0x0 Dual-edge triggered 0x1 Pos-edge triggered 0x2 Neg-edge triggered 0x3 Reserved (No trigger) Table 37: SYS_GPIO1_0 (0x12) Bit Type Symbol Description [4:1] RW GPIO1_MODE GPIO function mode select. Initial value is determined by CONF pin setting at the start -up in CONF_EN = 1 Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 Reserved 0x3 Reserved 0x4 DVC1 input 0x5 Reserved 0x6 Reserved 0x7 RELOAD input 0x8 PG1 output 0x9 Reserved 0xA Reserved 0xB Reserved 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] RW GPIO1_OBUF GPIO output buffer select. Initial value is determined by CONF pin setting at the start -up in CONF_EN = 1 Value Description 0x0 open -drain output 0x1 push -pull output
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 34 Table 38: SYS_GPIO1_1 (0x13) Bit Type Symbol Description [7] RW GPIO1_DEB_FALL GPI debou nce falling edge. Initial value is determined by CONF pin setting at the start -up in CONF_EN = 1 [6] RW GPIO1_DEB_RISE GPI debounce rising edge. Initial value is determined by CONF pin setting at the start -up in CONF_EN = 1 [5:4] RW GPIO1_DEB GPI debounce time. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 100 µs debou nce 0x1 1 ms debou nce 0x2 10 ms debounce 0x3 100 ms debounce [3] RW GPIO1_PUPD GPIO pull -up/pull -down enable. Initial value is determined by CONF pin setting at the start -up in CONF_EN = 1 Value Description 0x0 GPI: pull -down disabled, GPO: pull -up to AVDD disabled 0x1 GPI: pull -down enabled, GPO: pull -up to AVDD enabled [2] RW GPIO1_POL GPIO polarity. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 GPIO is active -high 0x1 GPIO is active -low [1:0] RW GPIO1_TRIG GPI trigger type. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 Dual-edge triggered 0x1 Pos-edge triggered 0x2 Neg-edge triggered 0x3 Reserved (No trigger)
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 35 Table 39: SYS_GPIO2_0 (0x14) Bit Type Symbol Description [4:1] RW GPIO2_MODE GPIO function mode select. Initial value is determined by CONF pin setting at the start -up in CONF_EN = 1 Value Description 0x0 GPIO disable 0x1 EN1 input 0x2 Reserved 0x3 Reserved 0x4 DVC1 input 0x5 Reserved 0x6 Reserved 0x7 RELOAD input 0x8 PG1 output 0x9 Reserved 0xA Reserved 0xB Reserved 0xC nIRQ output 0xD Reserved 0xE Low output 0xF High output [0] RW GPIO2_OBUF GPIO output buffer select. Initial value is determined by CONF pin setting at the start -up in CONF_EN = 1 Value Description 0x0 open -drain output 0x1 push -pull output Table 40: SYS_GPIO2_1 (0x15) Bit Type Symbol Description [7] RW GPIO2_DEB_FALL GPI debou nce falling edge. Initial value is determined by CONF pin setting at the start -up in CONF_EN = 1 [6] RW GPIO2_DEB_RISE GPI debounce rising edge. Initial value is determined by CONF pin setting at the start -up in CONF_EN = 1 [5:4] RW GPIO2_DEB GPI debounce time. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 100 µs debou nce 0x1 1 ms debou nce 0x2 10 ms debounce 0x3 100 ms debounce
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 36 Bit Type Symbol Description [3] RW GPIO2_PUPD GPIO pull -up/pull -down enable. Initial value is determined by CONF pin setting at the start -up in CONF_EN = 1 Value Description 0x0 GPI: pull -down disabled, GPO: pull -up to AVDD disabled 0x1 GPI: pull -down enabled, GPO: pull -up to AVDD enabled [2] RW GPIO2_POL GPIO polarity. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 GPIO is active -high 0x1 GPIO is active -low [1:0] RW GPIO2_TRIG GPI trigger type. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Value Description 0x0 Dual-edge triggered 0x1 Pos-edge triggered 0x2 Neg-edge triggered 0x3 Reserved (No trigger) Table 41: SYS_CFG_SLVADDR (0xA1) Bit Type Symbol Description [6:0] RW I2C_SLAVE_ADDR Slave address of the device. Default 0x68 (translated to 0xD0 8 -bit I2C address ), changed by OTP .
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7.1.2 Buck1
Table 42: BUCK_BUCK1_0 (0x20) Bit Type Symbol Description [6:4] RW CH1_SR_DVC_DWN Voltage slew -rate for DVC ramp -down Value Description 0x0 10 mV/8 µs 0x1 10 mV/4 µs 0x2 10 mV/2 µs 0x3 10 mV/µs 0x4 20 mV/µs 0x5 Reserved 0x6 Reserved 0x7 Reserved [3:1] RW CH1_SR_DVC_UP Voltage slew -rate for DVC ramp -up Value Description 0x0 10 mV/8 µs 0x1 10 mV/4 µs 0x2 10 mV/2 µs 0x3 10 mV/µs 0x4 20 mV/µs 0x5 40 mV/µs 0x6 Reserved 0x7 Reserved [0] RW CH1_EN Channel enable. Initial value is determined by CONF pin setting at the start-up in CONF_EN = 1 Table 43: BUCK_BUCK1_1 (0x21) Bit Type Symbol Description [6:4] RW CH1_SR_SHDN Voltage slew -rate during shut -down Value Description 0x0 10 mV/8 µs 0x1 10 mV/4 µs 0x2 10 mV/2 µs 0x3 10 mV/µs 0x4 20 mV/µs 0x5 Reserved 0x6 Reserved 0x7 Immediate power -down
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 38 Bit Type Symbol Description [3:1] RW CH1_SR_STARTUP Voltage slew -rate during startup Value Description 0x0 10 mV/8 µs 0x1 10 mV/4 µs 0x2 10 mV/2 µs 0x3 10 mV/µs 0x4 20 mV/µs 0x5 40 mV/µs 0x6 Reserved 0x7 Reserved [0] RW CH1_PD_DIS Pull-down while buck is disabled. 0: enable, 1: disable Table 44: BUCK_BUCK1_2 (0x22) Bit Type Symbol Description [3:0] RW CH1_ILIM Select OCP threshold per phase (A). The value is configured by OTP and should not be modified whil e the buck is active. Value Description 0x0 Reserved 0x1 3.5 0x2 4.0 0x3 4.5 0x4 5.0 0x5 5.5 0x6 6.0 0x7 6.5 0x8 7.0 0x9 7.5 0xA 8.0 0xB 8.5 0xC 9.0 0xD 9.5 0xE 10.0 0xF Disable
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 39 Table 45: BUCK_BUCK1_3 (0x23) Bit Type Symbol Description [7:0] RW CH1_VMAX VOUT max setting (V): From 0.30 V (0x1E) to 1.90 V (0xBE) in 10 mV steps. This is a read -only register. Value Description 0x1E 0.3 0x1F 0.31 0x20 0.32 Continuing through… 0x99 1.53 To… 0xBD 1.89 0xBE 1.9 Table 46: BUCK_BUCK1_4 (0x24) Bit Type Symbol Description [4] RW CH1_VSEL Output voltage and operation selection: 0: A, 1: B. Initial value is determined by CONF pin setting at the start -up in CONF_EN = 1 [3:2] RW CH1_B_MODE Operation mode selection. Initial value is determined by CONF pin setting at the start -up in CONF_EN = 1 Value Description 0x0 Force PFM operation 0x1 Force PWM operation (full phase) 0x2 Force PWM operation (with phase shedding) 0x3 Auto mode [1:0] RW CH1_A_MODE Operation mode selection. Initial value is determined by CONF pin setting at the start -up in CONF_EN = 1 Value Description 0x0 Force PFM operation 0x1 Force PWM operation (full phase) 0x2 Force PWM operation (with phase shedding) 0x3 Auto mode
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 40 Table 47: BUCK_BUCK1_5 (0x25) Bit Type Symbol Description [7:0] RW CH1_A_VOUT Output voltage setting A: Initial value is determined by CONF pin setting at the start -up in CONF_EN = 1 From 0.30 V (0x1E) to 1.90 V (0xBE) in steps of 10 mV (default 1.0 V) Write-protected when value is written below 0.30 V or above 1.90 V Value Description 0x1E 0.3 0x1F 0.31 0x20 0.32 Continuing through… 0x64 1 To… 0xBC 1.88 0xBD 1.89 0xBE 1.9 Table 48: BUCK_BUCK1_6 (0x26) Bit Type Symbol Description [7:0] RW CH1_B_VOUT Output voltage setting B: Initial value is determined by CONF pin setting at the start -up in CONF_EN = 1 From 0.30 V (0x1E) to 1.90 V (0xBE) in steps of 10 mV (default 1.0 V) Write-protected when value is written below 0.30 V or above 1.90 V Value Description 0x1E 0.3 0x1F 0.31 0x20 0.32 Continuing through… 0x64 1 To… 0xBC 1.88 0xBD 1.89 0xBE 1.9
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7.1.3 Serialization
Table 49: OTP_DEVICE_ID (0x48) Bit Type Symbol Description [7:0] R DEV_ID Device ID Table 50: OTP_VARIANT_ID (0x49) Bit Type Symbol Description [7:4] R MRC Mask Revision Code [3:0] R VRC Chip Variant Code Table 51: OTP_CUSTOMER_ID (0x4A) Bit Type Symbol Description [7:0] R CUST_ID Customer ID Table 52: OTP_CONFIG_ID (0x4B) Bit Type Symbol Description [7:0] R CONFIG_REV OTP Variant
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 42 8. Moisture Sensitivity Level The Moisture Sensitivity Level (MSL) is an indicator for the maximum allowable time period (floor lifetime) in which a moisture sensitive plastic device, once removed from the dry bag, can be exposed to an environment with a specified maximum temperature and a maximum relative humidity before the solder reflow process. The MSL classification is defined in Table 53. For detailed information on MSL levels, refer to the IPC/JEDEC standard J-STD-020, which can be downloaded from http://www.jedec.org . The FCQFN package is qualified for MSL 3. Table 53: MSL classification MSL level Floor lifetime Conditions MSL 4 72 hours 30°C/60% RH MSL 3 168 ho urs 30°C/60% RH MSL 2A 4 weeks 30°C/60% RH MSL 2 1 year 30°C/60% RH MSL 1 Unlimited 30°C/85% RH
8.1 Soldering Information
Refer to the IPC/JEDEC standard J -STD-020 for relevant soldering information. This document can be downloaded from http://www.jedec.org .
9.1 Package Outlines
Figure 14. Package Outline Drawing
9.2 Package Marking
2nd D A 9 1 3 0 Orientation/Part No. A or AT optionally indicate the Automotive and Automotive high temp test options.
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 44 10. Ordering Information The ordering number consists of the part number followed by a suffix indicating the packing method. For details and availability, please consult your Renesas local sales representative. Table 54: Ordering information Part number Package Package Description MOQ DA9130-xxRT2 24 FCQFN wettable flanks, 3.3 x 4.8 T&R, 4800 pcs 3 Reels - 14400 DA9130-xxRT1 24 FCQFN wettable flanks Tray, 490 pcs 30 Trays - 14700 pcs
10.1 Variants Ordering Information
DA9130 supports delivery of variants indicated by xx in the part number above, where xx is replaced with the actual variant number. Please contact your Renesas local sales representative to discuss requirements.
Figure 15. DA9130 Footprint ▪ Standard pads are 0.85 mm x 0.3 mm with 0.05 mm radius corners. ▪ Solder paste on custom pads is split into multiple apertures meeting standard area coverage of 30 to 70 %.
11.1 Custom Pads Details
Figure 16. DA9130 Footprint Details
R16DO0058EJ0301 Rev.03.01 July 01, 2025 CFR0011-120-00 Page 46 RoHS Compliance Renesas Electronics’ suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from our suppliers are available on request.
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