DA9083

Renesas Technology Corp

High Current, Highly Configurable System PMIC 18-Mar-2022

Manufacturer: Renesas Technology Corp

Document: 63 Pages / 700Kb

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DA9083 RENESAS | Alldatasheet

Document overview

Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 63

Technical content

Datasheet sections

1 Terms and Definitions
2 References
3 Block Diagram
4 Pinout
5 Characteristics
5.1 Absolute Maximum Ratings
5.2 Electrostatic Discharge Ratings
5.3 Recommended Operating Conditions
5.4 Thermal Characteristics
5.5 CH1 Buck Converter Characteristics
5.6 CH2 Buck Converter Characteristics
5.7 CH3 Buck Converter Characteristics
5.8 CH4 Buck Converter Characteristics
5.9 Load Switch Characteristics
5.10 LDO Electrical Characteristics
5.11 Supervision Characteristics
5.12 I2C Characteristics
5.13 Digital I/O Characteristics
6 Functional Description
6.1 Function State
6.2 Normal Sequence
6.2.1 Power On and Power Off Sequence
6.2.2 Sleep Mode Enter and Exit Sequence
6.3 Fault and Protection
6.4 Buck Converters
6.4.1 Buck Operation Mode
6.5 LDO
6.6 I2C Communication
7 Register Definitions
7.1 Register Map
8 Register Descriptions
8.1.1 PMIC Function Registers
9 Package Information
9.1 Moisture Sensitivity Level
9.2 WLCSP Handling
9.3 Soldering Information
10 Ordering Information

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 1 of 63 © 2022 Renesas Electronics General Description DA9083 is a six-channel, advanced, system power management IC (PMIC) that integrates four buck converters, one LDO, and one load switch. This high current, integrated PMIC is ideal for Client and Enterprise SSD Modules, Hybrid Drives, and other memory management applications. Due to its highly configurable and flexible design, it supports a wide variety of other applications with integrated microcontrollers, DSPs, and FPGAs in embedded applications and a host of other Internet of Things (IoT) and consumer applications. DA9083 includes many robust protection features, a dedicated I2C interface, and programmable output voltages. Dynamic voltage control (DVC) enables supply voltage controllability based on the application requirements. This PMIC is capable of achieving high efficiencies and fast transient responses to line and load changes while keeping the overall board space to a minimum. All of these features and functionality is offered in a compact 36-lead CSP package. Key Features ■ Power supply voltage (VIN) 2.9 V to 5.5 V ■ 4 buck converters ■ Selectable output voltage range for all bucks: □ 1.5 V to 2.7 V, 20 mV step □ 0.55 V to 1.9 V, 10 mV step ■ Maximum output current: □ CH1, CH2, CH3 Bucks: 2.5 A □ CH4 Buck: 5.0 A ■ Interleaving of switching phases of bucks ■ LDO: □ VOUT: 1.4 V to 1.9 V, 20 mV step □ IOUT: 0.1 A (max) ■ Load switch (LSW) □ RDS_ON: 20 mΩ (typ) □ Current limit at soft start: 100 mA □ Current limit: 4 A ■ Protection functions: □ Over-current protection □ Over/Under-voltage protection □ Thermal shutdown protection ■ I2C control interface: □ Standard mode (100 kbit/s) □ Fast mode (400 kbit/s) □ Fast mode+ (1 Mbit/s) □ High-speed mode (3.4 Mbit/s)

Applications

■ SSD (solid state drive) module ■ Portable devices ■ Home entertainment equipment System Diagram DA9083 SoC NAND FLASH I2C VDD_CORE VDD_PCIe VDD_ANALOG VDD_NAND_IO VDD_NAND PCIe 3.3 V Input Figure 1: System Diagram

1 Terms and Definitions

DVC Dynamic voltage control ESD Electrostatic discharge HBM Human Body Model HPM High Power mode LPM Low Power mode OTP One-time programmable OVP Over-voltage protection POR Power-on reset PMIC Power management integrated circuit PWM Pulse width modulation PFM Pulse frequency modulation TSD Thermal shut down UVLO Under-voltage lock out UVP Under-voltage protection

2 References

[1] I2C-Bus Specification Rev 06 UM1010204, issued on 4 April 2014

3 Block Diagram

Figure 2: Block Diagram

4 Pinout

A B C D E F LX2 PGND1 LX1 SCL SDA FB1 LX2PGND2 POR FB2 AGND LX4 LX3 FB3 FB4 PGND4 PGND3 VOUTLDOOUT VOUT VIN VIN VOUT VIN PVIN3 CH1SEL LDOIN PVIN4 VSEL PVIN1 PVIN2PGND4LX4 LX4LX4 PGND4 No connectionMixed signal Noisy groundDigital signal Analog signalSwitching signal, high current Static signal, high current Quiet ground Figure 3: WLCSP Pinout Diagram (Top View) Table 1: Pin Description Pin # Pin Name Type (Table 2) Description A1 PGND3 GND CH3 DCDC buck converter ground A2 LDOOUT AO LDO output, bypass to ground with ceramic capacitor A3 VOUT AO Load Switch output A4 VOUT AO Load Switch output A5 VIN PWR Load Switch input A6 VIN PWR Load Switch input B1 LX3 AIO CH3 DCDC buck converter switching node B2 LDOIN PWR LDO input, bypass to ground with a ceramic capacitor

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 8 of 63 © 2022 Renesas Electronics Pin # Pin Name Type (Table 2) Description B3 SCL DI I2C interface data, connect SCL to the logic rail through a pull-up resistor B4 VOUT AO Load Switch output B5 VIN PWR Load Switch input B6 PGND1 GND CH1 Buck converter power ground C1 PVIN3 PWR CH3 Buck converter input C2 FB3 AI CH3 Buck output voltage feedback connection C3 POR DOD Power-on-Reset release output signal (Power Good), output open-drain C4 SDA DIOD I2C interface data. Connect SDA to the logic rail through a pull-up resistor C5 CH1SEL DI Reserved. Needs to be tied to ground C6 LX1 AIO CH1 Buck converter switching node D1 PVIN4 PWR CH4 Buck converter power D2 VSEL DI Reserved. Needs to be tied to ground D3 FB4 AI CH4 Buck output voltage feedback connection D4 AGND GND Quiet ground connection, Connect to a quiet ground area D5 FB1 AI CH1 Buck output voltage feedback connection D6 PVIN1 PWR CH1 Buck converter input E1 LX4 AIO CH4 Buck converter switching node E2 LX4 AIO CH4 Buck converter switching node E3 PGND4 GND CH4 Buck converter power ground E4 PGND4 GND CH4 Buck converter power ground E5 FB2 AI CH2 Buck output voltage feedback connection E6 PVIN2 PWR CH2 Buck converter input F1 LX4 AIO CH4 Buck converter switching node F2 LX4 AIO CH4 Buck converter switching node F3 PGND4 GND Power ground for the CH4 Buck converter F4 PGND2 GND Power ground for the CH2 Buck converter F5 LX2 AIO CH2 Buck converter switching node F6 LX2 AIO CH2 Buck converter switching node Table 2: Pin Type Definition Pin Type Description Pin Type Description DI Digital input AI Analog input DO Digital output AO Analog output DIOD Digital input/output open drain AIO Analog input/output DOD Digital output open drain GND Ground PWR Power

5 Characteristics

5.1 Absolute Maximum Ratings

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Table 3: Absolute Maximum Ratings Parameter Description Conditions Min Max Unit TSTG Storage temperature -60 150 °C VSYS System supply voltage Referenced to AGND -0.3 6 V VPIN All other terminals Referenced to AGND -0.3 6 V

5.2 Electrostatic Discharge Ratings

Table 4: Electrostatic Discharge Ratings Parameter Description Conditions Value Unit ESDHBM Maximum ESD protection Human body model (HBM) All exposed pins 2 kV ESDCDM Maximum ESD protection Charged device model (CDM) 0.5 kV

5.3 Recommended Operating Conditions

Table 5: Recommended Operating Conditions Parameter Description Conditions Min Typ Max Unit TA Operating ambient temperature -40 85 °C TJ Operating junction temperature -40 125 °C VIN Input Supply voltage 2.9 5.5 V VPIN Voltage on pins -0.3 VIN+0.3 V

5.4 Thermal Characteristics

Table 6: Package Ratings Parameter Description Conditions Min Typ Max Unit RƟ_JA Package thermal resistance Note 1 28.6 °C/W PD Power dissipation Derating factor above TA= 70°C, 35 mW/°C (1/RƟ_JA) 2450 mW Note 1 Obtained from package thermal simulation, 4-layer board (JEDEC). Influenced by PCB technology and layout.

5.5 CH1 Buck Converter Characteristics

Table 7: CH1 Buck Converter Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External Electrical Conditions VIN Input voltage of power stage 2.7 3.3 5.5 V COUT Output capacitance, including voltage and temperature coefficient Only local capacitor without decoupling capacitor at load side. 11 22 29 μF ESRCOUT Output capacitor series resistance f > 100 kHz 3 mΩ L Inductor value, including current and temperature dependence 0.23 0.47 0.61 μH DCRL Inductor DC resistance 20 50 mΩ Electrical Performance IQ_LPM Quiescent current in Low Power mode (no switching) VIN = 3.3 V TA = 27 °C 18 μA IQ_AUTO Quiescent current in Auto mode (no switching) VIN = 3.3 V TA = 27 °C 42 μA fSW Switching frequency 1.9 2 2.1 MHz VDROPOUT Voltage drop from PVIN to VOUT 1 V VOUT_DIV Range of output voltage with divider (OTP option), programmable in 20 mV steps. PVIN1 = 2.7 V to 5.5 V 1.5 2.7 V VOUT_NO_DIV Range of output voltage without divider (OTP option), programmable in 10 mV steps. PVIN1 = 2.7 V to 5.5 V 0.5 1.9 V SRSS Soft start slew rate 2.5 mV/μs VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT ≥ 1 V TA = 27 °C -1 1 % VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT < 1 V -10 10 mV RON_PMOS On resistance of switching PMOS VIN = 3.3 V TA = 27 °C 62 mΩ RON_NMOS On resistance of switching NMOS VIN = 3.3 V TA = 27 °C 28 mΩ

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 11 of 63 © 2022 Renesas Electronics Parameter Description Conditions Min Typ Max Unit IPOSLIM Positive current limit threshold With default setting VIN = 3.3 V TA = 27 °C 3 4 A VTHR_OVP_RISE Over-voltage protection threshold +200 +300 +400 mV VTHR_UVP_FALL Under-voltage protection threshold -400 -300 -200 mV RDCHG Discharge resistance for LX node VIN = 3.3 V TA = 27 °C 10 Ω tON_MIN Buck minimum On-time VIN = 3.3 V TA = 27 °C 20 ns

5.6 CH2 Buck Converter Characteristics

Table 8: CH2 Buck Converter Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External Electrical Conditions VIN Input voltage of power stage 2.7 3.3 5.5 V COUT Output capacitance, including voltage and temperature coefficient Only local capacitor without decoupling capacitor at load side. 11 22 29 μF ESRCOUT Output capacitor series resistance f > 100 kHz 3 mΩ L Inductor value, including current and temperature dependence 0.23 0.47 0.61 μH DCRL Inductor DC resistance 20 50 mΩ Electrical Performance IQ_LPM Quiescent current in Low Power mode (no switching) VIN = 3.3 V TA = 27 °C 17 μA IQ_AUTO Quiescent current in Auto mode (no switching) VIN = 3.3 V TA = 27 °C 42 μA fSW Switching frequency 1.9 2 2.1 MHz VDROPOUT Voltage drop from PVIN to VOUT 1 V VOUT_DIV Range of output voltage with divider (OTP option), programmable in 20 mV steps. PVIN2 = 2.7 V to 5.5 V 1.5 2.7 V

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 12 of 63 © 2022 Renesas Electronics Parameter Description Conditions Min Typ Max Unit VOUT_NO_DIV Range of output voltage with no divider (OTP option), programmable in 10 mV steps. PVIN2 = 2.7 V to 5.5 V 0.5 1.9 V SRSS Soft start slew rate 2.5 mV/μs VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT ≥ 1 V TA = 27 °C -1 1 % VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT < 1 V -10 10 mV RON_PMOS On resistance of switching PMOS VIN = 3.3 V TA = 27 °C 62 mΩ RON_NMOS On resistance of switching NMOS VIN = 3.3 V TA = 27 °C 28 mΩ IPOSLIM Positive current limit threshold With default setting VIN = 3.3 V TA = 27 °C 3 4 A VTHR_OVP_RISE Over-voltage protection threshold +200 +300 +400 mV VTHR_UVP_FALL Under-voltage protection threshold -400 -300 -200 mV RDCHG Discharge resistance for LX node VIN = 3.3 V TA = 27 °C 20 Ω tON_MIN Buck minimum On-time VIN = 3.3 V TA = 27 °C 20 ns

5.7 CH3 Buck Converter Characteristics

Table 9: CH3 Buck Converter Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External Electrical Conditions VIN Input voltage of power stage 2.7 3.3 5.5 V COUT Output capacitance, including voltage and temperature coefficient Only local capacitor without decoupling capacitor at load side. 11 22 29 μF ESRCOUT Output capacitor series resistance f > 100 kHz 5 mΩ L Inductor value, including current and temperature dependence 0.23 0.47 0.61 μH

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 13 of 63 © 2022 Renesas Electronics Parameter Description Conditions Min Typ Max Unit DCRL Inductor DC resistance 20 50 mΩ Electrical Performance IQ_LPM Quiescent current in Low Power mode (no switching) VIN = 3.3 V TA = 27 °C 17 μA IQ_AUTO Quiescent current in Auto mode (no switching) VIN = 3.3 V TA = 27 °C 42 μA fSW Switching frequency 1.9 2 2.1 MHz VDROPOUT Voltage drop from PVIN to VOUT 1 V VOUT_DIV Range of output voltage with divider (OTP option), programmable in 20 mV steps. PVIN3 = 2.7 V to 5.5 V 1.5 2.7 V VOUT_NO_DIV Range of output voltage with no divider (OTP option), programmable in 10 mV steps. PVIN3 = 2.7 V to 5.5 V 0.5 1.9 V SRSS Soft start slew rate 2.5 mV/μs VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT ≥ 1 V TA = 27 °C -1 1 % VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT < 1 V -10 10 mV RON_PMOS On resistance of switching PMOS VIN = 3.3 V TA = 27 °C 62 mΩ RON_NMOS On resistance of switching NMOS VIN = 3.3 V TA = 27 °C 28 mΩ IPOSLIM Positive current limit threshold With default setting VIN = 3.3 V TA = 27 °C 3 4 A VTHR_OVP_RISE Over-voltage protection threshold +200 +300 +400 mV VTHR_UVP_FALL Under-voltage protection threshold -400 -300 -200 mV RDCHG Discharge resistance for LX node VIN = 3.3 V TA = 27 °C 30 Ω tON_MIN Buck minimum On-time VIN = 3.3 V TA = 27 °C 20 ns

5.8 CH4 Buck Converter Characteristics

Table 10: CH4 Buck Converter Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External Electrical Conditions VIN Input voltage of power stage 2.7 3.3 5.5 V COUT Output capacitance, including voltage and temperature coefficient Only local capacitor without decoupling capacitor at load side. 11 22 29 μF ESRCOUT Output capacitor series resistance f > 100 kHz 3 mΩ L Inductor value, including current and temperature dependence 0.23 0.47 0.61 μH DCRL Inductor DC resistance 20 50 mΩ Electrical Performance IQ_LPM Quiescent current in Low Power mode (no switching) VIN = 3.3 V TA = 27 °C 17 μA IQ_AUTO Quiescent current in Auto mode (no switching) VIN = 3.3 V TA = 27 °C 42 μA fSW Switching frequency 1.9 2 2.1 MHz VDROPOUT Voltage drop from PVIN to VOUT 1 V VOUT_DIV Range of output voltage with divider (OTP option), programmable in 20 mV steps. PVIN4 = 2.7 V to 5.5 V 1.5 2.7 V VOUT_NO_DIV Range of output voltage with no divider (OTP option), programmable in 10 mV steps. PVIN4 = 2.7 V to 5.5 V 0.5 1.9 V SRSS Soft start slew rate 2.5 mV/μs VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT ≥ 1 V TA = 27 °C -1 1 % VOUT_ACC Output voltage accuracy, including static line and load regulation VOUT < 1 V -10 10 mV RON_PMOS On resistance of switching PMOS VIN = 3.3 V TA = 27 °C 52 mΩ RON_NMOS On resistance of switching NMOS VIN = 3.3 V TA = 27 °C 20 mΩ

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 15 of 63 © 2022 Renesas Electronics Parameter Description Conditions Min Typ Max Unit IPOSLIM Positive current limit threshold With default setting VIN = 3.3 V TA = 27 °C 7 8.5 A VTHR_OVP_RISE Over-voltage protection threshold +200 +300 +400 mV VTHR_UVP_FALL Under-voltage protection threshold -400 -300 -200 mV RDCHG Discharge resistance for LX node VIN = 3.3 V TA = 27 °C 25 Ω tON_MIN Buck minimum On-time VIN = 3.3 V TA = 27 °C 20 ns

5.9 Load Switch Characteristics

Table 11: Load Switch Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External Electrical Conditions VIN Input voltage 2.2 3.3 5.5 V Electrical Performance IQ Quiescent current VIN = 3.3 V TA = 27 °C 14.5 μA RON On resistance VIN = 3.3 V TA = 27 °C IOUT = 200 mA 20 mΩ ILIM_SOFTSTART Current limit at soft start VIN = 3.3 V TA = 27 °C 50 100 150 mA ILIM Current limit VIN = 3.3 V TA = 27 °C 4 A tSOFTSTART Soft start time No load condition VIN = 3.3 V COUT = 50 μF 1.5 ms

5.10 LDO Electrical Characteristics

Table 12: LDO Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External Electrical Conditions VIN Input voltage of power stage 2.7 3.3 5.5 V COUT Output capacitance, including voltage and temperature coefficient 2.3 4.7 6.1 μF Electrical Performance IQ Quiescent current VIN = 3.3 V TA = 27 °C 3.5 μA VOUT Output voltage range 1.4 1.9 V VOUT_STEP Output voltage programable step 20 mV VOUT_ACC Output voltage accuracy, including static line and load regulation VIN = 3.3 V VLDOOUT = 1.8 V IOUT = 10 mA TA = 27 °C, 1.782 1.8 1.818 V tSOFTSTART Soft start time No load condition VIN = 3.3 V VLDOOUT = 1.8 V TA = 27 °C COUT = 4.7 μF 0.5 0.8 ms IINRUSH Inrush current VIN = 3.3 V TA = 27 °C COUT = 4.7 μF 200 mA ILIM Current limit threshold VIN = 3.3 V VLDOOUT = 1.8 V TA = 27 °C COUT = 4.7 μF 200 mA VDROPOUT Voltage drop from LDOIN to LDOOUT VIN = 3.3 V VLDOOUT = 1.8 V IOUT = 200 mA TA = 27 °C COUT = 4.7 μF 250 530 mV VTHR_OVP_RISE Over-voltage protection threshold 2.2 2.25 2.3 V VTHR_UVP_FALL Under-voltage protection threshold 0.95 1 1.05 V RDCHG Discharge resistance 47 Ω

5.11 Supervision Characteristics

Table 13: Supervision Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External Electrical Conditions VIN Input voltage 2.9 5.5 V Electrical Performance IQ Quiescent current 11.5 μA VTHR_OVP_RISE VIN over-voltage protection threshold for VIN rising 5.6 5.7 5.85 V VTHR_OVP_HYS VIN over-voltage protection hysteresis 0.3 V VTHR_UVLO_FALL VIN UVLO threshold for VIN falling 2.1 2.3 V VTHR_UVLO_HYS VIN UVLO hysteresis 0.1 V VTHR_POR_FALL VOUT POR threshold for VOUT falling 2.6 2.7 2.8 V VTHR_POR_HYS VOUT POR hysteresis 0.05 0.1 0.15 V tD_POR POR delay time until POR pin is asserted. 6 ms TTHR_SHDN Thermal shutdown threshold 130 140 150 °C TTHR_SHDN_HYS Thermal shutdown hysteresis 15 °C

5.12 I2C Characteristics

Table 14: I2C Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical Performance Standard/Fast/Fast+ Mode tBUS Bus free time between a STOP and START condition 0.5 μs CBUS Bus line capacitive load 150 pF fSCL SCL clock frequency 1000 kHz tLO_SCL SCL low time 0.5 μs tHI_SCL SCL high time 0.26 μs tRISE SCL and SDA rise time. Requirement for input. 1000 ns tFALL SCL and SDA fall time. Requirement for input. 300 ns tSETUP_START Start condition setup time 0.26 μs tHOLD_START Start condition hold time 0.26 μs tSETUP_STOP Stop condition setup time 0.26 μs tDATA Data valid time 0.45 μs tDATA_ACK Data valid acknowledge time 0.45 μs tSETUP_DATA Data setup time 50 ns tHOLD_DATA Data hold time 0 ns tSPIKE Spike suppression pulse width 0 50 ns HS Mode CBUS Bus line capacitive load 100 pF fSCL SCL clock frequency 3400 kHz tLO_SCL SCL low time 160 ns tHI_SCL SCL high time 60 ns tRISE SCL and SDA rise time. Requirement for input. 160 ns tFALL SCL and SDA fall time. Requirement for input. 160 ns tSETUP_START Start condition setup time 160 ns tHOLD_START Start condition hold time 160 ns

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 19 of 63 © 2022 Renesas Electronics Parameter Description Conditions Min Typ Max Unit tSETUP_STOP Stop condition setup time 160 ns tSETUP_DATA Data setup time 10 ns tHOLD_DATA Data hold time 0 ns tSPIKE Spike suppression pulse width 0 10 ns

5.13 Digital I/O Characteristics

Table 15: Digital I/O Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical Performance VIH_SCL_SDA Input high voltage, SCL, SDA 1.2 V VIL_SCL_SDA Input low voltage, SCL, SDA 0.4 V VOL_POR Output low voltage, POR IOUT = 3 mA 0.4 V VOL_SDA Output low voltage, SDA IOUT = 3 mA 0.4 V VIH_VSEL Input high voltage, VSEL 1.2 V VIL_VSEL Input low voltage, VSEL 0.4 V VIH_CH1SEL Input high voltage, CH1SEL 1.2 V VIL_CH1SEL Input low voltage, CH1SEL 0.4 V RPD_VSEL Pull-down resistor, VSEL 1 10 100 kΩ RPU_VSEL Pull-up resistor, VSEL 1 10 100 kΩ ILKG_POR VPOR = 3.3 V 1 μA

6 Functional Description

6.1 Function State

The function state flow is described in Figure 4 and Table 16. Normal sequences such as start-up and shut-down are controlled by this flow. Fault protection also follows this flow. CPOR OTP LSW ACTIVE SEQ SLEEP WAKE FAULT FAULT FAULT FAULT cpor_n cpor_n any state SLEEP SLEEP VIN CHECK uv_vin_n high AND ov_vin lowFAULT (except for VIN UVLO and VIN OVP) Hiccup- VIN_UVLO Hiccup- TSD/VIN_OVP Latch-off- VOUT_POR Latch-off- ALL NOT VIN_UVLO VIN_UVLO TSD VIN_OVP VIN_UVLO FAULT

VIN UVLO
VIN OVP
VOUT POR
OVP/UVP
TSD VOUT_POR TSD VIN_OVP OVP UVP VIN_UVLO FAULT FAULT NOT FAULT VIN_UVLO else FAULT Figure 4: Function State Control Flow Table 16: Function State State Name Function CPOR Enter this state when VIN < CPOR (2.0 V). All registers are cleared. (Digital hardware reset) OTP Initialize registers by loading OTP contents. Clear all the fault event bits (VOUT POR, OVPs, UVPs and TSD) for transition from Hiccup-VIN_UVLO. VIN CHECK Check VIN level and wait until it is within the appropriate range.

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 21 of 63 © 2022 Renesas Electronics State Name Function LSW Activate LSW SEQ Activate Buck CH<x> and LDO. Then assert POR pin. ACTIVE All rails active, wait for SLEEP command. SLEEP Shutdown rails by SLEEP command. WAKE Activate rails by WAKE command. Latch-Off-ALL Latch-off all rails (CH<x>, LDO, LSW, and POR = L). Latch-Off- VOUT_POR Latch-off rails except for LSW (CH<x>, LDO, and POR = L). Hiccup-VIN_UVLO Hiccup all rails (CH<x>, LDO, LSW, and POR = L) and go to RESET (OTP) state. Hiccup- TSD/VIN_OVP Hiccup all rails (CH<x>, LDO, LSW, and POR = L) and go to Non Reset (VIN CHECK).

6.2 Normal Sequence

6.2.1 Power On and Power Off Sequence

Power on and power off sequence can be cofigured by OTP. Wake-up timings of all buck converters and the LDO during power-on sequence are selectable from 15 time slots by PMC_CH<x>CH<y>_WAKEUP_TIME and PMC_LDO_WAKEUP_TIME registers. Each time slot is approximately 0.5 ms. POR delay timing is programmed from 3 ms to 6 ms with 1 ms step. For an example power on and power off sequence, see Figure 5. This sequence only works at start- up by power on. (LSW_) VIN VIN UVLO release @ Vin=2.3V POR release @ Vout=2.8V(LSW_) VOUT Vin=2.9V (Vin spec min) 110us Tdelay = 3/4/5/6ms <1.5ms I(LSW) < Ilimit (>4A) TS01 (512us) TS02 (512us) LDO TS03 (512us) CH2 CH3 CH4 CH1 POR 1.8V 1.2V 1.2V/1.5V/1.8V 0.8V/1.2V 2.5V Ilmt_softstart (~0.1A) Disconnect Vin POR fall @ Vout=2.7V VIN UVLO fall @ Vin=2.2V OFF Figure 5: Power On and Off Sequence

6.2.2 Sleep Mode Enter and Exit Sequence

DA9083 enters Sleep mode immediately when SLEEP bit of PMC_SLEEP_REG0 register is asserted. All the buck converters and the LDO move to their SLEEP state according to CH<x>_ALIVE and LDO_ALIVE bits of PMC_SLEEP_REG0. Some of them are disabled and the others are in Low Power mode (LPM). DA9083 exits Sleep mode when SLEEP bit of PMC_SLEEP_REG0 register is negated. Wake -up delays of disabled buck converters and LDO are the same as power-on sequence. For an example sleep enter and exit sequence, see Figure 6. CH2 wakes up in TS02 and CH1 wakes up in TS03. Figure 6: Sleep Enter and Exit Sequence

6.3 Fault and Protection

Protection functions are triggered by fault events. The behavior depends on type of fault event, see Table 17. Table 17: Fault Events and Protection Functions Fault Events Shut-Down Blocks Recovery from Shut-Down Register OCP None N/A N/A POR (LSW VOUT) CH1-4 Buck, LDO Latch-off Keep OVP (Buck) CH1 Buck to CH4 Buck, LDO, LSW Latch-off Keep UVP (Buck and LDO) CH1 Buck to CH4 Buck, LDO, LSW Latch-off Keep (LSW_) VIN (LSW_) VOUT I(LSW) LDO CH2 CH3 CH4 CH1 POR Enter sleep Exit sleep 100us 1.8V 1.2V 1.2V/1.5V/1.8V 0.8V/1.2V 2.5V TS01 (512us) TS02 (512us) TS03 (512us) LPM LPM Disabled Disabled

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 23 of 63 © 2022 Renesas Electronics Fault Events Shut-Down Blocks Recovery from Shut-Down Register VIN OVP CH1 Buck to CH4 Buck, LDO, LSW Hiccup Keep VIN UVLO CH1 Block to CH4 Block, LDO, LSW Hiccup Reset TSD CH1 Block to CH4 Block, LDO, LSW Hiccup Keep As an OTP option, POR pin can be assigned as IRQ output. In this case, fault events such as over- current, over-voltage, under-voltage, and/or over-temperature can be set to trigger IRQ.

6.4 Buck Converters

DA9083 has four channels of switching buck converters, CH1 Buck to CH4 Buck. Each of the bucks has an I2C programable voltage register, PMC_CH<x>_SEL_REG, which defines the output voltage. When a buck is enabled, its output voltage gradually goes up with soft-start. When the buck output reaches the target voltage, Power Good condition is shown via the CH<x>_NT_UV_OV status bit in PMC_RAIL_STATUS_REG1 register. When the buck output drops below VTHR_UVP_FALL, the device sets the CH<x>_UV bit in the PMC_RAIL_STATUS_REG2 register to 0x1. When the buck output increases above VTHR_OVP_RISE the device sets the CH<x>_OV bit in the PMC_RAIL_STATUS_REG3 register to 0x1. The status of the Power Good indicator, for both a UVP event and an OVP event and for each of the buck converters, can be read back via I2C from the CH<x>_NT_UV_OV, CH<x>_UV, and CH<x>_OV bits. The Power Good status on each of buck converter is masked during the buck start-up period. The buck converters support DVC, with the following features: ■ When the value of the target voltage (PMC_CH<x>_SEL_REG) changes, the output voltage updates to the new target value. ■ The DVC controller operates in pulse width modulation (PWM) mode with synchronous rectification. During DVC operation the PMC_RAIL_STATUS_REG1 register remains at 0xFC to indicate a Power Good condition. ■ The slew rate of the DVC transition for each channel is programmed in bits CH<x>_TSTEP<1:0> in registers PMC_CH<x>_CFG_REG. Each of the bucks has current limit and its threshold is programable with CH<x>_ILMAX<1:0> and OTP option. A pull-down resistor for each channel is enabled when the channel is disabled. This feature can be disabled by setting register bits CH<x>_DIS to 0x0 (register PMC_DISCHARGE_REG0).

6.4.1 Buck Operation Mode

Buck operation modes are selected, via I2C, by bits CH<X>_ALIVE, LDO_ALIVE and SLEEP in the PMC_SLEEP_REG0 register. Operation mode of CH<X> during High Power mode is selected by CH<X>_PWM. See Table 18.

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 24 of 63 © 2022 Renesas Electronics Table 18: Buck Operation Mode Operation Mode Buck Mode Normal mode High Power mode (HPM) Auto mode Force PWM mode Low Power mode (LPM) Disable Sleep mode Low Power mode (LPM) Disable

6.5 LDO

DA9083 has one LDO. It has an I2C programable voltage register (PMC_LDO_SEL_REG) which defines the output voltage. It has soft-start function and its output voltage gradually increases when the LDO is enabled. When the output voltage reaches the target, a Power Good condition is shown via the LDO_NT_UV_OV status bit in the PMC_RAIL_STATUS_REG1 register. It indicates that the output voltage is higher than the under-voltage protection level (VTHR_UVP_FALL) and lower than the over- voltage protection threshold level (VTHR_OVP_RISE). When the output drops below VTHR_UVP_FALL, the device sets the LDO_UV bit in the PMC_RAIL_STATUS_REG2 register to 0x1. When the output exceeds VTHR_OVP_RISE, the device sets the LDO_OV bit in the PMC_RAIL_STATUS_REG3 register to 0x1. The status of the Power Good indicator, UVP event, and OVP event of the LDO can be read via I2C from the LDO_NT_UV_OV, LDO_UV, and LDO_OV bits respectively. The Power Good status on LDO is masked during the buck start-up period.

6.6 I2C Communication

DA9083 includes an I2C-compatible 2-wire serial interface to access the internal registers. Through the I2C interface, the host processor controls each channel and reads back system status. The DA9083 only operates as a slave device. For detailed information about each register, refer to Section 7 and Section 8. The host processor provides the serial clock at the SCL pin. DA9083 supports I2C Standard-mode at 100 kHz and Fast-mode at 400 kHz, see [1]. DA9083 SLAVE address is 0x1B. The I2C data pin, SDA, is open drain which allows multiple devices to share a communication line. All transmissions begin with a START condition issued from the Master while the bus is in an IDLE state (the bus is free). The START condition is initiated by a high to low transition on SDA while SCL is high. Alternately, a STOP condition is indicated by a low to high transition on SDA while SCL is high, see Figure 7. SDA SCL Data SDA must be stable during high part of clock SCL Data sampled on SCL rising edge and driven on SCL falling edge Start(S ) is SDA falling while SCL high Stop (P ) is SDA rising while SCL high Figure 7: I2C Start (S) and Stop (P)

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 26 of 63 © 2022 Renesas Electronics address is given with a write and Repeated START, consecutive addresses are read from the write address. SLAVEadr W AREGadr NADATAA P 7-bits 1-bit 8-bits 8-bits Master to Slave S Slave to Master S = START condition A = Acknowledge (low) P = STOP condition W = Write (low) Sr = Repeated START condition NA = No Acknowledge 8-bits MASTER Code = 0000 1XXX R = Read (Hgih) Sr R 7-bits 1-bit adr=REGadr A 8-bits8-bits Repeated reads adr=REGadr+1 adr=REGadr+2 SLAVEadr A DATA A DATA A Figure 11: Consecutive Read Command DA9083 also supports I2C High-Speed mode (HS-mode), which can transfer information at bit rates of up to 3.4 Mbit/s, see [1]. Operation in High Speed mode at 3.4 MHz requires a mode change to enable spike suppression and slope control characteristics compatible with the I2C-bus specification. High-Speed mode can be enabled on a transfer-by-transfer basis by sending the master code (0000 1XXX) at the beginning of the transfer. DA9083 does not make use of clock stretching and delivers read data without additional delay up to 3.4 MHz.

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 28 of 63 © 2022 Renesas Electronics The DA9083 also supports a multiple byte read protocol in High-Speed mode. If the host responds to the returned data with an Acknowledge rather than Not Acknowledge and STOP, data will be read from sequential addresses until a Not Acknowledge and STOP command is given, see Figure 15. If a read address is given with a write and Repeated START, consecutive addresses are read from the write address. SLAVEadr W AREGadr NADATAA P 7-bits 1-bit 8-bits 8-bits Master to Slave Sr Slave to Master S = START condition A = Acknowledge (low) P = STOP condition W = Write (low) Sr = Repeated START condition NA = No Acknowledge NAMASTER CodeS 1-bit8-bits 8-bits MASTER Code = 0000 1XXX R = Read (Hgih) Sr SLAVEadr R A 7-bits 1-bit adr=REGadr A DATA A DATA A 8-bits8-bits Repeated reads adr=REGadr+1 adr=REGadr+2 Figure 15: High-Speed Mode Consecutive Read Command

7 Register Definitions

7.1 Register Map

Addr Register 7 6 5 4 3 2 1 0 Reset Functional Registers PMIC Function Registers 0x0000 PMC_RAIL_STATUS_REG1 CH1_NT_UV_OV CH2_NT_UV_OV CH3_NT_UV_OV CH4_NT_UV_OV LDO_NT_UV_OV POR Reserved Reserved 0x00 0x0001 PMC_RAIL_STATUS_REG2 CH1_UV CH2_UV CH3_UV CH4_UV LDO_UV Reserved Reserved Reserved 0x00 0x0002 PMC_RAIL_STATUS_REG3 CH1_OV CH2_OV CH3_OV CH4_OV LDO_OV VIN_OV PMIC_OT Reserved 0x00 0x0003 PMC_CH1_CFG_REG CH1_ILMAX<1:0> CH1_TSTEP<1:0> CH1_FREQ<2:0> Reserved 0x6A 0x0005 PMC_CH2_CFG_REG CH2_ILMAX<1:0> CH2_TSTEP<1:0> CH2_FREQ<2:0> Reserved 0x6A 0x0007 PMC_CH3_CFG_REG CH3_ILMAX<1:0> CH3_TSTEP<1:0> CH3_FREQ<2:0> Reserved 0x6A 0x0009 PMC_CH4_CFG_REG CH4_ILMAX<1:0> CH4_TSTEP<1:0> CH4_FREQ<2:0> Reserved 0x6A 0x000B PMC_LDO_SEL_REG LDO_SEL<4:0> Reserved Reserved Reserved 0xA0 0x000F PMC_DCDCCTRL0_REG0 LSW_EN CH1_EN Reserved CH2_EN CH3_EN CH4_EN LDO_EN Reserved 0x00 0x0010 PMC_SLEEP_REG0 CH1_ALIVE Reserved CH2_ALIVE CH3_ALIVE CH4_ALIVE LDO_ALIVE Reserved SLEEP 0x1C 0x0011 PMC_DCDCCTRL1_REG CH1_PWM CH2_PWM CH3_PWM CH4_PWM Reserved Reserved Reserved Reserved 0x00 0x0012 PMC_DISCHARGE_REG0 CH1_DIS CH2_DIS CH3_DIS CH4_DIS LDO_DIS LSW_DIS Reserved Reserved 0xF8 0x0013 PMC_DCDCCTRL2_REG CH1_LPM Reserved CH2_LPM CH3_LPM CH4_LPM LDO_LPM Reserved Reserved 0x00 0x0014 PMC_CH1CH2_WAKEUP_TIME CH1_WAKEUP_TIME<3:0> CH2_WAKEUP_TIME<3:0> 0x32 0x0015 PMC_CH3CH4_WAKEUP_TIME CH3_WAKEUP_TIME<3:0> CH4_WAKEUP_TIME<3:0> 0x22 0x0016 PMC_LDO_WAKEUP_TIME LDO_WAKEUP_TIME<3:0> Reserved Reserved Reserved Reserved 0x10 0x001E PMC_VOUT_CH1 CH1_VOUT<7:0> 0x55 0x001F PMC_VOUT_CH2 CH2_VOUT<7:0> 0x6E 0x0020 PMC_VOUT_CH3 CH3_VOUT<7:0> 0x6E 0x0021 PMC_VOUT_CH4 CH4_VOUT<7:0> 0x46

8 Register Descriptions

8.1.1 PMIC Function Registers

Table 19: PMC_RAIL_STATUS_REG1 (0x0000) Bit Type Field Name Description Reset [7] R CH1_NT_UV_OV Status bit. Indicates UV/OV not triggered on CH1 Value Description 0x0 CH1 OV or UV triggered. 0x1 CH1 OV and UV not triggered. 0x0 [6] R CH2_NT_UV_OV Status bit. Indicates UV/OV not triggered on CH2 Value Description 0x0 CH2 OV or UV triggered. 0x1 CH2 OV and UV not triggered. 0x0 [5] R CH3_NT_UV_OV Status bit. Indicates UV/OV not triggered on CH3 Value Description 0x0 CH3 OV or UV triggered. 0x1 CH3 OV and UV not triggered. 0x0 [4] R CH4_NT_UV_OV Status bit. Indicates UV/OV not triggered on CH4 Value Description 0x0 CH4 OV or UV triggered. 0x1 CH4 OV and UV not triggered. 0x0 [3] R LDO_NT_UV_OV Status bit. Indicates UV/OV not triggered on LDO Value Description 0x0 LDO OV or UV triggered. 0x1 LDO OV and UV not triggered. 0x0 [2] R POR Status bit. Indicates POR pin output. Value Description 0x0 POR pin low 0x1 POR pin high 0x0 Table 20: PMC_RAIL_STATUS_REG2 (0x0001) Bit Type Field Name Description Reset [7] RW1C CH1_UV Status bit. Indicates UV on CH1 Value Description 0x0 CH1 UV not breached 0x1 CH1 UV breached 0x0

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 31 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset [6] RW1C CH2_UV Status bit. Indicates UV on CH2 Value Description 0x0 CH2 UV not breached 0x1 CH2 UV breached 0x0 [5] RW1C CH3_UV Status bit. Indicates UV on CH3 Value Description 0x0 CH3 UV not breached 0x1 CH3 UV breached 0x0 [4] RW1C CH4_UV Status bit. Indicates UV on CH4 Value Description 0x0 CH4 UV not breached 0x1 CH4 UV breached 0x0 [3] RW1C LDO_UV Status bit. Indicates UV on LDO Value Description 0x0 LDO UV not breached 0x1 LDO UV breached 0x0 Table 21: PMC_RAIL_STATUS_REG3 (0x0002) Bit Type Field Name Description Reset [7] RW1C CH1_OV Status bit. Indicates OV on CH1 Value Description 0x0 CH1 OV not breached 0x1 CH1 OV breached 0x0 [6] RW1C CH2_OV Status bit. Indicates OV on CH2 Value Description 0x0 CH2 OV not breached 0x1 CH2 OV breached 0x0 [5] RW1C CH3_OV Status bit. Indicates OV on CH3 Value Description 0x0 CH3 OV not breached 0x1 CH3 OV breached 0x0 [4] RW1C CH4_OV Status bit. Indicates OV on CH4 Value Description 0x0 CH4 OV not breached 0x1 CH4 OV breached 0x0

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 32 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset [3] RW1C LDO_OV Status bit. Indicates OV on LDO Value Description 0x0 LDO OV not breached 0x1 LDO OV breached 0x0 [2] RW1C VIN_OV Status bit. Indicates OV on VIN Value Description 0x0 VIN OV not breached 0x1 VIN OV breached 0x0 [1] RW1C PMIC_OT Status bit. Indicates OT on PMIC Value Description 0x0 PMIC OT not breached 0x1 PMIC OT breached 0x0 Table 22: PMC_CH1_CFG_REG (0x0003) Bit Type Field Name Description Reset [7:6] RW CH1_ILMAX CH1 ILMAX setting (A) Value Description 0x0 3.0 0x1 4.0 0x2 5.0 0x3 6.0 0x1 [5:4] RW CH1_TSTEP CH1 TSTEP setting Value Description 0x0 up: 20 mV/µs, down: 5m V/µs 0x1 up: 15 mV/µs, down: 5mV/µs 0x2 up: 10mV/µs, down: 5mV/µs 0x3 up: 5mV/µs, down: 5mV/µs 0x2 [3:1] RW CH1_FREQ CH1 FREQ is fixed to 2 MHz 0x5 Table 23: PMC_CH2_CFG_REG (0x0005) Bit Type Field Name Description Reset [7:6] RW CH2_ILMAX CH2 ILMAX setting (A) Value Description 0x0 3.0 0x1 4.0 0x2 5.0 0x3 6.0 0x1

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 33 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset [5:4] RW CH2_TSTEP CH2 TSTEP setting Value Description 0x0 up: 20 mV/µs, down: 5 mV/µs 0x1 up: 15mV/µs, down: 5mV/µs 0x2 up: 10mV/µs, down: 5mV/µs 0x3 up: 5mV/µs, down: 5mV/µs 0x2 [3:1] RW CH2_FREQ CH2 FREQ is fixed to 2 MHz 0x5 Table 24: PMC_CH3_CFG_REG (0x0007) Bit Type Field Name Description Reset [7:6] RW CH3_ILMAX CH3 ILMAX setting (A) Value Description 0x0 3.0 0x1 4.0 0x2 5.0 0x3 6.0 0x1 [5:4] RW CH3_TSTEP CH3 TSTEP setting Value Description 0x0 up: 20 mV/µs, down: 5 mV/µs 0x1 up: 15 mV/µs, down: 5 mV/µs 0x2 up: 10 mV/µs, down: 5 mV/µs 0x3 up: 5 mV/µs, down:5 mV/µs 0x2 [3:1] RW CH3_FREQ CH3 FREQ is fixed to 2 MHz 0x5 Table 25: PMC_CH4_CFG_REG (0x0009) Bit Type Field Name Description Reset [7:6] RW CH4_ILMAX CH4 ILMAX setting (A) Value Description 0x0 5.5 0x1 7.0 0x2 8.5 0x3 10.0 0x1 [5:4] RW CH4_TSTEP CH4 TSTEP setting Value Description 0x0 up: 20 mV/µs, down: 5 mV/µs 0x1 up: 15 mV/µs, down: 5 mV/µs 0x2 up: 10 mV/µs, down: 5 mV/µs 0x3 up: 5 mV/µs, down: 5 mV/µs 0x2

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 34 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset [3:1] RW CH4_FREQ CH4 FREQ is fixed to 2 MHz 0x5 Table 26: PMC_LDO_SEL_REG (0x000B) Bit Type Field Name Description Reset [7:3] RW LDO_SEL LDO output voltage (V). Value Description 0x00 1.40 0x01 1.42 0x02 1.44 0x03 1.46 0x04 1.48 0x05 1.50 0x06 1.52 0x07 1.54 0x08 1.56 0x09 1.58 0x0A 1.60 0x0B 1.62 0x0C 1.64 0x0D 1.66 0x0E 1.68 0x0F 1.70 0x10 1.72 0x11 1.74 0x12 1.76 0x13 1.78 0x14 1.80 0x15 1.82 0x16 1.84 0x17 1.86 0x18 1.88 0x19 1.90 0x1A 1.90 0x1F 1.90 0x14

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 35 of 63 © 2022 Renesas Electronics Table 27: PMC_DCDCCTRL0_REG0 (0x000F) Bit Type Field Name Description Reset [7] RW LSW_EN LSW enable Value Description 0x0 Disable 0x1 Enable 0x0 [6] RW CH1_EN CH1 Buck enable Value Description 0x0 Disable 0x1 Enable 0x0 [4] RW CH2_EN CH2 Buck enable Value Description 0x0 Disable 0x1 Enable 0x0 [3] RW CH3_EN CH3 Buck enable Value Description 0x0 Disable 0x1 Enable 0x0 [2] RW CH4_EN CH4 Buck enable Value Description 0x0 Disable 0x1 Enable 0x0 [1] RW LDO_EN LDO enable Value Description 0x0 Disable 0x1 Enable 0x0 Table 28: PMC_SLEEP_REG0 (0x0010) Bit Type Field Name Description Reset [7] RW CH1_ALIVE Set CH1 Buck operation during sleep. Value Description 0x0 When Sleep, CH1 turn off 0x1 When Sleep, CH1 alive and enter LPM 0x0 [5] RW CH2_ALIVE Set CH2 Buck operation during sleep. Value Description 0x0 When Sleep, CH2 turn off 0x1 When Sleep, CH2 alive and enter LPM 0x0

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 36 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset [4] RW CH3_ALIVE Set CH3 Buck operation during sleep. Value Description 0x0 When Sleep, CH3 turn off 0x1 When Sleep, CH3 alive and enter LPM 0x1 [3] RW CH4_ALIVE Set CH4 Buck operation during sleep. Value Description 0x0 When Sleep, CH4 turn off 0x1 When Sleep, CH4 alive and enter LPM 0x1 [2] RW LDO_ALIVE Set LDO operation during sleep. Value Description 0x0 When Sleep, LDO turn off 0x1 When Sleep, LDO alive and enter LPM 0x1 [0] RW SLEEP Sleep mode setting Value Description 0x0 Exit Sleep mode 0x1 Enter Sleep mode 0x0 Table 29: PMC_DCDCCTRL1_REG (0x0011) Bit Type Field Name Description Reset [7] RW CH1_PWM CH1 operation mode while not in LPM Value Description 0x0 Auto mode 0x1 Forced PWM mode 0x0 [6] RW CH2_PWM CH2 operation mode while not in LPM Value Description 0x0 Auto mode 0x1 Forced PWM mode 0x0 [5] RW CH3_PWM CH3 operation mode while not in LPM Value Description 0x0 Auto mode 0x1 Forced PWM mode 0x0 [4] RW CH4_PWM CH4 operation mode while not in LPM Value Description 0x0 Auto mode 0x1 Forced PWM mode 0x0

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 37 of 63 © 2022 Renesas Electronics Table 30: PMC_DISCHARGE_REG0 (0x0012) Bit Type Field Name Description Reset [7] RW CH1_DIS Enable discharge of CH1 output while channel is disabled Value Description 0x0 Discharge disabled 0x1 Discharge enabled 0x1 [6] RW CH2_DIS Enable discharge of CH2 output while channel is disabled Value Description 0x0 Discharge disabled 0x1 Discharge enabled 0x1 [5] RW CH3_DIS Enable discharge of CH3 output while channel is disabled Value Description 0x0 Discharge disabled 0x1 Discharge enabled 0x1 [4] RW CH4_DIS Enable discharge of CH4 output while channel is disabled Value Description 0x0 Discharge disabled 0x1 Discharge enabled 0x1 [3] RW LDO_DIS Enable discharge of LDO output while channel is disabled Value Description 0x0 Discharge disabled 0x1 Discharge enabled 0x1 [2] RW LSW_DIS Enable discharge of LSW output while channel is disabled Value Description 0x0 Discharge disabled 0x1 Discharge enabled 0x0 Table 31: PMC_DCDCCTRL2_REG (0x0013) Bit Type Field Name Description Reset [7] RW CH1_LPM CH1 Buck LPM mode Value Description 0x0 High Power mode 0x1 Low Power mode 0x0

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 38 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset [5] RW CH2_LPM CH2 Buck LPM mode Value Description 0x0 High Power mode 0x1 Low Power mode 0x0 [4] RW CH3_LPM CH3 Buck LPM mode Value Description 0x0 High Power mode 0x1 Low Power mode 0x0 [3] RW CH4_LPM CH4 Buck LPM mode Value Description 0x0 High Power mode 0x1 Low Power mode 0x0 [2] RW LDO_LPM LDO Buck LPM mode Value Description 0x0 High Power mode 0x1 Low Power mode 0x0 Table 32: PMC_CH1CH2_WAKEUP_TIME (0x0014) Bit Type Field Name Description Reset [7:4] RW CH1_WAKEUP_TIME The duration between wake-up signal and a rail rising edge, tWAKE_UP_DELAY = 150 µs + (N-1) * 512 µs Value Description 0x0 Disable wake-up 0x1 Time slot 1 0x2 Time slot 2 0x3 Time slot 3 0x4 Time slot 4 0x5 Time slot 5 0x6 Time slot 6 0x7 Time slot 7 0x8 Time slot 8 0x9 Time slot 9 0xA Time slot 10 0xB Time slot 11 0xC Time slot 12 0xD Time slot 13 0xE Time slot 14 0xF Time slot 15 0x3

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 39 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset [3:0] RW CH2_WAKEUP_TIME The duration between wake-up signal and a rail rising edge, tWAKE_UP_DELAY = 150µs + (N-1) * 512 µs Value Description 0x0 Disable wake-up 0x1 Time slot 1 0x2 Time slot 2 0x3 Time slot 3 0x4 Time slot 4 0x5 Time slot 5 0x6 Time slot 6 0x7 Time slot 7 0x8 Time slot 8 0x9 Time slot 9 0xA Time slot 10 0xB Time slot 11 0xC Time slot 12 0xD Time slot 13 0xE Time slot 14 0xF Time slot 15 0x2 Table 33: PMC_CH3CH4_WAKEUP_TIME (0x0015) Bit Type Field Name Description Reset [7:4] RW CH3_WAKEUP_TIME The duration between wake-up signal and a rail rising edge, tWAKE_UP_DELAY = 150 µs + (N-1) * 512 µs Value Description 0x0 Disable wake-up 0x1 Time slot 1 0x2 Time slot 2 0x3 Time slot 3 0x4 Time slot 4 0x5 Time slot 5 0x6 Time slot 6 0x7 Time slot 7 0x8 Time slot 8 0x9 Time slot 9 0xA Time slot 10 0xB Time slot 11 0x2

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 40 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0xC Time slot 12 0xD Time slot 13 0xE Time slot 14 0xF Time slot 15 [3:0] RW CH4_WAKEUP_TIME The duration between wake-up signal and a rail rising edge, tWAKE_UP_DELAY = 150 µs + (N-1) * 512 µs Value Description 0x0 Disable wake-up 0x1 Time slot 1 0x2 Time slot 2 0x3 Time slot 3 0x4 Time slot 4 0x5 Time slot 5 0x6 Time slot 6 0x7 Time slot 7 0x8 Time slot 8 0x9 Time slot 9 0xA Time slot 10 0xB Time slot 11 0xC Time slot 12 0xD Time slot 13 0xE Time slot 14 0xF Time slot 15 0x2

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 41 of 63 © 2022 Renesas Electronics Table 34: PMC_LDO_WAKEUP_TIME (0x0016) Bit Type Field Name Description Reset [7:4] RW LDO_WAKEUP_TIME The duration between wake-up signal and a rail rising edge, tWAKE_UP_DELAY = 150 µs + (N-1) * 512 µs Value Description 0x0 Disable wake-up 0x1 Time slot 1 0x2 Time slot 2 0x3 Time slot 3 0x4 Time slot 4 0x5 Time slot 5 0x6 Time slot 6 0x7 Time slot 7 0x8 Time slot 8 0x9 Time slot 9 0xA Time slot 10 0xB Time slot 11 0xC Time slot 12 0xD Time slot 13 0xE Time slot 14 0xF Time slot 15 0x1 Table 35: PMC_VOUT_CH1 (0x001E) Bit Type Field Name Description Reset [7:0] RW CH1_VOUT CH1 output voltage (V). Format is (without divider)/(with divider). Default selectable by VSEL. Value Description 0x00 Reserved 0x32 0.50/Reserved 0x33 0.51/Reserved 0x34 0.52/Reserved 0x35 0.53/Reserved 0x36 0.54/Reserved 0x37 0.55/Reserved 0x38 0.56/Reserved 0x39 0.57/Reserved 0x3A 0.58/Reserved 0x3B 0.59/Reserved 0x55

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 42 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0x3C 0.60/Reserved 0x3D 0.61/Reserved 0x3E 0.62/Reserved 0x3F 0.63/Reserved 0x40 0.64/Reserved 0x41 0.65/Reserved 0x42 0.66/Reserved 0x43 0.67/Reserved 0x44 0.68/Reserved 0x45 0.69/Reserved 0x46 0.70/Reserved 0x47 0.71/Reserved 0x48 0.72/Reserved 0x49 0.73/Reserved 0x4A 0.74/Reserved 0x4B 0.75/1.50 0x4C 0.76/1.52 0x4D 0.77/1.54 0x4E 0.78/1.56 0x4F 0.79/1.58 0x50 0.80/1.60 0x51 0.81/1.62 0x52 0.82/1.64 0x53 0.83/1.66 0x54 0.84/1.68 0x55 0.85/1.70 0x56 0.86/1.72 0x57 0.87/1.74 0x58 0.88/1.76 0x59 0.89/1.78 0x5A 0.90/1.80 0x5B 0.91/1.82 0x5C 0.92/1.84 0x5D 0.93/1.86 0x5E 0.94/1.88 0x5F 0.95/1.90 0x60 0.96/1.92

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 43 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0x61 0.97/1.94 0x62 0.98/1.96 0x63 0.99/1.98 0x64 1.00/2.00 0x65 1.01/2.02 0x66 1.02/2.04 0x67 1.03/2.06 0x68 1.04/2.08 0x69 1.05/2.10 0x6A 1.06/2.12 0x6B 1.07/2.14 0x6C 1.08/2.16 0x6D 1.09/2.18 0x6E 1.10/2.20 0x6F 1.11/2.22 0x70 1.12/2.24 0x71 1.13/2.26 0x72 1.14/2.28 0x73 1.15/2.30 0x74 1.16/2.32 0x75 1.17/2.34 0x76 1.18/2.36 0x77 1.19/2.38 0x78 1.20/2.40 0x79 1.21/2.42 0x7A 1.22/2.44 0x7B 1.23/2.46 0x7C 1.24/2.48 0x7D 1.25/2.50 0x7E 1.26/2.52 0x7F 1.27/2.54 0x80 1.28/2.56 0x81 1.29/2.58 0x82 1.30/2.60 0x83 1.31/2.62 0x84 1.32/2.64 0x85 1.33/2.66

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 44 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0x86 1.34/2.68 0x87 1.35/2.70 0x88 1.36/Reserved 0x89 1.37/Reserved 0x8A 1.38/Reserved 0x8B 1.39/Reserved 0x8C 1.40/Reserved 0x8D 1.41/Reserved 0x8E 1.42/Reserved 0x8F 1.43/Reserved 0x90 1.44/Reserved 0x91 1.45/Reserved 0x92 1.46/Reserved 0x93 1.47/Reserved 0x94 1.48/Reserved 0x95 1.49/Reserved 0x96 1.50/Reserved 0x97 1.51/Reserved 0x98 1.52/Reserved 0x99 1.53/Reserved 0x9A 1.54/Reserved 0x9B 1.55/Reserved 0x9C 1.56/Reserved 0x9D 1.57/Reserved 0x9E 1.58/Reserved 0x9F 1.59/Reserved 0xA0 1.60/Reserved 0xA1 1.61/Reserved 0xA2 1.62/Reserved 0xA3 1.63/Reserved 0xA4 1.64/Reserved 0xA5 1.65/Reserved 0xA6 1.66/Reserved 0xA7 1.67/Reserved 0xA8 1.68/Reserved 0xA9 1.69/Reserved 0xAA 1.70/Reserved

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 45 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0xAB 1.71/Reserved 0xAC 1.72/Reserved 0xAD 1.73/Reserved 0xAE 1.74/Reserved 0xAF 1.75/Reserved 0xB0 1.76/Reserved 0xB1 1.77/Reserved 0xB2 1.78/Reserved 0xB3 1.79/Reserved 0xB4 1.80/Reserved 0xB5 1.81/Reserved 0xB6 1.82/Reserved 0xB7 1.83/Reserved 0xB8 1.84/Reserved 0xB9 1.85/Reserved 0xBA 1.86/Reserved 0xBB 1.87/Reserved 0xBC 1.88/Reserved 0xBD 1.89/Reserved 0xBE 1.90/Reserved 0xBF Reserved 0xFF Reserved Table 36: PMC_VOUT_CH2 (0x001F) Bit Type Field Name Description Reset [7:0] RW CH2_VOUT CH2 output voltage (V). Format is (without divider)/(with divider). Default selectable by VSEL. Value Description 0x00 Reserved 0x36 Reserved 0x37 0.55/Reserved 0x38 0.56/Reserved 0x39 0.57/Reserved 0x3A 0.58/Reserved 0x3B 0.59/Reserved 0x3C 0.60/Reserved 0x3D 0.61/Reserved 0x6E

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 46 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0x3E 0.62/Reserved 0x3F 0.63/Reserved 0x40 0.64/Reserved 0x41 0.65/Reserved 0x42 0.66/Reserved 0x43 0.67/Reserved 0x44 0.68/Reserved 0x45 0.69/Reserved 0x46 0.70/Reserved 0x47 0.71/Reserved 0x48 0.72/Reserved 0x49 0.73/Reserved 0x4A 0.74/Reserved 0x4B 0.75/1.50 0x4C 0.76/1.52 0x4D 0.77/1.54 0x4E 0.78/1.56 0x4F 0.79/1.58 0x50 0.80/1.60 0x51 0.81/1.62 0x52 0.82/1.64 0x53 0.83/1.66 0x54 0.84/1.68 0x55 0.85/1.70 0x56 0.86/1.72 0x57 0.87/1.74 0x58 0.88/1.76 0x59 0.89/1.78 0x5A 0.90/1.80 0x5B 0.91/1.82 0x5C 0.92/1.84 0x5D 0.93/1.86 0x5E 0.94/1.88 0x5F 0.95/1.90 0x60 0.96/1.92 0x61 0.97/1.94 0x62 0.98/1.96

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 47 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0x63 0.99/1.98 0x64 1.00/2.00 0x65 1.01/2.02 0x66 1.02/2.04 0x67 1.03/2.06 0x68 1.04/2.08 0x69 1.05/2.10 0x6A 1.06/2.12 0x6B 1.07/2.14 0x6C 1.08/2.16 0x6D 1.09/2.18 0x6E 1.10/2.20 0x6F 1.11/2.22 0x70 1.12/2.24 0x71 1.13/2.26 0x72 1.14/2.28 0x73 1.15/2.30 0x74 1.16/2.32 0x75 1.17/2.34 0x76 1.18/2.36 0x77 1.19/2.38 0x78 1.20/2.40 0x79 1.21/2.42 0x7A 1.22/2.44 0x7B 1.23/2.46 0x7C 1.24/2.48 0x7D 1.25/2.50 0x7E 1.26/2.52 0x7F 1.27/2.54 0x80 1.28/2.56 0x81 1.29/2.58 0x82 1.30/2.60 0x83 1.31/2.62 0x84 1.32/2.64 0x85 1.33/2.66 0x86 1.34/2.68 0x87 1.35/2.70

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 48 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0x88 1.36/Reserved 0x89 1.37/Reserved 0x8A 1.38/Reserved 0x8B 1.39/Reserved 0x8C 1.40/Reserved 0x8D 1.41/Reserved 0x8E 1.42/Reserved 0x8F 1.43/Reserved 0x90 1.44/Reserved 0x91 1.45/Reserved 0x92 1.46/Reserved 0x93 1.47/Reserved 0x94 1.48/Reserved 0x95 1.49/Reserved 0x96 1.50/Reserved 0x97 1.51/Reserved 0x98 1.52/Reserved 0x99 1.53/Reserved 0x9A 1.54/Reserved 0x9B 1.55/Reserved 0x9C 1.56/Reserved 0x9D 1.57/Reserved 0x9E 1.58/Reserved 0x9F 1.59/Reserved 0xA0 1.60/Reserved 0xA1 1.61/Reserved 0xA2 1.62/Reserved 0xA3 1.63/Reserved 0xA4 1.64/Reserved 0xA5 1.65/Reserved 0xA6 1.66/Reserved 0xA7 1.67/Reserved 0xA8 1.68/Reserved 0xA9 1.69/Reserved 0xAA 1.70/Reserved 0xAB 1.71/Reserved 0xAC 1.72/Reserved

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 49 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0xAD 1.73/Reserved 0xAE 1.74/Reserved 0xAF 1.75/Reserved 0xB0 1.76/Reserved 0xB1 1.77/Reserved 0xB2 1.78/Reserved 0xB3 1.79/Reserved 0xB4 1.80/Reserved 0xB5 1.81/Reserved 0xB6 1.82/Reserved 0xB7 1.83/Reserved 0xB8 1.84/Reserved 0xB9 1.85/Reserved 0xBA 1.86/Reserved 0xBB 1.87/Reserved 0xBC 1.88/Reserved 0xBD 1.89/Reserved 0xBE 1.90/Reserved 0xBF Reserved 0xFF Reserved Table 37: PMC_VOUT_CH3 (0x0020) Bit Type Field Name Description Reset [7:0] RW CH3_VOUT CH3 output voltage (V). Format is (without divider)/(with divider). Default selectable by VSEL. Value Description 0x00 Reserved 0x36 Reserved 0x37 0.55/Reserved 0x38 0.56/Reserved 0x39 0.57/Reserved 0x3A 0.58/Reserved 0x3B 0.59/Reserved 0x3C 0.60/Reserved 0x3D 0.61/Reserved 0x3E 0.62/Reserved 0x3F 0.63/Reserved 0x6E

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 50 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0x40 0.64/Reserved 0x41 0.65/Reserved 0x42 0.66/Reserved 0x43 0.67/Reserved 0x44 0.68/Reserved 0x45 0.69/Reserved 0x46 0.70/Reserved 0x47 0.71/Reserved 0x48 0.72/Reserved 0x49 0.73/Reserved 0x4A 0.74/Reserved 0x4B 0.75/1.50 0x4C 0.76/1.52 0x4D 0.77/1.54 0x4E 0.78/1.56 0x4F 0.79/1.58 0x50 0.80/1.60 0x51 0.81/1.62 0x52 0.82/1.64 0x53 0.83/1.66 0x54 0.84/1.68 0x55 0.85/1.70 0x56 0.86/1.72 0x57 0.87/1.74 0x58 0.88/1.76 0x59 0.89/1.78 0x5A 0.90/1.80 0x5B 0.91/1.82 0x5C 0.92/1.84 0x5D 0.93/1.86 0x5E 0.94/1.88 0x5F 0.95/1.90 0x60 0.96/1.92 0x61 0.97/1.94 0x62 0.98/1.96 0x63 0.99/1.98 0x64 1.00/2.00

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 51 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0x65 1.01/2.02 0x66 1.02/2.04 0x67 1.03/2.06 0x68 1.04/2.08 0x69 1.05/2.10 0x6A 1.06/2.12 0x6B 1.07/2.14 0x6C 1.08/2.16 0x6D 1.09/2.18 0x6E 1.10/2.20 0x6F 1.11/2.22 0x70 1.12/2.24 0x71 1.13/2.26 0x72 1.14/2.28 0x73 1.15/2.30 0x74 1.16/2.32 0x75 1.17/2.34 0x76 1.18/2.36 0x77 1.19/2.38 0x78 1.20/2.40 0x79 1.21/2.42 0x7A 1.22/2.44 0x7B 1.23/2.46 0x7C 1.24/2.48 0x7D 1.25/2.50 0x7E 1.26/2.52 0x7F 1.27/2.54 0x80 1.28/2.56 0x81 1.29/2.58 0x82 1.30/2.60 0x83 1.31/2.62 0x84 1.32/2.64 0x85 1.33/2.66 0x86 1.34/2.68 0x87 1.35/2.70 0x88 1.36/Reserved 0x89 1.37/Reserved

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 52 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0x8A 1.38/Reserved 0x8B 1.39/Reserved 0x8C 1.40/Reserved 0x8D 1.41/Reserved 0x8E 1.42/Reserved 0x8F 1.43/Reserved 0x90 1.44/Reserved 0x91 1.45/Reserved 0x92 1.46/Reserved 0x93 1.47/Reserved 0x94 1.48/Reserved 0x95 1.49/Reserved 0x96 1.50/Reserved 0x97 1.51/Reserved 0x98 1.52/Reserved 0x99 1.53/Reserved 0x9A 1.54/Reserved 0x9B 1.55/Reserved 0x9C 1.56/Reserved 0x9D 1.57/Reserved 0x9E 1.58/Reserved 0x9F 1.59/Reserved 0xA0 1.60/Reserved 0xA1 1.61/Reserved 0xA2 1.62/Reserved 0xA3 1.63/Reserved 0xA4 1.64/Reserved 0xA5 1.65/Reserved 0xA6 1.66/Reserved 0xA7 1.67/Reserved 0xA8 1.68/Reserved 0xA9 1.69/Reserved 0xAA 1.70/Reserved 0xAB 1.71/Reserved 0xAC 1.72/Reserved 0xAD 1.73/Reserved 0xAE 1.74/Reserved

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 53 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0xAF 1.75/Reserved 0xB0 1.76/Reserved 0xB1 1.77/Reserved 0xB2 1.78/Reserved 0xB3 1.79/Reserved 0xB4 1.80/Reserved 0xB5 1.81/Reserved 0xB6 1.82/Reserved 0xB7 1.83/Reserved 0xB8 1.84/Reserved 0xB9 1.85/Reserved 0xBA 1.86/Reserved 0xBB 1.87/Reserved 0xBC 1.88/Reserved 0xBD 1.89/Reserved 0xBE 1.90/Reserved 0xBF Reserved 0xFF Reserved Table 38: PMC_VOUT_CH4 (0x0021) Bit Type Field Name Description Reset [7:0] RW CH4_VOUT CH4 output voltage (V). Format is (without divider)/(with divider). Default selectable by VSEL. Value Description 0x00 Reserved 0x36 Reserved 0x37 0.55/Reserved 0x38 0.56/Reserved 0x39 0.57/Reserved 0x3A 0.58/Reserved 0x3B 0.59/Reserved 0x3C 0.60/Reserved 0x3D 0.61/Reserved 0x3E 0.62/Reserved 0x3F 0.63/Reserved 0x40 0.64/Reserved 0x41 0.65/Reserved 0x46

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 54 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0x42 0.66/Reserved 0x43 0.67/Reserved 0x44 0.68/Reserved 0x45 0.69/Reserved 0x46 0.70/Reserved 0x47 0.71/Reserved 0x48 0.72/Reserved 0x49 0.73/Reserved 0x4A 0.74/Reserved 0x4B 0.75/1.50 0x4C 0.76/1.52 0x4D 0.77/1.54 0x4E 0.78/1.56 0x4F 0.79/1.58 0x50 0.80/1.60 0x51 0.81/1.62 0x52 0.82/1.64 0x53 0.83/1.66 0x54 0.84/1.68 0x55 0.85/1.70 0x56 0.86/1.72 0x57 0.87/1.74 0x58 0.88/1.76 0x59 0.89/1.78 0x5A 0.90/1.80 0x5B 0.91/1.82 0x5C 0.92/1.84 0x5D 0.93/1.86 0x5E 0.94/1.88 0x5F 0.95/1.90 0x60 0.96/1.92 0x61 0.97/1.94 0x62 0.98/1.96 0x63 0.99/1.98 0x64 1.00/2.00 0x65 1.01/2.02 0x66 1.02/2.04

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 55 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0x67 1.03/2.06 0x68 1.04/2.08 0x69 1.05/2.10 0x6A 1.06/2.12 0x6B 1.07/2.14 0x6C 1.08/2.16 0x6D 1.09/2.18 0x6E 1.10/2.20 0x6F 1.11/2.22 0x70 1.12/2.24 0x71 1.13/2.26 0x72 1.14/2.28 0x73 1.15/2.30 0x74 1.16/2.32 0x75 1.17/2.34 0x76 1.18/2.36 0x77 1.19/2.38 0x78 1.20/2.40 0x79 1.21/2.42 0x7A 1.22/2.44 0x7B 1.23/2.46 0x7C 1.24/2.48 0x7D 1.25/2.50 0x7E 1.26/2.52 0x7F 1.27/2.54 0x80 1.28/2.56 0x81 1.29/2.58 0x82 1.30/2.60 0x83 1.31/2.62 0x84 1.32/2.64 0x85 1.33/2.66 0x86 1.34/2.68 0x87 1.35/2.70 0x88 1.36/Reserved 0x89 1.37/Reserved 0x8A 1.38/Reserved 0x8B 1.39/Reserved

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 56 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0x8C 1.40/Reserved 0x8D 1.41/Reserved 0x8E 1.42/Reserved 0x8F 1.43/Reserved 0x90 1.44/Reserved 0x91 1.45/Reserved 0x92 1.46/Reserved 0x93 1.47/Reserved 0x94 1.48/Reserved 0x95 1.49/Reserved 0x96 1.50/Reserved 0x97 1.51/Reserved 0x98 1.52/Reserved 0x99 1.53/Reserved 0x9A 1.54/Reserved 0x9B 1.55/Reserved 0x9C 1.56/Reserved 0x9D 1.57/Reserved 0x9E 1.58/Reserved 0x9F 1.59/Reserved 0xA0 1.60/Reserved 0xA1 1.61/Reserved 0xA2 1.62/Reserved 0xA3 1.63/Reserved 0xA4 1.64/Reserved 0xA5 1.65/Reserved 0xA6 1.66/Reserved 0xA7 1.67/Reserved 0xA8 1.68/Reserved 0xA9 1.69/Reserved 0xAA 1.70/Reserved 0xAB 1.71/Reserved 0xAC 1.72/Reserved 0xAD 1.73/Reserved 0xAE 1.74/Reserved 0xAF 1.75/Reserved 0xB0 1.76/Reserved

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 57 of 63 © 2022 Renesas Electronics Bit Type Field Name Description Reset 0xB1 1.77/Reserved 0xB2 1.78/Reserved 0xB3 1.79/Reserved 0xB4 1.80/Reserved 0xB5 1.81/Reserved 0xB6 1.82/Reserved 0xB7 1.83/Reserved 0xB8 1.84/Reserved 0xB9 1.85/Reserved 0xBA 1.86/Reserved 0xBB 1.87/Reserved 0xBC 1.88/Reserved 0xBD 1.89/Reserved 0xBE 1.90/Reserved 0xBF Reserved 0xFF Reserved

9 Package Information

Figure 16: Package Outline Diagram

9.1 Moisture Sensitivity Level

The Moisture Sensitivity Level (MSL) is an indicator for the maximum allowable time period (floor lifetime) in which a moisture sensitive plastic device, once removed from the dry bag, can be exposed to an environment with a specified maximum temperature and a maximum relative humidity before the solder reflow process. The MSL classification is defined in Table 39. For detailed information on MSL levels refer to the IPC/JEDEC standard J-STD-020, which can be downloaded from http://www.jedec.org. The package is qualified for MSL 1. Table 39: MSL Classification MSL Level Floor Lifetime Conditions MSL 4 72 hours 30 °C / 60 % RH MSL 3 168 hours 30 °C / 60 % RH MSL 2A 4 weeks 30 °C / 60 % RH MSL 2 1 year 30 °C / 60 % RH MSL 1 Unlimited 30 °C / 85 % RH

9.2 WLCSP Handling

Manual handling of WLCSP packages should be reduced to the absolute minimum. In cases where it is still necessary, a vacuum pick-up tool should be used. In extreme cases plastic tweezers could be used, but metal tweezers are not acceptable, since contact may easily damage th e silicon chip. Removal of a WLCSP package will cause damage to the solder balls. Therefore a removed sample cannot be reused. WLCSP packages are sensitive to visible and infrared light. Precautions should be taken to properly shield the chip in the final product.

9.3 Soldering Information

Refer to the IPC/JEDEC standard J-STD-020 for relevant soldering information. This document can be downloaded from http://www.jedec.org.

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 60 of 63 © 2022 Renesas Electronics The ordering number consists of the part number followed by a suffix indicating the packing method. For details and availability, please consult Dialog Semiconductor’s customer support portal or your local sales representative. Table 40: Ordering Information Part Number (Note 1) Package Size (mm) Shipment Form Pack Quantity DA9083-xxUUA2 36 WLCSP 2.5 x 2.5 T&R 6000 DA9083-xxUUA6 36 WLCSP 2.5 x 2.5 Waffle Tray 500 Note 1 xx repesents the OTP variant.

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 61 of 63 © 2022 Renesas Electronics Load SwitchVIN AGND PVIN1 VOUT1 LX1 PGND1 FB1 CH1 Buck CVOUT1 CPVIN1 LOUT1 PVIN4 Vout4LX4 PGND4 FB4 CH4 Buck Cvout4 CPVIN4 LOUT4 PVIN2 VOUT2 Lx2 PGND2 FB2 CH2 Buck CVOUT2 CPVIN2 LOUT2 PVIN3 VOUT3 LX3 PGND3 FB3 CH3 Buck Cvout3 CPVIN3 LOUT3 VOUT CVIN CVOUT VOUT VOUT VOUT VOUT VOUT TSD Control Logic SDA SCL POR VSEL CH1SEL LDOOUT LDOIN LDOOUT CLDOUT VOUT LDO CLDOIN Figure 17: Applications Diagram

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 62 of 63 © 2022 Renesas Electronics Status Definitions Revision Datasheet Status Product Status Definition 1.<n> Target Development This datasheet contains the design specifications for product development. Specifications may be changed in any manner without notice. 2.<n> Preliminary Qualification This datasheet contains the specifications and preliminary characterization data for products in pre-production. Specifications may be changed at any time without notice in order to improve the design. 3.<n> Final Production This datasheet contains the final specifications for products in volume production. The specifications may be changed at any time in order to improve the design, manufacturing and supply. Major specification changes are communicated via Customer Product Notifications. Datasheet changes are communicated via www.dialog-semiconductor.com. 4.<n> Obsolete Archived This datasheet contains the specifications for discontinued products. The information is provided for reference only. RoHS Compliance Dialog Semiconductor’s suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certifi cates from our suppliers are available on request.

High Current, Highly Configurable System PMIC Datasheet Revision 3.2 18-Mar-2022 CFR0011-120-00 63 of 63 © 2022 Renesas Electronics Important Notice and Disclaimer RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OT HER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERT Y RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible fo r (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, a nd (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without no tice. Renesas grants you permission to use these resources only for development of an applic ation that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third part y intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Con ditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. © 2022 Renesas Electronics Corporation. All rights reserved. Corporate Headquarters TOYOSU FORESIA, 3-2-24 Toyosu Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: https://www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. (Rev.1.0 Mar 2020)

Product Information

DA9083 specifications and overview.

Summary

High Current, Highly Configurable System PMIC 18-Mar-2022

Description

High Current, Highly Configurable System PMIC 18-Mar-2022

Source title DA9083 Datasheet(PDF) - Renesas Technology Corp

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