DA9080-XXFCBC

DA9080_V01 RENESAS | Alldatasheet

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Technical content

High Current, Highly Configurable System PMIC with Four Bucks and One LDO R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 1 © 2025 Renesas Electronics DA9080 is a five-channel advanced, configurable, system power management IC (PMIC) with four buck regulators and one LDO. This highly integrated, flexible PMIC is capable of up to 10 A of output current. The output voltage of the regulators can be programmed and sequenced based on the application needs. The also integrates an 8-bit ADC, along with several other features that simplifies overall system design. Dynamic voltage control (DVC), robust protection features, and a dedicated I2C interface that supports multiple modes extend the applicability of this device to a wide range of end applications. The high-efficiency, fast transient response, and small footprint of the DA9080 lends itself to become the preferred power solution for a host of complex, high-performance applications. The DA9080 is offered in a FCQFN package. Key Features ▪ Power supply voltage (VIN) 4.0 V to 5.5 V ▪ Four buck converters ▪ Selectable output voltage range for bucks:

• CH1 Buck: 2.1 V to 3.3 V, 20 mV step
• CH2 Buck: 1.5 V to 2.6 V, 20 mV step
• CH3 Buck: 0.9 V to 1.3 V, 5 mV step (supports 1.35 V and 1.8 V)
• CH4 Buck: 0.8 V to 1.4 V, 5 mV step ▪ Maximum output current:
• CH1, CH2, and CH3 Buck: 1.5 A
• CH4 Buck: 5.0 A ▪ Interleaving of switching phases of bucks ▪ LDO:
• VOUT: 3.3 V, IOUT: 0.2 A (max) ▪ General purpose ADC:
• 8-bit SAR ADC
• Two external inputs
• Die temperature sense ▪ Protection functions:
• Over-current protection
• Over/under-voltage protection
• Thermal shutdown protection ▪ I2C control interface:
• Standard mode (100 kbit/s)
• Fast mode (400 kbit/s)
• Fast mode+ (1 Mbit/s) ▪ Package: 32 lead FCQFN, 5.0 mm x 5.0 mm

Applications

▪ Client and Enterprise SSD modules ▪ Embedded Computing ▪ Integrated Microcontroller of Internet of Things ▪ DSPs or FPGAs with Peripherals

Figure 1. System Diagram

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 3

Contents

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 7 1. Terms and Definitions ADC Analog to digital converter CH<x> Channel <x>, where x = 1 to 4 DVC Dynamic voltage control ESD Electrostatic discharge FCQFN Flip chip quad flat-pack no-lead (package) GPADC General purpose ADC LDO Low dropout regulator MSB Most significant bit OCP Over-current protection OTP One-time programmable OVP Over-voltage protection OVLO Over-voltage lockout PFM Pulse frequency modulation PMIC Power management integrated circuit POR Power-on reset PWM Pulse width modulation SAR Successive approximation register TSD Thermal shutdown UVP Under-voltage protection UVLO Under-voltage lockout 2. References [1] NXP Semiconductors N.V., UM10204 I2C-Bus Specification and User Manual, Revision 6 Note 1 References are for the latest published version, unless otherwise indicated.

3.1 Block Diagram

Figure 2. Block Diagram

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 9 4. Pin Information

4.1 Pin Assignments

Noisy groundDigital signal Analog signal Static signal, high current Quiet ground No connectionSwitching signal, high current PGND1 FB1 LX3 PVIN3 PVIN1 LX1 FB3 VSYS LX4 LX4 LX4 PVIN4 PVIN2 LX2 PGND2 FB2 VSYS AGND AN0 AN1 PG2 FB4 PGND4 PGND4 SDA SCL PG1 EN LDOIN LDOOUT NC VDDIO DA9080 (Top view) Pin 1 GND (PGND) plane Figure 3. FCQFN Pinout Diagram (Top View)

4.2 Pin Descriptions

Table 1. Pin Description

Description

1 VDDIO PWR Supply to enable the I2C communication

2 SDA DIOD I2C interface data, connect SDA to the logic rail via a pull-up resistor

3 SCL DI I2C interface data, connect SCL to the logic rail via a pull-up resistor

4 NC DI Not used, connect to GND

5 PG1 DO Power-good output 1, open drain

6 EN DI Chip enable (when pulled low, shuts down entire chip after power down

sequencing complete)

7 LDOIN PWR LDO input, bypass to ground with a ceramic capacitor

8 LDOOUT PWR Output of LDO

9 FB2 AI CH2 Buck output voltage feedback connection

10 PGND2 GND CH2 Buck converter power ground

11 LX2 PWR CH2 Buck converter switching node

12 PVIN2 PWR CH2 Buck converter input

13 PVIN4 PWR CH4 Buck converter input

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 10 Pin # Pin Name Type (Table 2) 14, 15, LX4 PWR CH4 Buck converter switching node 17, 18 PGND4 GND CH4 Buck converter power ground

19 FB4 AI CH4 Buck output voltage feedback connection

20 PG2 DO Power-good output 2, open drain

21 AN1 AI Input to ADC

22 AN0 AI Input to ADC

23 AGND GND Quiet ground connection, connect to a quiet ground area

24, 31 VSYS PWR Filtered from VIN through an RC to provide a clean 5 V supply

25 FB1 AI CH1 Buck output voltage feedback connection

26 PGND1 GND CH1 Buck converter power ground

27 LX1 PWR CH1 Buck converter switching node

28 PVIN1 PWR CH1 Buck converter input – internally connected to PVIN3

29 PVIN3 PWR CH3 Buck converter input – internally connected to PVIN1

30 LX3 PWR CH3 Buck converter switching node

32 FB3 AI CH3 Buck output voltage feedback connection

Table 2. Pin Type Definition

5.1 Absolute Maximum Ratings

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Rating conditions for extended periods may affect device reliability. conditions can adversely impact product reliability and result in failures not covered by warranty.

5.2 Electrostatic Discharge Ratings

Table 4. Electrostatic Discharge Ratings

5.3 Recommended Operating Conditions

5.4 Thermal Specifications

Table 6. FCQFN Ratings TA = 65 °C with 36 thermal vias. Influenced by PCB technology and layout.

5.5 Electrical Specifications

and are valid over the full operating temperature range and power supply range unless otherwise noted. Typical values are based on characterization results at default measurement conditions and are informative only. Default measurement conditions (unless otherwise specified): VIN = 5.0 V, TA = 25 °C.

5.5.1 CH1 Buck Converter Characteristics

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 13 Parameter Description Conditions Min Typ Max Unit VOUT_ACC_DFLT Accuracy of default output voltage In PWM mode VOUT = 3.3 V IOUT = 1 A 3.267 3.3 3.33 V VOUT_ACC_DC Output voltage accuracy in PWM mode, including static line and load regulation -1 1 % VOUT_ACC_LINE Static line regulation 0.5 %/V VOUT_ACC_LD Static load regulation In PWM mode IOUT = 1.5 A 0.1 %/A VOUT_ACC_ACDC Output voltage accuracy, including PWM/PFM ripple and load transient VOUT = 3.3 V COUT = 2 x 47 μF Load transient 1: from 0.5*IMAX to IMAX in 0.2 A/μs Load transient 2: from 50 mA to 0.5*IMAX in 0.2 A/μs IMAX = 1.5 A VIN = 5.0 V TA = 25 °C -2 3 % IPOSLIM Positive over-current limit threshold 3 4 A VTHR_OVP_RISE Over-voltage protection threshold 200 300 400 mV VTHR_UVP_FALL Under-voltage protection threshold -400 -300 -200 mV SRDVC Output voltage slew rate 2.5 mV/μs RDCHG Discharge resistance for LX node 67 Ω tON_MIN Buck LX minimum on time 20 ns SRSS Soft start slew rate 2.5 mV/μs SRSDCHG Soft discharge slew rate 2.5 mV/μs

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5.5.2 CH2 Buck Converter Characteristics

Table 8: CH2 Buck Converter Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External electrical conditions VIN Input voltage of power stage 4 5 5.5 V COUT Output capacitance, including voltage and temperature coefficient 2 x 47 μF 47 94 122.2 μF ESRCOUT Output capacitor series resistance f > 100 kHz 3 mΩ L Inductor value, including current and temperature dependence 0.23 0.47 0.61 μH DCRL Inductor DC resistance 20 50 mΩ Electrical performance IOUT Maximum output current 1500 mA IQ_AUTO Quiescent current in Auto mode (no switching) 51 μA fSW Switching frequency 1.9 2 2.1 MHz VOUT Output voltage range, VOUT_STP Output voltage programable step 20 mV VOUT_ACC_DFLT Accuracy of default output voltage In PWM mode VOUT = 1.8 V IOUT = 1 A 1.782 1.8 1.818 V VOUT_ACC_DC Output voltage accuracy in PWM mode, including static line and load regulation -1 1 % VOUT_ACC_LINE Static line regulation 0.5 %/V VOUT_ACC_LD Static load regulation In PWM mode IOUT = 1.5 A 0.1 %/A VOUT_ACC_ACDC Output voltage accuracy, including PWM/PFM ripple and load transient VOUT = 1.8 V COUT = 2 x 47 μF Load transient 1: from 0.5*IMAX to IMAX in 0.2 A/μs Load transient 2: from 50 mA to 0.5*IMAX in 0.2 A/μs IMAX = 1.5 A VIN = 5.0 V TA = 25 °C -2 3 % IPOSLIM Positive over-current limit threshold 3 4 A

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 15 Parameter Description Conditions Min Typ Max Unit VTHR_OVP_RISE Over-voltage protection threshold 200 300 400 mV VTHR_UVP_FALL Under-voltage protection threshold -400 -300 -200 mV RDCHG Discharge resistance for LX node 67 Ω SRDVC Output voltage slew rate 2.5 mV/μs tON_MIN Buck LX minimum on time 20 ns SRSS Soft start slew rate 2.5 mV/μs SRSDCHG Soft discharge slew rate 2.5 mV/μs

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5.5.3 CH3 Buck Converter Characteristics

Table 9: CH3 Buck Converter Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External electrical conditions VIN Input voltage of power stage 4 5 5.5 V COUT Output capacitance, including voltage and temperature coefficient 3 x 47 μF 70.5 141 183.3 μF ESRCOUT Output capacitor series resistance f > 100 kHz 3 mΩ L Inductor value, including current and temperature dependence 0.23 0.47 0.61 μH DCRL Inductor DC resistance 20 50 mΩ Electrical performance IOUT Maximum output current 1500 mA IQ_AUTO Quiescent current in Auto mode (no switching) 56 μA fSW Switching frequency 1.9 2 2.1 MHz VOUT_STP Output voltage programable step 5 mV VOUT_ACC_DFLT Accuracy of default output voltage In PWM mode VOUT = 1.2 V IOUT = 1 A 1.188 1.2 1.1212 V VOUT_ACC_DC Output voltage accuracy in PWM mode, including static line and load regulation -1 1 % VOUT_ACC_LINE Static line regulation 0.5 %/V VOUT_ACC_LD Static load regulation In PWM mode IOUT = 1.5 A 0.1 %/A VOUT_ACC_ACDC Output voltage accuracy, including PWM/PFM ripple and load transient VOUT = 1.2 V COUT = 3 x 47 μF Load transient 1: from 0.5*IMAX to IMAX in 0.2 A/μs Load transient 2: from 50 mA to 0.5*IMAX in 0.2 A/μs IMAX = 1.5 A VIN = 5.0 V TA = 25 °C -2 4 % IPOSLIM Positive over-current limit threshold 3 4 A

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 17 Parameter Description Conditions Min Typ Max Unit VTHR_OVP_RISE Over-voltage protection threshold 200 300 400 mV VTHR_UVP_FALL Under-voltage protection threshold -400 -300 -200 mV SRDVC Output voltage slew rate 10 mV/μs RDCHG Discharge resistance for LX node 67 Ω tON_MIN Buck LX minimum on time 20 ns SRSS Soft start slew rate 1.25 mV/μs SRSDCHG Soft discharge slew rate 1.25 mV/μs NOTE VOUT can be extended to 1.35 V and 1.8 V. To set VOUT = 1.35 V, write the following sequence: WRITE DA9080_I2C 0x0009 0x50 //VOUT = 1.3 V WRITE DA9080_I2C 0x005D 0x00 //Enable write access to Register 0x0017 WRITE DA9080_I2C 0x005E 0xB0 WRITE DA9080_I2C 0x005E 0xA9 WRITE DA9080_I2C 0x005E 0x8A WRITE DA9080_I2C 0x005E 0xA7 WRITE DA9080_I2C 0x005E 0xA8 WRITE DA9080_I2C 0x005E 0xB1 WRITE DA9080_I2C 0x0017 0x5F //VOUT = 1.35 V WRITE DA9080_I2C 0x005D 0x00 //Disable write access to Register 0x0017 WRITE DA9080_I2C 0x005E 0x00 To set VOUT = 1.8 V, write the following sequence: WRITE DA9080_I2C 0x0009 0x50 //VOUT = 1.3 V WRITE DA9080_I2C 0x005D 0x00 //Enable write access to Register 0x0017 WRITE DA9080_I2C 0x005E 0xB0 WRITE DA9080_I2C 0x005E 0xA9 WRITE DA9080_I2C 0x005E 0x8A WRITE DA9080_I2C 0x005E 0xA7 WRITE DA9080_I2C 0x005E 0xA8 WRITE DA9080_I2C 0x005E 0xB1 WRITE DA9080_I2C 0x0017 0x8C //VOUT = 1.8 VS WRITE DA9080_I2C 0x005D 0x00 //Disable write access to Register 0x0017 WRITE DA9080_I2C 0x005E 0x00

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5.5.4 CH4 Buck Converter Characteristics

Table 10: CH4 Buck Converter Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External electrical conditions VIN Input voltage of power stage 4 5 5.5 V COUT Output capacitance, including voltage and temperature coefficient 4 x 47 μF 94 188 244.4 μF ESRCOUT Output capacitor series resistance f > 100 kHz 3 mΩ L Inductor value, including current and temperature dependence 0.23 0.47 0.61 μH DCRL Inductor DC resistance 20 50 mΩ Electrical performance IOUT Maximum output current 5000 mA IQ_AUTO Quiescent current in Auto mode (no switching) 56 μA fSW Switching frequency 1.9 2 2.1 MHz VOUT Output voltage range VIN = 4.0 V to 5.5 V 0.8 1 1.4 V VOUT_STP Output voltage programable step 5 mV VOUT_ACC_DFLT Accuracy of default output voltage In PWM mode VOUT = 1.0 V IOUT = 1 A 0.99 1 1.01 V VOUT_ACC_DC Output voltage accuracy in PWM mode, including static line and load regulation -1 1 % VOUT_ACC_LINE Static line regulation 0.5 %/V VOUT_ACC_LD Static load regulation In PWM mode IOUT = 5 A 0.1 %/A VOUT_ACC_ACDC Output voltage accuracy, including PWM/PFM ripple and load transient VOUT = 1.0 V COUT = 4 x 47 μF Load transient 1: from 0.5*IMAX to IMAX in 0.2 A/μs Load transient 2: from 50 mA to 0.5*IMAX in 0.2 A/μs IMAX = 5 A VIN = 5.0 V TA = 25 °C -4 4 %

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 19 Parameter Description Conditions Min Typ Max Unit VOUT_ACC_ACDC_FULL Output voltage accuracy, including PWM/PFM ripple and load transient in full load VOUT = 1.0 V COUT = 4 x 47 μF Load transient: from 50 mA to IMAX in 0.2 A/μs IMAX = 5 A VIN = 5.0 V TA = 25 °C -5 5 % IPOSLIM Positive over-current limit threshold 7 8.5 A VTHR_OVP_RISE Over-voltage protection threshold 200 300 400 mV VTHR_UVP_FALL Under-voltage protection threshold -400 -300 -200 mV SRDVC Output voltage slew rate 10 mV/μs RDCHG Discharge resistance for LX node 67 Ω tON_MIN Buck LX minimum on time 20 ns SRSS Soft start slew rate 1.25 mV/μs SRSDCHG Soft discharge slew rate 1.25 mV/μs

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5.5.5 LDO Characteristics

Table 11: LDO Electrical Characteristics Parameter Description Conditions Min Typ Max Unit External electrical conditions VIN Input voltage of power stage 4 5 5.5 V COUT Output capacitance, including voltage and temperature coefficient 2.3 4.7 6.1 μF Electrical performance IOUT Maximum output current 200 mA IQ Quiescent current 3.7 μA VOUT Output voltage 3.3 V VOUT_ACC_DFLT Accuracy of default output voltage VIN = 5 V IOUT = 10 mA TA = 25 °C 3.267 3.3 3.33 V VOUT_ACC_LINE Static line regulation IOUT = 10 mA 0.1 %/V VOUT_ACC_LD Static load regulation IOUT = 0 mA to 0.2 A 0.83 %/A VOUT_ACC_ACDC Output voltage accuracy including load transient COUT = 4.7 μF Transient1: Load = 5 mA to 50 mA @ 0.2 A/μs Transient2: Load = 50 mA to 0.1 A @ 0.2 A/μs -30 30 mV tSS Soft start time (not DVC controlled) No load condition COUT = 4.7 μF 0.56 0.8 ms tSS_TOUT Soft start timeout time 1.3 ms tLDO_OFF Time slot allocated for LDO off sequence 1.3 ms IINRUSH Inrush current VIN = 5 V TA = 25 °C COUT = 4.7 μF 300 mA ILIM Current limit threshold COUT = 4.7 μF 200 mA VTHR_UVP_FALL Under-voltage protection threshold 2.92 V VTHR_PG_RISE Power-good threshold 3 V VHYS_PG Power-good hysteresis 80 mV VDROPOUT Voltage drop from LDOIN to LDOOUT IOUT = 200 mA TA = 25 °C COUT = 4.7 μF 200 400 mV RDCHG Discharge resistance 47 Ω

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5.5.6 ADC Characteristics

Table 12: ADC Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance VIN AN0/1 Input voltage range 0 5.1 V RIN AN0/1 Input Resistance 1.235 MΩ M ADC resolution 8 bit VERR_RT Total conversion error AN0/1 = 0.05 V to 5.1 V TA = 25 °C -20 20 mV VERR Total conversion error AN0/1 = 0.05 V to 5.1 V -40 40 mV VOFS 0 V input offset error AN0/1 = 0 V -40 50 mV DNL Differential non-linearity AN0/1 = 0.05 V to 5.1 V -1 1 LSB INL Integral non-linearity AN0/1 = 0.05 V to 5.1 V -2 2 LSB VRES Voltage resolution With respect to AN0/1 20 mV/LS B TRES_SENSE Temperature sensor resolution Per step -1.97 °C/step tACQ_TOT Total acquisition Time 100 μs IQ Quiescent current ADC enabled 160 μA

5.5.7 Supervision Characteristics

Table 13: Supervision Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance tFALL_DEB VSYS UVLO/VINGOOD Falling Debounce time 10 μs tRISE_DEB VSYS UVLO/VINGOOD Rising Debounce time 1 ms VTHR_UVLO_FALL VIN UVLO threshold for VIN falling 3.6 V VTHR_UVLO_HYS VIN UVLO hysteresis 0.2 V VTHR_RISE Input voltage good threshold Voltage rising 4.6 V VTHR_RISE_ACC Input voltage good threshold accuracy -2 2 % VTHR_HYS Input voltage good hysteresis 0.2 V TTHR_SHDN Thermal shutdown threshold 130 140 150 °C TTHR_SHDN_HYS Thermal shutdown hysteresis 15 °C

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 22 Parameter Description Conditions Min Typ Max Unit tFLT_DEB Fault detect debounce time OVP and UVP 10 μs tHICCUP Hiccup restart delay 64 ms tPG Individual supply PG delay 2 ms tPG1_2 PG1 and PG2 pins PG delay 10 ms

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5.5.8 Quiescent Current Characteristics

Table 14: Quiescent Current Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance IVSYS_SHDN Total current of VSYS pin SHUTDOWN mode VSYS = 5 V VDDIO = 0 V TA = -40 °C to 85 °C EN = L or FORCE_DISABLE = H CH<x> = All OFF 10 30 μA IPVINx_SHDN Total current from PVIN1, PVIN2, PVIN3, and PVIN4 pins SHUTDOWN mode VSYS = 5 V VDDIO = 0 V TA = -40 °C to 85 °C EN = L or FORCE_DISABLE = H CH<x> = All OFF 0 10 μA ILDOIN_SHDN Total current of LDOIN pin SHUTDOWN mode VSYS = 5 V VDDIO = 0 V TA = -40 °C to 85 °C EN = L or FORCE_DISABLE = H CH<x> = All OFF 0 1 μA IVSYS_OP Total current of VSYS pin OPERATING mode EN = H and FORCE_DISABLE = L CH<x> = All ON Buck: ON with no switching and no load LDO: ON with no load ADC: ON IO: Non I2C communication 500 600 μA IPVINx_OP Total current from PVIN1, PVIN2, PVIN3, and PVIN4 pins OPERATING mode EN = H and FORCE_DISABLE = L CH<x> = All ON Buck: ON with no switching and no load 0 10 μA IVDDIO Total current from VDDIO pin No I2C communication VSYS = 5 V VDDIO = 3.3 V SCL = SDA = H 0.16 1 μA

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 24 Parameter Description Conditions Min Typ Max Unit ILDOIN_OP Total current of LDOIN pin OPERATING mode EN = H and FORCE_DISABLE = L CH<x> = All ON LDO: ON with no load 2.7 10 μA

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5.5.9 I2C Characteristics

Table 15: I2C Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance Standard/Fast/Fast+ Mode tBUS Bus free time between a STOP and START condition 0.5 μs CBUS Bus line capacitive load 150 pF fSCL SCL clock frequency 1000 kHz tLO_SCL SCL low time 0.5 μs tHI_SCL SCL high time 0.26 μs tRISE SCL and SDA rise time. Requirement for input. 1000 ns tFALL SCL and SDA fall time. Requirement for input. 300 ns tSETUP_START Start condition setup time 0.26 μs tHOLD_START Start condition hold time 0.26 μs tSETUP_STOP Stop condition setup time 0.26 μs tDATA Data valid time 0.45 μs tDATA_ACK Data valid acknowledge time 0.45 μs tSETUP_DATA Data setup time 50 ns tHOLD_DATA Data hold time 0 ns tSPIKE Spike suppression pulse width 0 50 ns

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5.5.10 Digital I/O Characteristics

Table 16: Digital I/O Electrical Characteristics Parameter Description Conditions Min Typ Max Unit Electrical performance VIH_SCL_SDA Input high voltage, SCL, SDA 1.2 V VIL_SCL_SDA Input low voltage, SCL, SDA 0.4 V VOL_PG1 PG1 output low voltage, POR IOUT = 3 mA 0.4 V VOL_PG2 PG2 output low voltage, POR IOUT = 3 mA 0.4 V VOL_SDA Output low voltage, SDA IOUT = 3 mA 0.4 V VIH_EN Input high voltage, CH1SEL 1.2 V VIL_EN Input low voltage, CH1SEL 0.4 V tENH_DEB EN Pin rising debounce time 100 ms tENL_DEB EN Pin falling debounce time 10 μs

DA9080 functional states are shown in Figure 38.

• Digital core POR signal
• NOT POR pin output. DEVICE_READ DY Check VIN UVLO Check OV/UV Unmask GLOBAL_EN FAULT_SHUTDOWN = 0 FAULT Hiccup FAULT
• VIN UVLO
• OVP/UVP for BUCK
• UVP for LDO
• TSD FAULT including VIN_UVLO FAULT_SUTDOWN (to SEQ/BUCK) = 1 FAULT Count 64 ms FAULT_SHUTDOWN = 1 OTP load done Analog Core active Not FAULT VIN CHECK uv_vin_n high WaitBandGap Wait 30 µs acore_dout_bias_ ok(sync) == 0

Figure 38. FSM States

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 34 8. Sequencer

8.1 Functional Description

DA9080 includes a sequencer to control the power-up and power-down behavior. Any number of voltage supplies (bucks and LDO) can be grouped and assigned to a sequencer slot; for example, CH2 Buck and LDO may both be assigned to slot one. Four sequencer slots are provided. When the sequencer starts, all supplies in slot one are enabled. The sequencer then waits until all the enabled supplies have started correctly as confirmed by the corresponding power-good indicator (see Section 9.3). A blanking time is applied during supply startup to prevent fault conditions being registered. A delay, t PG, is applied between a supply starting correctly and that supply's power-good (PG) indicator being set. Once all the power-good indicators have been set in slot one, the sequencer moves to slot two and repeat the process. When all slots are completed, the power-up sequence is finished. If no supplies have been assigned to a slot then the slot completes immediately and the sequencer moves on to the next slot. For power-down the sequencer is run with reverse slot order. Supplies assigned to slot four are disabled first. When disabled, each buck ramps down the output voltage to the minimum code and then discharges using the internal pull-down resistor. As the LDO is unable to actively discharge its output voltage, when disabled, the LDO uses an internal pull-down resistor to discharge the output voltage. Once the output voltage discharge ramp is finished, and after a suitable delay, the slot is completed and the sequencer moves to slot three and repeats the process. When all slots are complete, the power -down sequence is finished. The startup and shutdown sequencers may be triggered by register write. The FORCE_DISABLE register bit will shut down the regulators if written high whilst the chip is enabled. When using this register care should be taken that the regulators are not also disabled by writing their individual enable registers: The FORCE DISABLE register is located in the same register bank as the individual regulator enable bits (EN1/2/3/4/L) If the regulator enables are set low when FORCE_DISABLE is used then the regulators will not restart when FORCE_DISABLE is cleared.

8.2 Timing Diagrams

The following diagrams show examples of chip power-up and power-down. Figure 39. Timing Diagram Example for Power-Up

Figure 40. Timing Diagram Example for Power-Down by EN Pin

Figure 41. Timing Diagram Example for Power-Down by DISABLE Bit

9.1 Input Voltage Monitoring and Under-Voltage Lockout

voltage monitor comparator has a 4.6 V rise threshold, 4.4 V fall threshold, and 0.2 V hysteresis, see Figure 42. Figure 42. VSYS Monitoring time (tHICCUP), provided there is no UVLO condition, see Figure 43.

Figure 43. Timing Diagram Example for Power-Down by UVLO

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9.2 Fault Protection

9.2.1 Over-Voltage, Under-Voltage, and Over-Current Protection

Each buck has over-voltage (OV), under-voltage (UV), and over-current (OC) fault protection. Each buck has a current limit, IPOSLIM. When the current limit is reached, the BUCK<x>_OC_EVENT bit in the PMC_CH_OC register is set to 0x1. Although the shutdown operation is not executed by the OC fault protection, if the current is exceeding IPOSLIM, the output voltage falls below VTHR_UVP_FALL. When the buck output drops below VTHR_UVP_FALL, or increases above VTHR_OVP_RISE, the BUCK<x>_PG_STAT bit in the PMC_PGOOD_UV register is set to 0x0. Additionally, BUCK<x>_UV_EVENT, or BUCK<x>_OV_EVENT, bit is set as 0x1 in its respective register. (PMC_CH_UV or PMC_CH_OV). The LDO has under-voltage (UV) and over-current (OC) fault protection. When either of these conditions are met, status bits are set to 0x1 in dedicated registers, in a similar way to the bucks. A supply voltage fault condition, on any supply, causes a power down and all supplies are disabled. The sequencer is run with reverse slot order. Supplies assigned to slot four are disabled first. A re-start is initiated, after a blanking time, with a hiccup behavior. The outputs are discharged by the internal pull-down resistors prior to being enabled again. The UV, OV and OC register bits are sticky and remain set through a hiccup cycle, see Figure 44. The register bits are only cleared on a register write of 1.

9.2.2 Thermal Shutdown

DA9080 also has a thermal shutdown (TSD) function. When the die temperature goes above 140 °C (typ) (TTHR_SHDN), all the regulator outputs and the GPADC are shutdown. The sequencer is run with reverse slot order. Supplies assigned to slot four are disabled first. The TSD event is recorded in a register OVERTEMP_EVENT bit<7> in PMC_CH_OC (0x01). When the die temperature goes below 125 °C(typ), the start-up sequence is restarted. Note that the I2C communication is halted during TSD, the OVERTEMP_EVENT bit cannot be read back at this time. The host should check the OVERTEMP_EVENT bit after the device has recovered from TSD. The OVERTEMP_EVENT bit is sticky and is cleared by over-writing the bit with 1.

Figure 44. Timing Diagram Example for a Hiccup Cycle

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 42

9.3 Power-Good Indicator

Each supply has a power-good (PG) indicator that is set once the supply has been enabled and has started correctly. After the supply becomes valid there is a delay, tPG, before the PG indicator is set. For the bucks the PG indicator is the logical NOR of the UV and OV fault indicators. During soft start the PG indicator is held low while the supply output is being ramped. When this ramp is completed, and assuming no fault conditions exist, the PG indicator is set (after tPG). If a fault exists once the soft-start voltage ramp is completed a fault will be registered and all supplies are immediately disabled. For the LDO there is a soft-start timeout period, tSS_TIMEOUT, during which UV fault detection is blanked. After this period the LDO output is monitored for fault conditions. During a dynamic voltage ramp the PG detection is blanked and held high. After the ramp has completed the blanking is removed and the PG status is re-evaluated. The PG indicators are cleared immediately in the event of a fault.

9.3.1 Monitoring Groups of Power-Good Indicators via PG Pins

The output pins PG1 and PG2 are used to monitor the status of groups of PG indicators. Each pin's group is determined by setting a register bit associated with an individual supply's PG indicator. A PG pin is only set when all the PG indicators assigned to its group are set. If no supplies are assigned to a PG pin then the pin is high impedance. A delay is applied between the condition for the PG pin to be set and the PG1 or PG2 pin going high. This delay is in addition to the delay added to the individual supply PG indicators. The status of any PG indicator can be read back via I2C.

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 43 10. Buck Converters DA9080 has four channels of switching buck converters, CH1 Buck to CH4 Buck. Each of the bucks has an I2C programable voltage register, which defines the output voltage. The channels are phase shifted by 0°, 90°, 180°, or 270°. When a buck is enabled, its output voltage is controlled by a soft-start, output voltage ramp. When the buck output reaches the target voltage, the power-good indicator status bit is set. If a buck is enabled while the output capacitor is already charged (at a non-zero voltage) the buck will not discharge the output during startup. The buck will not draw negative current while the soft -start target voltage is lower than the actual output voltage and the voltage will then rise smoothly once the soft-start voltage ramp exceeds the actual output voltage. After a buck is disabled, the output voltage is completely discharged by the integrated pull -down resistor before a new start-up is executed. A pull-down resistor for each channel is enabled when the channel is disabled. This feature can be disabled by setting dedicated register bits, each pull-down can be disabled individually per-buck.

10.1 Dynamic Voltage Control

Each buck converter supports DVC, with the following features: ■ When the value of the target voltage changes, the output voltage updates to the new target value. ■ The DVC controller operates in pulse width modulation (PWM) mode (Note 1) with synchronous rectification. During DVC operation the power-good indicator is available. Note 1 At higher loads the bucks will operate in PWM at a fixed frequency. To support light loads the bucks will operate in pulse frequency modulation (PFM) mode. The bucks move between PFM and PWM automatically depending on the load requirements.

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 44 11. LDO DA9080 has one LDO which provides a fixed, regulated 3.3 V output voltage. The LDO has soft-start function and its output voltage gradually increases when the LDO is enabled. A pull-down resistor for the LDO output is enabled when the LDO is disabled. This feature can be disabled by setting dedicated register bits.

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 45 12. General Purpose Analog-to-Digital Converter DA9080 features an 8-bit successive approximation register (SAR) analog-to-digital converter (ADC). The GPADC allows measurement of: ▪ Die temperature ▪ External voltages (AN0 and AN1) The GPADC consists of an analog-to-digital converter (ADC) with 8-bit resolution, combined with an analog input multiplexer to select a variety of channels. The input MUX selects from the inputs and presents the channel to be measured to the ADC input.

12.1 Measurements on Internal Die Temperature Sensors

A die temperature sensor is placed near known heat sources on the die for managing power. The sensor consists of a bipolar junction diode which is fed by a current source. A measurement on this channel produces a reading of the voltage across the diode. When using the ADC to measure the die temperature sensor, the output ADC code can be converted into ºC using the formula: T(ºC) = -1.97 * CODE + 349.

12.2 Measurements of External Analog Signals

External analog signals can be measured using the GPADC. The pins AN0 and AN1 are provided as inputs for signals to be measured. Signals to be measured should be in the range 0 V to 5.1 V. In the case where the supply voltage, VSYS, is lower than 5.1 V this does not limit the range of the GPADC and signals up to 5.1 V can still be measured. Signals from AN0 and AN1 are directly input to the GPADC during conversion and so should not vary during conversion period. The GPADC assumes signals are DC for the duration of the conversion. When using the ADC to measure the external signals, the output ADC code can be converted into a voltage by using the formula: AN0/1 = CODE * 20 mV + 10 mV.

12.3 Triggering GPADC Conversions

GPADC operations are enabled by setting ADC_EN = 0x1. The ADC automatically converts all inputs sequentially, an ADC read command automatically updates all ADC input values. The 8-bit result is stored in the PMC_TEMP, PMC_ADC0, and PMC_ADC1 registers.

The register PMC_OPTION_02 is password protected.

14.1 Register Maps

Table 17. Register Map

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 49 Addr Register 7 6 5 4 3 2 1 0 Reset 0x000 PMC_VOUT_BUCK2 VBUCK2<7:0> 0x0F 0x000 PMC_VOUT_BUCK3 VBUCK3<7:0> 0x3C 0x000 A PMC_VOUT_BUCK4 VBUCK4<7:0> 0x28 0x000 B PMC_PHASE_INTERLEA VING BUCK4_PHASE<1:0> BUCK3_PHASE<1:0> BUCK2_PHASE<1:0> BUCK1_PHASE<1:0> 0xE4 0x000 C PMC_BUCK_SEQ_GRP BUCK4_GRP<1:0> BUCK3_GRP<1:0> BUCK2_GRP<1:0> BUCK1_GRP<1:0> 0xF9 0x000 D PMC_LDO_SEQ_GRP Reserved Reserved Reserved Reserved Reserved Reserved LDO_GRP<1:0> 0x00 0x000 E PMC_PG1 Reserved Reserved Reserved BUCK4_PG1 BUCK3_PG1 BUCK2_PG1 BUCK1_PG1 LDO_PG1 0x04 0x000 F PMC_PG2 Reserved Reserved Reserved BUCK4_PG2 BUCK3_PG2 BUCK2_PG2 BUCK1_PG2 LDO_PG2 0x1A 0x001 PMC_DISCHARGE Reserved Reserved Reserved BUCK4_DISCHARG E BUCK3_DISCHA RGE BUCK2_DISCHA RGE BUCK1_DISCHARG E LDO_DISCHAR GE 0x1F 0x001 PMC_TEMP TEMP<7:0> 0x00 0x001 PMC_ADC0 ADC0<7:0> 0x00 0x001 PMC_ADC1 ADC1<7:0> 0x00 0x001 PMC_REVISION_ID REVISION_ID<7:0> 0xE9 0x001 D PMC_OPTION_02 Reserved Reserved Reserved Reserved CH1_PWM CH2_PWM CH3_PWM CH4_PWM 0xF0 OTP Control 0x006 OTP_CONFIG_ID CONFIG_REV<7:0> 0x00

14.2 Register Descriptions

14.2.1 PMIC Function Registers

Table 18. PMC_PGOOD_UV (0x0000) by a POR or writing 1 via I2C. [5] R UV_CURRENT Indicates current VSYS under-voltage (UV) status. [4] R BUCK4_PG_STAT CH4 Buck power good (PG) status. [3] R BUCK3_PG_STAT CH3 Buck PG status. [2] R BUCK2_PG_STAT CH2 Buck PG status. [1] R BUCK1_PG_STAT CH1 Buck PG status. [0] R LDO_PG_STAT LDO PG status.

Table 19. PMC_CH_OC (0x0001) 0x0 No over-temperature event.

Table 20. PMC_CH_OV (0x0002) Table 21. PMC_CH_UV (0x0003)

Table 22. PMC_ADC_ENABLE (0x0004) Table 23. PMC_CH_EN (0x0005) cleared to 0 when the external EN pin is toggled low.

Table 24. PMC_VOUT_BUCK1 (0x0007) outside the range stated in the electrical table. Table 25. PMC_VOUT_BUCK2 (0x0008) Table 26. PMC_VOUT_BUCK3 (0x0009) Table 27. PMC_VOUT_BUCK4 (0x000A)

Table 28. PMC_PHASE_INTERLEAVING (0x000B) [7:6] R BUCK4_PHASE CH4 Buck phase interleave. [5:4] R BUCK3_PHASE CH3 Buck phase interleave. [3:2] R BUCK2_PHASE CH2 Buck phase interleave. [1:0] R BUCK1_PHASE BUCK1 phase interleave. Table 29. PMC_BUCK_SEQ_GRP (0x000C)

Table 30. PMC_LDO_SEQ_GRP (0x000D) [1:0] RW LDO_GRP Assign LDO to a power-up / power-down sequencing slot. Table 31. PMC_PG1 (0x000E) [4] RW BUCK4_PG1 Assign CH4 Buck to PG1 monitor group. [3] RW BUCK3_PG1 Assign CH3 Buck to PG1 monitor group. [2] RW BUCK2_PG1 Assign CH2 Buck to PG1 monitor group.

[1] RW BUCK1_PG1 Assign CH1 Buck to PG1 monitor group. [0] RW LDO_PG1 Assign LDO to PG1 monitor group. Table 32. PMC_PG2 (0x000F) [4] RW BUCK4_PG2 Assign CH4 Buck to PG2 monitor group. [3] RW BUCK3_PG2 Assign CH3 Buck to PG2 monitor group. [2] RW BUCK2_PG2 Assign CH2 Buck to PG2 monitor group. [1] RW BUCK1_PG2 Assign CH1 Buck to PG2 monitor group. [0] RW LDO_PG2 Assign LDO to PG2 monitor group.

Table 33. PMC_DISCHARGE (0x0010) ground when channel is shut down. capacitors (NOT recommended). buck output voltage has completed ramping down to 0 V.

Table 34. PMC_TEMP (0x0011) [7:0] RW TEMP Indicates ADC TEMP value. Table 35. PMC_ADC0 (0x0012) Table 36. PMC_ADC1 (0x0013) Table 37. PMC_REVISION_ID (0x0014) Table 38. PMC_OPTION_02 (0x001D) [3] RW CH1_PWM CH1 operation mode while not in LPM. [2] RW CH2_PWM CH2 operation mode while not in LPM. [1] RW CH3_PWM CH3 operation mode while not in LPM. [0] RW CH4_PWM CH4 operation mode while not in LPM.

14.2.2 Chip ID

Table 38. OTP_CONFIG_ID (0x0062)

15.1 Package Outlines

15.2 Moisture Sensitivity Level

MSL classification is defined in Table 39. The package is qualified for MSL 3. Table 39. MSL Classification

15.3 FCQFN Handling

tweezers are not acceptable, since contact may easily damage the silicon chip.

15.4 Soldering Information

downloaded from http://www.jedec.org.

and availability of OTP variants, please consult your Renesas Electronics local sales representative. Table 40. Ordering Information Table 41 shown the list of MPU devices that are compatible with the specific variant. Table 41. Target MPU

The following recommended components are references selected from requirements of a typical application.

1 VDDIO

23 AGND

21 AN1

7 LDOIN

12 PVIN2

26 PGND1

10 PGND2

13 PVIN4

Figure 50. Application Diagram

18.1 Capacitor Selection

Table 42. Recommended Capacitor Types

18.2 Resistor Selection

Table 43. Recommended Resistor Type

18.3 Inductor Selection

Critical for the converter efficiency and should therefore be minimized. per output. Use of larger output inductance degrades the load transient performance of the buck converter. Table 44. Recommended Inductor Type

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 65 A. ECAD Design Information This appendix contains information that supports the development of the PCB ECAD model for this device. It is intended to be used by PCB designers. A.1 Part Number Indexing Orderable Part Number Number of Pins Package Type Package Code/POD Number DA9080-xxFCB2 32 FCQFN FQ0032AA/PSC-5139-01 DA9080-xxFCBC 32 FCQFN FQ0032AA/PSC-5139-01 1. xx: OTP variant A.2 Symbol Pin Information A.2.1 32-FCQFN Pin Number Primary Pin Name Primary Electrical Type Alternate Pin Name(s)

1 VDDIO Power -

2 SDA I/O -

3 SCL Input -

4 NC Passive -

5 PG1 Output -

6 EN Input -

7 LDOIN Power -

8 LDOOUT Power -

9 FB2 Input -

10 PGND2 Power -

11 LX2 Power -

12 PVIN2 Power -

13 PVIN4 Power -

14 LX4 Power -

15 LX4 Power -

16 LX4 Power -

17 PGND4 Power -

18 PGND4 Power -

19 FB4 Input -

20 PG2 Output -

21 AN1 Input -

22 AN0 Input -

23 AGND Power -

24 VSYS Power -

25 FB1 Input -

26 PGND1 Power -

27 LX1 Power -

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 66 Pin Number Primary Pin Name Primary Electrical Type Alternate Pin Name(s)

28 PVIN1 Power -

29 PVIN3 Power -

30 LX3 Power -

31 VSYS Power -

32 FB3 Input -

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 67 A.3 Symbol Parameters Orderable Part Number Interface Max Junction Temperature (Tj) Max Input Voltage Min Input Voltage Max Operating Temperature Min Operating Temperature Max Output Current Max Output Voltage Min Output Voltage Mounting Type Qualification RoHS Switching Frequency DA9080-xxFCB2 I2C +150 °C 5.5 V 4 V +85 °C -40 °C 5 A 3.3 V 0.8 V SMD Industrial Compliant 2 MHz DA9080-xxFCBC I2C +150 °C 5.5 V 4 V +85 °C -40 °C 5 A 3.3 V 0.8 V SMD Industrial Compliant 2 MHz

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 68 A.4 Footprint Design Information A.4.1 32-FCQFN IPC Footprint Type Package Code/ POD Number Number of Pins FCQFN FQ0032AA/PSC-5139-01 32 Description Dimension Value (mm) Diagram Minimum body span (vertical side) Dmin 4.95 Maximum body span (vertical side) Dmax 5.05 Minimum body span (horizontal side) Emin 4.95 Maximum body span (horizontal side) Emax 5.05 Minimum Lead Width Bmin 0.20 Maximum Lead Width Bmax 0.30 Minimum Lead Length Lmin 0.35 Maximum Lead Length Lmax 0.45 Maximum Height Amax 0.60 Minimum Standoff Height A1min 0.00 Minimum Lead Thickness cmin 0.10 Maximum Lead Thickness cmax 0.20 Number of pins (vertical side) PinCountD 8 Number of pins (horizontal side) PinCountE 8 Distance between the center of any two adjacent pins (vertical side) PitchD 0.50 Distance between the center of any two adjacent pins (horizontal side) PitchE 0.50 Location of pin 1; S2 = corner of D side (top left), C1 = center of E side(center). Pin1 S2 Thermal pad Chamfer. If not present give hyphen (-). CH - Minimum thermal pad size (vertical side) D2min 1.85 Maximum thermal pad size (vertical side) D2max 1.95 Minimum thermal pad size (horizontal side) E2min 0.80 Maximum thermal pad size (horizontal side) E2max 0.90 Recommended Land Pattern Description Dimension Value (mm) Diagram Distance between left pad toe to right pad toe (horizontal side) ZE 5.30 Distance between top pad toe to bottom pad toe (vertical side) ZD 5.30 Distance between left pad heel to right pad heel (horizontal side) GE 4.20 Distance between top pad heel to bottom pad heel (vertical side) GD 4.20 Pad Width X 0.25 Pad Length Y 0.55

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 69

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 70 RoHS Compliance Renesas Electronics’ suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from our suppliers are available on request.

R16DS0519EJ0340 Rev. 3.4 Mar 24, 2025 CFR0011-120-00 Page 71 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD-PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers who are designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only to develop an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third-party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising from your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Disclaimer Rev.1.01) Corporate Headquarters TOYOSU FORESIA, 3-2-24 Toyosu Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit www.renesas.com/contact-us Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2025 Renesas Electronics Corporation. All rights reserved.

TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www. renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit www.renesas.com /contact-us/ . Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SU BSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD-PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers who are designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicabl e standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only to develop an application that uses Renesas products. Other reproduction or use of these resour ces is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third-party intellectual property. Renesas disclaims responsibility for, and you will fully indem nify Renesas and its representatives again st, any claims, damages, costs, losses, or liabilities arising from your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writ ing. No use of any Renesas re sources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Disclaimer Rev.1.01) © 2026 Renesas Electronics Corporation. All rights reserved.