DA9072-XXOH6

Renesas Technology Corp

Ultra-Low Quiescent Current PMIC 13-Jun-2023

Manufacturer: Renesas Technology Corp

Document: 117 Pages / 2Mb

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DA9072_V01 RENESAS | Alldatasheet

Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 117

Technical content

Datasheet sections

1 Pinout
2 Characteristics
2.1 Absolute Maximum Ratings
2.2 Electrostatic Discharge Ratings
2.3 Recommended Operating Conditions
2.4 Electrical Characteristics
2.4.1 Battery Charger
2.4.2 Battery Temperature Monitor
2.4.3 LDO / Load Switches
2.4.4 Digital Inputs
2.4.5 I2C Interface
2.4.6 Input Currents
2.4.7 Power Path Management and Current Limit
2.4.8 Protection
2.4.9 Pushbutton Timer
2.4.10 Digital Outputs
2.4.11 Buck Regulator
2.4.12 Battery Monitors
2.5 Thermal Characteristics
3 Typical Performance Graphs
4 Functional Description
4.1 Overview
4.2 Battery-Powered Operation
4.2.1 Active Battery and High Impedance Modes
4.2.2 Battery Protection
4.3 Analog Battery Monitor Functions
4.3.1 Battery Discharge Current Monitoring
4.3.2 Battery Voltage Monitoring
4.4 Battery Charging
4.4.1 Battery Charging Process
4.4.2 Charge in Progress
4.4.3 Pre-Charge and Termination Current
4.4.4 Fast Charge Current
4.4.5 CV Voltage Regulation and Termination
4.4.6 Charge Done and Recharge
4.4.7 Charge Faults
4.4.8 Safety Timers

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 1 of 117 © 2023 Renesas Electronics General Description DA9072 is a highly integrated, configurable, low quiescent current power management IC (PMIC) that integrates the most common needs for wearables, home automation, and low power battery applications. The PMIC comprises a linear charger with power path management, ultra-low quiescent current (IQ) buck regulator and LDO/load switches, analog battery monitor, watchdog and protection features in an I2C configurable compact WLCSP package. DA9072 has several power saving modes to increase battery life whether the product sits on the shelf or is in operation. Further savings in power are achieved with the ultra-low IQ buck converter (efficient down to 10 µA load currents) and low IQ LDOs. The uncommitted inputs of LDOs can be connected to either the battery or buck output. DA9072 provides charge current up to 500 mA to speed up the charge cycle. The charge profile is programmable by external resistors or in software, allowing either stand-alone operation or host control. DA9072 includes dynamic power path management which automatically balances current delivered to the system and for battery charging. Suitable for small battery applications, the battery monitors facilitate on-demand battery voltage and discharge current information to an external MCU’s ADC to support software-based fuel gauging. Key Features ■ Increased battery life □ 800 nA (no load, total battery current) buck converter, programmable down to 0.6 V, 300 mA-capable □ Three configurable 800 nA quiescent current LDOs/load switches, 150 mA- capable ■ Power saving modes optimized for storage and operation ■ Battery protection □ Battery thermal- and over-discharge protection □ 20 V tolerant input □ Automatic battery temperature monitoring in all operation modes ■ Configurable battery monitors □ Battery current (IMON) □ Battery voltage (VBAT_DIV) □ Battery temperature (TEMP_SNS) ■ High integration and configurability □ I2C enabled analog battery monitors for software-based fuel gauging □ Watchdog input and power cycling to prevent system stall □ Reset input and status outputs □ Low external component count □ Compact 42 pin, 2.97 mm x 2.66 mm WLCSP package ■ Fast charge □ 500 mA (max) charge current; 2 mA (min) □ Programmable pre-charge, fast charge, and termination voltage □ Dynamic power path balances multiple power sources □ Termination current programmable down to 500 µA □ ±0.5 % accurate termination voltage

Applications

■ Wearable devices - fitness trackers, smart watches, wireless headphones ■ Home automation devices - smoke detectors, smart thermostats, smart door locks ■ Health monitoring medical accessories ■ Rechargeable toys ■ High efficiency, ultra-low power applications

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 2 of 117 © 2023 Renesas Electronics System Diagram VBAT_SNS GND VTEMP Control NTC MonitorTEMP_SNS ILIM_PWR ILIM_CHG ITER_CHG DA9072 Standalone Mode NTC temp sense BATTERY PACK VBAT AGND VDD_PWR 1.0µF USB VDD_SYSvdd_sys 4.7µF VTEMP Charger and Power Path Control 20V OVP Protection MODE PWR_FLT SYS_FLT SDA SCL ROUT_N WDHost VDDIO Host Communication RIN_N PUSHBUTTON RESET PGND_BUCK FB_BUCK SW_BUCK Vo_buck 0.6V – 2.1V 300mA VDD_BUCK vdd_sys LDO1 0.8V – 3.3V 150mA LDO2 0.8V – 3.3V 150mA LDO 0 (LV) VLDO0 VDD_LDO0 LDO0 0.8V – 3.15V 150mA Vo_buck LDO 1 (HV) VLDO1 VDD_LDO1 LDO 2 (HV) VLDO2 VDD_LDO2 Buck Vo buck 2.2µH 10µF vdd_sys 2.2µF 1µF VBAT_DIV GND_DIV IMON ADC (fuel gauge) Analog Battery Monitors Figure 1: System Diagram

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 8 of 117 © 2023 Renesas Electronics Terms and Definitions ADC Analog-to-digital converter BAT Battery CC Constant current CV Constant voltage DCHG Discharge DPM Dynamic power management DPPM Dynamic Power Path mode Hi-Z High impedance I2C Inter-Integrated Circuit IMON Current monitor ITER Termination current LDSW Load switch LDO Low dropout regulator MCU Microcontroller unit NTC Negative temperature coefficient (thermistor) OVP Over-voltage protection OVT Over-temperature PMIC Power management integrated circuit PoR Power-on reset RMEAS External resistance programming SNS Sense SYS System TEMP Temperature TSD Thermal shutdown USB Universal serial bus UVLO Under-voltage lockout WD Watchdog WLCSP Wafer-level

1 Pinout

CommonBuckCharger/Power Path LDO2LDO0 7 6 5 4 3 A B C D E F PGND_B UCK FB_BUC K VDD_BU CK VDD_SY S GND VDD_SY S VBAT_DI V VLDO2 SW_BU CK VDD_DL VLDO0 VLDO1 SDA AGND SLC ROUT_NPWR_FL T VDD_LD VDD_LD RIN_N MODE TEMP_S NS SYS_FL T WD IMON ILIM_CH G GND VDDIOGND_DI V GND GND VDD_P WR VBAT ITER_C HG ILIM_PW R VTEMP NC GND VBAT VBAT_S NS VDD_SY S GND Figure 2: Pinout Diagram (Bottom View) Note 1 Although Pin D1 is connected to VDD_SYS, it does not handle any current. Therefore, it does not need to be routed by large current rule. Table 1: Pin Description Pin # Pin Name Type (Table 2) Description A1, D3, E1, F2, F3, F4 GND GND Ground connection. Connect to the ground plane. A2 VDD_PWR POWER Input power supply. VDD_PWR is a 20 V-tolerant input. Bypass to GND with a minimum 1 µF ceramic capacitor. A3, A4, D1 VDD_SYS POWER VDD_SYS is the intermediate rail which typically supplies VDD_BUCK. Bypass to ground with a 4.7 µF ceramic capacitor. A5 VDD_BUCK POWER Input of the buck converter. Bypass to PGND_BUCK with a minimum 2.2 µF ceramic capacitor. A6 SW_BUCK POWER Buck switching node. Connect to the buck inductor. A7 PGND_BUCK POWER Power ground for the buck. Connect to the buck input capacitor and ground plane.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 10 of 117 © 2023 Renesas Electronics Pin # Pin Name Type (Table 2) Description B1, B2 VBAT POWER Battery connection. Connect to the positive terminal of the battery. Bypass to ground with a minimum 1 µF ceramic capacitor. B3 IMON AO Battery discharge current monitor output. B4 TEMP_SNS AI Battery pack NTC monitor. Connect to a resistive network and thermistor. B5 SYS_FLT DOD Open drain status output. Connect to VDDIO through a 1 kΩ to 100 kΩ pull-up resistor. B6 SDA DIO I2C interface data. Connect SDA to VDDIO through a 2 kΩ to10 kΩ pull-up resistor. B7 FB_BUCK AI Buck output voltage feedback connection. C1 VBAT_SNS AI Battery voltage sense connection. Connect to the positive battery terminal. C2 ITER_CHG AI Termination current setting pin. Connect a resistor between ITER_CHG and ground to set the pre-charge and termination currents (ITER). Alternatively, short this pin to ground to allow ITER to be programmed by register setting. C3 ILIM_CHG AI Fast-charge current setting pin. Connect a resistor between ILIM_CHG and ground to set the fast-charge current (ICHG). Alternatively, short this pin to ground to allow ICHG to be programmed by register setting. C4 WD DI Watchdog input. Toggle WD within the watchdog time-out period to avoid power reset. C5 RIN_N DI Manual reset input pin. RIN_N is internally pulled high. Pulling this pin low wakes up the device from Ship mode or performs a reset. C6 SCL DI I2C interface clock. Connect SCL to VDDIO through a 2 kΩ to10 kΩ pull-up resistor. C7 AGND GND Quiet ground connection. Connect to a quiet ground area. D2 ILIM_PWR AI Input current limit setting pin. Connect a resistor between ILIM_PWR and ground to set the VDD_PWR current limit (ILIM). Alternatively, short this pin to ground to allow ILIM to be programmed by register. D4 VBAT_DIV AO Battery voltage divider, positive output. D5 MODE DI Mode control input pin. MODE is internally pulled low. If VDD_PWR is powered, driving MODE high disables charging. If VDD_PWR is unpowered, driving MODE low enables Hi-Z mode. D6 ROUT_N DOD Reset output pin. Connect this open-drain output to VDDIO through a 1 kΩ to 100 kΩ pull-up resistor. D7 PWR_FLT DOD Power status indicator output. Connect this open-drain output to VDDIO through a 1 kΩ to 100 kΩ pull-up resistor. PWR_FLT pulls low when VDD_PWR is plugged into a valid power source. E2 VTEMP AO Switched VDD_SYS supply for battery temp sense resistor divider. E3 VDDIO POWER IO voltage. E4 GND_DIV AO Battery voltage divider, ground reference.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 11 of 117 © 2023 Renesas Electronics Pin # Pin Name Type (Table 2) Description E5 VDD_LDO2 POWER Input to Load Switch / LDO2. Bypass to ground with a minimum 1 µF ceramic capacitor. E6 VDD_LDO1 POWER Input to Load Switch / LDO1. Bypass to ground with a minimum 1 µF ceramic capacitor. E7 VDD_LDO0 POWER Input to Load Switch / LDO0. Bypass to ground with a minimum 1 µF ceramic capacitor. F1 NC F5 VLDO2 POWER Load Switch or LDO2 output. Bypass to ground with a minimum 1 µF ceramic capacitor. F6 VLDO1 POWER Load Switch or LDO1 output. Bypass to ground with a minimum 1 µF ceramic capacitor. F7 VLDO0 POWER Load Switch or LDO0 output. Bypass to ground with a minimum 1 µF ceramic capacitor. Table 2: Pin Type Definition Pin Type Description Pin Type Description DI Digital input AI Analog input DOD Digital output open drain AO Analog output DIO Digital input/output PWR Power GND Ground

2 Characteristics

2.1 Absolute Maximum Ratings

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Table 3: Absolute Maximum Ratings Parameter Description Conditions Min Max Unit TS Storage temperature -65 150 °C VDD_PWR VDD_PWR 1 V / µs max slew rate -0.3 22 V VBAT VBAT, VBAT_SNS -0.3 6 V VDD_SYS VDD_SYS, VDD_BUCK, SW_BUCK, VDD_LDOx, VTEMP -0.3 6 V VIO VDDIO and all IO pins (unless otherwise stated) Note 1 -0.3 6 V Note 1 VDDIO and IO voltages must be less than the higher of VBAT or VDD_PWR.

2.2 Electrostatic Discharge Ratings

Table 4: Electrostatic Discharge Ratings Parameter Description Conditions Value Unit VESD_HBM Maximum ESD protection Human body model (HBM) All exposed pins Note 1 2000 kV VESD_CDM Maximum ESD protection Charged device model (CDM) Note 2 500 kV Note 1 Per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. Note 2 Per ANSI/ESDA/JEDEC JS-002. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

2.3 Recommended Operating Conditions

Recommended operating conditions are conditions for which the device is intended to be functional, but parameter specifications may not be guaranteed. For guaranteed specifications and associated test conditions, refer to the Electrical Characteristics tables. Table 5: Recommended Operating Conditions Parameter Description Conditions Min Typ Max Unit TA Operating Ambient Temperature -40 85 °C VDD_PWR VDD_PWR voltage Including OVP range 3.6 5 20 V VDD_PWR operating voltage 3.6 5 5.5 V VBAT Battery voltage VDD_PWR supplied 0 3.7 4.7 V Battery voltage (act.bat) VDD_PWR not supplied 2.5 3.7 4.7 V

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 13 of 117 © 2023 Renesas Electronics Parameter Description Conditions Min Typ Max Unit VDD_LDO VDD_LDO voltage Load Switch (LDSW) mode 0.8 5.5 V VDD_LDO voltage LDO mode 1.8 5.5 V VDDIO IO voltage VDDIO < VDD_PWR or VBAT, whichever is greater 1.4 1.8 3.3 V VDD_BUCK Buck input voltage Note 1 2.5 5.5 V Note 1 VDD_BUCK must be greater than buck output voltage +600 mV.

2.4 Electrical Characteristics

Electrical characteristics table limits are guaranteed by production testing, design, or correlation using standard statistical quality control methods unless otherwise stated. Typical (Typ) specifications are mean or average values 25 °C and are not guaranteed. Unless otherwise noted: VBAT = 3.7 V, VDD_SYS = 3.7 V, VDD_PWR = 5.0 V, VDDIO = 1.8 V, and TA = -40 °C to 85 °C.

2.4.1 Battery Charger

Table 6: Battery Charger Parameter Description Conditions Min Typ Max Unit Electrical Performance VDD_SYS_THR _DPPM VDD_SYS DPPM voltage threshold VDD_SYS falling, above VBAT_CHG 0.2 V RON_CHG_INT Battery charger MOSFET on resistance Measured from VBAT to VDD_SYS 300 400 mΩ VDROP_BAT_T O_VDD_SYS VBAT - VDD_SYS VBAT > 3 V, IBAT discharge = 400 mA 120 160 mV VBAT_SUP Threshold to enter the battery supplement mode VVBAT > VVBAT_UVLO VDD_ SYS < VBAT V IBAT_DCHG_RN G Discharge current limit setting range Selectable 0.2 A / step 0.55 1.75 A VBAT_CHG Charge voltage range Operating in voltage regulation, programmable range in 10 mV steps 3.6 4.65 V VBAT_CHG_AC C Charge voltage accuracy 0 °C< TJ < 85 °C -0.5 0.5 % ICHG Fast charge current range 2 500 mA ICHG_ACC Fast charge current accuracy -5 5 % ITER_RNG Termination and pre-charge current setting range Termination current programmable range maximum over I2C 0.5 50 mA ITER_ACC Termination charge current accuracy Peak current below termination threshold -10 10 % tTER_DEGLITCH Termination deglitch time Charge current falling 64 ms

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 14 of 117 © 2023 Renesas Electronics Parameter Description Conditions Min Typ Max Unit VTHR_PRE_TO _FASTCHG Pre charge to fast charge threshold voltage range 2.7 3.2 V ICHG_PRE_ACC Pre-charge current accuracy VBAT > 2V -10 10 % VRCHG Recharge threshold voltage VBAT below VBAT_CHG 100 120 140 mV tRCHG_DEGLIT CH Recharge threshold deglitch time tFALL = 100 ns (typ), VRCHG falling 32 ms

2.4.2 Battery Temperature Monitor

Table 7: Battery Temperature Monitor Parameter Description Conditions Min Typ Max Unit Electrical Performance VTEMP_HI High temperature threshold % of VDD_SYS, VTEMP_SNS falling 14.5 15 15.2 % VTEMP_WARM Warm threshold % of VDD_SYS, VTEMP_SNS falling 20.1 20.5 20.8 % VTEMP_COOL Cool threshold % of VDD_SYS, VTEMP_SNS rising 34.4 35 35.4 % VTEMP_LO Low temperature threshold % of VDD_SYS, VTEMP_SNS rising 39.3 39.8 40.2 % VOFF_TEMP_S NS TEMP_SNS disable threshold % of VDD_SYS for rising VTEMP_SNS 55 60 % tTEMP_SNS_DE GLITCH TEMP_SNS deglitch time TEMP_SNS at any threshold 10 ms

2.4.3 LDO / Load Switches

Table 8: LDO0 / Loadswitch (LV) Parameter Description Conditions Min Typ Max Unit Electrical Performance VIN_LDSW_0 Input voltage range for LDSW Load Switch mode VDD_LDO > VLDO 0.8 5.5 V VIN_LDO_0 Input voltage range for LDO LDO mode, VDD_LDO > VLDO 1.8 5.5 V VOUT_ACC_LO _0 DC output accuracy VDD_LDO > VLDO + 0.2 V -3 3 % VOUT_LDO_0 Output range Programmable range, 50 mV or 75 mV steps 0.8 3.15 V VOUT_LINE_0 DC line regulation 1.8 V < VDD_LDO < 5.5 V IOUT = 500 μA -0.8 0.8 %

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 15 of 117 © 2023 Renesas Electronics Parameter Description Conditions Min Typ Max Unit VOUT_LD_0 DC load regulation 0 < IOUT < 50 mA VDD_LDO = 1.85 V VLDO = 1.8 V -3 0 % VOUT_TR2_LD_

0 Load transient

2 μA to 50 mA 100 mA/μsec VDD_LDO > 2.0 V VLDO = 1.8 V -120 60 mV VOUT_TR_LD_0 Load transient 2 μA to 50 mA 100 mA/μsec VDD_LDO = 1.85 V VLDO = 1.8 V -140 60 mV RON_LDSW_ILI M_0 On resistance of LDSW mode with current limit VDD_LDO = 3.7 V 0.7 Ω RON_LDSW_N O_ILIM_0 On resistance of LDSW mode without current limit VDD_LDO = 3.7 V 0.11 Ω RDCHG_LDO_O N_0 MOSFET on resistance for LDO discharge ILD = -10 mA 32 Ω ILIM_OUT_LDO_ Output current limit for LDO mode VLDO = 0.9 * VLDO(nom) 155 mA IOUT_LDO_LO_ 0 Output current VDD_LDO = 1.85 V VLDO = 1.8 V 50 mA IOUT_LDO_HI_0 Output current VDD_LDO > VLDO + 0.2 V VLDO = 1.8 V 150 mA IIN_LDO_ON_0 Quiescent current LDO mode 0.75 μA IIN_LDO_OFF_0 OFF state supply current 0.001 μA PSRR_vddldo _0 Power supply rejection ratio @10 kHz IOUT = 75 mA 43 dB tSTART_LDO0 LDO start-up delay time 20 ms Table 9: LDO1 / Loadswitch (HV) Parameter Description Conditions Min Typ Max Unit Electrical Performance VIN_LDSW_1 Input voltage range for Load Switch Load Switch mode VDD_LDO > VLDO 0.8 5.5 V VIN_LDO_1 Input voltage range for LDO LDO mode, VDD_LDO > VLDO 1.8 5.5 V VOUT_ACC_LO _1 DC output accuracy VDD_LDO > VLDO + 0.2 V -3 3 % VOUT_LDO_1 Output range Programmable range, 50 mV or 75 mV steps 0.8 3.3 V

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 16 of 117 © 2023 Renesas Electronics Parameter Description Conditions Min Typ Max Unit VOUT_LINE_1 DC line regulation 1.8 V < VDD_LDO < 5.5 V IOUT = 500 μA -0.8 0.8 % VOUT_LD_1 DC load regulation 2 μA < IOUT < 100 mA VDD_LDO > VOUT_LDO + 0.2 V VLDO = 3.0 V -3 0 % VOUT_TR_LD_1 Load transient 2 μA to 100 mA, 100 mA/μsec VDD_LDO > VLDO + 0.2 V VLDO = 3.0 V -120 60 mV RON_LDSW_ILI M_1 On resistance of LDSW mode with current limit VDD_LDO = 3.7 V 1.5 Ω RON_LDSW_N O_ILIM_1 On resistance of LDSW mode without current limit VDD_LDO = 3.7 V 0.27 Ω RDCHG_LDO_O N_1 MOSFET on resistance for LDO discharge ILD = -10 mA 32 Ω ILIM_OUT_LDO_ Output current limit (LDO MODE) VLDO = 0.9 * VLDO(nom) 155 mA IOUT_LDO_HI1_ 1 Output current VDD_LDO > VLDO + 0.2 V 150 mA IIN_LDO_ON_1 Quiescent current LDO mode 0.8 μA IIN_LDO_OFF_1 OFF state supply current 0.001 μA PSRR_vddldo _1 Power supply rejection ratio @10 kHz IOUT = 75 mA 40 dB tSTART_LDO1 LDO start-up delay time 20 ms Table 10: LDO2 / Loadswitch (HV+Power cycle) Parameter Description Conditions Min Typ Max Unit Electrical Performance VIN_LDSW_2 Input voltage range for Load Switch Load Switch mode, VDD_LDO > VLDO 0.8 5.5 V VIN_LDO_2 Input voltage range for LDO LDO mode, VDD_LDO > VLDO 1.8 5.5 V VOUT_ACC_LO _2 DC output accuracy VDD_LDO > VLDO + 0.2 V -3 3 % VOUT_LDO_2 Output range for LDO Programmable range, 50 mV or 75 mV steps 0.8 3.3 V VOUT_LINE_2 DC line regulation 1.8 V < VDD_LDO < 5.5 V IOUT = 500 μA -0.8 0.8 %

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 17 of 117 © 2023 Renesas Electronics Parameter Description Conditions Min Typ Max Unit VOUT_LD_2 DC load regulation 2 μA < IOUT < 100 mA VDD_LDO > VOUT_LDO + 0.2 V VLDO = 3.0 V -3 0 % VOUT_TR_LD_2 Load transient 2 μA to 100 mA, 100 mA/μsec VDD_LDO > VLDO + 0.2 V VLDO = 3.0 V -120 60 mV RON_LDSW_ILI M_2 On resistance of LDSW mode with current limit VDD_LDO = 3.7 V 1.5 Ω RON_LDSW_N O_ILIM_2 On resistance of LDSW mode without current limit VDD_LDO = 3.7 V 0.27 Ω RDCHG_LDO_O N_2 MOSFET on resistance for LDO discharge ILD = -10 mA 32 Ω ILIM_OUT_LDO_ Output current limit (LDO MODE) VLDO = 0.9 * VLDO(nom) 155 mA IOUT_LDO_HI1_ 2 Output current VDD_LDO > VLDO + 0.2 V 150 mA IIN_LDO_ON_2 Quiescent current LDO mode 0.8 μA IIN_LDO_OFF_2 OFF state supply current 0.001 μA PSRR_vddldo _@ Power supply rejection ratio @10 kHz IOUT = 75 mA 35 dB tSTART_LDO2 LDO start-up delay time 20 ms

2.4.4 Digital Inputs

Table 11: Digital Input Pins (MODE, WD) Parameter Description Conditions Min Typ Max Unit External Electrical Conditions tMIN_WD WD minimum input pulse width 25 μs Electrical Performance VIN_LO Input low threshold 0.25*V DDIO V VIN_HI Input high threshold 0.75*V DDIO V RPD_MODE Internal pull-down resistance 900 kΩ t_DEGLITCH_M ODE MODE pin deglitch time rising/falling 100 μs

2.4.5 I2C Interface

Table 12: I2C interface Parameter Description Conditions Min Typ Max Unit Electrical Performance fI2C_CLK SCL frequency range 100 400 kHz VOUT_LO Output low threshold level SDA 5 mA sink current VDDI O*0.25 V VIN_LO Input low threshold level Input low threshold level for SDA and SCL VDDI O*0.25 V VIN_HI Input high threshold level Input high threshold level for SDA and SCL VDDI O*0.75 V ILKG_HILVL leakage current SDA and SCL, high level 1 μA

2.4.6 Input Currents

Table 13: Input Currents Parameter Description Conditions Min Typ Max Unit Electrical Performance IBAT_HIZ_BUCK _ON_LDO_OFF Battery discharge current in Hi-Z mode, no LDOs enabled 0 °C < TJ < 60 °C VDD_PWR = 0 V or floating Hi-Z mode Buck switching No load 0.8 1.5 μA IBAT_HIZ_BUCK _ON_LDO0_ON Battery discharge current in Hi-Z mode, LDO0 enabled 0 °C < TJ < 60 °C VDD_PWR = 0 V Hi-Z mode Buck switching LDO0 enabled No load 1.6 μA IBAT_ACT_LDO 0_LDO1_ON Battery discharge current in Active Battery mode 0 °C < TJ < 85 °C VDD_PWR = 0 V Active Battery mode Buck switching LDO0 and LDO1 enabled I2C enabled VBAT_UVLO < VBAT < 4.65 V 2.5 μA

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 19 of 117 © 2023 Renesas Electronics Parameter Description Conditions Min Typ Max Unit IBAT_ACT_BUC K_ON_LDO_OFF Battery discharge current in Active Battery mode 0 °C < TJ < 85 °C VDD_PWR < VDD_PWR_UVLO Active Battery mode Buck switching LDO disabled I2C enabled MODE = low VBAT_UVLO < VBAT < 4.65 V 1.1 μA IBAT_SHIP Battery discharge current in Ship mode 0 °C < TJ < 85 °C VDD_PWR = 0 V Ship mode 2 200 nA IIN_BUCK_ON Supply current for control VOVP and VDD_PWR > VBAT + VSLP Buck switching 0.8 3 mA IIN_CHG_READ Y Supply current for control 0 °C < TJ < 85 °C VDD_PWR = 5 V Charge ready 1.5 mA

2.4.7 Power Path Management and Current Limit

Table 14: Power-Path Management and ILIM Parameter Description Conditions Min Typ Max Unit Electrical Performance IUSBSUSPEND Input current in USB suspend mode 2.5 mA VDROP_IN_TO_ VDD_SYS VDD_PWR - VDD_SYS VDD_PWR = 5 V IIN = 300 mA Includes ball resistance 125 170 mV IDDPWR_LIM_M AX Input Current limit Programmable Range MAX, 50 mA steps 600 mA IDDPWR_LIM_M IN Input Current limit Programmable Range MIN, 50 mA steps 50 mA IDDPWR_LIM_A CC_RNG_LO Current limit accuracy 50 mA to 100 mA -12 12 % IDDPWR_LIM_A CC_RNG_HI Current limit accuracy 100 mA to 600 mA -5 5 % VDDPWR_IIN_D WN DPM threshold At VDD_PWR, programmable range, 100 mV steps 4.2 4.9 V VDDPWR_IIN_D WN_ACC DPM threshold accuracy -3 3 %

2.4.8 Protection

Table 15: Protection Parameter Description Conditions Min Typ Max Unit Electrical Performance VBAT_SHRT_T HR Battery short circuit threshold Battery voltage falling VDD_PWR = 5 V 2 V VBAT_SHRT_H YS Hysteresis for VBAT_SHRT 100 mV IBAT_SHRT Battery short circuit charge current ITER mA VBAT_UVLO_T HR Battery under-voltage lockout threshold range Programmable range 100 mV steps VBAT falling 2.5 3 V VBAT_UVLO_A CC Default battery under-voltage lockout accuracy VBAT_UVLO = 2.5 V -3 3 % VBAT_UVLO_H YS Battery under-voltage lockout threshold hysteresis 200 mV VDDPWR_OVP VDD_PWR over-voltage protection threshold voltage VDD_PWR rising 5.35 5.55 5.75 V VDDPWR_OVP_ HYS Over-voltage protection hysteresis 100 mV tDEGLITCH_OV P Over-voltage protection recovery deglitch time VDD_PWR falling 32 ms VSLP Sleep entry threshold VDD_PWR - VBAT VDD_PWR falling 65 120 mV VSLP_HYS Sleep mode hysteresis VDD_PWR rising 80 130 200 mV TSHDN Thermal shutdown TJ 118 °C THYS Thermal shutdown hysteresis TJ 20 °C tDEGLITCH_TH_ SHDN Thermal shutdown deglitch time TJ rising 1 ms VDDPWR_UVL O_HYS VDD_PWR under-voltage lockout threshold hysteresis VDD_PWR falling 150 mV VDDPWR_UVL O_THR VDD_PWR under-voltage lockout threshold VDD_PWR rising 3.4 3.6 3.8 V

2.4.9 Pushbutton Timer

Table 16: Pushbutton Timer (RIN_N) Parameter Description Conditions Min Typ Max Unit Electrical Performance VRIN_N_LOLVL Low-level input voltage 0.3 V RPU_RIN_N Internal pull-up resistance 120 kΩ

2.4.10 Digital Outputs

Table 17: Digital Output Pins (SYS_FLT, PWR_FLT, and ROUT_N) Parameter Description Conditions Min Typ Max Unit Electrical Performance VOUT_LO Low level output threshold Sinking current = 5 mA 0.25*V DDIO V ILKG_TO_IN Leakage current into pin High impedance state 0 12 nA tINTR Interrupt pulse width SYS_FLT 128 μs tRST_D Reset pulse duration ROUT_N 400 ms

2.4.11 Buck Regulator

Table 18: Buck Parameter Description Conditions Min Typ Max Unit Electrical Performance RON_PMOS High-side on resistance 600 800 mΩ RON_NMOS Low-side on resistance 300 450 mΩ tSTART Start-up delay time From BUCK_EN = 1 to switching 3 ms ILIM_SW_PMOS SW current limit PMOS VFB_BUCK = 1.8 V 600 mA tOFF_BUCK Off time VFB_BUCK = 1.8 V 270 ns fSW_BUCK Switching frequency Continuous conduction mode 3 MHz ILIM_PMOS_SO FTSTART PMOS switch current limit during softstart 300 mA VOUT_FB_BUC K Buck output voltage range Programmable range, 50 mV steps (VOUT_FB_BUCK_HI > 1.9 V, VDD_BUCK > 2.7 V) 0.6 2.1 V VOUT_FB_BUC K_HI Buck output voltage range HI programmable range, 50 mV steps, VOUT_RANGE_HI = 1 1.3 2.1 V

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 22 of 117 © 2023 Renesas Electronics Parameter Description Conditions Min Typ Max Unit VOUT_FB_BUC K_LO Buck output voltage range LO programmable range, 50 mV steps, VOUT_RANGE_HI = 0 0.6 1.3 V VOUT_VBUCK_ OUT_ACC Buck output voltage accuracy VDD_BUCK = 5 V PFM mode IOUT = 10 mA VFB_BUCK = 1.8 V -2.5 0 2.5 % VOUT_LD1_BU CK DC output voltage load regulation VOUT = 1.8 V 100 mA < IOUT < 300 mA 0.01 %/mA VOUT_LD2_BU CK DC output voltage load regulation VOUT = 0.9 V 100 mA < IOUT < 300 mA 0.02 %/mA VOUT_LINE_BU CK DC output voltage line regulation VOUT = 1.8 V IOUT = 100 mA 0.1 %/V tSTARTUP_BUC K Softstart time VOUT = 1.8 V No load 50 μs tSTARTUP_L Softstart time VOUT = 0.9 V No load 25 μs

2.4.12 Battery Monitors

Table 19: Battery Monitors (VBAT_DIV and IMON) Parameter Description Conditions Min Typ Max Unit Electrical Performance AIMON_GAIN IMON current gain 1 mA/A IIMON VBAT IQ current increase with IMON enabled 0 A discharge current 4 μA IMON_ACC_HI IMON accuracy Discharge current range 100 mA to 1 A -20 20 % IMON_ACC_LO IMON accuracy Discharge current range 10 mA to 100 mA -40 40 % VIMON_MAX IMON maximum recommended voltage 2.5 V <VBAT< 4.7 V IIMON x RIMON 1.4 V RBAT_DIV Voltage divider resistance From VBAT_SNS to GND_DIV 150 kΩ VBAT_DIV1 Voltage 2.5 V < VBAT < 4.65 V 0 °C < TJ < 85 °C VBAT* 0.585 VBAT* 0.6 VBAT* 0.615 V VBAT_DIV2 Voltage 2.5 V < VBAT < 4.65 V 0 °C < TJ < 85 °C VBAT* 0.285 VBAT* 0.3 VBAT* 0.315 V

2.5 Thermal Characteristics

Table 20: Thermal Characteristics Parameter Description Conditions Min Typ Max Unit RTH_JA_A Junction-to-ambient thermal resistance JEDEC 8-layer pcb, no airflow 34 °C/W RPSI_JC Junction-to-case (top) thermal resistance ∆JT 0.5 °C/W RTH_JB Junction-to-board thermal resistance 1 mm from IC edge 10 °C/W RTH_JA_B Junction-to-ambient thermal resistance 25 mm x 25 mm pcb, 8- layer, no airflow 79 °C/W

3 Typical Performance Graphs

Unless otherwise noted, VBAT = 3.6 V, TA = 25 °C Figure 3: Buck Efficiency, VOUT = 1.8 V Figure 4: Buck Regulation, VOUT = 1.8 V Figure 5: Buck Efficiency, VOUT = 0.9 V Figure 6: Buck Regulation, VOUT = 0.9 V

4 Functional Description

4.1 Overview

In a typical application, DA9072 manages two power inputs: a battery at pin VBAT and a USB supply at pin VDD_PWR. The larger of these supplies feeds the unregulated system output voltage at pin VDD_SYS. VDD_SYS in turn is used as the input supply to the linear charger, buck, and LDOs. Due to its extremely low IQ (< 1 µA), the buck can remain always on as the primary system power rail without draining the battery excessively. When USB power is present, VDD_SYS is near 5 V and the linear charger is active. When USB power in not connected, VDD_SYS tracks the battery voltage. DA9072 actively manages this power path, reducing charging current and input current as necessary, and allowing VDD_SYS to draw current from both supplies during peak loads. The DA9072 includes multiple configurable protection features including battery and input over- current. All settings can be controlled by I2C, but stand-alone operation is also possible with features such as a pushbutton input timer, resistor programmable charge settings, and the MODE pin to enable and disable charging. As there are two input sources, DA9072 has multiple regions of operation, see Figure 20. VDD_PWR VBAT 5.5 V VDD_PWR UVLO (3.4 V) VBAT_UVLO (2.0 V to 3.0 V) POR 4.65 V 20 V OVP SLEEP ACTIVE POWER / CHARGING ACTIVE BATTERY, HiZ, or SHIP UVLO Figure 20: Regions of Operation

4.2 Battery-Powered Operation

Ship mode is an ultra-low leakage standby state that minimizes battery depletion while the product sits on the shelf. Typical battery current in Ship mode is 5 nA. There are two methods to enter Ship mode: 1. By register write: a. Disconnect VDD_PWR b. Set MODE pin high c. Set EN_SHIPMODE bit (register 0x000D[0]) = 0x1 DA9072 enters Ship mode immediately. Note: If VDD_PWR is plugged in, Ship mode entry is delayed until power is removed. 2. By pushbutton timer pin, RIN_N: a. Disconnect VDD_PWR b. Set MODE pin high c. Enable RIN_N control of Ship mode: set RIN_N_RST_REC (register 0x0010 [1:0]) = 0x01 d. Pull RIN_N pin low for longer than the reset period, set by RIN_N_PER_RST (register 0x0010 [7:6]) The IC enters Ship mode when RIN_N is released (internally pulled up). To exit Ship mode, apply VDD_PWR or toggle RIN_N low for longer than 50 ms. On waking from Ship mode, all pre-programmed OTP values are loaded.

4.2.1 Active Battery and High Impedance Modes

Under battery power there are two modes of operation, both controlled by the MODE pin. A rising edge on MODE puts DA9072 in Active Battery mode. In this mode, all functions are active. Conversely, a falling edge on MODE puts DA9072 into Hi-Z mode, intended to be used during system standby states with low power consumption. In Hi-Z mode, the following communication functions are placed in a high impedance state to reduce leakage from the battery:

I2C interface
SYS_FLT and PWR_FLT status outputs
watchdog timer (WD) All other functions and outputs remain active, with the exception of TSD. CAUTION The Thermal Shutdown function is not active in Hi-Z mode. Hi-Z mode should not be used in high power dissipation or heavy load conditions. Hi-Z mode can also be entered by setting the HZ_MODE bit (register 0x000D [1]) = 0x1; or by using RIN_N pushbutton by setting RIN_N_RST_REC (register 0x0010 [1:0]) = 0x2 and pulling RIN_N low for more than the RIN_N reset time (set by register RIN_N_PER_RST 0x0010 [7:6]). DA9072 exits Hi-Z mode at a MODE pin rising edge or when VDD_PWR is applied. When VDD_PWR is removed, DA9072 enters Active Battery mode regardless of the MODE pin state. The behavior of the MODE pin depends on whether VDD_PWR is connected, shown in Table 21. The MODE pin is internally pulled low.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 30 of 117 © 2023 Renesas Electronics Table 21: MODE Functionality VDD_PWR MODE = 0 MODE = 1 Disconnected Hi-Z mode (edge triggered) Active Battery mode Connected Charge enabled if CE_N = 0 Charge disabled if CE_N = 1 Charge disabled

4.2.2 Battery Protection

DA9072 includes several types of battery protection. The battery is protected during discharge from over-current conditions by the IBAT_DCHG function and from over-discharge conditions by the VBAT_UVLO (under-voltage lockout) functions. During charging, the temperature sense (TEMP_SNS) function protects against over-temperature, and highly accurate voltage regulation and charging current prevent over-voltage and over-current conditions.

4.2.2.1 VBAT Over-Current Protection

The battery discharge over-current protection threshold, IBAT_DCHG_RNG, is programmable from 0.55 A to 1.75 A by IDISCHG_OCP (register 0x0029 [4:2]). Over-current protection clamps the maximum battery current at the set threshold and is available in all modes of operation. Battery current starts to be limited approximately 150 mA below the protection clamp. When an over-current condition occurs during charging, safety timers and charge termination are suspended. In an over-current fault, a VBAT_OCP interrupt is generated at SYS_FLT pin and indicated by the event bit ISR_VBAT_OCP (register 0x0004 [2]). All battery current flows from VBAT to VDD_SYS. Therefore, set the IBAT_DCHG threshold higher than the maximum expected system current from VDD_SYS. However, if the threshold is set higher than the battery can support, battery voltage may drop below VBAT_UVLO before the current is limited. When the IBAT_DCHG function clamps the battery current, VDD_SYS droops. This may cause secondary fault conditions such as VDD_SYS UVLO.

4.2.2.2 VBAT Under-Voltage and Short Protection

The battery under-voltage protection threshold (VBAT_UVLO_THR) can be set from 2.5 V to 3.0 V by bits BUVLO (register 0x000E [2:0]). This should be set at or above the battery’s minimum discharge voltage specification. VBAT_UVLO protects the battery from over-discharge by disconnecting the discharge path when the battery voltage falls below the UVLO threshold. When a VBAT_UVLO occurs in battery powered modes (VDD_PWR not connected), the DA9072 outputs, including VDD_SYS, shut down and all registers are reset to their default PoR values. VBAT_UVLO generates an interrupt at SYS_FLT and is indicated by the ISR_VBAT_UVLO event bit (register 0x0004 [0]). With VDD_PWR connected, VBAT_UVLO is ignored, making pre-charge level charging available down to 0 V at VBAT. In this case, a separate fault condition applies: VBAT_SHORT. The VBAT_SHORT threshold is typically 2.0 V and is indicated by event bit ISR_VBAT_SHORT (register 0x0004[3]).

4.2.2.3 Battery Temperature Sensing

The TEMP_SNS function uses the battery’s NTC thermistor to monitor battery temperature. If the battery is too cold or hot, either the fast charge current (or target voltage) is reduced or charging is terminated. Table 22 summarizes what protective measures are taken in each temperature range.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 31 of 117 © 2023 Renesas Electronics Table 22: Battery Thermal Protection Measures Temperature Range Voltage at TEMP_SNS Charger Action Interrupt name TBAT < TLO VTEMP_SNS > VTEMP_LOR Charging terminated TS COLD TCOLD < TBAT < TCOOL VTEMP_LO > VTEMP_SNS > VTEMP_COOL Charge current = 0.5 * ICHG setting TS COOL TCOOL < TBAT < TWARM VTEMP_COOL > VTEMP_SNS > VTEMP_WARM Normal charging TWARM < TBAT < THI VTEMP_WARM > VTEMP_SNS > VTEMP_HI Target voltage (VBAT_CHG) reduced by 140 mV TS WARM THI < TBAT VTEMP_SNS < VTEMP_HI Charging terminated TS HOT VTEMP_SNS > VOFF_TEMP_SNS Temp sense disabled, Optional Fault TS OFF Setting the Resistor Divider The four temperature thresholds are fixed percentages of VTEMP, see Section 2.4.2. VTEMP is enabled in short pulses to allow the battery temperature to be monitored without drawing unnecessary current through the resistor divider. VTEMP is derived from the VDD_SYS voltage. The TEMP_SNS voltage is measured after a deglitch time of 10 msec, which precludes any need for filtering at TEMP_SNS. To avoid measurement error, no filter capacitance larger than 10 nF should be added to TEMP_SNS pin. Temperature monitoring can be disabled by TS_EN_CHG (register 0x0026 [0]) and TS_EN_DISCHG bits (register 0x0026 [1]), or by pulling TEMP_SNS above the VOFF_TEMP_SNS threshold (TS_OFF state). The TS_OFF state disables temperature sensing and can optionally be flagged as a fault condition by setting register bit TS_OFF_MODE (register 0x0026:[2]) = 0x1. When TEMP_SNS is pulled high to enter TS_OFF state, the state is latched until TEMP_SNS is disabled. Temp sense is disabled in Hi-Z mode. Each temp sense threshold generates an interrupt at SYS_FLT and each has an event bit at register SYS_ISR_1 (0x0004 [7:4]) and SYS_ISR_2 (0x0005 [6]). The battery NTC interfaces to the TEMP_SNS input through a resistive divider, see Figure 21. TEMP_SNS RHI VTEMP RLO VBAT NTC Figure 21: Battery Temperature Sensing with NTC The resistor divider values (RHI and RLO) are selected as shown below so that the cold and hot TEMP_SNS thresholds are reached at the corresponding NTC values.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 32 of 117 © 2023 Renesas Electronics Equation 1: 𝑅(𝐿𝑂) = 𝑅(𝐶𝑂𝐿𝐷) × 𝑅(𝐻𝑂𝑇) × ( 1 0.398 − 1 0.15) 𝑅(𝐻𝑂𝑇) × ( 1 0.398 − 1) Equation 2: 𝑅(𝐻𝐼) = ( 1 0.398 − 1) ( 1 𝑅(𝐿𝑂) + 1 𝑅(𝐶𝑂𝐿𝐷) Where

R(HOT) = the NTC resistance at the hot temperature
R(COLD) = the NTC resistance at the cold temperature The cool and warm thresholds are not independently programmable and are fixed once the cold and hot values are determined. The cool and warm thresholds can be determined by the NTC value at the threshold: Equation 3: 𝑅(𝐶𝑂𝑂𝐿) = 𝑅(𝐿𝑂) × 𝑅(𝐻𝐼) × 0.35 𝑅(𝐿𝑂) − 𝑅(𝐿𝑂) × 0.35 − 𝑅(𝐻𝐼) × 0.35 Equation 4: 𝑅(𝑊𝐴𝑅𝑀) = 𝑅(𝐿𝑂) × 𝑅(𝐻𝐼) × 0.205 Where
R(COOL) = the NTC resistance at the cool temperature
R(WARM) = the NTC resistance at the warm temperature Temp Sense Modes of Operation The DA9072 provides two modes of battery temperature sense control: Auto mode and Host Control mode. In Auto mode, the DA9072 enables the VTEMP voltage every 2 s or every 50 ms depending on the VDD_PWR state. At the start of each cycle, the VTEMP voltage is activated for 10 ms after which the TEMP_SNS voltage is checked. This timing is shown in Figure 22. Auto mode does not rely on the host to operate; therefore, it is ideally suited to provide continuous safety monitoring. In battery powered operation, VTEMP is enabled for only 0.5 % of the time which reduces the typical current required for temperature sensing to less than 1 µA. While VDD_PWR is applied, the Temp Sense function is in Auto mode and host control of the VTEMP period is not available. This is illustrated in the Active Power section of Figure 22. If lower current consumption is needed, temperature sensing can be controlled by the host. In host- controlled mode, an I2C command activates the same 10 ms VTEMP and TEMPS_SNS cycle.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 33 of 117 © 2023 Renesas Electronics 10 ms 10 ms TEMP_SNS update VTEMP active I2C Trigger TEMP_SNS active TEMP_SNS update Host Controlled Mode 10 ms TEMP_SNS update 50 ms 10 ms 10 ms TEMP_SNS update VTEMP active Auto-mode Period TEMP_SNS active TEMP_SNS update Active Power (Charging) 50 ms 2 s 10 ms 10 ms TEMP_SNS update VTEMP active Auto-mode Period TEMP_SNS active TEMP_SNS update Active Battery (Discharging) 2 s Figure 22: Battery Temperature Sense Timing

4.3 Analog Battery Monitor Functions

DA9072 incorporates two features to support accurate fuel gauging: battery discharge current monitor (IMON) and battery voltage (VBAT_DIV). These provide analog discharge current and battery voltage information scaled for compatibility with typical ADC inputs. CAUTION Filter capacitors on IMON and VBAT_DIV should not be used, or should be minimized, in order to minimize any time lag when using these outputs for fuel gauging.

4.3.1 Battery Discharge Current Monitoring

The IMON function sources a current proportional to the battery discharge current at a 1 mA/A scale. An external resistor from pin IMON to GND should be selected to optimize the dynamic range based on battery current range and maximum tolerance of both DA9072 and the ADC inputs. To maintain accuracy, a maximum voltage of 1.4 V is allowed at the IMON pin. The IMON function is enabled and disabled by bit IDISCHG_MON_EN (register 0x002A [1]). When enabled, the function draws an additional 4 µA of quiescent current from VBAT.

4.3.2 Battery Voltage Monitoring

VBAT. Use the dedicated ground at GND_DIV as the reference point for the VBAT_DIV output. This is ideal for driving the differential input of an external ADC in battery monitoring functions. disconnected from VBAT to eliminate current drain.

4.4 Battery Charging

4.4.1 Battery Charging Process

Table 24. Charging is enabled and disabled by the MODE pin and CE_N bit (register 0x0020:[0]). This status is indicated by the STS_CHG bits (register 0x0002 [5:4]). value and change the value immediately when the charge status changes. pulled low. There is approximately 2.5 ms delay between enabling charging and charge starting. and constant voltage (CV). These regions are shown in the typical charging example of Figure 23. ready to charge in-progress to charge done states.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 35 of 117 © 2023 Renesas Electronics Figure 23: Typical Charging Example Note 1 70 mAh Charge Cycle (VCHG_PRE = 3.0 V, ICHG_PRE = 7 mA, ICHG = 70 mA, VTER = 4.2 V)

4.4.2 Charge in Progress

Assuming a depleted battery, the battery is initially charged at ICHG_PRE until VBAT reaches the pre- charge threshold, at which point the charge current is increased to ICHG. The charger continues to charge at constant current (CC) until VBAT approaches the target voltage programmed by VBCHG (register 0x0024:[6:0]). The battery is then charged at near constant voltage (CV) and the charge current gradually falls. Charging ends when the charge current falls below ITER (ITER current is the same as ICHG_PRE, see Section 4.7.1). If the VDD_PWR remains connected, recharging starts when VBAT falls below the recharge threshold, VBAT_CHG - 120 mV (typical). Charging modes are shown in Table 25. Table 25: Charging Modes VBAT Voltage Charge Current Charge Mode Pre-Charge Timer Main Timer VBAT < VCHG_PRE ICHG_PRE Pre-charge Running Running VCHG_PRE < VBAT < VBAT_CHG ICHG CC (fast charge) Reset Running VBAT = VBAT_CHG < ICHG CV Reset Running VBAT = VBAT_CHG = ITER Termination Reset Reset From the charge ready state, the device enters charge in-progress state when all conditions below are met.

VDD_PWR > VBAT + VSLP (not in Sleep mode)
VBAT < VRCHG
RMEAS sequence completed, if enabled by RMEAS_EN (register 0x0020 [1])
50 ms TEMP_SNS delay, if periodic sampling is enabled by TS_DISCHG_MODE_SEL (register 0x0026 [5])
MODE input is pulled low and CE_N register is set to 0 If these conditions are met, charging starts automatically at the appropriate level when VDD_PWR is connected.

4.4.3 Pre-Charge and Termination Current

In Pre-Charge mode, a constant low-level charge current is supplied to the battery, up to 50 mA. Termination current is the charge current in CV mode at which charging is terminated. Both pre- charge current and termination current are identical and cannot be controlled independently. The current setting is selectable by the IPRETERM bits (register 0x0023 [6:0]) within a range of 0.5 mA to 50 mA. Pre-charge and termination currents can also be set by an external resistor connected to the ITER_CHG pin. Charge termination can be disabled by setting the termination enable bit, TE (register 0x0021 [4]) = 0. TS_WARM (register 0x0021 [5]) and TS_COOL (register 0x0021 [6]) conditions can also optionally disable termination. This may be useful in conditions where the available charging current is reduced due to system load, or when charge current is reduced due to fault conditions. The pre-charge-to-fast-charge threshold voltage is programmable between 2.7 V and 3.2 V via BPRECHG bits (register 0x0025 [2:0)]. The threshold has 200 mV of hysteresis. When VBAT rises above the pre-charge threshold voltage, fast charging begins. Pre-charging is indicated by an SYS_FLT interrupt and ISR_PRECHG event bit (register 0x0005 [2]).

4.4.4 Fast Charge Current

In Fast Charge mode, a constant charging current is supplied to the battery at up to 500 mA. Fast charge current is selectable by the ICHG bits (register 0x0022 [6:0]). This can also be set by an external resistor connected to ILIM_CHG pin. Charge current is programmable from 5 mA to 500 mA with an accuracy of +/-5 % over the full range. Fast charge current settings down to 2 mA are available with some OTP variants. When VBAT reaches VBAT_CHG the device ends CC fast charge operation and starts CV operation.

4.4.5 CV Voltage Regulation and Termination

CV mode begins when the battery voltage rises into the regulation range. The regulated battery voltage, VBAT_CHG, is set between 3.6 V and 4.65 V by the VBCHG bits (register 0x0024 [6:0]. Regulation accuracy is +/-0.5 % in CV mode. When the DA9072 enters CV mode, charge current begins gradually decreasing, while battery voltage remains regulated at VBAT_CHG. When charge current drops to the termination current level, charging is terminated and the charge status, STS_CHG, changes to charge done. Charge done is indicated by an SYS_FLT interrupt and event bit ISR_CHG_DONE (register 0x0005 [3]). To ensure that the charging current is below the termination level, termination does not occur until the peak current is below the threshold. In noisy conditions or at very low termination currents, the average battery current at termination may be a few mA below the set threshold.

4.4.6 Charge Done and Recharge

To prevent rapid iterations of charging and discharging from the charge done state, there is 120 mV of hysteresis below the CV regulation level, VRCH. Charging does not restart until VBAT falls below this threshold. In addition, there is a 32 msec deglitch time for noise immunity. Recharging starts automatically, when VBAT falls below the VRCH threshold. Recharging is indicated by an SYS_FLT interrupt and event bit ISR_RECHG_START (register 0x0005 [4]).

4.4.7 Charge Faults

The DA9072 identifies multiple conditions as charge faults, indicated by the STS_CHG status bits (register 0x0002 [5:4]). These conditions may reduce the charge current, reduce the target battery voltage, or take other actions. All are indicated by an interrupt and event bit. When the charger is unable to provide the programmed charge current to the battery, such as when VDD_PWR is in current limit, the termination current is ignored and charging is allowed to continue until the safety timer expires. All of the fault and event interrupts that affect charging are summarized in Table 26.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 37 of 117 © 2023 Renesas Electronics VBAT_UVLO and VBAT_SHORT are included in the table although they are not indicated as faults when VDD_PWR is present. Normal pre-charging continues in both cases. Table 26: Charge Faults Fault Charging Action STS_CHG Termination Safety timer VDD_PWR OVP Suspend VDD_PWR open Fault - Reset VDD_PWR UVLO Suspend VDD_PWR open Fault - Reset VDD_PWR DPM Continue VDD_PWR current limit decreased Fault Disable x2 VDD_PWR ILIM Continue VDD_PWR current limited Fault Disable x2 VBAT DPPM Continue Charge current reduced Fault Disable x2 VBAT OCP Suspend VBAT current limited Fault - Suspend Sleep mode Suspend Fault - Suspend Supplement mode Suspend Battery discharging Fault - Suspend TS COLD Suspend Fault - Suspend TS HOT Suspend Fault - Suspend TS COOL Continue Charge current reduced to half In- progress Disable x2 TS WARM Continue VBAT_CHG reduced by 140 mV In- progress Disable x1 TS OFF (fault option) Suspend Fault - Reset Safety timer Suspend Fault - Reset Over-temp. Suspend Fault - Reset VDD_SYS UVLO Suspend Power cycle Fault Reset VBAT Short Pre-charge In- progress x1 There are several option bits available to modify the fault behavior described above. Termination can be enabled during TS_WARM and TS_COOL, a TS_HOT fault can trigger a power cycle, and a TS_OFF condition can trigger a fault or simply disable the battery Temp Sense feature.

4.4.8 Safety Timers

The safety timer starts counting as soon as a charge cycle begins, ensuring that the charge cycle is terminated even if the battery fails to reach the termination condition. The duration of the timer, tMAXCHG, is set by bit TMR (register 0x0021 [1:0]) between 30 minutes and 9 hours. If the safety timer expires before charging is terminated, SYS_FLT toggles, and the ISR_CHG_TMR event bit (register 0x005 [5]) is set to 1. In Pre-Charge mode, the timer period is 10 % of the safety timer setting. The pre-charge timer counts during pre-charging and is reset at the transition to Fast-Charge mode. If the charger is still in pre- charge at the end of the pre-charge timer period, the charge cycle is terminated. The main safety time is running during both fast charge and pre-charge modes.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 38 of 117 © 2023 Renesas Electronics To reset the safety timer and resume charging after the timer has expired, toggle the MODE pin or the CE_N bit (register 0x0020 [0]), or remove and re-connect VDD_PWR. Charge faults may cause the timer duration to be doubled, suspended, or reset, see Table 27. The timer doubling function can be doubled using the TMRX2_EN bit (register 0x0021:[3]). Table 27: Safety Timer Register Settings (0x0021) TMR Pre-Charge Timer Main Timer 0x0 3 min 30 min 0x1 18 min 3 h 0x2 54 min 9 h 0x3 (Disable) (Disable)

4.5 USB Powered Operation and Power Path Management

The DA9072 monitors battery voltage and current as well as VDD_PWR input voltage and current during all modes of operation. At all levels of operation, the appropriate charge current is maintained while protecting the battery, system connections, and the input supply from over-voltage and over- current and other potential fault conditions. The DA9072 power path management features ensure smooth transitions from charging, to reduced charging, to battery supplementing the load during load peaks.

4.5.1 Under-Voltage Lockout

The UVLO threshold for VDD_PWR is 3.6 V (typical). Below this voltage, VDD_PWR is disconnected from the power path and DA9072 is in battery powered operation. VDD_PWR UVLO causes SYS_FLT to toggle and sets event bit ISR_VDD_PWR_UVLO (register 0x0003 [1]) = 1. The UVLO threshold has typically 150 mV of hysteresis on the rising edge. When VDD_PWR rises above this threshold, charging is re-enabled. UVLO recovery also toggles the SYS_FLT interrupt and sets the UVLO recovery event bit.

4.5.2 Sleep Mode

Sleep mode behavior is similar to UVLO, but the falling threshold is relative to VBAT. When VDD_PWR falls within 65 mV (typical) of VBAT, Sleep mode is activated. In Sleep mode, VDD_PWR is disconnected from the power path, SYS_FLT toggles, and event bit ISR_SLP (register 0x0005 [0]) = 1. When VDD_PWR falls into the range of Sleep mode, DPPM mode is already active (VDD_PWR < VBAT_CHG) and the charge current is already reduced to zero, see Section 4.5.5.

4.5.3 VDD_PWR Current Limit

The VDD_PWR current limit (IDDPWR_LIM) feature protects both the DA9072 and the USB supply from excessive current. The current limit threshold is programmable from 50 mA to 600 mA in 50 mA steps via bits ILIM (register 0x0027 [3:0]. When the input current reaches the set threshold, VDD_PWR current is clamped and event bit ISR_VDD_PWR_ILIM (register 0x0003 [4]) = 0x1. If the load at VDD_SYS increases the VDD_SYS voltage drops, eventually triggering a VDD_SYS UVLO. The dynamic power management (DPM) function, when enabled, reduces the current limit threshold as USB input voltage is reduced.

4.5.4 Input Voltage Dynamic Power Management

If the charge current and system load exceed the current capability of the VDD_PWR input source, the input voltage drops. Dynamic power management (DPM) prevents the input from dropping below the nominal USB range and into Dynamic Power Path mode (DPPM) by scaling down the VDD_PWR current limit (IDDPWR_LIM) until it matches current capability of the USB source.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 39 of 117 © 2023 Renesas Electronics This feature becomes active when VDD_PWR falls below VDDPWR_IIN_DWN, which is programmable between 4.2 V and 4.9 V by bit VDD_PWR_DPM (register 0x0028:[2:0]). The DPM feature can be disabled by setting bit VDD_PWR_DPM_DIS (register 0x0028 [4]) = 0x1. However, when DPM is disabled, the USB power source may be pulled down, triggering Sleep mode or input UVLO. The event bit ISR_VDD_PWR_DPM (register 0x0003 [3]) is set to 0x1 and the SYS_FLT pin toggles whenever the DA9072 is in this current-limited mode. In Charging mode, termination is ignored to allow the battery to be charged with any remaining current.

4.5.5 Dynamic Power Path Mode

Dynamic Power Path mode (DPPM) manages the situation in which the total charging and system current exceeds the VDD_PWR current limit. When the input current is clamped, VDD_SYS drops until it reaches VDD_SYS_THR_DPPM (DPPM threshold). In DPPM, charging current is reduced to service the system current at VDD_SYS. DPPM is only active during charging and toggles SYS_FLT and set an interrupt bit ISR_VBAT_DPPM (register 0x0004 [1]) = 0x1. If VDD_SYS drops further due to increasing load, the DA9072 eventually enters Battery Supplement mode.

4.5.6 Battery Supplement Mode

The DA9072 enters Battery Supplement mode when VDD_SYS falls below VBAT. Battery Supplement mode occurs in USB powered operation, regardless of whether the battery is charging or not. Similar to DPPM mode, the total current at VDD_SYS exceeds the VDD_PWR current limit, causing VDD_SYS to drop until it reaches the VBAT voltage. In this mode, the battery supplies current to VDD_SYS, thus supplementing the input current to supply the system demands. In Battery Supplement mode, the discharge current from the battery is limited by the over-discharge protection. Battery Supplement mode toggles the SYS_FLT pin and sets an event bit ISR_BAT_SPPL (register 0x0005 [1]) = 0x1. The device exits Battery Supplement mode when the system load is reduced and VDD_SYS rises above VBAT.

4.5.7 Input Over-Voltage Protection

The DA9072 protects itself (and downstream connections to VDD_SYS) against input over-voltage conditions by disconnecting VDD_PWR from the power path. Over-voltage protection (OVP) kicks in immediately when VDD_PWR exceeds the OVP threshold. Over-voltage events are common at USB plug-in due to the inductance of the long cable, where the transient overshoot may exceed 10 V depending on cable length, quality, and input capacitance. The VDD_PWR input is capable of withstanding up to 20 V and remains in OVP until the voltage returns to nominal levels. During OVP, VDD_PWR is disconnected from the power path and DA9072 is in normal battery powered operation. When an over-voltage occurs, the event bit ISR_VDD_PWR_OVP (reg 0x0003 [0]) = 0x1 and SYS- FLT toggles.

4.5.8 VDD_PWR Input Supply Impedance

The DA9072 charging path is typically supplied by a 5 V USB source. USB cable resistance can range from hundreds of milliohms to ohms. At higher charging currents, this parasitic input impedance may cause VDD_PWR to drop from 5 V into the DPM range. High USB cable resistance can lead to oscillations in DPM or Sleep mode. As VDD_PWR drops, the DA9072 attempts to reduce current demand, which in turn causes VDD_PWR and current draw to increase again. Follow the guidelines in Figure 24 to ensure that the DA9072’s internal hysteresis is be sufficient to overcome these effects. The worst case is at highest battery voltage, the VBAT_CHG regulation point. It is recommended to always enable the DPM function, with the threshold set at least 0.4 V above the VBAT_CHG voltage. Referring to Figure 24, with a DPM setting of 4.5 V and VBAT = 4.2 V, the system has the potential to oscillate at any current greater than 75 mA. Note that this would only

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 40 of 117 © 2023 Renesas Electronics occur if VDD_PWR drops into the DPM or sleep region. For this example, a DPM setting of 4.6 V or 4.7 V is recommended for currents above 75 mA. Note Figure 24: VDD_PWR DPM Setting Recommendations (Based on Typical USB Cable Impedance)

4.6 Power Cycling

The power cycle function disables all outputs (buck, and LDOs) for a programmable time period and then restarts. Power cycling can be initiated by a fault condition, RIN_N pushbutton, VDD_PWR insertion, or I command. The primary purpose of power cycling is to clear a serious fault condition such as IC over-temperature (OVT) or to reset the host.

4.6.1 Requested Power Cycle

The power cycle settings are configured at by SYS_PWR_CYC_0 (register 0x0012). There are three methods to request a power cycle: by register write to PWR_CYC_FRC, by holding the RIN_N push button low for the reset period, or by inserting and removing VDD_PWR. The setting options are summarized in Table 28. Table 28: Power Cycle Trigger Settings PWR_CYC_EN 0x0012 [0] PWR_CYC_MODE 0x0012 [1] RIN_N RESET Wake-Up Timer VDD_PWR Insertion / Removal PWR_CYC_FRC 0x0012 [2] 0x0 N/A Disable Disable Disable 0x1 0x0 Disable Enable Enable 0x1 0x1 Enable Disable Enable After any of these three host or user-initiated power cycles the buck and LDO outputs are disabled. When auto-restart occurs, only the buck restarts. All register settings are preserved at restart with the exception of the output enable registers. There is also a READ clear event bit STS_PWR_CYC (register 0x0002 [1]) to indicate that a power cycle has occurred.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 41 of 117 © 2023 Renesas Electronics Two timers apply to power cycling: the wait timer and the period timer. The wait time allows the host to take action before power is shut down and can be set between 0 s and 2 s. The period timer controls how long the outputs are powered down before restart and can be set between 5 s and 20 s. Both timers are programmable, the wait timer by PWR_CYC_WAIT_PER (register 0x0012 [7:6]) and the period timer by PWR_CYC_PER (register 0x0012 [5:4]). The power cycle timing using the RIN_N pushbutton is shown in Figure 25. The RESET time is set by bits RIN_N_PER_RST (register 0x0010 [7:6]). The RIN_N push button timer can be used for power cycling only when VDD_PWR is present. RIN_N SYS_FLT ROUT_N tINTR tRST_D tWAKE2 tWAKE1 (don t care) LDOx tINTR tINTR tRESET tWAIT tPERIOD Buck Figure 25: Power Cycle by Push Button Timer Alternately, the VDD_PWR plug can be used to initiate a power cycle as shown in Figure 26. VDD_PWR must go low and high three times within 8 s. After the 8 s period, the power cycle begins. VDD_PWR (case 1) SYS_FLT ROUT_N tRST_D LDOx tINTR < 8 sec tPERIOD UVLO tWAIT UVLOVDD_PWR (case 2) >150ms >150ms Buck Figure 26: Power Cycle by VDD_PWR Insertion The force power cycle bit PWR_CYC_FRC (register 0x0012 [2]) follows the same power cycle period and behavior but does not impose any wait time; power cycle shutdown occurs immediately.

4.6.2 Fault Triggered Power Cycle

The DA9072 also initiates a power cycle in response to various fault conditions, listed in Table 29. Those not listed as always on trigger a power cycle only if that option is enabled. Fault triggered power cycles are intended to protect the system from a potentially damaging condition. The behavior is different to a user-initiated power cycle. When a fault triggered power cycle occurs, the wait time is skipped and all outputs are shut down immediately. When the power cycle period ends, the initial OTP register values are re-loaded at restart, including any outputs that are enabled by default.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 42 of 117 © 2023 Renesas Electronics A fault triggered power cycle also disables VDD_SYS, creating a complete power system restart (a host or user-initiated power cycle does not disable VDD_SYS). Table 29: Power Cycle Faults Power Cycle Fault Triggers 0x0013 Register Bit I2C Selectable Register Reset Battery Temp Sense HOT 0 YES YES Thermal Shutdown (OVT) NA Always On YES VBAT UVLO (in Active Battery mode) NA Always On YES VDD_SYS UVLO NA Always On YES There are also three power cycle faults associated with the buck, listed in Table 30. Any of these faults cause an immediate power cycle. Buck faults do not re-load the OTP register values and only the buck restarts after a buck fault power cycle. Table 30: BUCK Power Cycle Faults Power Cycle Fault Triggers 0x0013 Register Bit I2C Selectable Register Reset BUCK OCP 4 YES NO BUCK OVP NA Always On NO BUCK UVP 6 YES NO

4.7 Standalone Mode

The DA9072 can operate without I2C communication using external resistors to program three settings. Fast charge current, input current limit, and termination and pre-charge current can be set by external resistors at the ITER_CHG, ILIM_PWR and ILIM_CHG pins, respectively. This feature is enabled by the RMEAS_EN bit (register 0x0020 [1]). Whenever VDD_PWR is plugged-in, these three external resistors are evaluated and the control registers are set appropriately. If the pins are connected to ground the internal register values are used. If used, all three resistors must be installed. If any of the three pins are grounded all three currents are determined by their respective register values. The specification of RMEAS_EN register is described in Table 31. Table 31: Enabling External Resistor Setting Mode RMEAS_EN (0x0020 [1]) External Resistance [Ω] Setting

0 N/A Register settings used

1 0 Register settings used 1 > 0 Calculated from external resistance

4.7.1 Termination and Pre-Charge Current Programming

The pre-charge (ICHG_PRE) and termination (ITER) currents are the same value and set with the same resistor. When using the external resistor setting method, they can be set to 5 %, 10 %, 15 %, or 20 % of the fast charge current, ICHG.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 43 of 117 © 2023 Renesas Electronics Connect a resistor (RITER_CHG) from the ITER_CHG pin to ground. Table 32 shows the recommended resistor values to set the pre-charge and termination currents. Table 32: ITER_CHG Pin Recommended Resistor Values % of ICHG (Typ) Resistance (kΩ) 5 68 10 22 15 8.2 20 2.2 Register setting at 0x0023 is used 0 Once VDD_PWR is connected, ICHG_PRE and ITER values can be read at register 0x0020 [5:4]. ICHG_PRE cannot be set higher than 50 mA, or lower than 0.5 mA. Settings which are out of range result in the minimum or maximum current setting. For example, with a 400 mA fast charge current, a 20 % setting would result in 80 mA, but the actual pre-charge current is the maximum value, 50 mA.

4.7.2 Input Current Limit Programming

VDD_PWR input current limit (IDDPWR_LIM) is programmed by a resistor connected from the ILIM_PWR pin to ground. The resistor value is calculated as: 𝑅𝐼𝐿𝐼𝑀_𝑃𝑊𝑅(Ω) = 1000 𝐼𝐷𝐷𝑃𝑊𝑅_𝐿𝐼𝑀(𝐴) Not all current limit register settings are available in Resistor Setting mode. The available current limit settings and corresponding resistor values are shown in Table 33. Table 33: ILIM_PWR Pin Recommended Resistor Values IDDPWR_LIM (Typ) Resistance (kΩ) Register setting at 0x0027 is used 0 600 mA 1.6 500 mA 2.0 400 mA 2.7 300 mA 3.6 200 mA 5.1 150 mA 6.8 100 mA 10.0 50 mA 20.0

4.7.3 Charge Current Programming

Fast charge current (ICHG) is programmed by a resistor connected from the ILIM_CHG pin to ground. The resistor value is calculated as: 𝑅𝐼𝐿𝐼𝑀_𝐶𝐻𝐺(Ω) = 1000 𝐼𝐶𝐻𝐺(𝐴) Not all fast charge register settings are available. The available current limit settings and corresponding resistor values are shown in Table 34. Table 34: ILIM_CHG Pin Recommended Resistor Values ICHG (Typ) Resistance (kΩ) Register setting at 0x0022 is used 0 500 mA 2.0 400 mA 2.7

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 44 of 117 © 2023 Renesas Electronics ICHG (Typ) Resistance (kΩ) 300 mA 3.6 200 mA 5.1 150 mA 6.8 100 mA 10.0 70 mA 15.0 50 mA 20.0 40 mA 27.0 30 mA 36.0 20 mA 51.0 15 mA 68.0 10 mA 100.0 7 mA 150.0 5 mA 200.0

4.8 Host and Pushbutton Communication

The DA9072 features multiple digital pins for host and user communication, see Table 35, with connections shown in Figure 27. Table 35: Digital Pins for Host and Pushbutton Interface Pin Name Description SCL / SDA I2C interface MODE Mode control input Used to enter Hi-Z mode and control charging (Edge triggered for Hi-Z control; level triggered for charge control) RIN_N Pushbutton interface Used to wake up from Ship mode and Hi-Z mode Also used to generate a low-active reset pulse on ROUT_N SYS_FLT IRQ interrupt output flag Also functions as a charging status indicator PWR_FLT Power input status flag Can also be configured as a voltage shifted RIN_N output ROUT_N Host reset output which is controlled by RIN_N WD Watchdog input

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 45 of 117 © 2023 Renesas Electronics DA9072 Host SCL MODE ROUT_N SYS_FLT PWR_FLT RIN_N (always-on) WD SDA Figure 27: Digital Pin Connections

4.8.1 Watchdog Input and Timer

A programmable watchdog timer, WD, is available to detect a stall in the host. The WD function is enabled or disabled by bit WD_EN (register 0x0014 [1:0]). Each time the host initiates I2C or toggles the watchdog input, the timer resets. If no host activity is detected within the timeout period, the DA9072 toggles the SYS_FLT flag and sets the WD event bit, ISR_WD (register 0x0007 [4]), to 1. If the register reset on timeout option is enabled, bit WD_RST_REGS_EN (register 0x0014 [7]) the outputs are disabled for a period of typically 20 msec and then re-enabled to reset the host. The watchdog is automatically re-activated and the pre-programmed OTP values are loaded (except for RIN_N_RST_ROUT_EN and RIN_N_RST_REC at register 0x0010 [3:0]). The watchdog timeout period, tWATCHDOG in Figure 28, is programmable to 25 s or 50 s via WD_TMR_PER (register 0x0014 [5:4]). Optionally, the WD function can also toggle the ROUT_N pin, this is enabled by WD_ROUT_EN (register 0x0014 [6]). The WD_EN bits (register 0x0014 [1:0]) selects when the watchdog timer is enabled in different modes, see Table 36. Table 36: Watchdog Timer Enable Settings for Different Modes WD_EN Charge Mode Active Battery Mode Hi-Z Mode 0x00 Disable Disable Disable 0x01 Enable Disable Disable 0x02 Enable Enable Disable 0x03 Enable Enable Enable The WD_CLR_SEL bits (register 0x0014 [3:2]) select which activity the WD uses to clear the timer, see Table 37. Table 37: Watchdog Timer Clear Settings WD_CLR_SEL Description 0x00 Only I2C clears the timer 0x01 Only WD pin clears the timer 0x02 Both I2C and WD pin clear the timer 0x03 Reserved

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 46 of 117 © 2023 Renesas Electronics Figure 28 shows how to periodically feed the watchdog and what happens when the processor stalls. VBAT_UVLO_THR BAT SYS I2C WD Battery connected Buck enabled Watchdog activated tWATCHDOG tWATCHDOG tWATCHDOG tWATCHDOG tWATCHDOG tWATCHDOG tWATCHDOG Watchdog toggled tWATCHDOG tWATCHDOG tWATCHDOG tWATCHDOG Watchdog time-out Buck disabled Watchdog re-actived Buck re-enabled Host stalls Figure 28: Watchdog Behavior

4.8.2 VDDIO

VDDIO is the I/O supply rail for DA9072. I2C communication (SDA, SCL), MODE, WD, ROUT_N, SYS_FLT, and PWR_FLT pins are all referenced to the VDDIO level. VDDIO is an input pin, which can be supplied with any voltage between 1.4 V and 3.3 V as required to interface with the host. However, the VDDIO voltage must not be higher than the VDD_PWR and VBAT voltages. Therefore, it is recommended to use the buck or LDO output to supply VDDIO. The VDDIO pin should be bypassed with a 1 µF capacitor, placed close to the pin and grounded to AGND.

4.8.3 Interrupt Events and Status Control

DA9072 has an interrupt interface for 35 individual events. Some of these events are categorized as charge fault events, see Section 4.4.7. There is a read-only event bit for each interrupt in the SYS_ISR_<n> registers 0x0003 through 0x0007. A high state indicates that an event has occurred. The bit is kept in a high state, even if the fault condition is removed, until the bit is cleared. These are read-to-clear bits which are read once to identify the event and read a second time to reset the bit to 0. The DA9072 provides two open drain output pins to indicate system status and interrupts, SYS_FLT and PWR_FLT. These should be pulled up to VDDIO with a 1 kΩ to 100 kΩ resistor. Both pins have configuration options, set by PWR_FLT_MODE (register 0x0011 [4]) and SYS_FLT_MODE (register 0x0011 [0]). The PWR_FLT output can be configured as an indicator of the VDD_PWR status, or as a level- shifted RIN_N monitor, see Figure 29 and Figure 30. When used as a level shifted RIN_N monitor, there is a typical delay of 1.5 ms between RIN_N and PWR_FLT signals. In the case of VDD_PWR status indicator, PWR_FLT goes low only when VDD_PWR is within a valid range. In both cases a high state is high impedance. RIN_N PWR_FLT Figure 29: PWR_FLT Configured as RIN_N Monitor

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 47 of 117 © 2023 Renesas Electronics VDD_PWR VVDD_PWR_OVP PWR_FLT VVDD_PWR_UVLO Figure 30: PWR_FLT Configured as VDD_PWR Status Indicator The SYS_FLT output indicates interrupt events with a 128 µs pulse and can be configured to indicate charging in progress. SYS_FLT is configured by SYS_FLT_MODE (register 0x0011 [0]), see Table 38. Table 38: SYS_FLT Configuration SYS_FLT_MODE Setting Charge Indicator IRQ Interrupt Polarity

0 Disabled Active-low

1 SYS_FLT low when charge in

Active-low when charge is not in-progress Active-high when charge is in-progress The SYS_FLT interrupt flag can be masked for each individual interrupt by setting its mask bit to 1. Mask registers, SYS_IMR_<n>, are at registers 0x0008 through 0x000C. Masking an interrupt masks the SYS_FLT flag but does not mask the event bit. Once an interrupt has occurred, the SYS_FLT flag does not toggle a second time for the same interrupt. The event bit must first be read cleared before SYS_FLT responds to that event again.

4.8.4 Pushbutton Reset Timer and Reset Output

The RIN_N input can be used to manually control DA9072 in Ship mode, Hi-Z mode, or when the host has stalled. The pin has three functions: enter/exit Ship mode, enter Hi-Z mode, and toggle the ROUT_N reset output. RIN_N is active in all modes of operation. The pin is internally pulled high and can be pulled directly to ground with an external pushbutton to activate the timer. When RIN_N is pulled low, a reset timer begins counting. There are three programmable RIN_N timers; each associated with an event bit. Each time the RIN_N timer passes the programmable count the SYS_FLT flag toggles, and a WAKE event bit is set. In this way, requests to the host can be generated by pressing the button for different durations. The first two timers are WAKE1 and WAKE2; the third timer is the RESET timer. If RIN_N is held low for the set RESET time, the DA9072 can be set to enter Ship mode, enter Hi-Z, or initiate a power cycle. The WAKE and RESET periods are set as shown in Table 39. Table 39: RIN_N Pushbutton Wake-Up Timer Control Timer Name Timer Control Bits Programmable Period WAKE1 RIN_N_PER_WAKE1 0x0010 [4] 50 ms 500 ms WAKE2 RIN_N_PER_WAKE2 0x0010 [5] 1.0 s 1.5 s RESET RIN_N_PER_RST 0x0010 [7:6] 4 s 8 s 10 s 14 s The timer status bits,ISR_RIN_N_WAKE2, ISR_RIN_N_WAKE1, and ISR_RIN_N_RST, are at 0x0007. As with all other events, the SYS_FLT flag can be masked. The RIN_N timing is described in Figure 31.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 48 of 117 © 2023 Renesas Electronics RIN_N SYS_FLT RIN_N_WAKE1 RIN_N_WAKE2 RIN_N_RST ROUT_N tINTR tINTR tINTR tRST_D tWAKE2 tRST tWAKE1 (don’t care) Figure 31: RIN_N Pushbutton Reset Timer Timing Diagram The RESET behavior is configurable with the options shown in Table 40. Table 40: RIN_N Reset Timer Configuration Bits Configuration Description RIN_N_RST_REC 0x0010 [1:0] 0: RESET event has no effect 1: Enter Ship mode at RESET 2: Enter Hi-Z mode at RESET PWR_CYC_MODE 0x0012 [1] 0: Power cycle triggered by VDD_PWR insertion / removal 1: Power cycle triggered by RESET timer when VDD_PWR present RIN_N_RST_ROUT_EN 0x0010 [3:2] 0: Disable ROUT_N toggle at RESET 1: Enable ROUT_N toggle at RESET 2: Enable ROUT_N toggle at RESET only when VDD_PWR is present The RIN_N timer can also be used to exit Ship mode. A WAKE1 event triggers Ship mode exit, with WAKE2 and RESET being ignored. If ROUT_N is enabled, a RESET event causes the ROUT_N output to toggle low for 400 ms (typ). ROUT_N is an open-drain output, pull up this pin to the logic rail with a 1 kΩ to 100 kΩ resistor.

4.8.5 System Status Register

The System Status register (0x0002) indicates the status of four system functions:

BUCK: High = enabled with no faults
Charge Status: Ready, Charge in Progress, Charge Done, or Fault
MODE: Logic state of the MODE pin
Power Cycle: High indicates that a power cycle has occurred Only the power cycle bit shows previous events and is read-clear. The others are READ only, reflecting the current status.

4.8.6 I2C Programming

DA9072 includes an I2C compatible interface which allows READ/WRITE access to all registers. The interface is disabled in some modes and is configurable, see Table 41.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 49 of 117 © 2023 Renesas Electronics Table 41: I2C Interface Configuration I2C_HIZ_EN 0x0015 [0] Ship Mode Hi-Z Mode Active Battery Mode Charge Mode 0 disabled disabled active active 1 disabled active active active I2C communication uses the SDA and SCL are open drain I/O pins. Pull these up to VDDIO with a 1 kΩ to 100 kΩ resistor. SCL is the serial clock generated by the host and SDA is the serial address and data input/output. DA9072 is compatible with the standard I2C protocol but only operates as a slave. The I2C bus supports a frequency range of 400 kHz (Fast mode) to 100 kHz (Slow mode). The transfer protocol is the same whether operating in Fast or Slow mode. The device supports 8-bit addressing only. The I2C slave ID is 7-bit and can be set at register 0x0040 [6:0], with a range of 00 to 7F. When active, the I2C bus is monitored at all times for a valid SLAVE address, and an ACKNOWLEDGE (ACK) bit is generated if the SLAVE address is true. This indicates to the master that the communication link has been established. The master then generates SCL clock cycles to transmit or receive data. After receiving data, an ACK is generated either by the DA9072 or the master. Basic communication is described below and in Figure 32.

A START condition is initiated by a high to low transition on the SDA line while the SCL is in the high state
A STOP condition is indicated by a low to high transition on the SDA line while the SCL is in the high state
An ACK is indicated by the receiver pulling the SDA line low during the following clock cycle SDA SCL Data SDA must be stable during high part of clock SCL Data sampled on SCL rising edge and driven on SCL falling edge Start(S ) is SDA falling while SCL high Stop (P ) is SDA rising while SCL high Figure 32: I2C Start and Stop Conditions Each data sequence is 9-bit, consisting of 8-bit data and 1-bit ACK. Data sequences can be repeated indefinitely. At the end of the data transfer, the master generates a STOP condition. The bus returns to IDLE if during a message a new START or STOP condition occurs. Data is transmitted as MSB first for both READ and WRITE operations.

4.9 Buck Regulator

DA9072 includes a nano-ampere quiescent current buck regulator with adjustable output voltage, up to 300 mA load capability, and Power Saving mode for excellent efficiency at light load. It also features dynamic voltage scaling (DVS) capability and multiple protection features.

4.9.1 Buck Output Voltage Programmability

The DA9072 buck regulator output voltage is programmable in 50 mV steps between 0.6 V and 2.1 V. The output voltage is set by BUCK_VOUT (register 0x0030 [4:0]). The voltage can be set within two ranges based on the value of the VOUT_RANGE_HI bit (register 0x0030 [6]). The output voltage can be changed within one of the two range settings while the buck is enabled (0.6 V to 1.3 V or 1.3 V to 2.1 V). The range setting, however, can only be changed while the buck is disabled.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 50 of 117 © 2023 Renesas Electronics If a command is received outside of the allowable range (that is above 1.3 V for VOUT_RANGE_HI = 0 or below 1.3 V for VOUT_RANGE_HI = 1), BUCK_VOUT<3:0> is forced to 01110 (1.3 V) digitally. Although the output voltage can be set up to 2.1 V, there is a headroom requirement of 600 mV for VDD_BUCK. Therefore, if the output voltage is set to 2.0 V or 2.1 V then VBAT UVLO must be set to 2.6 V or 2.7 V respectively to ensure proper operation.

4.9.2 Buck Enable and Soft Start Operation

DA9072 buck integrates a soft start circuit to minimize output voltage over-shoot and input voltage droop during start-up. Writing 1 to BUCK_EN (register 0x0030 [7]) enables the buck and switching starts after a typical delay of 3 ms. During soft-start, the cycle-by-cycle peak current limit is reduced to 300 mA (typ) to limit inrush current. Although the startup time is not controlled directly, a smooth startup can be expected with timing variations due to input and output voltage conditions. Due to the reduced current limit in startup, starting the buck regulator into a heavy load is not recommended.

4.9.3 Power Saving Mode Operation

The DA9072 buck regulator features Power Saving mode that greatly reduces the quiescent current in light load conditions. When the load decreases to a certain level, the buck regulator enters Discontinuous mode (DCM) and operates with pulse frequency modulation (PFM). The low-side FET is turned off based on a zero-crossing comparator to prevent negative inductor current, which can result in additional conduction loss. If both high and low-side FETs remain off for a certain delay time after the inductor current crosses zero, the buck enters Power Saving mode. In this mode, most of the internal circuitry is shut down to reduce quiescent current. The lighter the load, the longer the duration Power Saving mode lasts; therefore, achieving the lowest quiescent current and improving light load efficiency. At no-load the buck regulator consumes only 900 nA of quiescent current typically. At heavier loads, the buck operates in Continuous Conduction mode (CCM) with constant off-time. The off timer imposes a minimum off time on the switching cycle, placing a ceiling on the switching frequency.

4.9.4 Dynamic Voltage Control

The DVC feature allows the buck output voltage to ramp up or down to a new target value in a controlled manner. When a new voltage setting is applied, the register setting value is incremented or decremented by one bit every 4 ms, which results in an output voltage slew rate of 50 mV / 4 ms. Since the buck output voltage can only be changed within the high or low range while enabled, DVC also has this restriction. DVC can be enabled and disabled by bits DVC_STEP (register 0x0050 [1:0]). The buck works in DCM under light load; therefore, it cannot quickly discharge the output voltage during DCM. When a voltage ramp down is commanded in DCM, the slew rate depends on the load. In CCM, the falling slew rate is the same (50 mV / 4 ms) as the rising slew rate. Different DVC slew rates are available by OTP.

4.9.5 Over-Current Protection

Over-current protection (OCP) monitors the peak current through high-side FET on a cycle-by-cycle basis. When the sensed current exceeds the current limit threshold, the high-side FET is turned off immediately to limit the inductor current. The high-side FET is turned on again after the constant-off time expires. Exceeding the current limit threshold triggers the ISR_BUCK_OCP event bit (register 0x0006 [0]) and pin SYS_FLT toggles. In current limit conditions the output voltage drops, potentially causing an under-voltage fault. Both over-current and under-voltage can be set to initiate a power cycle, restarting the buck after a

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 51 of 117 © 2023 Renesas Electronics programmable wait time. The power cycle triggers are configured by register SYS_PWR_CYC_1

4.9.6 Output Under-Voltage Protection

When a buck output short or heavy loading occurs, inductor current increases until the peak reaches the cycle-by-cycle current limit. As the output is shorted, the inductor current down slope is very small during low-side FET on time. In this condition, the inductor current can potentially increase with each cycle. To prevent the inductor current from running away in a short circuit condition, the buck output voltage is monitored. If an over-current condition happens and the buck output drops 400 mV below the reference voltage, the ISR_BUCK_UVP event bit (register 0x006 [2]) is set. Under-voltage protection (UVP) can be set to trigger a power cycle by bit BUCK_UVP_PWR_CYC_EN (register 0x0013 [6]). UVP is not active during startup. Therefore, a short circuit during startup may not trigger a fault event or a power cycle.

4.9.7 Output Over-Voltage Protection

Over-voltage protection (OVP) protects the load from unexpected output overshoots. When the buck output voltage is 200 mV greater than the target voltage, the high side FET is immediately turned off. Simultaneously, the output discharge FET is turned on to discharge the output capacitor. An ISR_BUCK_OVP event bit (register 0x0006 [1]) is set and the SYS_FLT flag toggles. The buck remains off with the output pulled down until the fault is cleared. BUCK_OVP is set to initiate a power cycle by default (OTP setting).

4.9.8 Automatic Output Voltage Discharge

To speed up the discharging of the buck output capacitor and ensure a safe restart, the buck regulator provides automatic output voltage discharge when the buck is disabled or shuts down due to a fault. Automatic output discharge when the buck is forced off by a fault is enabled by default (OTP setting).. Automatic discharge when the buck is disabled is set by bit BUCK_PD_CFG2 (register 0x0031 [5]). The output of the buck regulator is discharged through the FB_BUCK pin with resistance of 33 Ω (typical).

4.9.9 External Component Selection

The choice of inductor and output capacitor is a trade-off between light load efficiency and load transient response. In general, the combination of a smaller L and larger COUT improves load transient performance and reduces the voltage ripple at light loads. A larger L improves light load efficiency by reducing the frequency of switching cycles and therefore switching losses. The inductor must have a saturation rating which exceeds the maximum value of the current limit (ILIM_SW_PMOS). In order to optimize efficiency, decide the inductor value first and then select the inductor with the lowest DCR possible given the PCB constraints. For recommended component values, see Table 42. Table 42: External Buck Components Component Value L 2.2 µH COUT 10 µF

4.10 LDO / Load Switches

Each of the three LDOs is configurable as either a load switch or an LDO and capable of delivering 150 mA to the load in either mode. All LDOs have uncommitted inputs which can be connected to VDD_SYS, the buck output, or another suitable source. If using the buck output, confirm that the buck provides sufficient headroom and current capability. In LDO mode, LDO0 can be programmed between 0.8 V and 3.15 V in 25 mV or 50 mV steps. LDO1 and LDO2 can be set between 0.8 V and 3.3 V in 50 mV or 75 mV steps. To ensure good regulation and full load capability, 200 mV of headroom is recommended at VDD_LDO<n>, with load capability decreasing with lower headroom. With sufficient headroom the LDOs are current limited at a minimum of 215 mA. LDO0 is designed to operate with lower headroom. To achieve the best performance from the LDOs, it is recommended that the input bypass cap is placed as close as possible to the LDO input pins (VDD_LDO<n>). A 1 µF input capacitor is typically sufficient for each LDO, provided that there is at least that much capacitance at the VDD_SYS or BUCK output. Each LDO is enabled and output voltage set by registers VOUT_LS_LDO<n> (0x0032 through 0x0034). The LDOs can be configured as load switches by bits SEL_LDSW_<n> (register 0x0035 [2:0]). There is an approximately 20 ms delay between the I2C enable command and LDO startup. When the LDOs are operating as load switches, there are two modes of operation: Current Limit Enabled mode and Full-On mode. Full-On mode disables the load switch current limit, while providing a much lower on-resistance. In Current Limit mode, current limit is active with the same limit as the LDO mode limit. Each load switch can operate over a wider range compared to LDO mode, with a minimum input voltage of 0.8 V. In either mode, the load switch current capability is reduced at lower input voltages. At the minimum input voltage, expect a maximum load-switch capability of 1 mA.

4.11 Thermal Protection

DA9072 is protected from internal overheating by the over-temperature shutdown function. When the junction temperature reaches TSHDN , the device initiates a power cycle and the safety timer is reset. When the power cycle ends, VDD_SYS recovers for several milliseconds. After this period, if the junction temperature is still above TSHDN, a power cycle is initiated again. In this way, the DA9072 continually attempts to restart with an active duty cycle of less than 1 %, sufficient to allow the IC to cool down. When the junction temperature has dropped below TSHDN – THYS, power cycling stops. When an over-temperature fault occurs, SYS_FLT toggles and the ISR_OVT bit (register 0x0007 [3]) is set to 1. To avoid tripping thermal shutdown, limit power dissipation to no more than: 𝑃𝐷𝐼𝑆𝑆 < 118℃ − 𝑇𝐴 𝑅𝑇𝐻_𝐽𝐴 Where TA is the ambient temperature, RTH_JA is the combined thermal resistance of the package and PCB. Typical values for RTH_JA vary with PCB size, layer count, airflow, and other factors. A typical value of 40 ºC/W is a good starting point. PDISS can be estimated as: 𝑃𝐷𝐼𝑆𝑆 = 𝑃𝐵𝑈𝐶𝐾 + 𝑃𝐿𝐷𝑂0 +𝑃𝐿𝐷𝑂1 + 𝑃𝐿𝐷𝑂2 + 𝑃𝐶𝐻𝐺 Where:

PLDO0 = (VDD_LDO0 – VLDO0) * ILDO0
PLDO1 = (VDD_LDO1 – VLDO1) * ILDO1
PLDO2 = (VDD_LDO2 – VLDO2) * ILDO2
PCHG = (VDD_PWR – VBAT) * ICHG
PBUCK = VO_BUCK * IOUT_BUCK * (1/η 1) – DCR * IOUT_BUCK ○ where η is the efficiency of the buck converter and DCR is the inductor’s DC resistance.

4.12 PCB Layout Guidelines

To ensure proper operation and maximize optimal thermal performance following these guidelines. The first priority is to reduce and isolate high frequency switching noise so that it does not disturb sensitive nodes. For the buck regulator, the primary sources of noise are at the input capacitor ground and VDD_BUCK nodes. Connect the input capacitor as close as possible to the PGND_BUCK and VDD_BUCK pins. This reduces the parasitic inductance responsible for many of the voltage spikes during switching. Route the current carrying traces (VDD_BUCK, PGND, VOUT) directly to the pads of all capacitors, not through vias or separate traces. This applies to both input and output capacitors and is good practice in general. Where possible these current carrying traces should be wide or large copper areas to reduce impedance and improve thermal resistance. Route these traces on the top layer only. Connect VDD_SYS and VDD_BUCK close to, or at, the pins to further reduce impedance. The second largest noise sources are the SW nodes. Although the current here is not switching, the fast voltage swings can introduce noise through capacitive coupling. To reduce this, use the smallest area possible for the SW nodes, while keeping in mind the current handling requirements. SW_BUCK should be routed on the second layer with multiple vias, which allows the best routing for the buck input caps. As much as possible, surround the SW nodes with GND copper to help shield the nearby FB traces. Route all signal traces such as FB, SDA, and SCL away from the SW nodes, buck input caps, and the inductor. Shield these sensitive traces with GND copper or route on a lower layer with a ground plane to provide shielding. To create a good shield, flood one inner layer with copper and connected as a common ground to the GND pins of the IC (A1, D3, E1, F2, F3, and F4) and external GND connections. Layer 2 is recommended. Connect PGND_BUCK directly to the buck input cap before connecting to the ground plane. Multiple ground planes, for example a mid-layer and bottom layer plane, are helpful to control high frequency noise and improve thermal performance. Important: Do not use the AGND node as a ground plane. Instead, connect all AGNDs to a small area or by star connection to the AGND pin. Connect the AGND pin to the larger ground plane in a quiet location. For an example of top and second layer routing, see Figure 33 and Figure 34. The buck input cap is C21. The cap is placed close to the IC with no vias between the pin and the cap. C23 is the buck output cap, connected on the top layer. L20 is the buck inductor; its SW node is routed on layer 2 and connected by multiple vias. Layer-2 is a mostly filled GND plane, which provides shielding around the SW nodes routed on this layer. The isolated AGND area is on the right side of Figure 34. AGND is connected to the GND area at a single point on another layer, not shown here. Note 1 Figure 33 and Figure 34 are the PCB layout of DA9073. For DA9072, L30 and the SW node area on layer-2 can be removed and filled with GND plane.

5 Registers

5.1 Register Map

5.1.1 System

Table 43: System Register Map System Register Addr 7 6 5 4 3 2 1 0 SYS_STS_0 0x00

02 Reserved STS_BUCK STS_CHG<1:0> Reserved Reserved STS_PWR_CYC STS_MODE

SYS_ISR_0 0x00

03 Reserved Reserved ISR_VDD_SYS_

ISR_VDD_PWR_ILI M ISR_VDD_PWR _DPM ISR_VDD_PWR_UVL O_RCV ISR_VDD_PWR_ UVLO ISR_VDD_PWR _OVP SYS_ISR_1 0x00

04 ISR_TS_HOT ISR_TS_WARM ISR_TS_COOL ISR_TS_COLD ISR_VBAT_SH

ORT ISR_VBAT_OCP ISR_VBAT_DPP M ISR_VBAT_UVL O SYS_ISR_2 0x00

05 Reserved ISR_TS_OFF ISR_CHG_TMR ISR_RECHG_STAR

T ISR_CHG_DON E ISR_PRECHG ISR_BAT_SPPL ISR_SLP SYS_ISR_3 0x00

06 Reserved Reserved Reserved Reserved Reserved ISR_BUCK_UVP ISR_BUCK_OVP ISR_BUCK_OC

P SYS_ISR_4 0x00 ISR_PWR_PL GGD ISR_MODE_FALL ISR_MODE_RIS E ISR_WD ISR_OVT ISR_RIN_N_RST ISR_RIN_N_WA KE2 ISR_RIN_N_WA KE1 SYS_IMR_0 0x00

08 Reserved Reserved IMR_VDD_SYS_

IMR_VDD_PWR_ILI M IMR_VDD_PWR _DPM IMR_VDD_PWR_UV LO_RCV IMR_VDD_PWR _UVLO IMR_VDD_PWR _OVP SYS_IMR_1 0x00

09 IMR_TS_HOT IMR_TS_WARM IMR_TS_COOL IMR_TS_COLD IMR_VBAT_SH

ORT IMR_VBAT_OCP IMR_VBAT_DPP M IMR_VBAT_UV LO

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 56 of 117 © 2023 Renesas Electronics Register Addr 7 6 5 4 3 2 1 0 SYS_IMR_2 0x00 0A Reserved IMR_TS_OFF IMR_CHG_TMR IMR_RECHG_STAR T IMR_CHG_DON E IMR_PRECHG IMR_BAT_SPPL IMR_SLP SYS_IMR_3 0x00 0B Reserved Reserved Reserved Reserved Reserved IMR_BUCK_UVP IMR_BUCK_OVP IMR_BUCK_OC P SYS_IMR_4 0x00 IMR_PWR_PL GGD IMR_MODE_FALL IMR_MODE_RIS E IMR_WD IMR_OVT IMR_RIN_N_RST IMR_RIN_N_WA KE2 IMR_RIN_N_W AKE1 SYS_SYS_0 0x00 0D INIT_REGS Reserved Reserved Reserved Reserved Reserved 1 HZ_MODE EN_SHIPMODE SYS_BAT_0 0x00 0E Reserved Reserved Reserved VBAT_DIV_RATIO Reserved BUVLO<2:0> SYS_BAT_1 0x00 0F Reserved Reserved Reserved TS_TRIG Reserved Reserved IDISCHG_MON_ EN VBATDIV_EN SYS_RIN_N_ 0x00 AKE2 RIN_N_PER_WAKE SYS_STS_O UT_0 0x00

11 Reserved Reserved Reserved PWR_FLT_MODE Reserved Reserved Reserved SYS_FLT_MOD

E SYS_PWR_C YC_0 0x00

12 PWR_CYC_WAIT_PER<1:0> PWR_CYC_PER<1:0> Reserved PWR_CYC_FRC PWR_CYC_MO

DE PWR_CYC_EN SYS_PWR_C YC_1 0x00

13 Reserved BUCK_UVP_PWR_

CYC_EN Reserved 0 BUCK_OCP_PWR_ CYC_EN Reserved 0 Reserved Reserved 0 BTS_PWR_CY C_EN SYS_WD_0 0x00 WD_RST_REG SYS_I2C_0 0x00

15 Reserved Reserved Reserved Reserved Reserved I2C_RDCLR_DIS I2C_RST_TMR_

EN I2C_HIZ_EN

40 Reserved I2C_SLAVE_ADDR<6:0>

5.1.2 Charger

Table 44: Charger Register Map Charger and Power Path Register Addr 7 6 5 4 3 2 1 0 CHG_CHG_0 0x002 Reserve d Reserved IPRETERM_REXT<1:0> ICHG_MAX<1:0> RMEAS_EN CE_N CHG_CHG_1 0x002 Reserve d TE_TS_COO L TE_TS_WARM TE TMRX2_EN Reserved TMR<1:0> CHG_ICHG_0 0x002 Reserve d ICHG<6:0> CHG_IPRETERM_ 0x002 Reserve d IPRETERM<6:0> CHG_VBREG_0 0x002 Reserve d VBCHG<6:0> CHG_VBPRECHG 0x002 Reserve d Reserved Reserved VBPRECHG_COMP_D IS Reserved VBPRECHG<2:0> CHG_BAT_TS_0 0x002 Reserve d Reserved TS_DISCHG_MODE_S EL Reserved 0 TS_WARM_E N TS_OFF_MOD E TS_EN_DISCHG TS_EN_CHG

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 58 of 117 © 2023 Renesas Electronics Register Addr 7 6 5 4 3 2 1 0 CHG_VDD_PWR_ 0x002 Reserve d Reserved Reserved Reserved ILIM<3:0> CHG_VDD_PWR_ 0x002 Reserve d Reserved VDD_PWR_OVP_DIS VDD_PWR_DPM_DIS ILIM_EN VDD_PWR_DPM<2:0> CHG_IDISCHG_0 0x002 Reserve d Reserved Reserved IDISCHG_OCP<2:0> IDISCHG_OCP_HIZ_ EN IDISCHG_OCP_E N

5.1.3 Buck and LDO Control

Table 45: Buck and LDO Control Register Map VOUT Registers Register Addr 7 6 5 4 3 2 1 0 VOUT_BUCK 0x0030 BUCK_EN VOUT_RANGE_HI Reserved BUCK_VOUT<4:0> VOUT_BUCK_CFG 0x0031 Reserved Reserved BUCK_PD_CFG2 Reserved 0 Reserved Reserved SEL_ILIM_DLT<1:0> VOUT_LS_LDO0 0x0032 EN_LS_LDO_0 Reserved LS_LDO_0<5:0> VOUT_LS_LDO1 0x0033 EN_LS_LDO_1 Reserved LS_LDO_1<5:0> VOUT_LS_LDO2 0x0034 EN_LS_LDO_2 Reserved LS_LDO_2<5:0> VOUT_LS_LDO_CFG 0x0035 Reserved SEL_FULLON_2 SEL_FULLON_1 SEL_FULLON_0 Reserved SEL_LDSW_2 SEL_LDSW_1 SEL_LDSW_0 VOUT OPT Registers VOUT_BUCK_OPT0 0x0050 Reserved 0 Reserved 0 Reserved 0 Reserved 1 Reserved 1 Reserved 0 DVC_STEP<1:0>

5.2 Register Definitions

5.2.1 System

Table 46: Register SYS_STS_0 Address Register Name POR Value Status 0x0002 SYS_STS_0 0x00 7 6 5 4 3 2 1 0 Reserved STS_BUCK STS_CHG<1:0> Reserved Reserved STS_PWR_CYC STS_MODE Field Name Bits POR Description STS_BUCK [6] 0x0 Buck power good status STS_CHG [5:4] 0x0 Charge status Value Description 0x0 (POR) Charge ready 0x1 Charge in progress 0x2 Charge done 0x3 Fault STS_PWR_CYC [1] 0x0 Power cycle status register. Cleared after being read STS_MODE [0] 0x0 MODE pin status

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 60 of 117 © 2023 Renesas Electronics Table 47: Register SYS_ISR_0 Address Register Name POR Value IRQ status 0x0003 SYS_ISR_0 0x00 7 6 5 4 3 2 1 0 Reserved Reserved ISR_VDD_SYS_UVLO ISR_VDD_PWR_ILIM ISR_VDD_PWR_DPM ISR_VDD_PWR_UVLO_RCV ISR_VDD_PWR_UVLO ISR_VDD_PWR_OVP Field Name Bits POR Description ISR_VDD_SYS_UVLO [5] 0x0 VDD_SYS UVLO IRQ status ISR_VDD_PWR_ILIM [4] 0x0 VDD_PWR ILIM IRQ status ISR_VDD_PWR_DPM [3] 0x0 VDD_PWR DPM IRQ status ISR_VDD_PWR_UVLO_RCV [2] 0x0 VDD_PWR UVLO recovery IRQ status ISR_VDD_PWR_UVLO [1] 0x0 VDD_PWR UVLO IRQ status ISR_VDD_PWR_OVP [0] 0x0 VDD_PWR OVP IRQ status Table 48: Register SYS_ISR_1 Address Register Name POR Value IRQ status 0x0004 SYS_ISR_1 0x00 7 6 5 4 3 2 1 0 ISR_TS_HOT ISR_TS_WARM ISR_TS_COOL ISR_TS_COLD ISR_VBAT_SHORT ISR_VBAT_OCP ISR_VBAT_DPPM ISR_VBAT_UVLO

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 61 of 117 © 2023 Renesas Electronics Field Name Bits POR Description ISR_TS_HOT [7] 0x0 Battery temperature sensor IRQ status. TS_HOT ISR_TS_WARM [6] 0x0 Battery temperature sensor IRQ status. TS_WARM ISR_TS_COOL [5] 0x0 Battery temperature sensor IRQ status. TS_COOL ISR_TS_COLD [4] 0x0 Battery temperature sensor IRQ status. TS_COLD ISR_VBAT_SHORT [3] 0x0 VBAT short IRQ status ISR_VBAT_OCP [2] 0x0 VBAT OCP IRQ status ISR_VBAT_DPPM [1] 0x0 VBAT DPPM IRQ status ISR_VBAT_UVLO [0] 0x0 VBAT UVLO IRQ status Table 49: Register SYS_ISR_2 Address Register Name POR Value IRQ status 0x0005 SYS_ISR_2 0x00 7 6 5 4 3 2 1 0 Reserved ISR_TS_OFF ISR_CHG_TMR ISR_RECHG_START ISR_CHG_DONE ISR_PRECHG ISR_BAT_SPPL ISR_SLP Field Name Bits POR Description ISR_TS_OFF [6] 0x0 Battery temperature sensor IRQ status. TS_OFF ISR_CHG_TMR [5] 0x0 Charge safety timer IRQ status ISR_RECHG_START [4] 0x0 Recharge started IRQ status ISR_CHG_DONE [3] 0x0 Charge done IRQ status

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 62 of 117 © 2023 Renesas Electronics ISR_PRECHG [2] 0x0 Pre-charge IRQ status ISR_BAT_SPPL [1] 0x0 Battery Supplement mode IRQ status ISR_SLP [0] 0x0 Sleep mode IRQ status Table 50: Register SYS_ISR_3 Address Register Name POR Value IRQ status 0x0006 SYS_ISR_3 0x00 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved ISR_BUCK_UVP ISR_BUCK_OVP ISR_BUCK_OCP Field Name Bits POR Description ISR_BUCK_UVP [2] 0x0 Buck UVP IRQ status ISR_BUCK_OVP [1] 0x0 Buck OVP IRQ status ISR_BUCK_OCP [0] 0x0 Buck OCP IRQ status Table 51: Register SYS_ISR_4 Address Register Name POR Value IRQ status 0x0007 SYS_ISR_4 0x00 7 6 5 4 3 2 1 0 ISR_PWR_PLGGD ISR_MODE_FALL ISR_MODE_RISE ISR_WD ISR_OVT ISR_RIN_N_RST ISR_RIN_N_WAKE2 ISR_RIN_N_WAKE1

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 63 of 117 © 2023 Renesas Electronics Field Name Bits POR Description ISR_PWR_PLGGD [7] 0x0 VDD_PWR insertion/removal power cycle IRQ status ISR_MODE_FALL [6] 0x0 MODE pin falling edge IRQ status ISR_MODE_RISE [5] 0x0 MODE pin rising edge IRQ status ISR_WD [4] 0x0 Watchdog timer IRQ status ISR_OVT [3] 0x0 Over-temperature IRQ status ISR_RIN_N_RST [2] 0x0 RIN_N RESET timer IRQ status ISR_RIN_N_WAKE2 [1] 0x0 RIN_N WAKE2 timer IRQ status ISR_RIN_N_WAKE1 [0] 0x0 RIN_N WAKE1 timer IRQ status Table 52: Register SYS_IMR_0 Address Register Name POR Value IRQ mask 0x0008 SYS_IMR_0 0x3F 7 6 5 4 3 2 1 0 Reserved Reserved IMR_VDD_SYS_UVLO IMR_VDD_PWR_ILIM IMR_VDD_PWR_DPM IMR_VDD_PWR_UVLO_RCV IMR_VDD_PWR_UVLO IMR_VDD_PWR_OVP Field Name Bits POR Description IMR_VDD_SYS_UVLO [5] 0x1 VDD_SYS UVLO IRQ mask IMR_VDD_PWR_ILIM [4] 0x1 VDD_PWR ILIM IRQ mask IMR_VDD_PWR_DPM [3] 0x1 VDD_PWR DPM IRQ mask IMR_VDD_PWR_UVLO_RCV [2] 0x1 VDD_PWR UVLO recovery IRQ mask

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 64 of 117 © 2023 Renesas Electronics IMR_VDD_PWR_UVLO [1] 0x1 VDD_PWR UVLO IRQ mask IMR_VDD_PWR_OVP [0] 0x1 VDD_PWR OVP IRQ mask Table 53: Register SYS_IMR_1 Address Register Name POR Value IRQ mask 0x0009 SYS_IMR_1 0xFF 7 6 5 4 3 2 1 0 IMR_TS_HOT IMR_TS_WARM IMR_TS_COOL IMR_TS_COLD IMR_VBAT_SHORT IMR_VBAT_OCP IMR_VBAT_DPPM IMR_VBAT_UVLO Field Name Bits POR Description IMR_TS_HOT [7] 0x1 Battery temperature sensor IRQ mask. TS_HOT IMR_TS_WARM [6] 0x1 Battery temperature sensor IRQ mask. TS_WARM IMR_TS_COOL [5] 0x1 Battery temperature sensor IRQ mask. TS_COOL IMR_TS_COLD [4] 0x1 Battery temperature sensor IRQ mask. TS_COLD IMR_VBAT_SHORT [3] 0x1 VBAT short IRQ mask IMR_VBAT_OCP [2] 0x1 VBAT OCP IRQ mask IMR_VBAT_DPPM [1] 0x1 VBAT DPPM IRQ mask IMR_VBAT_UVLO [0] 0x1 VBAT UVLO IRQ mask Table 54: Register SYS_IMR_2 Address Register Name POR Value IRQ mask 0x000A SYS_IMR_2 0x7F

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 65 of 117 © 2023 Renesas Electronics 7 6 5 4 3 2 1 0 Reserved IMR_TS_OFF IMR_CHG_TMR IMR_RECHG_START IMR_CHG_DONE IMR_PRECHG IMR_BAT_SPPL IMR_SLP Field Name Bits POR Description IMR_TS_OFF [6] 0x1 Battery temperature sensor IRQ mask. TS_OFF IMR_CHG_TMR [5] 0x1 Charge safety timer IRQ mask IMR_RECHG_START [4] 0x1 Recharge started IRQ mask IMR_CHG_DONE [3] 0x1 Charge done IRQ mask IMR_PRECHG [2] 0x1 Pre-charge started IRQ mask IMR_BAT_SPPL [1] 0x1 Battery Supplement mode IRQ mask IMR_SLP [0] 0x1 Sleep mode IRQ mask Table 55: Register SYS_IMR_3 Address Register Name POR Value IRQ mask 0x000B SYS_IMR_3 0x3F 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved IMR_BUCK_UVP IMR_BUCK_OVP IMR_BUCK_OCP Field Name Bits POR Description IMR_BUCK_UVP [2] 0x1 Buck UVP IRQ mask IMR_BUCK_OVP [1] 0x1 Buck OVP IRQ mask

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 66 of 117 © 2023 Renesas Electronics IMR_BUCK_OCP [0] 0x1 Buck OCP IRQ mask Table 56: Register SYS_IMR_4 Address Register Name POR Value IRQ mask 0x000C SYS_IMR_4 0xFF 7 6 5 4 3 2 1 0 IMR_PWR_PLGGD IMR_MODE_FALL IMR_MODE_RISE IMR_WD IMR_OVT IMR_RIN_N_RST IMR_RIN_N_WAKE2 IMR_RIN_N_WAKE1 Field Name Bits POR Description IMR_PWR_PLGGD [7] 0x1 VDD_PWR insertion/removal power cycle IRQ mask IMR_MODE_FALL [6] 0x1 MODE pin falling edge IRQ mask IMR_MODE_RISE [5] 0x1 MODE pin rising edge IRQ mask IMR_WD [4] 0x1 Watchdog timer IRQ mask IMR_OVT [3] 0x1 Over-temperature IRQ mask IMR_RIN_N_RST [2] 0x1 RIN_N RESET timer IRQ mask IMR_RIN_N_WAKE2 [1] 0x1 RIN_N WAKE2 timer IRQ mask IMR_RIN_N_WAKE1 [0] 0x1 RIN_N WAKE1 timer IRQ mask Table 57: Register SYS_SYS_0 Address Register Name POR Value System configuration 0x000D SYS_SYS_0 0x04

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 67 of 117 © 2023 Renesas Electronics 7 6 5 4 3 2 1 0 INIT_REGS Reserved Reserved Reserved Reserved Reserved 1 HZ_MODE EN_SHIPMODE Field Name Bits POR Description INIT_REGS [7] 0x0 Initialize register trigger HZ_MODE [1] 0x0 Hi-Z mode entry control. Automatically cleared when HZ mode exit EN_SHIPMODE [0] 0x0 Ship mode entry control Table 58: Register SYS_BAT_0 Address Register Name POR Value System configuration 0x000E SYS_BAT_0 0x06 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved BUVLO<2:0> Field Name Bits POR Description BUVLO [2:0] 0x6 Battery UVLO threshold Value Description 0x0 Reserved 0x1 2.5 V 0x2 2.6 V 0x3 2.7 V 0x4 2.8 V

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 68 of 117 © 2023 Renesas Electronics 0x5 2.9 V 0x6 (POR) 3.0 V 0x7 Reserved Table 59: Register SYS_BAT_1 Address Register Name POR Value System configuration 0x000F SYS_BAT_1 0x00 7 6 5 4 3 2 1 0 Reserved Reserved Reserved TS_TRIG Reserved Reserved Reserved Reserved Field Name Bits POR Description TS_TRIG [4] 0x0 Trigger register for one-shot battery temp sense enable Table 60: Register SYS_RIN_N_0 Address Register Name POR Value RIN_N 0x0010 SYS_RIN_N_0 0x66 7 6 5 4 3 2 1 0 Field Name Bits POR Description RIN_N_PER_RST [7:6] 0x1 RIN_N RESET timer period

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 69 of 117 © 2023 Renesas Electronics Value Description 0x0 4 s 0x1 (POR) 8 s 0x2 10 s 0x3 14 s RIN_N_PER_WAKE2 [5] 0x1 RIN_N WAKE2 timer period Value Description 0x0 1.0 s 0x1 (POR) 1.5 s RIN_N_PER_WAKE1 [4] 0x0 RIN_N WAKE1 timer period Value Description 0x0 (POR) 50 ms 0x1 500 ms RIN_N_RST_ROUT_EN [3:2] 0x1 ROUT_N pulse output enable for RESET wake-up Value Description 0x0 Disable 0x1 (POR) Enable 0x2 Enable only when VDD_PWR is present 0x3 Reserved RIN_N_RST_REC [1:0] 0x2 Reset timer Hi-Z / Ship mode transition control

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 70 of 117 © 2023 Renesas Electronics Value Description 0x0 Reset timer is not used for both 0x1 Enter Ship mode after RIN_N reset timer hit 0x2 (POR) Enter Hi-Z mode after RIN_N reset timer hit 0x3 Reserved Table 61: Register SYS_STS_OUT_0 Address Register Name POR Value Status indicator 0x0011 SYS_STS_OUT_0 0x01 7 6 5 4 3 2 1 0 Reserved Reserved Reserved PWR_FLT_MODE Reserved Reserved Reserved SYS_FLT_MODE Field Name Bits POR Description PWR_FLT_MODE [4] 0x0 PWR_FLT mode select Value Description 0x0 (POR) Power good indicator 0x1 Voltage shifted RIN_N output SYS_FLT_MODE [0] 0x1 SYS_FLT mode select Value Description 0x0 IRQ I/F enabled and charge status indicator disabled 0x1 (POR) IRQ I/F enabled and charge status indicator enabled

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 71 of 117 © 2023 Renesas Electronics Table 62: Register SYS_PWR_CYC_0 Address Register Name POR Value Power cycle 0x0012 SYS_PWR_CYC_0 0x91 7 6 5 4 3 2 1 0 PWR_CYC_WAIT_PER<1:0> PWR_CYC_PER<1:0> Reserved PWR_CYC_FRC PWR_CYC_MODE PWR_CYC_EN Field Name Bits POR Description PWR_CYC_WAIT_PER [7:6] 0x2 Power cycle wait period setting Value Description 0x0 0 s 0x1 0.5 s 0x2 (POR) 1.0 s 0x3 2.0 s PWR_CYC_PER [5:4] 0x1 Power cycle period setting Value Description 0x0 5 s 0x1 (POR) 10 s 0x2 15 s 0x3 20 s PWR_CYC_FRC [2] 0x0 Write 1 to force power cycling PWR_CYC_MODE [1] 0x0 Power cycle trigger select

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 72 of 117 © 2023 Renesas Electronics Value Description 0x0 (POR) VDD_PWR insertion/removal 0x1 RESET wake-up timer when VDD_PWR present PWR_CYC_EN [0] 0x1 Power cycle enable Table 63: Register SYS_PWR_CYC_1 Address Register Name POR Value Power cycle 0x0013 SYS_PWR_CYC_1 0x00 7 6 5 4 3 2 1 0 Reserved BUCK_UVP_PWR _CYC_EN Reserved 0 BUCK_OCP_PWR_CY C_EN Reserved 0 Reserved Reserved 0 BTS_PWR_CYC _EN Field Name Bits POR Description BUCK_UVP_PWR_CYC_EN [6] 0x0 Power cycle enable triggered by Buck UVP BUCK_OCP_PWR_CYC_EN [4] 0x0 Power cycle enable triggered by Buck OCP BTS_PWR_CYC_EN [0] 0x0 Power cycle enable triggered by TS_HOT Table 64: Register SYS_WD_0 Address Register Name POR Value Watchdog timer 0x0014 SYS_WD_0 0x10

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 73 of 117 © 2023 Renesas Electronics 7 6 5 4 3 2 1 0 Field Name Bits POR Description WD_RST_REGS_EN [7] 0x0 Register reset on watchdog timeout enable WD_ROUT_EN [6] 0x0 Reset output on watchdog timeout enable WD_TMR_PER [5:4] 0x1 Watchdog timer timeout period Value Description 0x0 25 s 0x1 (POR) 50 s 0x2 Reserved 0x3 Reserved WD_CLR_SEL [3:2] 0x0 Watchdog timer clear condition Value Description 0x0 (POR) Only I2C clears the timer 0x1 Only WD pin clears the timer 0x2 Both I2C and WD pin clear the timer 0x3 Reserved WD_EN [1:0] 0x0 Watchdog timer enable Value Description 0x0 (POR) Disable

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 74 of 117 © 2023 Renesas Electronics 0x1 Enable only when VDD_PWR present 0x2 Disable in Hi-Z mode 0x3 Always enable Table 65: Register SYS_I2C_0 Address Register Name POR Value I2C 0x0015 SYS_I2C_0 0x00 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved I2C_RDCLR_DIS I2C_RST_TMR_EN I2C_HIZ_EN Field Name Bits POR Description I2C_RDCLR_DIS [2] 0x0 I2C read clear disable for ISR registers and STS_PWR_CYC register I2C_RST_TMR_EN [1] 0x0 I2C reset timer enable I2C_HIZ_EN [0] 0x0 I2C enable in Hi-Z mode

5.2.2 Config

Table 66: Register SYS_CFG_I2C_0 Address Register Name POR Value I2C 0x0040 SYS_CFG_I2C_0 0x68 7 6 5 4 3 2 1 0 Reserved I2C_SLAVE_ADDR<6:0> Field Name Bits POR Description I2C_SLAVE_ADDR [6:0] 0x68 I2C slave addr

5.2.3 Charger

5.2.3.1 Charger and Power Path

Table 67: Register CHG_CHG_0 Address Register Name POR Value Charge 0x0020 CHG_CHG_0 0x01 7 6 5 4 3 2 1 0 Reserved Reserved IPRETERM_REXT<1:0> ICHG_MAX<1:0> RMEAS_EN CE_N Field Name Bits POR Description IPRETERM_REXT [5:4] 0x0 Charge termination/pre-charge current range by RITER_CHG. Read-only. Value Description 0x0 (POR) 5 % of ICHG 0x1 10 % of ICHG 0x2 15 % of ICHG 0x3 20 % of ICHG ICHG_MAX [3:2] 0x0 Maximum charge current limit. Value Description 0x0 (POR) No limit 0x1 20 mA 0x2 70 mA

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 77 of 117 © 2023 Renesas Electronics 0x3 200 mA RMEAS_EN [1] 0x0 External resistance programming enable. Write-locked when CE_N is 0. CE_N [0] 0x1 Charge enable Value Description 0x0 Enable charging 0x1 (POR) Disable charging Table 68: Register CHG_CHG_1 Address Register Name POR Value Charge 0x0021 CHG_CHG_1 0x19 7 6 5 4 3 2 1 0 Reserved TE_TS_COOL TE_TS_WARM TE TMRX2_EN Reserved TMR<1:0> Field Name Bits POR Description TE_TS_COOL [6] 0x0 Termination enable during TS COOL. Write-locked when CE_N is 0. TE_TS_WARM [5] 0x0 Termination enable during TS WARM. Write-locked when CE_N is 0. TE [4] 0x1 Charge current termination enable. Write-locked when CE_N is 0. TMRX2_EN [3] 0x1 Safety timer half rate enable. Write-locked when CE_N is 0. TMR [1:0] 0x1 Safety timer period. Write-locked when CE_N is 0. Value Description 0x0 30 m

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 78 of 117 © 2023 Renesas Electronics 0x1 (POR) 3 h 0x2 9 h 0x3 Timer disabled Table 69: Register CHG_ICHG_0 Address Register Name POR Value Charge current 0x0022 CHG_ICHG_0 0x41 7 6 5 4 3 2 1 0 Reserved ICHG<6:0> Field Name Bits POR Description ICHG [6:0] 0x41 Charge current (mA) 2.0-4.8 mA settings are available when SEL_ICHG_LOW=1. Value Description 0x0 5 (2) 0x1 6 (2.4) 0x2 7 (2.8) 0x3 8 (3.2) 0x4 9 (3.6) 0x5 10 (4) 0x6 11 (4.4)

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 79 of 117 © 2023 Renesas Electronics 0x7 12 (4.8) 0x8 13 0x9 14 0x0A 15 0x0B 16 0x0C 17 0x0D 18 0x0E 19 0x0F 20 0x10 21 0x11 22 0x12 23 0x13 24 0x14 25 0x15 26 0x16 27 0x17 28 0x18 29 0x19 30 0x1A 31 0x1B 32

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 80 of 117 © 2023 Renesas Electronics 0x1C 33 0x1D 34 0x1E 35 0x1F Reserved 0x3F Reserved 0x40 40 0x41 (POR) 50 0x42 60 0x43 70 0x44 80 0x45 90 0x46 100 0x47 110 0x48 120 0x49 130 0x4A 140 0x4B 150 0x4C 160 0x4D 170 0x4E 180 0x4F 190

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 81 of 117 © 2023 Renesas Electronics 0x50 200 0x51 210 0x52 220 0x53 230 0x54 240 0x55 250 0x56 260 0x57 270 0x58 280 0x59 290 0x5A 300 0x5B 310 0x5C 320 0x5D 330 0x5E 340 0x5F 350 0x60 360 0x61 370 0x62 380 0x63 390 0x64 400

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 82 of 117 © 2023 Renesas Electronics 0x65 410 0x66 420 0x67 430 0x68 440 0x69 450 0x6A 460 0x6B 470 0x6C 480 0x6D 490 0x6E 500 0x6F Reserved 0x7F Reserved Table 70: Register CHG_IPRETERM_0 Address Register Name POR Value Pre-charge / termination current 0x0023 CHG_IPRETERM_0 0x04 7 6 5 4 3 2 1 0 Reserved IPRETERM<6:0> Field Name Bits POR Description IPRETERM [6:0] 0x4 Pre-charge / termination current

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 83 of 117 © 2023 Renesas Electronics Value Description 0x0 0.5 0x1 1 0x2 1.5 0x3 2 0x4 (POR) 2.5 0x5 3 0x6 3.5 0x7 4 0x8 4.5 0x9 5 0x0A Reserved 0x3F Reserved 0x40 6 0x41 7 0x42 8 0x43 9 0x44 10 0x45 11 0x46 12 0x47 13

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 84 of 117 © 2023 Renesas Electronics 0x48 14 0x49 15 0x4A 16 0x4B 17 0x4C 18 0x4D 19 0x4E 20 0x4F 21 0x50 22 0x51 23 0x52 24 0x53 25 0x54 26 0x55 27 0x56 28 0x57 29 0x58 30 0x59 31 0x5A 32 0x5B 33 0x5C 34

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 85 of 117 © 2023 Renesas Electronics 0x5D 35 0x5E 36 0x5F 37 0x60 38 0x61 39 0x62 40 0x63 41 0x64 42 0x65 43 0x66 44 0x67 45 0x68 46 0x69 47 0x6A 48 0x6B 49 0x6C 50 0x6D Reserved 0x7F Reserved

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 86 of 117 © 2023 Renesas Electronics Table 71: Register CHG_VBREG_0 Address Register Name POR Value Battery regulation voltage 0x0024 CHG_VBREG_0 0x3C 7 6 5 4 3 2 1 0 Reserved VBCHG<6:0> Field Name Bits POR Description VBCHG [6:0] 0x3C Battery regulation voltage Value Description 0x0 3.6 0x1 3.61 0x2 3.62 0x3 3.63 0x4 3.64 0x5 3.65 0x6 3.66 0x7 3.67 0x8 3.68 0x9 3.69 0x0A 3.7

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 87 of 117 © 2023 Renesas Electronics 0x0B 3.71 0x0C 3.72 0x0D 3.73 0x0E 3.74 0x0F 3.75 0x10 3.76 0x11 3.77 0x12 3.78 0x13 3.79 0x14 3.8 0x15 3.81 0x16 3.82 0x17 3.83 0x18 3.84 0x19 3.85 0x1A 3.86 0x1B 3.87 0x1C 3.88 0x1D 3.89 0x1E 3.9 0x1F 3.91

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 88 of 117 © 2023 Renesas Electronics 0x20 3.92 0x21 3.93 0x22 3.94 0x23 3.95 0x24 3.96 0x25 3.97 0x26 3.98 0x27 3.99 0x28 4 0x29 4.01 0x2A 4.02 0x2B 4.03 0x2C 4.04 0x2D 4.05 0x2E 4.06 0x2F 4.07 0x30 4.08 0x31 4.09 0x32 4.1 0x33 4.11 0x34 4.12

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 89 of 117 © 2023 Renesas Electronics 0x35 4.13 0x36 4.14 0x37 4.15 0x38 4.16 0x39 4.17 0x3A 4.18 0x3B 4.19 0x3C (POR) 4.2 0x3D 4.21 0x3E 4.22 0x3F 4.23 0x40 4.24 0x41 4.25 0x42 4.26 0x43 4.27 0x44 4.28 0x45 4.29 0x46 4.3 0x47 4.31 0x48 4.32 0x49 4.33

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 90 of 117 © 2023 Renesas Electronics 0x4A 4.34 0x4B 4.35 0x4C 4.36 0x4D 4.37 0x4E 4.38 0x4F 4.39 0x50 4.4 0x51 4.41 0x52 4.42 0x53 4.43 0x54 4.44 0x55 4.45 0x56 4.46 0x57 4.47 0x58 4.48 0x59 4.49 0x5A 4.5 0x5B 4.51 0x5C 4.52 0x5D 4.53 0x5E 4.54

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 91 of 117 © 2023 Renesas Electronics 0x5F 4.55 0x60 4.56 0x61 4.57 0x62 4.58 0x63 4.59 0x64 4.6 0x65 4.61 0x66 4.62 0x67 4.63 0x68 4.64 0x69 4.65 0x6A Reserved 0x7F Reserved Table 72: Register CHG_VBPRECHG_0 Address Register Name POR Value Battery pre-charge voltage 0x0025 CHG_VBPRECHG_0 0x06 7 6 5 4 3 2 1 0 Reserved Reserved Reserved VBPRECHG_COMP_DIS Reserved VBPRECHG<2:0>

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 92 of 117 © 2023 Renesas Electronics Field Name Bits POR Description VBPRECHG_COMP_DIS [4] 0x0 Pre-charge comparator disable. Charger operates in Pre-charge mode when VBAT short detected. Write-locked when CE_N is Value Description 0x0 (POR) Pre-charge threshold is as specified by VBPRECHG 0x1 Charger ignores pre-charge threshold VBPRECHG [2:0] 0x6 Battery pre-charge voltage (V) Value Description 0x0 Reserved 0x1 2.7 0x2 2.8 0x3 2.9 0x4 3 0x5 3.1 0x6 (POR) 3.2 0x7 Reserved Table 73: Register CHG_BAT_TS_0 Address Register Name POR Value Battery temperature sense 0x0026 CHG_BAT_TS_0 0x01

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 93 of 117 © 2023 Renesas Electronics 7 6 5 4 3 2 1 0 Reserved Reserved TS_DISCHG_MODE_SEL Reserved 0 TS_WARM_EN TS_OFF_MODE TS_EN_DISCHG TS_EN_CHG Field Name Bits POR Description TS_DISCHG_MODE_SEL [5] 0x0 Temp Sense mode selection during discharging Value Description 0x0 (POR) Periodic sampling with 2 s period 0x1 Host triggered sampling TS_WARM_EN [3] 0x0 TS WARM function enable. Write-locked when CE_N is 0, or when TS_EN is not 0. TS_OFF_MODE [2] 0x0 TS OFF mode control. Write-locked when CE_N is 0, or when TS_EN is not 0. Value Description 0x0 (POR) Battery TS feature is disabled when TS_OFF 0x1 Charger fault condition when TS_OFF TS_EN_DISCHG [1] 0x0 Battery temperature sense enable during discharging TS_EN_CHG [0] 0x1 Battery temperature sense enable during charging Table 74: Register CHG_VDD_PWR_0 Address Register Name POR Value VDD_PWR 0x0027 CHG_VDD_PWR_0 0x02 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved ILIM<3:0>

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 94 of 117 © 2023 Renesas Electronics Field Name Bits POR Description ILIM [3:0] 0x2 Input current limit (mA) Value Description 0x0 2.5 0x1 50 0x2 (POR) 100 0x3 150 0x4 200 0x5 250 0x6 300 0x7 350 0x8 400 0x9 450 0xA 500 0xB 550 0xC 600 0xD Reserved 0xE Reserved 0xF Reserved

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 95 of 117 © 2023 Renesas Electronics Table 75: Register CHG_VDD_PWR_1 Address Register Name POR Value VDD_PWR 0x0028 CHG_VDD_PWR_1 0x0C 7 6 5 4 3 2 1 0 Reserved Reserved VDD_PWR_OVP_DIS VDD_PWR_DPM_DIS ILIM_EN VDD_PWR_DPM<2:0> Field Name Bits POR Description VDD_PWR_OVP_DIS [5] 0x0 VDD_PWR OVP disable VDD_PWR_DPM_DIS [4] 0x0 VDD_PWR DPM disable ILIM_EN [3] 0x1 Input current limit enable VDD_PWR_DPM [2:0] 0x4 VDD_PWR DPM threshold voltage (V) Value Description 0x0 4.2 0x1 4.3 0x2 4.4 0x3 4.5 0x4 (POR) 4.6 0x5 4.7 0x6 4.8 0x7 4.9

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 96 of 117 © 2023 Renesas Electronics Table 76: Register CHG_IDISCHG_0 Address Register Name POR Value Battery discharge current limit 0x0029 CHG_IDISCHG_0 0x0D 7 6 5 4 3 2 1 0 Reserved Reserved Reserved IDISCHG_OCP<2:0> IDISCHG_OCP_HIZ_EN IDISCHG_OCP_EN Field Name Bits POR Description IDISCHG_OCP [4:2] 0x3 Battery discharge over-current protection setting (A) Value Description 0x0 0.55 0x1 0.75 0x2 0.95 0x3 (POR) 1.15 0x4 1.35 0x5 1.55 0x6 1.75 0x7 Reserved IDISCHG_OCP_HIZ_EN [1] 0x0 Battery discharge over-current protection enable, even during HiZ IDISCHG_OCP_EN [0] 0x1 Battery discharge over-current protection enable

5.2.4 Buck and LDO Control

5.2.4.1 VOUT User Registers

Table 77: Register VOUT_BUCK Address Register Name POR Value Buck enable and VOUT control 0x0030 VOUT_BUCK 0x5C 7 6 5 4 3 2 1 0 BUCK_EN VOUT_RANGE_HI Reserved BUCK_VOUT<4:0> Field Name Bits POR Description BUCK_EN [7] 0x0 BUCK enable VOUT_RANGE_HI [6] 0x1 Buck output range control. This register can be written when buck is disabled or when BUCK_EN is being written to 0. Value Description 0x0 0.60 V <= VBUCK <= 1.30 V 0x1 (POR) 1.30 V <= VBUCK <= 2.10 V BUCK_VOUT [4:0] 0x1C Buck output voltage setting (0.6 V to 2.1 V in 50 mV steps). Value Description 0x00 0.60 V 0x01 0.65 V

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 98 of 117 © 2023 Renesas Electronics 0x02 0.70 V 0x03 0.75 V 0x04 0.80 V 0x05 0.85 V 0x06 0.90 V 0x07 0.95 V 0x08 1.00 V 0x09 1.05 V 0x0A 1.10 V 0x0B 1.15 V 0x0C 1.20 V 0x0D 1.25 V 0x0E 1.30 V 0x0F 1.35 V 0x10 1.40 V 0x11 1.45 V 0x12 1.50 V 0x13 1.55 V 0x14 1.60 V 0x15 1.65 V 0x16 1.70 V

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 99 of 117 © 2023 Renesas Electronics 0x17 1.75 V 0x18 1.80 V 0x19 1.85 V 0x1A 1.90 V 0x1B 1.95 V 0x1C (POR) 2.00 V 0x1D 2.05 V 0x1E 2.10 V 0x1F Reserved Table 78: Register VOUT_BUCK_CFG Address Register Name POR Value Buck config 0x0031 VOUT_BUCK_CFG 0x00 7 6 5 4 3 2 1 0 Reserved Reserved BUCK_PD_CFG2 Reserved 0 Reserved Reserved SEL_ILIM_DLT<1:0> Field Name Bits POR Description BUCK_PD_CFG2 [5] 0x0 Output discharge enable at buck disable Value Description 0x0 (POR) Enable 0x1 Disable

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 100 of 117 © 2023 Renesas Electronics SEL_ILIM_DLT [1:0] 0x0 Buck peak current limit setting Value Description 0x0 (POR) Default -50 mA 0x1 Default current limit 0x2 Default +50 mA 0x3 Default +100 mA Table 79: Register VOUT_LS_LDO0 Address Register Name POR Value LS_LDO_0 control 0x0032 VOUT_LS_LDO0 0x24 7 6 5 4 3 2 1 0 Field Name Bits POR Description EN_LS_LDO_0 [7] 0x0 LS_LDO_0 enable. LDO becomes active 20 ms after LDO0 is enabled. LS_LDO_0 [5:0] 0x24 LDO0 voltage setting, cannot be written to when LS_LDO0 is enabled. Value Description 0x0 0.8 0x1 0.825 0x2 0.85

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 101 of 117 © 2023 Renesas Electronics 0x3 0.875 0x4 0.9 0x5 0.925 0x6 0.95 0x7 0.975 0x8 1 0x9 1.025 0x0A 1.05 0x0B 1.075 0x0C 1.1 0x0D 1.125 0x0E 1.15 0x0F 1.175 0x10 1.2 0x11 1.225 0x12 1.25 0x13 1.275 0x14 1.3 0x15 1.325 0x16 1.35 0x17 1.375

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 102 of 117 © 2023 Renesas Electronics 0x18 1.4 0x19 1.425 0x1A 1.45 0x1B 1.475 0x1C 1.5 0x1D 1.525 0x1E 1.55 0x1F 1.575 0x20 1.6 0x21 1.65 0x22 1.7 0x23 1.75 0x24 (POR) 1.8 0x25 1.85 0x26 1.9 0x27 1.95 0x28 2 0x29 2.05 0x2A 2.1 0x2B 2.15 0x2C 2.2

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 103 of 117 © 2023 Renesas Electronics 0x2D 2.25 0x2E 2.3 0x2F 2.35 0x30 2.4 0x31 2.45 0x32 2.5 0x33 2.55 0x34 2.6 0x35 2.65 0x36 2.7 0x37 2.75 0x38 2.8 0x39 2.85 0x3A 2.9 0x3B 2.95 0x3C 3 0x3D 3.05 0x3E 3.1 0x3F 3.15

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 104 of 117 © 2023 Renesas Electronics Table 80: Register VOUT_LS_LDO1 Address Register Name POR Value LS_LDO_1 control 0x0033 VOUT_LS_LDO1 0x28 7 6 5 4 3 2 1 0 Field Name Bits POR Description EN_LS_LDO_1 [7] 0x0 LS_LDO_1 enable. LDO becomes active 20 ms after LS_LDO_1 is enabled. LS_LDO_1 [5:0] 0x28 LDO1 voltage setting, cannot be written to when LS_LDO1 is enabled. Value Description 0x0 0.8 0x1 0.85 0x2 0.9 0x3 0.95 0x4 1 0x5 1.05 0x6 1.1 0x7 1.15 0x8 1.2 0x9 1.25

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 105 of 117 © 2023 Renesas Electronics 0x0A 1.3 0x0B 1.35 0x0C 1.4 0x0D 1.45 0x0E 1.5 0x0F 1.55 0x10 1.6 0x11 1.65 0x12 1.7 0x13 1.75 0x14 1.8 0x15 1.85 0x16 1.9 0x17 1.95 0x18 2 0x19 2.05 0x1A 2.1 0x1B 2.15 0x1C 2.2 0x1D 2.25 0x1E 2.3

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 106 of 117 © 2023 Renesas Electronics 0x1F 2.35 0x20 2.4 0x21 2.475 0x22 2.55 0x23 2.625 0x24 2.7 0x25 2.775 0x26 2.85 0x27 2.925 0x28 (POR) 3 0x29 3.075 0x2A 3.15 0x2B 3.225 0x2C 3.3 0x2D Reserved 0x3F Reserved Table 81: Register VOUT_LS_LDO2 Address Register Name POR Value LS_LDO_2 control 0x0034 VOUT_LS_LDO2 0x14

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 107 of 117 © 2023 Renesas Electronics 7 6 5 4 3 2 1 0 Field Name Bits POR Description EN_LS_LDO_2 [7] 0x0 LS_LDO_2 enable. LDO becomes active 20 ms after LS_LDO_2 is enabled. LS_LDO_2 [5:0] 0x14 LDO2 voltage setting, cannot be written to when LS_LDO2 is enabled. Value Description 0x0 0.8 0x1 0.85 0x2 0.9 0x3 0.95 0x4 1 0x5 1.05 0x6 1.1 0x7 1.15 0x8 1.2 0x9 1.25 0x0A 1.3 0x0B 1.35 0x0C 1.4

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 108 of 117 © 2023 Renesas Electronics 0x0D 1.45 0x0E 1.5 0x0F 1.55 0x10 1.6 0x11 1.65 0x12 1.7 0x13 1.75 0x14 (POR) 1.8 0x15 1.85 0x16 1.9 0x17 1.95 0x18 2 0x19 2.05 0x1A 2.1 0x1B 2.15 0x1C 2.2 0x1D 2.25 0x1E 2.3 0x1F 2.35 0x20 2.4 0x21 2.475

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 109 of 117 © 2023 Renesas Electronics 0x22 2.55 0x23 2.625 0x24 2.7 0x25 2.775 0x26 2.85 0x27 2.925 0x28 3 0x29 3.075 0x2A 3.15 0x2B 3.225 0x2C 3.3 0x2D Reserved 0x3F Reserved Table 82: Register VOUT_LS_LDO_CFG Address Register Name POR Value LS_LDO_CFG 0x0035 VOUT_LS_LDO_CFG 0x00 7 6 5 4 3 2 1 0 Reserved SEL_FULLON_2 SEL_FULLON_1 SEL_FULLON_0 Reserved SEL_LDSW_2 SEL_LDSW_1 SEL_LDSW_0

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 110 of 117 © 2023 Renesas Electronics Field Name Bits POR Description SEL_FULLON_2 [6] 0x0 LS_LDO2 current limit enable, cannot be written to when LS_LDO2 is enabled. Value Description 0x0 (POR) Enable 0x1 Disable SEL_FULLON_1 [5] 0x0 LS_LDO1 current limit enable, cannot be written to when LS_LDO1 is enabled. Value Description 0x0 (POR) Enable 0x1 Disable SEL_FULLON_0 [4] 0x0 LS_LDO0 current limit enable, cannot be written to when LS_LDO0 is enabled. Value Description 0x0 (POR) Enable 0x1 Disable SEL_LDSW_2 [2] 0x0 LS_LDO2 function select, cannot be written to when LS_LDO2 is enabled. Value Description 0x0 (POR) LDO 0x1 LDSW SEL_LDSW_1 [1] 0x0 LS_LDO1 function select, cannot be written to when LS_LDO1 is enabled. Value Description 0x0 (POR) LDO 0x1 LDSW

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 111 of 117 © 2023 Renesas Electronics SEL_LDSW_0 [0] 0x0 LS_LDO0 function select, cannot be written to when LS_LDO0 is enabled. Value Description 0x0 (POR) LDO 0x1 LDSW

5.2.4.2 VOUT Opt Registers

Table 83: Register VOUT_BUCK_OPT0 Address Register Name POR Value BUCK_OPT0 0x0050 VOUT_BUCK_OPT0 0x1B 7 6 5 4 3 2 1 0 Reserved 0 Reserved 0 Reserved 0 Reserved 1 Reserved 1 Reserved 0 DVC_STEP<1:0> Field Name Bits POR Description DVC_STEP [1:0] 0x3 DVC step control Value Description 0x0 No DVC 0x1 50 mV / 1 ms 0x2 50 mV / 2 ms 0x3 (POR) 50 mV / 4 ms

6 Package Information

6.1 Package Outlines

Figure 35: WLCSP-42 Package Outline Drawing, V3 Version

6.2 Moisture Sensitivity Level

The Moisture Sensitivity Level (MSL) is an indicator for the maximum allowable time period (floor lifetime) in which a moisture sensitive plastic device, once removed from the dry bag, can be exposed to an environment with a maximum temperature of 30 °C and a maximum relative humidity of 60 % RH before the solder reflow process. The MSL classification is defined in Table 84. The device package is qualified for MSL 1. Table 84: MSL Classification MSL Level Floor Lifetime Conditions MSL 1 Unlimited 30 °C / 85 % RH

6.3 Soldering Information

Refer to the IPC/JEDEC standard J-STD-020 for relevant soldering information. This document can be downloaded from http://www.jedec.org.

7 Ordering Information

The ordering number consists of the part number followed by a suffix indicating the OTP variant (xx), package type, and packing method. For details and availability, please consult Renesas Electronics’ customer support portal or your local sales representative. Table 85: Ordering Information Part Number Package Size (mm) Shipment Form Pack Quantity DA9072-xxV32 WLCSP 2.97 x 2.66 T&R 2000 DA9072-xxV36 WLCSP 2.97 x 2.66 Waffle 90 DA9072-xxOH2 WLCSP 2.97 x 2.66 T&R 2000 DA9072-xxOH6 WLCSP 2.97 x 2.66 Waffle 90

8 Application Information

8.1 Recommended External Components

Component values shown are typical values (not de-rated). For capacitors assume X5R type or better with a DC voltage rating of 2x the maximum applied voltage. For inductors, the saturation current rating is equal or greater than the current limit value. The Electrical Specifications are based on the typical values where applicable. Parameter Description Conditions Min Typ Max Unit CVDD_SYS VDD_SYS capacitance 3.3 4.7 100 µF CVDD_PWR VDD_PWR capacitance 1.0 4.7 10 µF CVBAT VBAT capacitance 1.0 2.2 10 µF CVOUT_BUCK Buck output capacitance 10 µF CVDD_BUCK Buck input capacitance 1.0 2.2 µF LBUCK Buck inductor 2.2 µH CVOUT_LDO LDO output capacitance 1.0 2.2 2.2 µF CVDD_LDO LDO input capacitance 1.0 µF

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 116 of 117 © 2023 Renesas Electronics Status Definitions Revision Datasheet Status Product Status Definition 1.<n> Target Development This datasheet contains the design specifications for product development. Specifications may be changed in any manner without notice. 2.<n> Preliminary Qualification This datasheet contains the specifications and preliminary characterization data for products in pre-production. Specifications may be changed at any time without notice in order to improve the design. 3.<n> Final Production This datasheet contains the final specifications for products in volume production. The specifications may be changed at any time in order to improve the design, manufacturing and supply. Major specification changes are communicated via Customer Product Notifications. Datasheet changes are communicated via www.renesas.com. 4.<n> Obsolete Archived This datasheet contains the specifications for discontinued products. The information is provided for reference only. RoHS Compliance Renesas Electronics’ suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from our suppliers are available on request.

Ultra-Low Quiescent Current PMIC Datasheet Revision 3.2 13-Jun-2023 CFR0011-120-00 117 of 117 © 2023 Renesas Electronics Important Notice and Disclaimer RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. © 2023 Renesas Electronics Corporation. All rights reserved. Corporate Headquarters TOYOSU FORESIA, 3-2-24 Toyosu Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: https://www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. (Rev.1.0 Mar 2020)

Product Information

DA9072-XXOH6 specifications and overview.

Summary

Ultra-Low Quiescent Current PMIC 13-Jun-2023

Description

Ultra-Low Quiescent Current PMIC 13-Jun-2023

Source title DA9072-XXOH6 Datasheet(PDF) - Renesas Technology Corp

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