Driver IC

DA7282-00FV2

Renesas Technology Corp

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory 10-Feb-2022

Manufacturer: Renesas Technology Corp

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LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 1 of 87 © 2022 Renesas Electronics General Description DA7282 is a linear resonant actuator (LRA) and eccentric rotating mass (ERM) haptic driver offering automatic closed-loop LRA resonant frequency tracking. The feature guarantees consistency across LRA production tolerances, operating temperature, aging, and mechanical coupling. DA7282 offers wideband operation that fully utilizes the capabilities of newer wideband and multi-directional LRAs. The differential output drive architecture and continuous actuator motion sensing enable efficient, calibration-free playback and minimize software complexity. Featuring wake-up on General Purpose Input (GPI) sequence triggers and/or I2C activity, DA7282 automatically returns to a low quiescent current state (typically 0.68 µA) between playbacks. In OFF mode the device consumes only 5 nA making it suitable for low power applications. To reduce system complexity, an integrated Waveform Memory allows haptic sequences to be pre- loaded to DA7282. Independent sequences can be triggered, with low-latency (0.75 ms), by up to three separate input pins without host interaction. Haptic sequences can also be streamed to DA7282 from an external source via I2C or pulse width modulated (PWM) signals. DA7282 actively monitors the back electromotive force (BEMF) while continuously driving and applies closed-loop Active Acceleration and Rapid Stopping for sharper clicks and a higher fidelity user experience. This offers significant advantages over existing solutions that need to move into a high-impedance state during drive to measure the BEMF, which adds a considerable amount of inactive time to the sequence and lowers the effective click strength for a given LRA. Key Features ■ LRA or ERM drive capability ■ Automatic LRA resonant frequency tracking ■ Wideband LRA support ■ I2C and PWM input streaming ■ Low latency (0.75 ms) I2C/GPI wake-up from low power consumption IDLE state, IQ = 0.68 µA ■ Ultra-low latency (0.15 ms) wake-up from STANDBY state, IQ = 0.8 mA ■ Three GPI pins for triggering of up to six independent haptic sequences ■ On-board Waveform Memory with amplitude, time, and frequency control ■ Active Acceleration and Rapid Stop technology for high-fidelity haptic feedback ■ Actuator diagnostics and fault handling ■ Configurable EMI suppression ■ No software requirements with embedded operation ■ Differential PWM output drive ■ Current driven system to deliver constant actuator power ■ Automatic short circuit protection ■ Ultra-low power consumption, IQ = 5 nA, when device is disabled ■ Ultra-low power consumption, IQ = 0.68 µA, with state retention in IDLE state ■ Supply monitoring, reporting, and automatic output limiting ■ Open- and closed-loop modes ■ Custom wave drive support ■ Small solution footprint requiring only one decoupling capacitor in both WLCSP and QFN

Applications

■ Smartphones, wearables, and hearables ■ Computer peripherals ■ Gaming ■ Automotive and industrial ■ Virtual and augmented reality controllers ■ Disposable consumer products References Battery Monitor Over- Temperature Protection VDDIO/EN SCL SDA GND nIRQ GPI_0/ PWM GPI_1 GPI_2 DA7282 VDD OUTP OUTN LRA/ ERM Regulation Loop ERC Driver ERC Driver Short Circuit Protection BEMF Sensing and Actuator Diagnostics I2C Resonant Frequency Tracking, Active Acceleration, Rapid Stop, and Waveform Memory

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 3 of 87 © 2022 Renesas Electronics System Diagrams GPI and I2C PWM Only I2C Only Embedded Operation DA7282 OUTN OUTP SCL SDA GPI_0/PWM GPI_1 GPI_2 LRA/ ERM VDD VBAT DA7282 OUTN OUTP SCL SDA GPI_0/PWM GPI_1 GPI_2 LRA/ ERM VDD VBAT DA7282 OUTN OUTP SCL SDA GPI_0/PWM GPI_1 GPI_2 LRA/ ERM VDD VBAT DA7282 OUTN OUTP SCL SDA GPI_0/PWM GPI_1 GPI_2 LRA/ ERM VDD VBAT DA7282 OUTN OUTP SCL SDA GPI_0/PWM GPI_1 GPI_2 LRA/ ERMSensor Hub or Button Press Detect VDD VBAT DA7282 OUTN OUTP SCL SDA GPI_0/PWM GPI_1 GPI_2 LRA/ ERM VDD VBAT GND GND GND GNDGND GND nIRQ nIRQnIRQ nIRQ nIRQ nIRQ Embedded Operation No Host External Boost up to 5.5V VBST External Boost Operation Host (startup only) VDDIO/EN VDDIO/EN VDDIO/EN VDDIO/EN VDDIO/EN System VDDIO VDDIO/EN System VDDIO System VDDIO Host System VDDIO Host Host System VDDIO Host System VDDIO Host Figure 1: System Diagrams

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 7 of 87 © 2022 Renesas Electronics Legal NOTWITHSTANDING ANYTHING TO THE CONTRARY IN THIS DOCUMENT OR IN ANY OTHER AGREEMENT, CUSTOMER ACKNOWLEDGES THAT THE PRODUCTS ARE PROVIDED WITHOUT ANY WARRANTY OF NON-INFRINGEMENT, AND THAT IF ANY LICENSE OR RIGHT IS REQUIRED TO BE OBTAINED FROM ANY THIRD PARTY, THIS RESPONSIBILITY SHALL REST SOLELY WITH CUSTOMER. Product Family Table 1: DA728x Feature Comparison Feature DA7280 DA7281 DA7282 DA7283 OFF state via VDDIO/EN pin No No Yes Yes OFF state current N/A N/A 5 nA 5 nA IDLE state current 360 nA 360 nA 680 nA 680 nA Number of GPI sequence trigger pins 3 1 3 3 I2C interface Yes Yes Yes No Multiple I2C addressing No Yes No N/A Operation without a host No No No Yes

1 Terms and Definitions

BEMF Back electromotive force CDM Charged device model DMA Dual mode actuator DRO Direct register override EMI Electromagnetic interference ERC Edge rate control ERM Eccentric rotating mass ESD Electrostatic discharge ETWM Edge triggered Waveform Memory FET Field-effect transistor GND Ground GPI General purpose input Half-period One half of the LRA resonant frequency period. For example if fLRA = 200 Hz, one half-period is 2.5 ms. HBM Human body model IRQs Interrupt requests LRA Linear resonant actuator OTP One time programmable PCB Printed circuit board PID Proportional-Integral-Derivative PoR Power-on reset PWL Piecewise linear PWM Pulse width modulated QFN Quad flat no leads RC Resistor-capacitor RTWM Register triggered Waveform Memory WLCSP Wafer level chip scale package

2 Block Diagram

Tracking, Active Acceleration, Rapid Stop, and Waveform Memory Regulation Loop VDDIO/EN SCL SDA GND nIRQ n-Side Output Driver with ERC p-Side Output Driver with ERC GPI_0/PWM GPI_1 GPI_2 DA7282 BEMF Sensing and Actuator Diagnostics VDD OUTP OUTN LRA/ ERM Short Circuit Protection Figure 2: DA7282 Block Diagram

3 Pinout

A B C D GPI_1 SDAnIRQ SCL GPI_2 OUTN OUTP GPI_0/PWM VDD VDDIO_EN GND_2 GND_1 Analog signalPower GroundDigital signal Top view 4 5 6 101112 VD D OUTP GND_1 SDA SCL nIRQ 3 7 9GPI_2 GPI_1 GPI_0/PW M GND_2 OUTN VD DIO/EN Pin 1 GroundAnalog signal Digital signalPower Top view Figure 3: DA7282 Pinout Diagrams (Top View) for WLCSP (Left) and QFN (Right) Table 2: Pin Description Pin No. WLCSP Pin No. QFN Pin Name Type (Table 3)

Description

A1 12 nIRQ DO Interrupt request line, open-drain, active low, connect to system VDDIO supply via external pull-up resistor A2 11 SCL DI I2C clock input, open-drain, connect to system VDDIO supply via external pull-up resistor A3 10 SDA DIO I2C data input/output, open-drain, connect to system VDDIO supply via external pull-up resistor B1 2 GPI_1 DI GPI sequence trigger 1 B2 1 GPI_2 DI GPI sequence trigger 2 B3 9 VDDIO/EN PWR Digital IO supply / device enable function, active low. Connect to system VDDIO via push-pull GPIO or small- value resistor C1 3 GPI_0/PWM DI GPI sequence trigger 0, or PWM input C2 8 OUTN AO Haptic driver negative output C3 7 GND_2 GND Ground D1 4 VDD PWR Haptic power supply; decouple to GND_1 D2 5 OUTP AO Haptic driver positive output D3 6 GND_1 GND Ground Table 3: Pin Type Definition Pin Type Description Pin Type Description DI Digital input AO Analog output

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 11 of 87 © 2022 Renesas Electronics Pin Type Description Pin Type Description DO Digital output PWR Power DIO Digital input/output GND Ground

4 Characteristics

4.1 Absolute Maximum Ratings

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification are not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Table 4: Absolute Maximum Ratings Parameter Description Conditions Min Max Unit VDD Haptic power supply (battery or regulated rail) Referenced to GND -0.3 6 V VDDIO_EN Digital IO supply and device enable -0.3 6 V VOUTN Haptic driver negative output -0.3 6 V VOUTP Haptic driver positive output -0.3 6 V VnIRQ Interrupt request line to host -0.3 6 V VSCL I2C clock input -0.3 6 V VSDA I2C data input/output -0.3 6 V VGPI General purpose inputs -0.3 6 V TA Operating ambient temperature -40 85 °C TJ Operating junction temperature -40 125 °C TSTG Storage temperature -65 150 °C ESDHBM ESD protection Human Body Model (HBM) All non-exposed pins 4 kV ESDCDM ESD protection Charged Device Model (CDM) 1 kV

4.2 Recommended Operating Conditions

Unless otherwise noted, the parameters listed in Table 5 are valid for TA = 25 ºC, VDD = 3.8 V, and VDDIO_EN = 1.8 V.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 12 of 87 © 2022 Renesas Electronics Table 5: Recommended Operating Conditions Parameter Description Conditions Min Typ Max Unit VDD Haptic power supply (battery or regulated rail) 2.8 3.8 5.5 V VDDIO_EN Digital IO supply and device enable (Note 1.35 1.8 5.5 V ZLD Nominal LRA DC impedance 4 50 Ω CLD Capacitance to ground on OUTP and OUTN 1 nF fLRA Nominal LRA resonant frequency Frequency tracking enabled 50 300 Hz fLRA_OL Nominal LRA resonant frequency, open-loop Frequency tracking disabled 25 1000 Hz Note 1 During device operation VDDIO_EN must be ≤ VDD if GPI_0, GPI_1, and GPI_2 are not grounded.

4.3 Electrical Characteristics

Unless otherwise noted, the parameters listed in Table 6 and Table 7 are valid for TA = 25 ºC, VDD = 3.8 V, and VDDIO_EN = 1.8 V. Table 6: Current Consumption Paramete r Description Conditions Min Typ Max Unit IQ_OFF System VDD current in OFF state VDDIO_EN = 0 V 5 nA IQ_IDLE System VDD current in IDLE state System waiting for playback request 0.68 1 μA IQ_EN VDDIO/EN pin current VDDIO_EN = system VDDIO No I/O or nIRQ activity 0.13 0.5 μA IQ_STANDBY System VDD current in STANDBY state System waiting for playback request 0.8 1 mA IQ_NO_LD System VDD current with no load High-impedance load >

10 MΩ, H-bridge switching

1.35 1.5 mA Table 7: Electrical Characteristics Paramete r Description Conditions Min Typ Max Unit ISHRT Short circuit protection threshold Short to GND or VDD 400 500 600 mA IOUT_MAX Maximum drive current 250 500 (Note 1) mA fTRCK_LRA LRA frequency tracking range Automatic tracking limits 50 300 (Note 2) Hz fTRCK_ACC_L RA LRA frequency tracking accuracy Frequency tracking accuracy during playback 0.5 Hz

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 13 of 87 © 2022 Renesas Electronics Paramete r Description Conditions Min Typ Max Unit fWIDEBAND Wideband frequency range User defined drive frequency 25 1000 Hz fOUT_PWM PWM output frequency Differential OUTP and OUTN switching frequency 183 187. 192 kHz ERC Programming range of output switching pins edge rate control OUTP and OUTN slope 25 100 100 mV/n s fIN_PWM PWM data input frequency 10 250 kHz RDS_ON H-bridge drain to source resistance when on High side plus low side FETs 2 Ω ZFLT_UZ Actuator under-impedance threshold Not applicable for coin ERM 4 Ω ZFTL_OZ Over-impedance threshold Not applicable for coin ERM 50 Ω ZOUT_OFF Output impedance when H- bridge not switching Pull-down enabled 15 kΩ VDD_POR_FA LL VDD Power-on-Reset (PoR) falling threshold 2.4 2.55 2.7 V Note 1 For operation up to 500 mA (instead of 250 mA), see Section 5.7.12. Note 2 For operation outside this range, see Section 5.7.1.

4.4 Timing Characteristics

Unless otherwise noted, the parameters listed in Table 8 are valid for TA = 25 ºC, VDD = 3.8 V, and VDDIO_EN = 1.8 V. Table 8: Timing Characteristics Parameter Description Conditions Min Typ Max Unit tON Cold boot to IDLE state time VDD present and VDDIO_EN= VDDIO 1.2 1.5 ms tOUT_IDLE Time to output from IDLE state From GPI or I2C trigger to output drive 0.7 ms tOUT_STANDB Y Time to output from STANDBY state From GPI or I2C trigger to output drive 0.1 ms STOP SDA SCL tFALL tRISE tFALL START tHOLD_START tHOLD_DATA 1/fSCL 70% 30% 70% 30% tSETUP_DATA tLO_SCL tHI_SCL tDATA ACK tDATA_ACK tSETUP_STOPtSETUP_START Figure 4: I2C Interface Timing

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 14 of 87 © 2022 Renesas Electronics Table 9: I2C Interface Timing Requirements Parameter Description Conditions Min Max Unit tBUF Bus free time from STOP to START condition 0.5 µs Standard, Fast, and Fast-Plus Modes CBUS Bus line capacitive load 520 pF fSCL SCL clock frequency 0 1000 (Note 1) kHz tSETUP_START Start condition setup time 0.26 µs tHOLD_START Start condition hold time 0.26 µs tLO_SCL SCL low time 0.5 µs tHI_SCL SCL high time 0.26 µs tRISE SCL and SDA rise time 120 ns tFALL SCL and SDA fall time 120 ns tSETUP_DATA Data setup time 50 ns tHOLD_DATA Data hold-time 0 ns tSETUP_STOP Stop condition setup time 0.26 µs tDATA Data valid time 0.45 µs tDATA_ACK Data valid acknowledge time 0.45 µs tSPIKE Spike suppression (SCL, SDA) Fast/Fast+ mode 50 ns Note 1 fSCL maximum is 400 kHz at VDDIO_EN ≤ 1.65 V and 1000 kHz at VDDIO_EN > 1.65 V.

4.5 Thermal Characteristics

Table 10: WLCSP Thermal Ratings Parameter Description (Note 1) Min Typ Max Unit RƟJA Junction-to-ambient thermal resistance 90.3 °C/W RƟJC_TOP Junction-to-case (top) thermal resistance 43.6 °C/W RƟJB Junction-to-board thermal resistance 49.0 °C/W JT Junction-to-top characterization parameter 6.4 °C/W JB Junction-to-board characterization parameter 45.8 °C/W Note 1 Multilayer JEDEC standard, still air, ambient temperature 25 °C, simulated value.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 15 of 87 © 2022 Renesas Electronics Table 11: QFN Thermal Ratings Parameter Description (Note 1) Min Typ Max Unit RƟJA Junction-to-ambient thermal resistance 88.2 °C/W RƟJC_TOP Junction-to-case (top) thermal resistance 54.6 °C/W RƟJB Junction-to-board thermal resistance 39.3 °C/W JT Junction-to-top characterization parameter 3.4 °C/W JB Junction-to-board characterization parameter 50.0 °C/W RƟJC_BOTTOM Junction-to-case (bottom) thermal resistance 4.4 °C/W Note 1 Multilayer JEDEC standard, still air, ambient temperature 25 °C, simulated value.

5 Functional Description

DA7282 is a haptic driver capable of driving both LRA and ERM actuators. The power-optimized architecture and advanced closed-loop digital algorithms achieve a very high-fidelity haptic drive. It features frequency control within an onboard Waveform Memory and three distinct GPI inputs, for triggering up to six distinct sequences. This helps with emulating button pressing in many applications including gaming, mobile, and wearable devices. The device controls the level of drive across the load and senses the movement of the actuator. The driven waveform is generated by a current regulated loop using a high-frequency PWM modulation. The differential output drive features a switching regulator architecture with H-bridge differential drive across the load at a frequency of 187.5 kHz. The drive level is based on the sequence from the data source selected by I2C interface, input PWM signal, or Waveform Memory. DA7282 is capable of closed-loop actuator monitoring while driving to enable calibration-free playback, frequency tracking (LRA only), Active Acceleration, Rapid Stop, and actuator diagnostics. Continuous resonant frequency tracking can be enabled while driving an LRA to track the mechanical resonance of the actuator through closed-loop control. This maximizes electrical to mechanical energy conversion efficiency for narrowband actuators and is especially useful in applications such as operating system notifications and alarms. Resonant frequency tracking can be disabled to operate DA7282 in open-loop wideband frequency operation while driving LRAs with a wider bandwidth frequency response. Active Acceleration and Rapid Stop features enable automated driving of both ERM and LRA loads (when frequency tracking is enabled). This reduces the time to reach the target acceleration level and the time for the actuator to come to a complete stop.

5.1 Features Description

Driving LRA and ERM Actuators DA7282 can drive both ERMs and LRAs depending on the register configuration, see Section 5.6.2. Automatic LRA Resonant Frequency Tracking LRA resonant frequency shifts over time due to changing operating conditions, such as temperature or position, and manufacturing spread. LRAs are high-Q systems; if driven at a fixed frequency, the consequences are loss of electrical to mechanical energy conversion efficiency, weaker than nominal actuator acceleration output, and significant part-to-part variation in the end-product haptic feel. Figure 5 illustrates that if the drive frequency is fixed, for example at 200 Hz, frequency variation in the resonant peak of only 10 Hz can result in a loss of 50 % of the output acceleration.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 18 of 87 © 2022 Renesas Electronics Frequency [Hz] Acceleration Output [g] 0.5 200 X-axis Resonance 100 Y-axis Resonance Useful Operating Range X-axis Vibration Y-axis Vibration Dual Mode LRA Figure 7: Dual Mode LRA Response across Frequency The ability of DA7282 to control the frequency (25 Hz to 1000 Hz) and amplitude of the drive over time as well as the type of output wave allows the use of wideband sequences fully utilizing the capabilities of wideband and dual mode actuators for creating a richer user experience, see Section 5.7.5. Example use cases in DMAs are excitation of both resonant peaks simultaneously for maximum perceptible vibration or distinct single-frequency event-signaling clicks at different resonant frequencies and physical directions. Both DMAs and wideband LRAs can also be used to augment user audio experience by playing audio-derived haptic sequences over their useful frequency operating range. DA7282 supports all of the above use cases and drives wideband LRAs via I2C or wideband Waveform Memory sequences triggered by I2C or GPIs. The output drive can be configured as either square wave, sine wave, or custom wave to create different end effects, see Section 5.7.6. Usually, LRA resonant frequency tracking is disabled during wideband operation. However, it can be enabled to either locate the resonant peak of wideband actuators, or to operate at a selected DMA resonance point and achieve the maximum possible actuator acceleration for a set input power, see Section 5.3 and Section 5.7.1. I2C and PWM Input Streaming Haptic playback data can be streamed externally either via I2C direct register override or from a PWM data source, see Section 5.2.2. The external input data PWM frequency is independent of the output PWM signal frequency driven to the actuator. The input PWM signal is low-pass filtered to create a varying DC level that is the envelope for the drive across the actuator. Ultra-Low Power Consumption when Disabled In the OFF state when VDDIO_EN = 0 V, DA7282 has an ultra-low current consumption from the power supply, at typically 5 nA. This is the lowest power state of the device. In OFF state the device is fully Low Latency I2C/GPI Wake-Up from IDLE State The device supports low latency (0.75 ms) wake-up from IDLE state, which is the lowest power state (typically 0.68 µA from VDD). Wake-up is triggered by either GPI or I2C activity. I2C is fully functional in all modes including IDLE state and DA7282 retains register settings in all modes, see Section 5.2.1. Three GPI Sequence Triggers for up to Six Independent Haptic Responses DA7282 supports up to three GPI inputs which can be used to trigger low-latency playback of up to six distinct sequences from IDLE state, see Section 5.2.7. Triggering is activated on events caused by rising or falling edges, or both. The sequence playback is configurable and a GPI can be

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 19 of 87 © 2022 Renesas Electronics associated with either one or two sequences. In the second case, odd events trigger one sequence, while even events another. On-Board Waveform Memory with Amplitude, Time, and Frequency Control DA7282 contains 100 bytes of highly optimized on-board Waveform Memory for user programmable haptic sequences, see Section 5.8. The Dialog Semiconductor specific format allows control of not only amplitude and time, but also frequency during the playback of a haptic sequence. This is specifically intended for use with wideband and dual mode actuators to create a richer user experience. Active Acceleration and Rapid Stop for High-Fidelity Haptic Feedback By measuring and responding to the BEMF of the actuator, DA7282 supports Active Acceleration which improves actuator response both when increasing and decreasing drive amplitude by overdriving or underdriving relative to the desired drive level. Similarly, Rapid Stop minimizes the time needed for the actuator to come to a complete stop by driving against the direction of actuator movement. These two features enable a high-fidelity haptic response of the actuator and improve on its inherent physical performance and mechanical time constant, see Section 5.4. Continuous Actuator Diagnostics and Fault Handling DA7282 monitors the actuator impedance at the start of each haptic sequence. The value of the impedance can be read back from a dedicated register, see Section 5.7.3. In addition, impedance, BEMF, and resonant frequency faults are flagged with automatic shutdown and notification via the nIRQ pin, see Section 5.6.6. No Software Requirements with Embedded Operation The device can function in a stand-alone embedded operation where no host action is needed to clear generated faults and the device will attempt to drive on each request. This also allows operation in GPI trigger mode without the need for a host device or host communication, see Section 5.7.7. Note that initial download of sequences to the device is still required. Once loaded, the Waveform Memory is retained in all states as long as the supply does not drop below the PoR threshold. Differential Output Drive DA7282 includes a full H-bridge differential output PWM drive that has the advantage of maximizing the power delivered to the LRA from a given supply and allows braking of DC motors by reversing voltage polarity. This doubles the voltage swing across the actuator and significantly increases system efficiency relative to a single transistor/LDO solution in legacy ERM or LRA applications. Current Driven System The device outputs regulated current, rather than voltage, which allows BEMF tracking without the need to stop driving to sense the BEMF. This maximizes power delivery to the actuator per unit time when compared to voltage driven solutions, resulting in shorter and sharper haptic clicks. In addition, constant current drive provides constant force into an actuator independently of the BEMF amplitude. Configurable EMI Suppression Switching node edge rate control (ERC) on the OUTP and OUTN pins reduces electromagnetic interference (EMI) and electrical interference via capacitive coupling in the end application, see Section 5.7.11. This eliminates any need for resistor-capacitor (RC) or ferrite bead filtering of the outputs, which offers a lower-cost bill of materials when using DA7282. Programmability of the ERC

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 20 of 87 © 2022 Renesas Electronics also gives DA7282 a distinct advantage over competing solutions as it helps fine-tune a system without any PCB modifications. Automatic Short Circuit Protection Automatic low-latency short circuit protection detects shorts on the OUTP and OUTN pins to supply, ground, or between OUTP and OUTN, and protects DA7282 by forcing the H-bridge into a high- impedance state, see Section 5.6.6. Ultra-Low Power Consumption with State Retention In IDLE state, DA7282 has an ultra-low current consumption from the power supply at typically 0.68 µA with a time to output of 0.75 ms. DA7282 returns automatically to IDLE state after completing playback, keeps its internal state, and is available for I2C communications, see Section 5.2.1. Ultra-Low Latency in STANDBY State In STANDBY state, the time to output is 0.15 ms with current consumption of typically 0.8 mA, see Section 5.2.1. Supply Monitoring, Reporting, and Automatic Output Limiting DA7282 monitors the power supply voltage level and adjusts the drive voltage accordingly, so that the output does not clip to the supply voltage. This feature guarantees controlled output allowing continued resonant frequency tracking and Active Acceleration/Rapid Stop functionality even when the device is operating under low power supply conditions or heavy battery load. Supply voltage can be read back by the host from a dedicated register, see Section 5.7.13. Open- and Closed-Loop Modes DA7282 can be configured in either open- or closed-loop mode. In open-loop mode any actuator BEMF monitoring is disabled and the device works as a simple current based drive without any auto- adjustment on the drive period or amplitude. This is useful in wideband LRA playback. In closed-loop mode, the user can optionally turn on the frequency tracking, Active Acceleration, Rapid Stop, and Open-Loop Sine/Custom Wave Drive Support In open-loop operation DA7282 can be configured to drive the actuator with a non-square wave signal. This improves the electrical efficiency, reduces audibility in some actuators, and allows simultaneous drive of multiple resonant points in DMAs. The exact shape of the output waveform can be configured via dedicated registers with the default set to a sine wave, see Section 5.7.6. Small Solution Footprint Available in an ultra-small 1.35 mm x 1.75 mm, 0.4 mm pitch, 0.545 mm height, 3 x 4 WLCSP, or a 3.0 mm x 3.0 mm, 0.65 mm pitch, 0.78 mm height, 12 lead QFN package, DA7282 minimizes the required PCB size and overall solution cost. In the typical application case, only a single 100 nF decoupling capacitor is required. See Section 9 and Section 10. Additional Features DA7282 also features:

A temperature and supply stable (±1.5 %) internal oscillator which guarantees consistent haptic playback in the frequency domain over a wide range of operating conditions.

Automatic over-temperature warning and shutdown capability.
Low pad leakage current (typ. < 50 nA, for all pads combined).
Low idle current from the VDDIO/EN pin (typ. 130 nA at 1.8 V).
I2C operation down to VDDIO = 1.35 V.
Output PWM frequency, at 187.5 kHz, is 167.5 kHz away from the audio band and at a non-audio sample rate multiple. This prevents audible fold back via supply disturbance common in near- audio-band switching haptic drivers.
Easy to use Dialog SmartCanvas™ GUI with a user tab for fast device setup without the need to directly interact with registers and an intuitive graphical environment for Waveform Memory editing and visualization.

5.2 Functional Modes

5.2.1 System States

DA7282 features IDLE and STANDBY states ensuring lowest power consumption and lowest start- up latency in different operating conditions. In addition, when any fault is detected, the device returns directly to the IDLE state. Figure 8 shows the device states and the transitions into and out of each state. When a power supply is applied, DA7282 loads the register default settings. Once BOOT is complete, DA7282 remains in the IDLE state and awaits further I2C communication. DA7282 enters the DRIVE state when playback of a haptic sequence begins. There are several different operating modes for playback, see Section 5.2.2. On completion of playback, DA7282 leaves DRIVE state and returns either to IDLE state (for low power consumption) or STANDBY state (for low latency-to-drive). This is configured using STANDBY_EN. If a fault condition occurs, DA7282 returns to the IDLE state, see Section 5.6.6 .

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 23 of 87 © 2022 Renesas Electronics IDLE (IQ = 0.68 µA) BOOT Boot complete OFF (IQ = 5 nA) DRIVESTANDBY (IQ = 0.8 mA) Start driving approx. 0.75 ms after drive request Stop driving Set STANDBY_EN = 0 STANDBY_EN VDD V VDDIO/EN V Start driving after approx. 0.15 ms delay Return to OFF at any time if: VDDIO/EN = 0 V or VDD < 2.6 V The conditions for start/ stop driving vary depending on OPERATION_MODE DA7282 returns to the IDLE state in a fault condition Figure 8: System State Diagram

5.2.2 Operating Modes

DA7282 offers multiple operating modes for use in different applications and to minimize power consumption, see Table 12. Table 12: Operating Modes Operating Mode Description OPERATION_MODE Inactive System waits in IDLE or STANDBY state based on STANDBY_EN setting Direct register override (DRO) Playback streaming via I2C; input written to OVERRIDE_VAL Pulse width modulated (PWM) Playback streaming from PWM data input source on pin GPI_0 / PWM

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 24 of 87 © 2022 Renesas Electronics Operating Mode Description OPERATION_MODE Register triggered waveform memory (RTWM) Playback from Waveform Memory triggered only by I2C write to SEQ_START Edge triggered waveform memory (ETWM) Playback from Waveform Memory triggered by rising/falling edge on any of three GPIs or via I2C write to SEQ_START

5.2.3 Inactive Mode

DA7282 can be configured to automatically return to IDLE (for lower IQ) or STANDBY (for minimized latency) state after completion of playback, see Section 5.2.1. In both states the register contents are retained. DA7282 remains in Inactive mode until it receives a playback request via either the GPI pins or I2C (providing any faults in the fault registers have been cleared, see Section 5.6.6). In the event of a fault the system will automatically return to the IDLE state, see Section 5.6.6.

5.2.4 Direct Register Override Mode

In DRO mode haptic sequences are streamed to DA7282 via I2C input. The drive level of the output is set via OVERRIDE_VAL. For optimal start-up timing, update OVERRIDE_VAL before setting OPERATION_MODE = 1. OVERRIDE_VAL is treated as a two's complement proportional value where: If ACCELERATION_EN = 1, the output drive level is equal to the value in OVERRIDE_VAL multiplied by the voltage stored in ACTUATOR_NOMMAX. OVERRIDE_VAL is interpreted as a proportion between 0 % (0x00) and 100 % (0x7F). The range from 0xFF to 0x80 is not used, see Figure 31. If enabled, the automatic Active Acceleration and Rapid Stop features will take the output up to the voltage in ACTUATOR_ABSMAX and/or reverse the drive level to be negative during level transitions, but in steady state the value will always scale to the voltage in ACTUATOR_NOMMAX. If ACCELERATION_EN = 0, the output drive level is equal to the value in OVERRIDE_VAL multiplied by the voltage stored in ACTUATOR_ABSMAX. In this case OVERRIDE_VAL is interpreted as a proportion between -100% (0x80) and 100% (0x7F), see Figure 32. When DA7282 is set up to drive an ERM, the negative value represents a change in drive voltage polarity, while for an LRA it represents a phase shift of 180° in the drive signal. Negative drive can be used to speed up output acceleration level changes without the use of the Active Acceleration and Rapid Stop. Note that in the ACCELERATION_EN = 0 case Rapid Stop can still be enabled if an automatic stop to zero actuator acceleration is required. Note: The output amplitude updates at twice the LRA frequency (when the differential voltage across the LRA crosses zero), therefore input changes more frequent than this are not required as sampling occurs only around a zero cross. Since the I2C is asynchronous to the output drive, updates to OVERRIDE_VAL will have a one LRA half-period of uncertainty before propagating to the output. Synchronization of OVERRIDE_VAL updates to the half period is possible via software by looking at the POLARITY register and updating the output drive level, see Section 5.7.8. When driving a wideband LRA in DRO mode, resonant frequency tracking can be turned off. This During playback, if a value written to OVERRIDE_VAL results in the output driving strength being maintained at 0 %, DA7282 will disable its output stage to save power. Drive is re-enabled automatically, with one LRA half-period delay, when a non-zero OVERRIDE_VAL value I2C input is received.

5.2.5 Pulse Width Modulation Mode

PWM mode is used to stream haptic sequences to DA7282 via the GPI_0/PWM input pin where the output drive level is determined by the duty cycle of the PWM signal. For optimal start-up timing, the PWM input signal needs to be provided before setting OPERATION_MODE = 2. The PWM duty cycle can be interpreted in two ways as follows: If ACCELERATION_EN = 1, the output drive level is equal to the input signal duty cycle multiplied by the voltage stored in ACTUATOR_NOMMAX. In this case the duty cycle is interpreted as a proportion between 0 % and 100 %, see Figure 31. The automatic Active Acceleration and Rapid Stop (if enabled) features will take the output up to the voltage in ACTUATOR_ABSMAX and/or reverse the drive level to be negative during level transitions, but in steady state the final value will always scale to the voltage in ACTUATOR_NOMMAX. If ACCELERATION_EN = 0, the output drive level is equal to the input signal duty cycle multiplied by the voltage stored in ACTUATOR_ABSMAX. In this case the duty cycle is interpreted as a proportion between -100 % and 100 % where 50 % duty cycle is 0 %, see Figure 32. When DA7282 is set up to drive an ERM, the negative value represents a change in drive voltage polarity, while for an LRA it represents a phase shift of 180° in the drive signal. Negative drive can be used to speed up output acceleration level changes without the use of the Active Acceleration and Rapid Stop. Note that in the ACCELERATION_EN = 0 case Rapid Stop can still be enabled if an automatic stop to zero actuator acceleration is required. Note: The output PWM frequency is always independent of the PWM input frequency regardless of whether frequency tracking is enabled or disabled. To maximize accuracy and minimize power consumption and noise, it is best to keep the input PWM frequency as low as possible. The PWM demodulator is rising edge sensitive. The minimum duty cycle that can be used to create the drive level can be configured in FULL_BRAKE_THR; any duty cycle below that value will produce a 0 % drive level. During playback streaming in PWM mode, if a 0 % drive level is maintained by applying a 0 % (or 50 % if Active Acceleration is disabled) duty cycle PWM input, the DA7282 output stage is disabled to save power. Drive is re-enabled automatically, with one LRA half-period delay, when the duty cycle forces the drive level to be greater than 0 %. ACCELERATION_EN = 0, 60% Duty Cycle ACCELERATION_EN = 0, 90% Duty Cycle ACCELERATION_EN = 0, 50% Duty Cycle ACCELERATION_EN = 0, 40% Duty Cycle ACCELERATION_EN = 0, 10% Duty Cycle PWM Signal DA7282 Output Figure 9: Example PWM Inputs with ACCELERATION_EN = 0 Note the 180° phase difference between driving > 50 % and < 50 %.

5.2.6 Register Triggered Waveform Memory Mode

If sequence consistency or I2C bus availability is a concern, register triggered waveform memory mode (RTWM) mode can be used to play back previously defined sequences from the Waveform Memory, see Section 5.8, via I2C register trigger only. Enter this mode by setting OPERATION_MODE = 3.

5.2.6.1 I2C Triggering and Sequence Looping

Sequence selection is done via PS_SEQ_ID with the additional option to loop the sequence up to 16 times using PS_SEQ_LOOP. To trigger a sequence, set SEQ_START = 1. Once a sequence completes, the event is reported by dropping the nIRQ pin low and signaling via SEQ_DONE_M. To repeat a sequence immediately following completion of playback, set SEQ_CONTINUE = 1.

5.2.7 Edge Triggered Waveform Memory Mode

If there is no host available, or for minimal host interaction, edge triggered waveform memory mode (ETWM) mode can be used to play back a previously defined sequences from the Waveform Memory, see Section 5.8, via external GPI edge trigger or also via I2C trigger, as in RTWM mode. The ETWM is also useful if deterministic timing is required without reliance on the I2C bus. Each of the GPI_0, GPI_1, and GPI_2 pins can be independently configured and will react according to the setting in GPIx_POLARITY as follows:

Rising edge trigger, GPIx_POLARITY = 0: only a rising GPI edge creates an event that triggers a pre-programmed sequence.
Falling edge trigger, GPIx_POLARITY = 1: only a falling GPI edge creates an event that triggers a pre-programmed sequence.
Rising and falling edge trigger, GPIx_POLARITY = 2: both edges create events that trigger a pre- programmed sequence. Any event received during playback from any GPI after the initial GPI trigger event will result in a sequence stop.
There are two ways of reacting to a GPI event based on GPIx_MODE:
Single sequence, GPIx_MODE = 0: no matter how many times a particular GPI is triggered, it will play the sequence located at GPIx_SEQUENCE_ID.
Multi-sequence, GPIx_MODE = 1: odd GPI events trigger the sequence at GPIx_SEQUENCE_ID, while even GPI events trigger the sequence located at the value of GPIx_SEQUENCE_ID + 1 bit. In ETWM mode, a maximum of six different sequences can be configured (two per GPI, when multi- sequence mode is enabled). The desired haptic sequence for each GPI must be set by programming GPIx_SEQUENCE_ID. Once a sequence has finished playing, a signal is sent via the nIRQ pin and DA7282 automatically returns to IDLE state, assuming STANDBY_EN = 0, to await the next trigger event. Sequence looping operates in the same way as RTWM mode, see Section 5.2.6.1.

5.3 Resonant Frequency Tracking

LRAs are high-Q systems that have to be driven exactly at resonance to achieve maximum possible output acceleration. DA7282 supports continuous resonant frequency tracking via BEMF sensing during playback to achieve optimum LRA acceleration output across manufacturing spread, operating temperature range, external damping, and actuator aging. When the FREQ_TRACK_EN is high, a digital resonant frequency tracking loop locks onto the LRA resonant frequency in real time by adjusting the drive period. This ensures that the actuator is always driven at the optimum frequency for the highest efficiency electrical to mechanical energy conversion. The loop range of 50 Hz to 300 Hz covers existing narrowband LRAs; typical resonant frequency lock accuracy is 0.5 Hz. To increase absolute accuracy of the lock during playback, DA7282 supports automatic scaling of the frequency tracking controller gain. The feature is enabled via FREQ_TRACKING_AUTO_ADJ and becomes active after the device has achieved initial lock, see Section 5.7.1. The resonant frequency tracking algorithm is designed to converge to the correct value from up to 25 % offset between the initial nominal datasheet value and the actual resonant frequency. This range is conservative in order to prevent unwanted behavior. A fault will trigger if the actuator resonant frequency is outside the 50 Hz to 300 Hz range. To block these two features, set FREQ_TRACKING_FORCE_ON = 1, see Section 5.7.1.

5.4 Active Acceleration and Rapid Stop

Mechanical systems such as LRAs and ERMs accelerate and decelerate exponentially and the time between transitions (for example from stopping of the drive signal to the actuator coming to a complete rest) can be perceptibly slow for the user. DA7282 features Active Acceleration and Rapid Stop to overcome this latency, which enables stronger clicks and a higher fidelity playback in both LRAs and ERMs. This capability offers a distinct advantage over legacy systems, which do not sense BEMF, because it allows the use of cheaper, slower response time actuators while keeping haptic effects crisp. Active Acceleration employs relative drive architecture based on BEMF sensing, which enables temporary overdrive on all level changes reducing the time required to achieve a target drive level. The DA7282 Active Acceleration algorithm does not require dedicated calibration procedures and enables accurate overdrive and underdrive throughout the lifetime of an actuator. The feature removes the need for a separate calibration sequence to determine the correct overdrive duration, see Figure 10 and Figure 11. Enabling Active Acceleration typically reduces the time to achieve the target drive level by a factor of two on sequence level changes. The Rapid Stop feature typically reduces the time to achieve a zero drive level by a factor of three when enabled. Figure 10 shows a drive sequence without the features enabled and Figure 11 illustrates the reduced time to target when Active Acceleration and Rapid Stop are enabled. Note: The Active Acceleration and Rapid Stop features require frequency tracking to be enabled. Figure 12 demonstrates the system with an actual LRA for an equivalent duration sequence without and with the Active Acceleration and Rapid Stop features. The nominal actuator acceleration is achieved faster and the stopping time is reduced by a factor of approximately eight. Active Acceleration and Rapid Stop are enabled using ACCELERATION_EN and RAPID_STOP_EN.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 29 of 87 © 2022 Renesas Electronics Accelerometer Output, Sensor next to LRA OUTP/N pins filtered by a 3kHz RC filter OUTP/N pins filtered by a 3kHz RC filter Accelerometer Output, Sensor next to LRA Length of Desired Effect Figure 12: Simple Drive (Top) versus Active Acceleration and Rapid Stop Enabled (Bottom)

5.5 Wideband Frequency Control

DA7282 can be configured for wideband LRA support in DRO, RTWM, and ETWM modes. This allows an actuator to be driven outside of resonance to create a richer user experience. In this mode frequency tracking, Active Acceleration, and Rapid Stop features should be disabled. The accessible frequency range becomes 25 Hz to 1000 Hz. After configuring the device, see Section 5.6, the following applies: In DRO mode, streaming is as described in Section 5.2.4. To change output frequency, a new value is uploaded to LRA_PER_H and LRA_PER_L. In RTWM or ETWM modes, the frequency information is encoded into the frames of a sequence, see required at the start of a sequence, the first frame of a sequence must contain frequency information.

5.6 Device Configuration and Playback

Minimal one-time setup is required to drive any given actuator. This consists of setting the chosen actuator type with its key parameters and selecting the drive mode. The Dialog SmartCanvas GUI

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 30 of 87 © 2022 Renesas Electronics automatically calculates the values required and sets the registers based on the entered actuator datasheet parameters. If the Dialog SmartCanvas GUI is not used, follow the steps outlined in this section.

5.6.1 Boot

DA7282 comes out of reset when a power supply is provided to the device and boots for 1.5 ms. This is followed by entry to the Inactive mode where the device is kept in its lowest power state.

5.6.2 Actuator Setup

The following setup procedure needs to be observed to program DA7282 to work with a specific actuator: 1. Choose the correct actuator type using ACTUATOR_TYPE, 0 = LRA and 1 = ERM. 2. Choose the correct nominal maximum voltage across the actuator by checking the actuator datasheet for the maximum allowed RMS voltage and writing the value to ACTUATOR_NOMMAX. The allowable range is between 0 V and 6 V in 23.4 mV steps. The ACTUATOR_NOMMAX setting can be calculated using the following formula: 𝐴𝐶𝑇𝑈𝐴𝑇𝑂𝑅_𝑁𝑂𝑀𝑀𝐴𝑋[7: 0] = 𝑉𝑎𝑐𝑡𝑢𝑎𝑡𝑜𝑟_𝑛𝑜𝑚𝑚𝑎𝑥 23.4 × 10−3 (1) 3. Choose the correct absolute maximum peak voltage across the actuator by checking the actuator datasheet and writing the value to ACTUATOR_ABSMAX. The allowable range is between 0 V and 6 V in 23.4 mV steps. The ACTUATOR_ABSMAX value can be calculated using the following formula: 𝐴𝐶𝑇𝑈𝐴𝑇𝑂𝑅_𝐴𝐵𝑆𝑀𝐴𝑋[7: 0] = 𝑉𝑎𝑐𝑡𝑢𝑎𝑡𝑜𝑟_𝑎𝑏𝑠𝑚𝑎𝑥 23.4 × 10−3 (2) 4. Program the IMAX value (in units of mA) for the actuator using the following formula: 𝐼𝑀𝐴𝑋[4: 0] = 𝐼max _𝑎𝑐𝑡𝑢𝑎𝑡𝑜𝑟_𝑚𝐴 − 28.6 7.2 – where Imax_actuator_mA is the actuator max rated current in mA, as listed in its datasheet. Note that in general this should slightly exceed the ACTUATOR_ABSMAX voltage divided by the actuator impedance. (3) 5. Program the impedance of the actuator by checking the actuator datasheet and calculating the values for V2I_FACTOR_H and V2I_FACTOR_L using the following formulae: 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0] = 𝑍 × (𝐼𝑀𝐴𝑋[4: 0] + 4) 1.6104 (4) 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐻[7: 0] = 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0] − 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐿[7: 0] 256 (5) 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐿[7: 0] = 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0] − 256 × 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐻[7: 0] (6) – Where V2I_FACTOR[15:0] is the 16-bit concatenation of V2I_FACTOR_H[7:0] and V2I_FACTOR_L[7:0], Z is the impedance of the actuator in Ω (as read from its datasheet), and IMAX[4:0] is the 5-bit value of IMAX. 6. Program the LRA resonant frequency in terms of period by updating LRA_PER_H and LRA_PER_L based on the following formula:

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 31 of 87 © 2022 Renesas Electronics 𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0] = 1 𝐿𝑅𝐴𝑓𝑟𝑒𝑞 × 1333.32 × 10−9 (7) 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐻[7: 0] = 𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0] − 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐿[6: 0] 128 (8) 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐿[6: 0] = 𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0] − 128 × 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐻[7: 0] (9) – Where LRAfreq represents the LRA resonant frequency in Hz, as listed in the actuator datasheet. Note: For ERM this value will signify the frequency of BEMF sensing; if more frequent updates are required, the value can be increased up to 300 Hz. For driving coin ERMs, see Section 5.7.18.

5.6.3 Automatic Output Control

DA7282 has several automatic control loops and mechanisms to ensure excellent playback fidelity and easy actuator setup:

Automatic frequency tracking - this feature allows resonant frequency tracking during playback and is enabled via FREQ_TRACK_EN. Frequency tracking must be enabled to use the Active Acceleration and Rapid Stop features. For fine-tuning the frequency tracking loop, see Section 5.7.1.
Active Acceleration - this feature improves playback fidelity by overdriving and underdriving the actuator to allow faster transitions between acceleration levels. This improves on the inherent actuator mechanical time constant. To enable Active acceleration set ACCELERATION_EN = 1. Note that the input data is interpreted as either unsigned (ACCELERATION_EN = 0) or signed (ACCELERATION_EN = 1). For more detail on data formatting, see Section 5.9.
Rapid Stop - this is a mechanism to allow the fastest possible stop to zero acceleration output for the actuator. DA7282 achieves this by driving in full reverse the actuator by applying a 180° phase shift in the case of an LRA or inverting the voltage across the actuator in the case of an ERM actuator. For fine-tuning the Rapid Stop feature, see Section 5.7.2.

5.6.4 Waveform Memory Setup

The Waveform Memory is initially empty. The user can create any set of haptic sequences by following the Waveform Memory format described in Section 5.8. For ease of use, the Dialog GUI also provides a graphical tool to create sequences. The sequences can then be uploaded to the DA7282 Waveform Memory by going through the following steps: 1. Ensure that DA7282 is in Inactive mode (no playback ongoing and at least 1.5 ms have passed since cold boot). 2. Ensure the Waveform Memory is unlocked, set WAV_MEM_LOCK = 1. 3. Read back the location of SNP_MEM_0 by checking WAV_MEM_BASE_ADDR. 4. Write the new contents of the Waveform Memory by starting from SNP_MEM_0. 5. If desired, re-lock the Waveform Memory, set WAV_MEM_LOCK = 0. Once the DA7282 Waveform Memory is configured, it is retained until a power-on reset event. The host can update the Waveform Memory as many times as needed during the lifetime of the device.

5.6.5 Mode Configuration

Set OPERATION_MODE according to the operating mode to be used. The device configuration flow the device in each of the operating modes.

5.6.5.1 Inactive Mode

In Inactive mode, DA7282 waits in a low-power state in between playback events. For more details 1. Set OPERATION_MODE = 0 for DA7282 to go to Inactive mode. 2. Configure STANDBY_EN to return to IDLE or STANDBY state after playback has finished.

5.6.5.2 Direct Register Override (DRO) Mode

Figure 13 shows how to operate the device in DRO mode. 1. Starting from either the IDLE or STANDBY state, write the initial drive amplitude of the haptic sequence to OVERRIDE_VAL. 2. When ready to begin playback, set OPERATION_MODE = 1. The output will begin switching after approximately 0.75 ms. 3. While in the DRIVE state, write to OVERRIDE_VAL to drive a new amplitude and create the desired envelope of the haptic sequence. If OVERRIDE_VAL = 0 during the DRIVE state, DA7282 will disable its output stage, but remain in a low latency-to-drive state and wait for further updates to OVERRIDE_VAL. 4. To stop driving set OPERATION_MODE = 0. DA7282 returns to either the IDLE or STANDBY state, depending on the value of STANDBY_EN. Note: The allowable range of values written to OVERRIDE_VAL depends on whether ACCELERATION_EN is set to 1 or 0. If ACCELERATION_EN = 1 then the usable range for OVERRIDE_VAL is 0x00 to 0x7F. If ACCELERATION_EN = 0 then the usable range for OVERRIDE_VAL is 0x00 to 0xFF in two’s complement. For further explanation, see Figure 31 and Figure 32.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 33 of 87 © 2022 Renesas Electronics I2C write to stop driving I2C writes to start driving Write to register OVERRIDE_VAL Output starts switching Write OPERATION_ MODE = 1 IDLE/STANDBY DRIVE Write OPERATION_ MODE = 0 DA7282 stops driving Change OVERRIDE_VAL Drive amplitude changes The allowable range differs depending on the state of ACCELERATION_EN Figure 13: Operation in DRO Mode

5.6.5.3 PWM Mode

Figure 14 shows how to operate the device in PWM mode. 1. Starting from either the IDLE or STANDBY state, apply a PWM signal to the GPI_0/PWM pin. 2. When ready to begin playback, set OPERATION_MODE = 2. The output will begin switching after approximately 0.75 ms with a drive amplitude proportional to the duty cycle of the incoming PWM signal. 3. While in the DRIVE state, update the duty cycle of the PWM signal to drive a new amplitude level and create the desired envelope of the haptic sequence. If the duty cycle of the PWM signal falls below the threshold set by FULL_BRAKE_THR, it is interpreted as a zero output drive level. 4. In order to stop driving, set OPERATION_MODE = 0. DA7282 will return to either the IDLE or STANDBY state depending on the value of STANDBY_EN. Note: The duty cycle of the PWM signal is interpreted differently depending on the value of ACCELERATION_EN. If ACCELERATION_EN = 1, then zero drive corresponds to 50 % duty cycle ± FULL_BRAKE_THR. If ACCELERATION_EN = 0, then zero drive corresponds to 0 % duty cycle + FULL_BRAKE_THR. For further explanation, see Figure 31 and Figure 32.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 34 of 87 © 2022 Renesas Electronics I2C write to stop driving I2C writes to start driving Apply PWM signal to GPI_0/PWM pin Output starts switching Write OPERATION_ MODE = 2 IDLE/STANDBY DRIVE Write OPERATION_ MODE = 0 DA7282 stops driving Change the duty cycle of the PWM signal Drive amplitude changes Figure 14: Operation in PWM Mode

5.6.5.4 Register Triggered Waveform Memory (RTWM) Mode

The following registers should be set up prior to operation in RTWM mode:

Set FREQ_WAVEFORM_TIMEBASE according to the minimum or maximum sequence timebase required.
Set SNP_MEM_x (where x = 0 to 99), see Section 5.8.
If custom waveform sequences are required, see Section 5.7.5.
Set WAV_MEM_LOCK = 0 to prohibit access to the waveform memory if required.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 35 of 87 © 2022 Renesas Electronics Figure 15 shows how to operate the device in RTWM mode. 1. While in the IDLE or STANDBY state, configure PS_SEQ_ID and PS_SEQ_LOOP to select the desired sequence from Waveform Memory. 2. For first-time playback, set OPERATION_MODE = 3. On subsequent sequence playbacks, this step can be skipped (if OPERATION_MODE = 3). The haptic sequence will not begin playing until a start event is created by setting SEQ_START = 1. 3. While in the DRIVE state, set SEQ_CONTINUE = 1 to repeat the sequence. 4. When the haptic sequence is completed, DA7282 will signal this by setting nIRQ = 0 and setting SEQ_DONE_M = 1. DA7282 will then return to IDLE or STANDBY state, depending on the value of STANDBY_EN. 5. Clear the nIRQ and SEQ_DONE_M signals, set SEQ_DONE_M =1. 6. At any time during operation in RTWM mode, set OPERATION_MODE or SEQ_START = 0 to return to the IDLE or STANDBY state. Output starts switching Write OPERATION_MODE = 3 IDLE/STANDBY Sequence playback Write SEQ_DONE_M = 1 to clear register and nIRQ DA7282 ready to play next sequence Sequence is continued Are PS_SEQ_ID and PS_SEQ_LOOP already configured? Configure the PS_SEQ_LOOP register Yes No Create a start event by writing to SEQ_START SEQ_CONTINUE = 1? Select a sequence via PS_SEQ_ID No Yes OPERATION_MODE = 3? Yes No nIRQ = 0 and SEQ_DONE_M = 1 Sequence playback is complete and output stops switching SEQ_CONTINUE can be set if required during playback Can be skipped for subsequent sequence playbacks Figure 15: Operation in RTWM Mode

5.6.5.5 Edge Triggered Waveform Memory (ETWM) Mode

The following registers should be set up prior to operation in ETWM mode:

Set SNP_MEM_x (where x = 0 to 99), see Section 5.8.
Set FREQ_WAVEFORM_TIMEBASE according to the minimum or maximum sequence timebase required.

If custom waveform sequences are required, see Section 5.7.5.
Set WAV_MEM_LOCK = 0 to prohibit access to the waveform memory if required. Figure 16 shows how to operate the device in ETWM mode. 1. Before first-time playback, set GPIx_SEQUENCE_ID, GPI_x_MODE, and GPIx_POLARITY, see Section 5.2.7. These bits determine which sequence each of the GPI pins points to, whether they trigger single or multiple sequences, and whether they react to rising, falling, or both edges. 2. Set PS_SEQ_ID and PS_SEQ_LOOP to select the sequence to play from Waveform Memory when a start event is created via writing to I2C (SEQ_START). Note: If this has already been done, then this step can be skipped. 3. Set OPERATION_MODE = 4. On subsequent sequence playbacks, this step can be skipped (if OPERATION_MODE = 4). Haptic sequences will not begin playing until a start event is detected either by an edge on one of the GPI pins, or by setting SEQ_START = 1 via I2C. 4. While in the DRIVE state, set SEQ_CONTINUE = 1 to repeat the sequence. 5. When the haptic sequence is completed, DA7282 will signal this by setting nIRQ = 0 and setting SEQ_DONE = 1. DA7282 will then return to IDLE or STANDBY state, depending on the value of the STANDBY_EN. 6. Clear the nIRQ and SEQ_DONE_M signals by setting SEQ_DONE_M = 0 via I2C. At any time during operation in ETWM mode, set OPERATION_MODE or SEQ_START = 0 to return to IDLE or STANDBY state.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 37 of 87 © 2022 Renesas Electronics Output starts switching Write OPERATION_MODE = 4 IDLE/STANDBY Sequence playback Write SEQ_DONE_M = 1 to clear register and nIRQ DA7282 ready to play next sequence Sequence is continued Are PS_SEQ_ID and PS_SEQ_LOOP already configured? Configure the PS_SEQ_LOOP register Yes No Trigger via GPIx or I2C SEQ_CONTINUE = 1? Select a sequence via PS_SEQ_ID No Yes OPERATION_MODE = 4? Yes No nIRQ = 0 and SEQ_DONE_M = 1 Sequence playback is complete and output stops switching Are GPIx_SEQUENCE_ID, GPIx_MODE, and GPIx_POLARITY already configured? Yes No Configure GPIx_SEQUENCE_ID Configure GPIx_MODE Configure GPIx_POLARITY SEQ_CONTINUE can be set if required during playback Can be skipped for subsequent sequence playbacks Figure 16: Operation in ETWM Mode

5.6.6 Events and Diagnostics

DA7282 supports a comprehensive system for device, supply, and actuator diagnostics based on faults, warnings, and notifications. Faults return DA7282 to IDLE state and hold the system in IDLE until cleared, while warnings and notifications are used for host information only. If events are generated, the host is notified by the open-drain nIRQ pin pulling low. A single IRQ_EVENT1 byte containing all faults is presented to the host for simplified signaling. Warnings are reported via IRQ_EVENT_WARNING_DIAG and input data faults via IRQ_EVENT_SEQ_DIAG. Table 13 provides a summary of the full array of faults: Table 13: Haptic Event Flag Descriptions Event Name Description Required Action Faults E_OC_FAULT Short circuit / over-current fault Write 1 to clear E_ACTUATOR_FAUL T An issue detected with the actuator impedance, BEMF amplitude, or resonant frequency Write 1 to clear E_SEQ_FAULT Sequence ID, Waveform Memory, or PWM fault has occurred Read IRQ_EVENT_SEQ_DIAG for diagnostic information E_OVERTEMP_CRIT Over-temperature event Write 1 to clear E_UVLO Under-voltage fault Write 1 to clear Notifications E_SEQ_DONE Memory sequence playback is complete Write 1 to clear E_SEQ_CONTINUE Playback of a new sequence has started by the host setting SEQ_CONTINUE Write 1 to clear E_WARNING A system warning is in effect Read warnings in IRQ_EVENT_WARNING_DIAG E_ADC_SAT The input to the voltage sense ADC has saturated Check if V2I_FACTOR_H/L is set correctly for the driven actuator Warnings E_LIM_DRIVE Playback is limited due to battery lower than sequence target Reduce drive level if needed E_LIM_DRIVE_ACC Acceleration is limited due battery lower than overdrive level Reduce drive level if needed E_MEM_TYPE Input memory data type does not match acceleration configuration Check data format Input Data Faults E_SEQ_ID_FAULT Requested sequence ID does not exist Reload PS_SEQ_ID and Waveform Memory E_MEM_FAULT Waveform Memory corruption (empty bytes, non-existent snippet ID, wrong frame parameter) Reload Waveform Memory

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 39 of 87 © 2022 Renesas Electronics Event Name Description Required Action E_PWM_FAULT PWM timeout Restart PWM interface and write 1 to E_SEQ_FAULT to clear All events are write 1 to clear and can be masked using IRQ_MASK1 and IRQ_MASK2. Some of the sources generating E_ACTUATOR_FAULT can be disabled, for frequency tracking see Section 5.7.1 and for BEMF voltage amplitude see Section 5.7.14. For self-clearing of faults once in IDLE state, see Section 5.7.7.

5.7 Advanced Operation

DA7282 features several advanced modes of operation to fine-tune actuator haptic performance.

5.7.1 Frequency Tracking

The closed-loop frequency tracking on DA7282 is implemented via a proportional-integral (PI) controller. The proportional coefficient is stored in FRQ_PID_Kp_H/L and the integral coefficient in FRQ_PID_Ki_H/L. The default values of the coefficients are optimized to cover a wide range of actuators with typical settling times of approximately 40 ms from a 20 % frequency offset. If further optimization is required to target a specific actuator the coefficients can be updated. The LRA tuning tool in the DA7282 SmartCanvas GUI provides an intuitive and graphical way to easily adjust the Kp and Ki coefficients. To increase absolute accuracy of the lock during playback, DA7282 supports automatic scaling of the frequency tracking controller proportional coefficient. This feature is enabled via FREQ_TRACKING_AUTO_ADJ and becomes active after the device has achieved initial frequency lock. The FRQ_LOCKED_LIM value is used to determine the threshold for the initial lock and can be scaled up or down depending on system requirements. If optimizing FRQ_PID_K<x> coefficients with the FREQ_TRACK_AUTO_ADJ enabled in normal operation, ensure that the closed loop is stable for a step response when FREQ_TRACK_AUTO_ADJ is set at either 0 or 1. The resonant frequency tracking algorithm converges to the correct value from up to 25 % offset between the initial nominal datasheet value and the actual resonant frequency. This range is conservative to prevent unwanted behavior. A fault triggers if the actuator resonant frequency is outside the 50 Hz to 300 Hz range. To block these checks, set FREQ_TRACKING_FORCE_ON = 1. FRQ_TRACK_BEMF_LIM disables the frequency tracking if the BEMF signal becomes too low. It should always be set lower than the value in RAPID_STOP_LIM. The instantaneous value of the resonant frequency period is updated every half-period and written to LRA_PER_ACTUAL_H/L. The values can be converted to period using the following formula: 𝐿𝑅𝐴 𝑝𝑒𝑟𝑖𝑜𝑑 (𝑚𝑠) = 1333.32 × 10−9 × (128 × 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝐶𝑇𝑈𝐴𝐿_𝐻 + 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝐶𝑇𝑈𝐴𝐿_𝐿) (10) If more accurate information is required (for example if a frequency tracking enabled sequence is played to determine the resonant frequency before entering wideband operation), the average resonant frequency information over the last four half-periods is written to LRA_PER_AVERAGE_H/L. The values can be converted to period using the following formula: 𝐿𝑅𝐴 𝑝𝑒𝑟𝑖𝑜𝑑 (𝑚𝑠) = 1333.32 × 10−9 × (128 × 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝑉𝐸𝑅𝐴𝐺𝐸_𝐻 + 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝑉𝐸𝑅𝐴𝐺𝐸_𝐿) (11)

5.7.2 Rapid Stop

The Rapid Stop algorithm relies on actuator BEMF sensing to detect actuator motion during a stop- to-zero LRA acceleration. The algorithm provides a stopping signal to the LRA until the actuator

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 40 of 87 © 2022 Renesas Electronics crosses the point of no acceleration. Since drive updates happen only at the zero cross point, this introduces latency that may cause the actuator to overshoot the stop position. Due to this, the Rapid Stop will also trigger at a pre-determined threshold set by RAPID_STOP_LIM. The default setup covers most actuators, but if Rapid Stop is too short (actuator not fully stopped), the register value should be decreased; and if Rapid Stop overshoots (actuator stopped and then reversed), the register value should be increased. Note: The Rapid Stop algorithm can be triggered only for sequences longer than three half-periods.

5.7.3 Initial Impedance Update

DA7282 performs an impedance measurement at the very first half-period of drive at the start of playback. This allows a one-shot update of V2I_FACTOR_H/L to take into account specific actuator variation for increased voltage accuracy of the drive. The result is reported to IMPEDANCE_H/L, which can be read by the host and converted to impedance using the following formula: 𝐴𝑐𝑡𝑢𝑎𝑡𝑜𝑟 𝐼𝑚𝑝𝑒𝑑𝑎𝑛𝑐𝑒(𝑅𝑠𝑒𝑟𝑖𝑒𝑠) = (𝐼𝑀𝑃𝐸𝐷𝐴𝑁𝐶𝐸_𝐻 × 4 + 𝐼𝑀𝑃𝐸𝐷𝐴𝑁𝐶𝐸_𝐿) × 0.0625Ω (12) To disable this feature, set V2I_FACTOR_FREEZE and CALIB_IMPEDANCE_DIS = 1.

5.7.4 Amplitude PID

Some cylinder based ERMs generate excessively large-amplitude BEMF voltages. DA7282 can compensate for this by reducing the drive current level, set AMP_PID_EN = 1. The result is an improved haptic response. Figure 17 describes how the actuator voltage and current differs when AMP_PID_EN enabled or disabled. Time [s] Output Voltage Envelope [V] VOUT IOUT AMP_PID_EN = 0 Time [s] Output Current Envelope [A] BEMF Voltage Time [s] Output Voltage Envelope [V] VOUT IOUT AMP_PID_EN = 1 Time [s] Output Current Envelope [A] IOUT drops automatically to compensate BEMF and keep VOUT constant Figure 17: Output Voltage and Current for Different AMP_PID_EN Values Note: This is not usually required for LRAs as the amplitude of the BEMF is typically very low.

5.7.5 Wideband Operation

DA7282 natively supports wideband LRAs and allows continuous frequency updates to the output signal while driving. Amplitude and frequency data use parallel data paths, for configuration see Section 5.6.5. This section describes how to use the frequency component only. For wideband operation, frequency tracking must be disabled, by setting FREQ_TRACK_EN = 0, because drive at frequencies different from the actuator resonant frequency is required. Rapid Stop and Active Acceleration also rely on frequency tracking so must be deactivated by setting ACCELERATION_EN = 0 and RAPID_STOP_EN = 0. There are two ways to operate DA7282 during wideband operation:

In the limited frequency range of 25 Hz to 300 Hz:

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 41 of 87 © 2022 Renesas Electronics ○ No further settings are required in RTWM and ETWM modes if the frequency information is already stored in the Waveform Memory frame data as described in Section 5.8.3. If the Waveform Memory does not contain frequency information, then each sequence can be played at a different frequency by setting LRA_PER_H and LRA_PER_L to the desired value via the formulae in Section 5.6.2 before triggering playback using the method described in ○ In the DRO and PWM modes, the frequency information can be updated via the LRA_PER_H and LRA_PER_L using the formulae in Section 5.6.2 either before triggering playback of amplitude, the one half-period uncertainty on the output frequency update also applies.

In the full range of 25 Hz to 1024 Hz, the same procedures apply for all modes, but the following registers need to be set: ○ BEMF_SENSE_EN = 0 ○ DELAY_H = 0 ○ DELAY_SHIFT_L = 0 ○ DELAY_FREEZE = 1

5.7.6 Custom Waveform Operation

With frequency tracking, Active Acceleration, and Rapid Stop disabled, and with the additional setup for wideband operation described in Section 5.7.5, DA7282 can be configured to drive a custom waveform to an LRA actuator. It is important to note that here the custom waveform denotes the actual output during a single LRA resonant period and not the overall amplitude envelope during drive events, which is controlled as previously described in Section 5.6.5. Amplitude and frequency data can be streamed as usual in DRO, PWM, RTWM, or ETWM modes. The waveform output during a single resonant period comprises of 16 distinct points, see Figure 18, where points 0 to 4 are mirrored and repeated to create, by default, a sine wave (for example, point 3 and point 5, and point 2 and point 6 have the same amplitude). Extrapolation point 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 Value to output Repeated Points Figure 18: Custom Wave Point Numbering

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 42 of 87 © 2022 Renesas Electronics Point 0 is corresponds to an amplitude of 0 % of the value of IMAX, point 4 corresponds to an amplitude of 100 %, and points 1, 2, and 3 are scaled to the IMAX value by the unsigned CUSTOM_WAVE_GEN_COEFF1, CUSTOM_WAVE_GEN_COEFF2, and CUSTOM_WAVE_GEN_COEFF3 coefficient values. The default coefficients are set to correspond to a sine wave but can be updated to recreate any required waveform that is built of four symmetrical sections, see Figure 18. Table 14 contains a summary of the default coefficients and their settings. Table 14: Default CUSTOM_WAVE_GEN_COEFFx Settings Point % of IMAX[4:0] Corresponding Bits 0 0 - 1 37.9 CUSTOM_WAVE_GEN_COEFF1 2 70.3 CUSTOM_WAVE_GEN_COEFF2 3 92.2 CUSTOM_WAVE_GEN_COEFF3 4 100 -

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 43 of 87 © 2022 Renesas Electronics Configure the following bits to enable custom waveform operation:

BEMF_SENSE_EN = 0
WAVEGEN_MODE = 1
V2I_FACTOR_FREEZE = 1
DELAY_H = 0
DELAY_SHIFT_L = 0
DELAY_FREEZE = 1
ACCELERATION_EN = 0
RAPID_STOP_EN = 0
AMP_PID_EN = 0 After the above setup is executed, amplitude data can be streamed in any mode, see Section 5.6.5, and output frequency can be updated, see Section 5.7.6.

5.7.7 Embedded Operation

Should DA7282 be required to operate in a setup where no host is present or due to software limitations unable to communicate with the device during its required operation, DA7282 can operate in embedded operation by setting EMBEDDED_MODE = 1. In this case DA7282 is configured to clear all system faults as it enters inactive mode when playback is finished or if a fault has been detected, see Section 5.6.6. For example, if a short circuit occurs, the system will react in its usual way: stop driving, disable the current loop, and go to Inactive mode. Once in Inactive mode, the generated interrupt is automatically cleared and DA7282 will attempt to drive again on the next playback request without the host having to come in and clear faults.

5.7.8 Polarity Change Reporting for Half-Period Control in DRO Mode

For advanced sequence playback in DRO mode, the host may require DA7282 to update the output drive amplitude every half period. Since the I2C clock is asynchronous to the DA7282 internal clock and the exact timing of the half-period will change dynamically based on the frequency tracking loop, this is not a trivial operation. To overcome this limitation, the register POLARITY provides feedback. POLARITY toggles at the start of every half-period (so at a rate of 400 Hz for a 200 Hz resonant frequency actuator). This allows software synchronization of the updates to the OVERRIDE_VAL, see Figure 19.

5.7.9 Loop Filter Configuration

Haptic actuators (both ERM and LRA) can be modelled as a series combination of a resistor (Series R) and inductor (Series L) followed by a BEMF voltage source, see Figure 21. RSERIES LSERIES BEMF O Figure 21: Equivalent Electrical Model of an Actuator The usual variation of RSERIES is from 8 Ω to 50 Ω and LSERIES is from 20 µH to either 2 mH or 3 mH. The current regulation loop in the output drive must be kept stable by applying the correct setting in the loop's filter. While the defaults cover the vast majority of available LRAs and ERMs further tuning is possible by adjusting LOOP_FILT_CAP_TRIM, LOOP_FILT_RES_TRIM, and LOOP_FILT_LOW_BW. For LOOP_FILT_CAP_TRIM apply the settings in Table 15. Table 15: LOOP_FILT_CAP_TRIM Register Trim Settings Actuator Series Resistance (Ω) Register < 18 18 to 28 28 to 41 > 41 LOOP_FILT_CAP_TRIM 3 2 1 0 For LOOP_FILT_RES_TRIM apply the settings in Table 16. Table 16: LOOP_FILT_RES_TRIM Register Trim Settings Lseries (µH) Rseries (Ω) 25 or lower 50 75 100 125 150 175 200 225 250 or higher 4 2 2 3 3 3 3 3 3 3 3 6 1 2 2 3 3 3 3 3 3 3 8 1 2 2 2 3 3 3 3 3 3 10 0 1 2 2 2 3 3 3 3 3 12 0 1 2 2 2 2 3 3 3 3 14 0 1 1 2 2 2 2 3 3 3 16 0 1 1 2 2 2 2 2 3 3 18 0 0 1 1 2 2 2 2 2 3 20 0 1 1 2 2 2 3 3 3 3 22 0 1 1 2 2 2 2 3 3 3

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 46 of 87 © 2022 Renesas Electronics Lseries (µH) 24 0 1 1 2 2 2 2 3 3 3 26 0 1 1 2 2 2 2 2 3 3 28 0 1 2 2 2 3 3 3 3 3 30 0 1 2 2 2 3 3 3 3 3 32 0 1 2 2 2 2 3 3 3 3 34 0 1 1 2 2 2 3 3 3 3 36 to 40 0 1 1 2 2 2 2 3 3 3 42 0 1 2 2 3 3 3 3 3 3 44 0 1 2 2 3 3 3 3 3 3 46 to 50 0 1 2 2 2 3 3 3 3 3 Set LOOP_FILT_LOW_BW high if the actuator inductance exceeds 1 mH.

5.7.10 UVLO Threshold

The DA7282 UVLO has a default fall threshold of 2.8 V. This is adjustable in 100 mV steps via REF_UVLO_THRES. The full range is 2.7 V to 3.0 V.

5.7.11 Edge Rate Control

DA7282 contains an advanced switching node ERC to minimize EMI and board disturbances. The slope of the ERC can be adjusted by changing the values of the HBRIDGE_ERC_LS_TRIM (for low- side FET ERC) and HBRIDGE_ERC_HS_TRIM (for high-side FET ERC). Default value is 100 mVn/s and the adjustable range is 25 mV/ns to 100 mV/ns in 25 mV/ns steps.

5.7.12 Double Output Current Range

The nominal current rating for the DA7282 current regulation output is 250 mA. This range covers existing LRAs, however some LRA manufacturers allow significant actuator overdrive over short periods of time. DA7282 supports this by enabling LOOP_IDAC_DOUBLE_RANGE, which doubles the maximum output current. When this is enabled, the following setup changes apply:

IMAX now corresponds to twice the value computed by the formula in Section 5.6.2.
When setting the impedance in V2I_FACTOR_H and V2I_FACTOR_L via the formula in Section 5.6.2, use Zformula = 2*Zreal.
When reading back from IMPEDANCE_H and IMPEDANCE_L, use an LSB of 0.03125 Ω.

5.7.13 Supply Monitoring, Reporting, and Automatic Output Limiting

DA7282 monitors the level of the supply during playback and reports it via ADC_VDD_H and ADC_VDD_L. The two should be concatenated and read using the following formula: 𝑉𝐷𝐷 𝑆𝑢𝑝𝑝𝑙𝑦 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 = (𝐴𝐷𝐶_𝑉𝐷𝐷_𝐻 × 128 + 𝐴𝐷𝐶_𝑉𝐷𝐷_𝐿) × 0.1831 𝑚𝑉 (13) DA7282 uses this information to prevent the device from clipping to supply by limiting the drive to a value determined by the VDD_MARGIN register in 187.5 mV steps where 0x0 corresponds to no margin, see Figure 22.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 47 of 87 © 2022 Renesas Electronics Output drive clipping to VDD – VDD_MARGIN, not ABSMAX Time [s] Voltage [V] VDD ABSMAX VDD - VDD_MARGIN VDD_MARGIN Figure 22: Automatic Output Limiting The functionality is needed as DA7282 regulates current and if supply clipping occurs, the regulation stops and the BEMF information is lost. Furthermore, the VDD_MARGIN register allows limiting of the power across the actuator for low supply values to prevent the battery from discharging too fast.

5.7.14 BEMF Fault Limit

To detect malfunctioning actuators that have stopped moving due to a mechanical fault, DA7282 can be configured to trigger an actuator fault if the BEMF voltage level falls below a threshold for long drive durations. The threshold for detection is set in BEMF_FAULT_LIM; a zero value of the register disables the fault checking.

5.7.15 Increasing Impedance Detection Accuracy

To increase the accuracy of the impedance reading in IMPEDANCE_H and IMPEDANCE_L, the register V2I_FACTOR_OFFSET_EN could be set to 0. This removes an algorithmic offset utilized by the acceleration algorithm. Should V2I_FACTOR_OFFSET_EN be equal to 0, ACCELERATION_EN is recommended to be set to 0.

5.7.16 Frequency Pause during Rapid Stop

To address low mechanical time constant LRAs (start/stop times less than 20 ms) and improve the braking behavior, DA7282 has the option to pause frequency tracking during the execution of the Rapid Stop algorithm by setting FRQ_PAUSE_ON_POLARITY_CHANGE to 1.

5.7.17 Frequency Pause during Rapid Stop

If DA7282 is used with LRAs that have significant BEMF voltage amplitude that can transiently exceed the IR drop across an actuator when reversing the phase of the drive signal, it is recommended to set DELAY_BYPASS to 0.

5.7.18 Coin ERM Operation

The term coin ERM is used to describe an eccentric rotating mass actuator that is flat and has coin- like external appearance. The eccentric rotating mass is circular and contains two coil windings that are used for commutation, see Figure 23.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 48 of 87 © 2022 Renesas Electronics INN INP Plan View Elevation View Case Case Rotor Top RotorRotor Bottom Stator Coils Commutator PCB Stator Magnet Brushes Shaft Electrical Commutation 1 2 A B C Commutator PCB Electrical Diagram A B C 1 2 A B C Commutation Event 1: Single Inductor 1 2 A B C Commutation Event 2: Double Inductor VOUT Constant Current Driven System Time [s] Voltage [V] VOUT Coil 1 in series with Coil 2 Coil 1 or Coil 2View w/o Case Rotor Stator Coil 1 and 2 in parallel 1 2 A B C Commutation Event 3: Parallel Inductors Figure 23: Coin ERM Physical and Electrical Summary Due to the commutation of the motor, the impedance varies between one coil, two coils in series, and for very short periods two coils in parallel. Due to this behavior, DA7282 cannot extract the BEMF and actuator motion is not detectable for coin ERM actuators. Therefore, Active Acceleration and Rapid Stop features are not available. Manual overdrive or underdrive of the coin ERM to speed up the transition between two levels of acceleration is possible and recommended for better user experience. Note that due to the varying impedance and the constant current drive of DA7282, the output voltage will vary, with no effect on the performance of the DA7282, see Figure 23. Recommended setup specific for a coin ERM, in addition to generic ERM setup described in Section 5.6.2:

ACCELERATION_EN = 0
RAPID_STOP_EN = 0
AMP_PID_EN = 0
V2I_FACTOR_FREEZE = 1
CALIB_IMPEDANCE_DIS = 1
BEMF_FAULT_LIM = 0
Set the V2I factor using the single winding impedance, see Section 5.6.2
Set IMAX using the maximum start-up current, see Section 5.6.2

5.7.19 VDDIO/EN Pin Control

The VDDIO/EN pin controls the entry and exit of the device from OFF state. When VDDIO_EN = 0 V, DA7282 is OFF and consumes typ. 5 nA of current from the VDD pin. Setting VDDIO_EN = VDDIO (the system supply level) enables the device and, after the initial boot sequence, it will reach IDLE state with typ. 680 nA of current consumption. Note that the device will have been hardware reset when it comes out of the OFF mode.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 49 of 87 © 2022 Renesas Electronics For lowest OFF mode current consumption control the enable function via a host-side GPIO push- pull that connects the VDDIO/EN pin either to GND or to the system VDDIO supply. If the VDDIO/EN pin is only needed as a device hardware reset, where it will only be pulled low for a short time (therefore IDLE state power consumption is not an issue), a possible system solution is to use an open-drain output with a pull-up resistor to the system VDDIO supply. In this configuration a larger pull-up resistor might require an additional capacitor. For recommended configurations and component values for the two examples, see Figure 24 and Table 17. Host GPIO Driver DA7282 GPIO system VDDIO supply GND VDDIO/EN R C Host GPIO Driver DA7282 GPIO system VDDIO supply GND VDDIO/EN R C Open Drain GPIO (for hardware reset function only) Push-Pull GPIO (for best OFF mode current consumption) Figure 24: VDDIO/EN Pin Control in Push-Pull Configuration and Open Drain Configuration Table 17: VDDIO/EN Pin Control Recommended Values of R and C Pullup Resistor R (kΩ) Decoupling Capacitor C (pF) < 200 None 0.2 to 2.2 100 2.2 to 10 1000

5.8 Waveform Memory

The Waveform Memory stores haptic drive sequences. A single haptic effect is called a sequence and each sequence is formed by one or more frames that address one or more snippets stored in memory. The overall Waveform Memory structure is described in detail in Section 5.8.1; NOTE It is recommended that the Dialog SmartCanvas GUI is used to construct sequences and upload them to the Waveform Memory. The easy to use GUI provides intuitive visualization of the sequences in the Waveform Memory and requires only basic knowledge of the overall memory format.

5.8.1 Waveform Memory Structure

The waveform memory structure has a 100-byte capacity for storing snippets, frames, and sequences. Sequences reference the snippets using frames to allow complex haptic sequences to be created in a memory efficient manner. The overall structure of the Waveform Memory can be seen in Figure 25. For Waveform Memory programming, see Section 5.6.4.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 51 of 87 © 2022 Renesas Electronics num_of_snippets[7:0] num_of_sequences[7:0] snippet_1_endpointer snippet_n_endpointer sequence_0_endpointer snippet_n sequence_0 sequence_n sequence_n_endpointer snippet_1 snippet_1_endpointer HEADER SECTIONDATA SECTION (SNIPPETS/SEQUENCES) WAVEFORM MEMORY

100 Bytes

PWL_point_ 0 PWL_point_n frame_0 frame_n Figure 25: Waveform Memory Structure

5.8.1.1 Header Section

The three sections constituting the header for the Waveform Memory are:

Byte 0: Defines the number of snippets stored.
Byte 1: Defines the number of sequences stored.
Byte 2 and onwards: The snippet(s) and sequence(s) end address pointer(s) are stored. Each pointer address occupies one byte. Up to 15 snippets can be addressed in addition to snippet 0, which is the silence snippet see Note 1. Up to 16 sequences can be addressed. A snippet or sequence pointer points to the location in the waveform memory where the last byte of the respective snippet or sequence resides.

5.8.1.2 Data Section

The upper memory section contains the PWL data describing the snippets, see Table 18. The lower part of the memory contains the pre-stored sequences.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 52 of 87 © 2022 Renesas Electronics Snippet IDs are determined by the order in which they are listed, starting from SNP_ID = 1. Sequence IDs are determined by the order in which they are listed, starting from 0.

5.8.2 Snippet Definition

Snippets are formed by storing a series of one or more piecewise linear (PWL) amplitude and time pairs. Snippets represent the basic building blocks used in the Waveform Memory. Table 18: PWL Byte Structure Bit 7 6 5 4 3 2 1 0 Description RMP TIME[6:4] AMP[3:0] A byte is allocated for each amplitude and time pair in the Waveform Memory, see Table 18. A snippet consists of one or more bytes containing RMP, TIME and AMP data.

RMP defines whether a ramp (RMP = 1) or a step (RMP = 0) is required between consecutive time and amplitude pairs.
TIME contains the unitless time information (number of timebases) with the minimum being 1 timebase. Consequently, TIME = 0 signifies time base of 1, TIME = 1 signifies time base of 2, and so on, with the longest duration at 8 timebases for TIME = 7.
AMP contains the amplitude information of the snippet. If ACCELERATION_EN = 1, AMP is unsigned and scales between 0 and 15, where 0 represents silence and 15 represents 100 % drive. If ACCELERATION_EN = 0, AMP is in two's compliment and scales between 7 and -7 where 7 represents 100 % full scale and -7 represents -100 % (full scale 180° reversed polarity). To maintain symmetry, -8 is interpreted as -7. For example, assuming ACCELERATION_EN = 1, the snippet shown in Figure 26 creates a waveform that ramps from zero to an amplitude of 1111 over a period of two timebases, then step from 1111 to 1000, and remains there for four timebases. The length (in milliseconds) of a timebase is specified using the TIMEBASE frame bits, see Section 5.8.3. Description RMP TIME[6:4] AMP[3:0] Ramp 1 0 1 0 1 1 1 1 Step 0 1 0 0 1 0 0 0 Amplitude Timebase 1111 1000 1 2 3 4 5 6 7 Figure 26: Snippet Ramp and Step with ACCELERATION_EN = 1 If a constant drive level oflonger than 8 timebases is required, set RMP = 0 for subsequent PWL points.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 53 of 87 © 2022 Renesas Electronics Figure 27 shows a generic example of a snippet, where Pn represents the PWL pair located at amplitude An and with time step Tn, where n represents the PWL pair number. Pn T2 T3 T4 T5 TnT0 = 0 An Amplitude [%] Time Time Pn T2 T3 T4 T5 TnT0 = 0 An Amplitude [%] Pn T2 T3 T4 T5 TnT0 = 0 An Amplitude [%] RMP = 1 for all PWL points RMP = 0 for all PWL points Time Figure 27: Snippet Example Note 1 A built-in snippet containing a single silent PWL point (amplitude = 0) is available by setting SNP_ID = 0. The duration is set to two timebases. Because of the existence of this snippet, customer defined snippets start at SNP_ID = 1. The snippet is inherent to the decoding and is not actually stored in the waveform memory. The number of snippets (byte 0) does not include snippet 0 and there is no end pointer for snippet 0 stored in the waveform memory.

5.8.3 Frame Definition

A frame consists of a collection of parameters used to define the playback of a snippet with differing gain, time base, carrier frequency, and number of repetitions. A frame consists of up to three bytes, its structure is shown in Figure 28. The frame parameters can be easily set up using the Dialog GUI.

Byte 1 is mandatory. For byte 1, always set COMMAND_TYPE = 0. If set incorrectly, the device will generate an interrupt of the type E_MEM_FAULT.Byte 2 is optional. When used, set COMMAND_TYPE = 1 in Byte 2.
Byte 3 is optional, for use in wideband sequences only, and contains the frame frequency's eight LSBs. If COMMAND_TYPE of frame Byte 2 is set to 1 and FREQ_CMD = 1, then the Byte 3 contains drive frequency data to enable wideband LRA support. All frame parameters except COMMAND_TYPE, SNP_ID_L, GAIN, and TIMEBASE are optional. For a full description, see Table 19. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 1 => COMMAND _TYPE = 0 GAIN [1:0] TIMEBASE[1:0] SNP_ID_L[2:0] Byte 2 => COMMAND _TYPE = 1 SNP_ID_LOOP[3:0] FREQ_CMD FREQ[8] SNP_ID_ H

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 54 of 87 © 2022 Renesas Electronics Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 3 => FREQ[7:0] Figure 28: Command Structure for a Single Frame Table 19: Bit Definitions for Frame Parameters Byte Number Register Bit Definitions COMMAND_TYPE COMMAND_TYPE labels the byte and tells the system how to interpret the following seven LSBs. COMMAND_TYPE = 0 in Byte 1 COMMAND_TYPE = 1 signifies Byte 2 is present

1 GAIN[1:0] Gain applied to the snippet identified by SNP_ID_L/H:

00 = 0 dB 01 = -6 dB 10 = -12 dB 11 = -18 dB 1 TIMEBASE[1:0] The timebase length of the snippet pointed to by the snippet ID. This register is interpreted differently depending on FREQ_WAVEFORM_TIMEBASE: If FREQ_WAVEFORM_TIMEBASE = 0 (default): 00 = 5.44 ms 01 = 21.76 ms 10 = 43.52 ms 11 = 87.04 ms If FREQ_WAVEFORM_TIMEBASE = 1: 00 = 1.36 ms 01 = 5.44 ms 10 = 21.76 ms 11 = 43.52 ms

1 SNP_ID_L[2:0] SNP_ID_L is mandatory and contains the LSBs of the snippet ID

(SNP_ID). Up to eight snippets can be addressed.

2 SNP_ID_LOOP[3:0

SNP_ID_LOOP is the loop multiplier of the snippet identified by SNP_ID_L/H and shows how many times a snippet is looped. If not present, the loop multiplier is 1. The number of loop iterations is equal to SNP_ID_LOOP + 1 (that is, 0 = 1 iteration, 15 = 16 iterations). When the loop multiplier is > 1, playback begins from P1 instead of P0, see Figure 27, after the first playback loop is complete.

2 FREQ_CMD If FREQ_CMD = 1, the frame is a 3-byte command with frequency

information. The frequency information is stored in FREQ[7:0]. 2 FREQ[8] Drive frequency MSB. The total frequency range is represented by the 9- bit concatenation of FREQ[8] and FREQ[7:0] (possible values: 0 to 511), which corresponds to the range 1 Hz to 1024 Hz. The LSB step size is 2 Hz and values below 25 Hz are interpreted as 25 Hz. The result is also converted from frequency to period and stored in the FRQ_LRA_PER_ACT_x registers for read-back.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 55 of 87 © 2022 Renesas Electronics Byte Number Register Bit Definitions 2 SNP_ID_H SNP_ID_H is the MSB of the snippet ID (SNP_ID). This can be used to increase the range of addressable snippets from 8 to 16. This bit is optional and if not present SNP_ID_H = 0. 3 FREQ[7:0] Drive frequency LSBs. The total frequency range is represented by the 9- bit concatenation of FREQ[8] and FREQ[7:0] (possible values: 0 to 511), which corresponds to the range 1 Hz to 1024 Hz. The LSB step size is 2 Hz and values below 25 Hz are interpreted as 25 Hz. The result is also converted from frequency to period and stored in the FRQ_LRA_PER_ACT_x registers for read-back. Note: The frequency command should be used only when FREQ_TRACK_EN = 0, otherwise the frequency tracking loop will update the frequency away from the set one. Note: The If FREQ_TRACK_EN = 0 and a frequency update containing frame is played, the new frequency will be maintained for all subsequent frames or sequences until a new frame with a new frequency command is played. Assume that Sequence 0 contains no frames with frequency commands, Sequence 1 has a frame with command setting the frequency at 150 Hz, and Sequence 2 has one at 200 Hz. If Sequence 0 is played after Sequence 1, it will be played at 150 Hz. If Sequence 0 is played after Sequence 2, it will be played at 200 Hz.

5.8.4 Sequence Definition

A sequence is built up of one or more frames, see Figure 29, and written to memory using the format described in Section 5.8.1. Sequence Frame0 Frame1 Frame2 FrameN Each frame points to an individual snippet with certain playback parameters Figure 29: Sequence Structure Note: Only sequences can be played. It is not possible to point directly to a snippet (although a sequence can be created which contains only one snippet). Note: If a sequence ends on a non-zero value, zero is assumed to follow and the device will end the haptic playback at the end of the sequence. Note: The starting amplitude at the beginning of a frame or snippet is dependent on the ending amplitude of the previous frame or snippet. The starting amplitude at the start of a sequence is zero. See Figure 26 for more details.

5.8.4.1 Pre-Stored Waveform Memory Example

Figure 30 shows an example of a typical Waveform Memory operation with all features enabled.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 56 of 87 © 2022 Renesas Electronics Waveform Memory ... Sequence 0 Addr Pointer Snippet 1 Addr Pointer Example Snippet_1 Snippet_M Example Sequence_0 snippet 7 0dB 2 loops Example Sequence_3 SEQ_0_FR_0 snippet 1 Timebase 20ms-6dB 0 loopsSEQ_0_FR_1 Freq :90Hz SEQ_3_FR_0 snippet 5 Timebase 5ms-6dB 1 loops snippet 2 Timebase 20ms0dB 0 loops SEQ_3_FR_1 Freq :162.5Hz ... Wideband Wideband Sequence_N Snip 7, @20ms snippet 1 Timebase 40ms0dB 0 loopsSEQ_0_FR_2 Snip 1 @ -6dB, 20ms loop 1 loop 2 Snip 1 @ 0dB, 40ms Narrowband Example , Sequence 0 Time Amplitude PWL : P1 = Ramp to 80%, time 4 PWL : P2 = Step to 80%, time 2 PWL : P3 = Ramp to 0%, time 4 p0 p1 p2 Time Amplitude Wideband Example , Sequence 3 Snip 5 @90Hz loop 1 @90Hz Snip 2 @162.5Hz PWL : P1 = Ramp to 60%, time 3 PWL : P2 = Step to 0%, time 1 PWL : P3 = Ramp to 40%, time 2 p0 Example Snippet_5 snippet 7 Timebase 5ms0dB 0 loopsSEQ_3_FR_3 snippet 0 Timebase 20ms 0 loopsSEQ_3_FR_2 Snip 7, @5ms, 162.5Hz Timebase 20ms PWL : P1 = Step to 50%, time 1 PWL : P2 = Step to 00%, time 1 p0 Example Snippet_7 ... PWL : P1 = Ramp to 50%, time 4 PWL : P2 = Step to 50%, time 1 PWL : P3 = Step to 100%, time 3 PWL : P4 = Step to 0%, time 2 p1 p2 Example Snippet_2 ... Snip 0 Three loops of Snippet 7 played with 20ms timebase and 0dB gain Snippet 1 is played at 20ms timebase and -6dB gain LRA drive frequency set @ 90Hz. Two loops of Snippet 5, 5ms timebase, -6dB gain. LRA drive frequency set @ 162.5Hz. Snippet 2 is played once at 20ms timebase, 0dB gain LRA drive frequency set @ 162.5Hz. Snippet 7 played with 5ms timebase and 0dB gain 40ms of silence Snippet 1 is played at 40ms timebase and 0dB gain. Number of Sequences Number of Snippets Snippet 2 Addr Pointer Snippet 5 Addr Pointer Sequence 3 Addr Pointer ... Figure 30: Waveform Memory Example

5.9 General Data Format

This section describes the data format used by the three different data input sources (DRO, PWM, and Waveform Memory). Four bits are used for storing the envelope value of snippets in Waveform Memory. Interpretation of the data is different depending on ACCELERATION_EN. For an overview of the data interpretation with and without Active Acceleration enabled, see Figure 31 and Figure 32. 100 % -100 % 0x7 0x6 0x5 0x2 0x1 0x0 0xF 0xE 0xD 0x9 0x8 0x7F 0x7E 0x7D 0x02 0x01 0x00 0xFF 0xFE 0xFD 0x81 0x80 PWM [Mark / space] DROMEM FULL_BRAKE_THRS[3:0] full brake (only for PWM) Drive positive direction Drive negative direction mark – space ratio 100% 50% Waveform/Data source Driving Strength [%] Data format for ERM and LRA ACCELERATION_EN = 0 4 bits 2's c. 8 bits 2's c. Figure 31: Overview of Data Formats with Acceleration Disabled

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 58 of 87 © 2022 Renesas Electronics 100 % -100 % 0xF 0xE 0xD 0x2 0x1 0x0 N/A N/A N/A N/A N/A 0x7F 0x7E 0x7D 0x02 0x01 0x00 0xFF 0xFE 0xFD 0x81 0x80 PWM [Mark / space] DROMEM FULL_BRAKE_THRS[3:0] full brake (only for PWM) Drive positive direction NO NEGATIVE DRIVE mark – space ratio 100% Waveform/Data source Driving Strength in ENV GEN [%] Data format for ERM and LRA ACCELERATION_EN = 1 4 bits uns. 8 bits 2's c. Drive negative direction Figure 32: Overview of Data Formats with Acceleration Enabled

5.9.1 DRO Mode

DRO data is supplied from I2C and is interpreted as 8-bit two’s complement signed number.

For ACCELERATION_EN = 0: ○ The most negative value corresponds to -100 % driving strength. ○ The most positive value corresponds to +100 % driving strength. ○ A zero value corresponds to no drive. ○ The full range is between 127 (100 %) and -127 (-100 %), with -128 interpreted as -127 to keep the ranges symmetrical
For ACCELERATION_EN = 1: ○ Negative values are omitted and substituted with zero. ○ The most positive value corresponds to +100 % driving strength.

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 59 of 87 © 2022 Renesas Electronics ○ Zero value corresponds to no drive.

5.9.2 PWM Mode

PWM provides mark / space ratio between 0 % and 100 %. The interpretation of duty cycle depends on the state of ACCELERATION_EN.

For ACCELERATION_EN = 0: ○ A 0 % duty cycle corresponds to -100 % driving strength. ○ A 50 % duty cycle corresponds to no drive. ○ A 100 % duty cycle corresponds to +100 % driving strength. ○ FULL_BRAKE_THR defines a lower threshold for driving strength, below this threshold, drive is interpreted as zero.
For ACCELERATION_EN = 1: ○ A 0 % duty cycle corresponds to no drive. ○ A 50 % duty cycle corresponds to +50 % driving strength. ○ A 100 % duty cycle corresponds to +100 % driving strength. ○ Negative drive is not possible. ○ FULL_BRAKE_THR defines a lower threshold for driving strength, below this threshold, drive is interpreted as zero. The encoded value of PWM data is converted to 8-bit two’s complement data using the DRO format and is written to OVERRIDE_VAL so it can be read back.

5.9.3 RTWM and ETWM Modes

For ACCELERATION_EN = 0: ○ The 4 bits of the amplitude value are interpreted as a two’s complement signed value. ○ The most negative value corresponds to -100 % driving strength. ○ The most positive value corresponds to +100 % driving strength. ○ A zero value corresponds to no drive. ○ The full range is between 7 (100 %) and -7 (-100 %), with -8 interpreted as -7 to keep the ranges symmetrical.
ACCELERATION_EN = 1 ○ The 4 bits of the amplitude value are interpreted as an unsigned value. ○ The most positive value corresponds to +100 % driving strength. ○ Negative drive is not possible. ○ A zero value corresponds to no drive.

5.10 I2C Control Interface

DA7282 is software controlled from the host by registers accessed via an I2C compatible serial control interface. Data is shifted into or out of the DA7282 under the control of the host processor, which also provides the serial clock. The DA7282 7 bit I2C slave address is 0x4A (1001010 binary), which is equivalent to 0x94 (8 bit) for writing and 0x95 (8 bit) for reading. The I2C clock is supplied by the SCL line and the bidirectional I2C data is carried by the SDA line. The I2C interface is open-drain supporting multiple devices on a single line. The bus lines have to be pulled HIGH by external pull-up resistors (1 kΩ to 20 kΩ range). The attached devices only drive the bus lines LOW by connecting them to ground. This means that two devices cannot conflict if they drive the bus simultaneously. DA7282 supports Standard-mode, Fast-mode, and Fast-mode Plus, with the highest frequency of the bus at 1 MHz in Fast-mode Plus. The exact frequency can be determined by the application and does not have any relation to the DA7282 internal clock signals. DA7282 will follow the host clock speed within the described limitations and does not initiate any clock arbitration or slow-down. Communication on the I2C bus always takes place between two devices, one acting as the master and the other as the slave. The DA7282 will only operate as a slave. Host Processor DA7282SDA SCL Peripheral Device SDA SCL SCL SDA VDDIO VDDIO Figure 33: Schematic of the I2C Control Interface Bus All data is transmitted across the I2C bus in groups of eight bits. To send a bit the SDA line is driven to the intended state while the SCL is LOW (a LOW on SCL indicates a zero bit). Once the SDA has settled, the SCL line is brought HIGH and then LOW. This pulse on SCL clocks the SDA bit into the receiver’s shift register. A two-byte serial protocol is used containing one byte for address and one byte for data. Data and address transfer is transmitted MSB first for both read and write operations. All transmission begins with the START condition from the master while the bus is in the Idle mode (the bus is free). It is initiated by a HIGH to LOW transition on the SDA line while the SCL is in the HIGH state (a STOP condition is indicated by a LOW to HIGH transition on the SDA line while the SCL line is in the HIGH state).

6 Register Overview

6.1 Register Map

All register bits classed as Reserved are Read-Only and can be ignored. Table 20: Register Map Addr Register 7 6 5 4 3 2 1 0 Reset 0x00 CHIP_REV CHIP_REV_MINOR<3:0> CHIP_REV_MAJOR<3:0> 0xDA 0x03 IRQ_EVENT E_OC_F AULT E_ACTU ATOR_F AULT E_WARN ING E_SEQ_ FAULT E_OVER TEMP_C RIT E_SEQ_ DONE E_UVLO E_SEQ_ CONTIN UE 0x00 0x04 IRQ_EVENT _WARNING_ DIAG E_LIM_D RIVE E_LIM_D RIVE_AC C Reserved E_MEM_ TYPE E_OVER TEMP_W ARN Reserved Reserved Reserve d 0x00 0x05 IRQ_EVENT _SEQ_DIAG E_SEQ_I D_FAUL T E_MEM_ FAULT E_PWM_ FAULT Reserve d Reserved Reserved Reserved Reserve d 0x00 0x06 IRQ_STATU STA_OC STA_AC TUATOR STA_WA RNING STA_SE Q_FAUL T STA_OV ERTEMP _CRIT STA_SE Q_DONE STA_UV LO_VBA T_OK STA_SE Q_CONT INUE 0x00 0x07 IRQ_MASK1 OC_M ACTUAT OR_M WARNIN G_M SEQ_FA ULT_M OVERTE MP_CRIT SEQ_DO NE_M E_UVLO SEQ_CO NTINUE 0x00 0x08 CIF_I2C1 I2C_WR_ MODE I2C_TO_ ENABLE Reserved Reserve d Reserved Reserved Reserved Reserve d 0x40 0x0A FRQ_LRA_P ER_H LRA_PER_H<7:0> 0x21 0x0B FRQ_LRA_P ER_L Reserved LRA_PER_L<6:0> 0x4F 0x0C ACTUATOR1 ACTUATOR_NOMMAX<7:0> 0x5A 0x0D ACTUATOR2 ACTUATOR_ABSMAX<7:0> 0x78 0x0E ACTUATOR3 Reserved Reserved Reserved IMAX<4:0> 0x17 0x0F CALIB_V2I_ H V2I_FACTOR_H<7:0> 0x01 0x10 CALIB_V2I_L V2I_FACTOR_L<7:0> 0x0D 0x11 CALIB_IMP_ H IMPEDANCE_H<7:0> 0x00 0x12 CALIB_IMP_ L Reserved Reserved Reserved Reserved Reserved Reserved IMPEDANCE_L<1:0> 0x00 0x13 TOP_CFG1 EMBEDD ED_MOD E Reserved ACTUAT OR_TYP E BEMF_S ENSE_E N FREQ_T RACK_E N ACCELE RATION_ EN RAPID_S TOP_EN AMP_PI D_EN 0x1E 0x14 TOP_CFG2 Reserved Reserved Reserved MEM_DA TA_SIGN ED FULL_BRAKE_THR<3:0> 0x01 0x15 TOP_CFG3 Reserved Reserved Reserved Reserved VDD_MARGIN<3:0> 0x03 0x16 TOP_CFG4 V2I_FAC TOR_FR EEZE CALIB_I MPEDAN CE_DIS Reserved Reserved Reserve d Reserved Reserved Reserve d 0x40 0x17 TOP_INT_CF FRQ_LOCKED_LIM<5:0> BEMF_FAULT_LIM<1: 0x81 0x1C TOP_INT_CF G6_H

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 64 of 87 © 2022 Renesas Electronics Addr Register 7 6 5 4 3 2 1 0 Reset 0x1D TOP_INT_CF G6_L 0x1E TOP_INT_CF G7_H 0x1F TOP_INT_CF G7_L 0x20 TOP_INT_CF Reserved RAPID_STOP_LIM<2:0> FRQ_TRACK_BEMF_LIM<3:0> 0x43 0x22 TOP_CTL1 Reserved Reserved Reserved SEQ_ST ART STANDB Y_EN OPERATION_MODE<2:0> 0x00 0x23 TOP_CTL2 OVERRIDE_VAL<7:0> 0x00 0x24 SEQ_CTL1 Reserved Reserved Reserved Reserved Reserved FREQ_W AVEFOR M_TIME BASE WAVEG EN_MOD E SEQ_CO NTINUE 0x08 0x25 SWG_C1 CUSTOM_WAVE_GEN_COEFF1<7:0> 0x61 0x26 SWG_C2 CUSTOM_WAVE_GEN_COEFF2<7:0> 0xB4 0x27 SWG_C3 CUSTOM_WAVE_GEN_COEFF3<7:0> 0xEC 0x28 SEQ_CTL2 PS_SEQ_LOOP<3:0> PS_SEQ_ID<3:0> 0x00 0x29 GPI_0_CTL Reserved GPI0_SEQUENCE_ID<3:0> GPI0_M ODE GPI0_POLARITY<1:0 0x00 0x2A GPI_1_CTL Reserved GPI1_SEQUENCE_ID<3:0> GPI1_M ODE GPI1_POLARITY<1:0 0x08 0x2B GPI_2_CTL Reserved GPI2_SEQUENCE_ID<3:0> GPI2_M ODE GPI2_POLARITY<1:0 0x10 0x2C MEM_CTL1 WAV_MEM_BASE_ADDR <7:0> 0x84 0x2D MEM_CTL2 WAV_ME M_LOCK Reserved Reserved Reserved Reserved Reserved Reserved Reserve d 0x80 0x2E ADC_DATA_ ADC_VDD_H<7:0> 0xFF 0x2F ADC_DATA_ Reserved ADC_VDD_L<6:0> 0x7F 0x43 POLARITY Reserved Reserved Reserved Reserved Reserved Reserved Reserved POLARI TY 0x00 0x44 LRA_AVR_H LRA_PER_AVERAGE_H<7:0> 0x00 0x45 LRA_AVR_L Reserved LRA_PER_AVERAGE_L<6:0> 0x00 0x46 FRQ_LRA_P ER_ACT_H LRA_PER_ACTUAL_H<7:0> 0x21 0x47 FRQ_LRA_P ER_ACT_L Reserved LRA_PER_ACTUAL_L<6:0> 0x4F 0x48 FRQ_PHASE DELAY_H<7:0> 0x25 0x49 FRQ_PHASE DELAY_ FREEZE Reserved Reserved Reserved Reserved DELAY_SHIFT_L<2:0> 0x05 0x4C FRQ_CTL Reserved Reserved Reserved Reserved Reserved Reserve d FREQ_T RACKIN G_AUTO _ADJ FREQ_T RACKIN G_FORC E_ON 0x02 0x5F TRIM3 Reserved LOOP_ID AC_DOU BLE_RA NGE LOOP_FI LT_LOW _BW REF_UVLO_THRES Reserve d Reserved Reserve d 0x0E 0x60 TRIM4 Reserved Reserved Reserved Reserved LOOP_FILT_CAP_TRI M<1:0> LOOP_FILT_RES_TRI M<1:0> 0x9C

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 65 of 87 © 2022 Renesas Electronics Addr Register 7 6 5 4 3 2 1 0 Reset 0x62 TRIM6 Reserved Reserved Reserved Reserved HBRIDGE_ERC_LS_T RIM<1:0> HBRIDGE_ERC_HS_ TRIM<1:0> 0x5F 0x6E TOP_CFG5 Reserved Reserved Reserved Reserved Reserve d DELAY_ BYPASS FRQ_PA USE_ON _POLARI TY_CHA NGE V2I_FAC TOR_OF FSET_E N 0x01 0x81 IRQ_EVENT _ACTUATOR _FAULT Reserved E_TEST_ ADC_SA T_FAULT Reserved Reserved Reserve d Reserved Reserved Reserve d 0x00 0x82 IRQ_STATU STA_ ADC_SA T Reserved Reserved Reserved Reserve d Reserved Reserved Reserve d 0x00 0x83 IRQ_MASK2 ADC_SA T_M Reserved Reserved Reserved Reserve d Reserved Reserved Reserve d 0x00 0x84 to 0xE7 SNP_MEM_x SNP_MEM_x<7:0> where x = 0 to 99 0x00

6.2 Register Descriptions

Table 21: CHIP_REV (0x0000) Bit Mode Symbol Description Reset [7:4] RO CHIP_REV_MINOR Device revision code ( minor ) 0xD [3:0] RO CHIP_REV_MAJOR Device revision code ( major ) 0xA Table 22: IRQ_EVENT1 (0x0003) Bit Mode Symbol Description Reset [7] RW E_OC_FAULT Over-current / short-circuit fault on the OUTP or OUTN pin (write 1 to clear) 0x0 [6] RW E_ACTUATOR_FAULT Actuator fault, see Section 5.6.6 (write 1 to clear) 0x0 [5] RW E_WARNING System warnings Read IRQ_EVENT_WARNING_DIAG for warning diagnostic (write 1 to clear) 0x0 [4] RW E_SEQ_FAULT Sequence faults: SEQ_ID_FAULT, memory fault or PWM fault Read IRQ_EVENT_SEQ_DIAG for diagnostic information (write 1 to clear) 0x0 [3] RW E_OVERTEMP_CRIT Critical chip temperature event, chip temperature has exceeded the critical limit of 125 °C (write 1 to clear) 0x0 [2] RW E_SEQ_DONE IRQ indicating that sequence playback from waveform memory is complete (write 1 to clear) 0x0 [1] RW E_UVLO Under-voltage fault, supply below the UVLO threshold Clear to attempt restart (write 1 to clear) 0x0

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 66 of 87 © 2022 Renesas Electronics Bit Mode Symbol Description Reset [0] RW E_SEQ_CONTINUE IRQ indicating that playback of a new sequence has occurred because SEQ_CONTINUE is set to 1 (write 1 to clear) 0x0 Table 23: IRQ_EVENT_WARNING_DIAG (0x0004) Bit Mode Symbol Description Reset [7] RW E_LIM_DRIVE IRQ indicating that playback is limited because the power supply level is lower than the sequence target (write 1 to E_WARNING to clear) 0x0 [6] RW E_LIM_DRIVE_ACC IRQ indicating that acceleration is limited because the power supply level is lower than required for the acceleration target (write 1 to E_WARNING to clear) 0x0 [4] RW E_MEM_TYPE Indicates that the memory data type configured in register MEM_DATA_SIGNED does not match the acceleration configuration (ACCELERATION_EN). MEM_DATA_SIGNED = 1 for ACCELERATION_EN = 0 MEM_DATA_SIGNED = 0 for ACCELERATION_EN = 1 (write 1 to E_WARNING to clear) 0x0 [3] RW E_OVERTEMP_WARN Over-temperature warning, chip temperature has exceeded the warning limit of 105 °C (write 1 to E_WARNING to clear) 0x0 Table 24: IRQ_EVENT_SEQ_DIAG (0x0005) Bit Mode Symbol Description Reset [7] RW E_SEQ_ID_FAULT IRQ indicating that requested sequence ID configured in PS_SEQ_ID is not valid (write 1 to E_SEQ_FAULTto clear) 0x0 [6] RW E_MEM_FAULT Indicates that the Waveform Memory is corrupted (empty, invalid snippet ID, invalid frame structure) (write 1 to E_SEQ_FAULTto clear) 0x0 [5] RW E_PWM_FAULT IRQ indicating that the PWM input signal has timed out (write 1 to E_SEQ_FAULTto clear) 0x0 Table 25: IRQ_STATUS1 (0x0006) Bit Mode Symbol Description Reset [7] RO STA_OC Over-current / short circuit fault status 0x0 [6] RO STA_ACTUATOR Actuator fault status 0x0 [5] RO STA_WARNING System warnings status 0x0 [4] RO STA_PAT_FAULT Sequence faults status 0x0 [3] RO STA_OVERTEMP_CRIT Over-temperature status 0x0 [2] RO STA_PAT_DONE Memory based sequence status 0x0

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 67 of 87 © 2022 Renesas Electronics Bit Mode Symbol Description Reset [1] RO STA_UVLO_VBAT_OK UVLO output status: 0 during normal operation; 1 if there is a UVLO event 0x0 [0] RO STA_SEQ_CONTINUE Continuous sequence status 0x0 Table 26: IRQ_MASK1 (0x0007) Bit Mode Symbol Description Reset [7] RW OC_M Over-current / short circuit fault mask 0x0 [6] RW ACTUATOR_M Actuator fault mask 0x0 [5] RW WARNING_M System warnings mask 0x0 [4] RW SEQ_FAULT_M Sequence faults mask 0x0 [3] RW OVERTEMP_CRIT_M Over-temperature fault mask 0x0 [2] RW SEQ_DONE_M Memory based sequence interrupt mask 0x0 [1] RW E_UVLO_M Soft shutdown fault mask 0x0 [0] RW SEQ_CONTINUE_M Continuous sequence interrupt mask 0x0 Table 27: CIF_I2C1 (0x0008) Bit Mode Symbol Description Reset [7] RW I2C_WR_MODE I2C write mode 0x0 = Auto-increment (addr, data, data, data,…) 0x1 = Repeat (addr, data, addr, data,...) 0x0 [6] RW I2C_TO_ENABLE I2C timeout enable. If there are no negative edges on SCL for approx. 35 ms, the slave resets. 0x0 = Disabled 0x1 = Enabled 0x1 Table 28: FRQ_LRA_PER_H (0x000A) Bit Mode Symbol Description Reset [7:0] RW LRA_PER_H Used for specifying the LRA drive frequency. MS-bits of the initial LRA resonant frequency period. 𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0] = 1 𝐿𝑅𝐴𝑓𝑟𝑒𝑞 × 1333.32 × 10−9 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐻[7: 0] = 𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0] − 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐿[6: 0] 128 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐿[6: 0] = 𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0] − 128 × 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐻[7: 0] Where LRAfreq represents the LRA resonant frequency (in Hz) as listed in the actuator datasheet. See Section 5.6.2. 0x21

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 68 of 87 © 2022 Renesas Electronics Bit Mode Symbol Description Reset Default corresponds to 174 Hz. Table 29: FRQ_LRA_PER_L (0x000B) Bit Mode Symbol Description Reset [6:0] RW LRA_PER_L Used for specifying the LRA drive frequency. LS-bits of the initial LRA resonant frequency period. 𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0] = 1 𝐿𝑅𝐴𝑓𝑟𝑒𝑞 × 1333.32 × 10−9 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐻[7: 0] = 𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0] − 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐿[6: 0] 128 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐿[6: 0] = 𝐿𝑅𝐴_𝑃𝐸𝑅[14: 0] − 128 × 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐻[7: 0] Where LRAfreq represents the LRA resonant frequency in Hz as listed in the actuator datasheet. See Section 5.6.2. Default corresponds to 174 Hz. 0x4F Table 30: ACTUATOR1 (0x000C) Bit Mod e Symbol Description Reset [7:0 RW ACTUATOR_NO MMAX Nominal actuator voltage rating, unsigned, see Section 5.6.2 Sets full-scale of unsigned haptic waveform when acceleration enabled (ACCELERATION_EN = 1) 𝐴𝐶𝑇𝑈𝐴𝑇𝑂𝑅_𝑁𝑂𝑀𝑀𝐴𝑋 = 𝑉𝑎𝑐𝑡𝑢𝑎𝑡𝑜𝑟_𝑛𝑜𝑚𝑚𝑎𝑥 23.4 × 10−3 Default: 0x5A = 2.106 V 0x5A Table 31: ACTUATOR2 (0x000D) Bit Mod e Symbol Description Reset [7:0 RW ACTUATOR_AB SMAX Absolute actuator maximum voltage rating, see Section 5.6.2. Overdrive is limited to this value when acceleration enabled (ACCELERATION_EN = 1) Sets full-scale of unsigned haptic waveform when acceleration disabled 𝐴𝐶𝑇𝑈𝐴𝑇𝑂𝑅_𝐴𝐵𝑆𝑀𝐴𝑋 = 𝑉𝑎𝑐𝑡𝑢𝑎𝑡𝑜𝑟_𝑎𝑏𝑠𝑚𝑎𝑥 23.4 × 10−3 Default: 0x78 = 2.808 V 0x78 Table 32: ACTUATOR3 (0x000E) Bit Mode Symbol Description Reset [4:0] RW IMAX Actuator max current rating 0x17

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 69 of 87 © 2022 Renesas Electronics Bit Mode Symbol Description Reset 𝐼𝑀𝐴𝑋 = 𝐼max _𝑎𝑐𝑡𝑢𝑎𝑡𝑜𝑟_𝑚𝐴 − 28.6 7.2 where Imax_actuator_mA is the actuator max rated current in mA, as listed in its datasheet, see Section 5.6.2. Default: 0x17 = 194 mA Table 33: CALIB_V2I_H (0x000F) Bit Mod e Symbol Description Reset [7:0 RW V2I_FACTOR_H MS-bits for translating actuator impedance to output voltage drive level 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0] = 𝑍 × (𝐼𝑀𝐴𝑋[4: 0] + 4) 1.6104 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐻[7: 0] = 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0] − 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐿[7: 0] 256 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐿[7: 0] = 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0] − 256 × 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐻[7: 0] Where V2I_FACTOR[15:0] is the 16-bit concatenation of V2I_FACTOR_H[7:0] and V2I_FACTOR_L[7:0], Z is the impedance of the actuator in Ω (as read from its datasheet), and IMAX[4:0] is the 5-bit value of IMAX, see Section 5.6.2. 0x01 Table 34: CALIB_V2I_L (0x0010) Bit Mode Symbol Description Reset [7:0] RW V2I_FACTOR_L LS-bits for translating actuator impedance to output voltage drive level 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0] = 𝑍 × (𝐼𝑀𝐴𝑋[4: 0] + 4) 1.6104 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐻[7: 0] = 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0] − 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐿[7: 0] 256 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐿[7: 0] = 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅[15: 0] − 256 × 𝑉2𝐼_𝐹𝐴𝐶𝑇𝑂𝑅_𝐻[7: 0] Where V2I_FACTOR[15:0] is the 16-bit concatenation of V2I_FACTOR_H[7:0] and V2I_FACTOR_L[7:0], Z is the impedance of the actuator in Ω (as read from its datasheet), and IMAX[4:0] is the 5-bit value of IMAX, see Section 5.6.2. 0x0D

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 70 of 87 © 2022 Renesas Electronics Table 35: CALIB_IMP_H (0x0011) Bit Mode Symbol Description Reset [7:0] RO IMPEDANCE_H MS-bits of calculated impedance (default 22 Ω), see Section 5.7.3. 𝐼𝑚𝑝𝑒𝑑𝑎𝑛𝑐𝑒 (Ω) = 4 × 62.5 × 10−3 × 𝐼𝑀𝑃𝐸𝐷𝐴𝑁𝐶𝐸_𝐻 + 62.5 × 10−3 × 𝐼𝑀𝑃𝐸𝐷𝐴𝑁𝐶𝐸_𝐿 0x00 Table 36: CALIB_IMP_L (0x0012) Bit Mode Symbol Description Reset [1:0] RO IMPEDANCE_L LS-bits of calculated impedance (default 22 Ω), see Section 5.7.3. 𝐼𝑚𝑝𝑒𝑑𝑎𝑛𝑐𝑒 (Ω) = 4 × 62.5 × 10−3 × 𝐼𝑀𝑃𝐸𝐷𝐴𝑁𝐶𝐸_𝐻 + 62.5 × 10−3 × 𝐼𝑀𝑃𝐸𝐷𝐴𝑁𝐶𝐸_𝐿 0x0 Table 37: TOP_CFG1 (0x0013) Bit Mode Symbol Description Reset [7] RW EMBEDDED_M ODE Embedded operation enable (self-clearing IRQs), see Section 5.7.7. 0x0 = Faults cleared by host 0x1 = DA7282 clears faults automatically 0x0 [5] RW ACTUATOR_TY PE Specifies actuator type: LRA or ERM, see Section 5.6.2. 0x0 = LRA 0x1 = ERM 0x0 [4] RW BEMF_SENSE_ EN Enable internal loop computations; should be disabled only in custom waveform and wideband operation, see Sections 5.7.5 and 5.7.6. 0x0 = Custom Waveform Operation 0x1 = Standard Operation 0x1 [3] RW FREQ_TRACK_ EN Enable resonant frequency tracking; ignored in ERM mode, see Section 5.3. 0x0 = frequency tracking disabled 0x1 = frequency tracking enabled 0x1 [2] RW ACCELERATIO N_EN Enable Active Acceleration, see Section 5.4. 0x0 = Active Acceleration disabled 0x1 = Active Acceleration enabled 0x1 [1] RW RAPID_STOP_E N Enable Rapid Stop, see Section 5.4. 0x0 = Rapid Stop disabled 0x1 = Rapid Stop enabled 0x1 [0] RW AMP_PID_EN Enable Amplitude PID, see Section 5.4. 0x0 = Amplitude PID disabled 0x1 = Amplitude PID enabled 0x0

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 71 of 87 © 2022 Renesas Electronics Table 38: TOP_CFG2 (0x0014) Bit Mod e Symbol Description Reset [4] RW MEM_DATA_SI GNED Memory data format; set according to the value of ACCELERATION_EN: 0x0 = unsigned (for ACCELERATION_EN = 1) 0x1 = signed (for ACCELERATION_EN = 0) 0x0 [3:0 RW FULL_BRAKE_T HR Full-brake threshold for PWM mode with step size 6.66%, see Section 5.2.5. 0x0 = brake threshold disabled 0x1 = 6.66 % of ACTUATOR_NOMMAX 0x2 = 13.33 % of ACTUATOR_NOMMAX ... …~6.66% steps… 0x15 = 100 % of ACTUATOR_NOMMAX 0x1 Table 39: TOP_CFG3 (0x0015) Bit Mod e Symbol Description Rese t [3:0 RW VDD_MARGIN VDD margin setting. Target voltage needs to be below VDD - VDD_MARGIN, otherwise voltage is clamped to VDD - VDD_MARGIN and a LIM_DRIVE IRQ is generated. See Section 5.7.13 for further details. 0x0 = 0 mV 0x1 = 187.5 mV 0x2 = 375 mV 0x3 = 562.5 mV ... …187.5 mV steps… 0xF = 2.8125 V 0x3 Table 40: TOP_CFG4 (0x0016) Bit Mod e Symbol Description Reset [7] RW V2I_FACTOR_F REEZE Stop automatic updates to V2I_FACTOR_x, see Section 5.7.3. 0x0 = updates enabled 0x1 = updates disabled 0x0 [6] RW CALIB_IMPEDA NCE_DIS Stop automatic updates to V2I_FACTOR_x during playback, see Section 5.7.3. 0x0 = updates enabled 0x1 = updates disabled 0x1

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 72 of 87 © 2022 Renesas Electronics Table 41: TOP_INT_CFG1 (0x0017) Bit Mod e Symbol Description Reset [7:2 RW FRQ_LOCKED_L IM Limit for generating frequency locked signal that enabled scaling of the frequency tracking PID gain, see Section 5.7.1. If error is below the FRQ_LOCKED_LIM*4 frequency is locked 0x20 [1:0 RW BEMF_FAULT_LI M Limit for BEMF fault generation. If voltage is below the threshold BEMF, a fault is generated, see Section 5.7.14. 0x0 = BEMF fault disabled 0x1 = 4.9 mV 0x2 = 27.9 mV 0x3 = 49.9 mV 0x1 Table 42: TOP_INT_CFG6_H (0x001C) Bit Mode Symbol Description Reset [7:0] RW FRQ_PID_Kp_H MS-bits of the frequency tracking loop PID Kp proportional coefficient, see Section 5.7.1 for details 0x0E Table 43: TOP_INT_CFG6_L (0x001D) Bit Mode Symbol Description Reset [7:0] RW FRQ_PID_Kp_L LS-bits of the frequency tracking loop PID Kp proportional coefficient, see Section 5.7.1 for details 0x20 Table 44: TOP_INT_CFG7_H (0x001E) Bit Mode Symbol Description Reset [7:0] RW FRQ_PID_Ki_H MS-bits of the frequency tracking loop PID Ki integral coefficient, see Section 5.7.1 for details 0x03 Table 45: TOP_INT_CFG7_L (0x001F) Bit Mode Symbol Description Reset [7:0] RW FRQ_PID_Ki_L LS-bits of the frequency tracking loop PID Ki integral coefficient, see Section 5.7.1 for details 0x20 Table 46: TOP_INT_CFG8 (0x0020) Bit Mod e Symbol Description Reset [6:4] RW RAPID_STOP_ LIM Selects the Rapid Stop threshold at which DA7282 stops driving while braking, see Section 5.7.2 0x4 [3:0] RW FRQ_TRACK_ BEMF_LIM Selects the frequency tracking threshold at which DA7282 pauses frequency tracking, see Section 5.7.1 0x3

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 73 of 87 © 2022 Renesas Electronics Table 47: TOP_CTL1 (0x0022) Bit Mode Symbol Description Reset [4] RW SEQ_START Start/stop control of Waveform Memory sequence playback 0x0 = Stop playback and return to IDLE state 0x1 = Start playback 0x0 [3] RW STANDBY_E N Sets the state DA7282 returns to after completion of playback, see Section 5.2.1. 0x0 = Return to IDLE state after playback 0x1 = Return to STANDBY state after playback 0x0 [2:0] RW OPERATION _MODE Haptic operation mode, see Section 5.2. 0x0 = Inactive mode 0x1 = Direct register override (DRO) mode 0x2 = Playback from PWM data source (PWM) mode 0x3 = Register triggered waveform memory (RTWM) mode 0x4 = Edge triggered waveform memory (ETWM) mode 0x0 Table 48: TOP_CTL2 (0x0023) Bit Mode Symbol Description Reset [7:0] RW OVERRIDE_ VAL Used to set the output drive level in DRO mode. Scales the contents of ACTUATOR_ABSMAX and/or ACTUATOR_NOMMAX, depending on whether Active Acceleration is enabled. See Section 5.2.4. OVERRIDE_VA L Value Scaling factor when ACCELERATION_ EN = 0 Scaling factor when ACCELERATION_ EN = 1 0x7F 1 1 0x7E 0.992 0.992 0x01 0.0079 0.0079 0x00 0 0 0xFF -0.0079 0 0x81 -1 0 0x80 -1 0 0x0 Table 49: SEQ_CTL1 (0x0024) Bit Mode Symbol Description Reset [2] RW FREQ_WAV EFORM_TIM EBASE Frequency waveform timebase setting for waveform memory frames. See Section 5.8.3. 0x0 5.44, 21.76, 43.52, 87.04 ms 0x1 1.36, 5.44, 21.76, 43.52 ms 0x0

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 74 of 87 © 2022 Renesas Electronics Bit Mode Symbol Description Reset [1] RW WAVEGEN_ MODE Enable bit for custom waveform operation, see Section 5.7.5.

If WAVEGEN_MODE = 0, then set BEMF_SENSE_EN = 1
If WAVEGEN_MODE = 1,then set BEMF_SENSE_EN = 0 0x0 = Normal wave mode (step/ramp sequences) 0x1 = Custom wave mode (sinewave sequences) 0x0 [0] RW SEQ_CONTI NUE Control for back-to-back Waveform Memory sequence playback during RTWM and ETWM modes. If SEQ_CONTINUE = 1, new sequence playback starts at end of current sequence. Register is self-cleared when the next sequence is started, see Section 5.6.5. 0x0 Table 50: SWG_C1 (0x0025) Bit Mode Symbol Description Rese t [7:0] RW CUSTOM_W AVE_GEN_C OEFF1 Coefficient1 for custom wave generation, represents a proportion of the set IMAX, see Section 5.7.5. Default corresponds to a sine wave. 0x00 = 0 % 0x01 = 0.4 % … …steps of approx. 0.4 % 0x61 = 37.9 % 0xFF = 100 % 0x61 Table 51: SWG_C2 (0x0026) Bit Mode Symbol Description Reset [7:0] RW CUSTOM_W AVE_GEN_C OEFF2 Coefficient2 for custom wave generation, represents a proportion of the set IMAX, see Section 5.7.5. Default corresponds to a sine wave. 0x00 = 0 % 0x01 = 0.4 % … …steps of approx. 0.4 % 0xB4 = 70.3 % 0xFF = 100 % 0xB4 Table 52: SWG_C3 (0x0027) Bit Mode Symbol Description Reset [7:0] RW CUSTOM_W AVE_GEN_C OEFF3 Coefficient1 for custom wave generation, represents a proportion of the set IMAX, see Section 5.7.5. Default corresponds to a sine wave. 0x00 = 0 % 0x01 = 0.4 % … …steps of approx. 0.4 % 0xEC

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 75 of 87 © 2022 Renesas Electronics Bit Mode Symbol Description Reset 0xEC = 92.2 % 0xFF = 100 % Table 53: SEQ_CTL2 (0x0028) Bit Mode Symbol Description Reset [7:4] RW PS_SEQ_LOOP Number of times the pre-stored sequence (pointed to by PS_SEQ_ID) is repeated, see Section 5.6.5. 0x0 = No repetition (sequence played once) 0x1 = 1 repetition (sequence played twice) … …step of 1… 0xF = 15 repetitions (sequence played 16 times) 0x0 [3:0] RW PS_SEQ_ID ID of pre-stored and read-back of GPI triggered sequence, see Section 5.6.5.4. 0x0 Table 54: GPI_0_CTL (0x0029) Bit Mod e Symbol Description Reset [6:3 RW GPI0_SEQUENCE_I D GPI_0 sequence ID, see Section 5.2.7. 0x0 [2] RW GPI0_MODE GPI_0 mode of operation, see Section 5.2.7. 0x0 = Single sequence 0x1 = Multi-sequence 0x0 [1:0 RW GPI0_POLARITY Selection which GPI edge triggers an event: 0x0 = Rising edge 0x1 = Falling edge 0x2 = Both edges 0x0 Table 55: GPI_1_CTL (0x002A) Bit Mode Symbol Description Reset [6:3] RW GPI1_SEQUENCE_ID GPI_1 sequence ID, see Section 5.2.7. 0x1 [2] RW GPI1_MODE GPI_1 mode of operation, see Section 5.2.7. 0x0 = Single sequence 0x1 = Multi-sequence 0x0 [1:0] RW GPI1_POLARITY Selection which GPI edge triggers an event: 0x0 = Rising edge 0x1 = Falling edge 0x2 = Both edges 0x0

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 76 of 87 © 2022 Renesas Electronics Table 56: GPI_2_CTL (0x002B) Bit Mode Symbol Description Reset [6:3] RW GPI2_SEQUENCE_ID GPI_2 mode of operation, see Section 5.2.7. 0x2 [2] RW GPI2_MODE GPI_2 mode of operation, see Section 5.2.7. 0x0 = Single sequence 0x1 = Multi-sequence 0x0 [1:0] RW GPI2_POLARITY Selection which GPI edge triggers an event: 0x0 = Rising edge 0x1 = Falling edge 0x2 = Both edges 0x0 Table 57: MEM_CTL1 (0x002C) Bit Mod e Symbol Description Reset [7:0 RO WAV_MEM_BAS E_ADDR Snippet memory start address, see Section 5.8. 0x84 Table 58: MEM_CTL2 (0x002D) Bit Mode Symbol Description Reset [7] RW WAV_MEM_LOCK Lock bit for preventing access to Waveform Memory, see Section 5.6.4. 0x0 = Locked 0x1 = Unlocked 0x1 Table 59: ADC_DATA_H1 (0x002E) Bit Mode Symbol Description Reset [7:0] RO ADC_VDD_H Unsigned VDD measurement, see Section 5.7.13 𝑉𝐷𝐷 𝑆𝑢𝑝𝑝𝑙𝑦 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 = (𝐴𝐷𝐶_𝑉𝐷𝐷_𝐻 × 128 + 𝐴𝐷𝐶_𝑉𝐷𝐷_𝐿) × 0.1831𝑚𝑉 0xFF Table 60: ADC_DATA_L1 (0x002F) Bit Mod e Symbol Description Rese t [6:0] RO ADC_VDD_L Unsigned VDD measurement, see Section 5.7.13 𝑉𝐷𝐷 𝑆𝑢𝑝𝑝𝑙𝑦 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 = (𝐴𝐷𝐶_𝑉𝐷𝐷_𝐻 × 128 + 𝐴𝐷𝐶_𝑉𝐷𝐷_𝐿) × 0.1831𝑚𝑉 0x7F Table 61: POLARITY (0x0043) Bit Mode Symbol Description Reset [0] RO POLARITY Current polarity read-back, see Section 5.7.8 0x0

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 77 of 87 © 2022 Renesas Electronics Table 62: LRA_AVR_H (0x0044) Bit Mode Symbol Description Reset [7:0] RO LRA_PER_AVE RAGE_H MS-bits of the average LRA resonant period based on the last four half-periods, see Section 5.7.1. The following formula describes the output: 𝐿𝑅𝐴 𝑝𝑒𝑟𝑖𝑜𝑑 (𝑚𝑠) × 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝑉𝐸𝑅𝐴𝐺𝐸_𝐻 + 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝑉𝐸𝑅𝐴𝐺𝐸_𝐿) 0x0 Table 63: LRA_AVR_L (0x0045) Bit Mode Symbol Description Rese t [6:0] RO LRA_PER_AVERA GE_L LS-bits of the average LRA resonant period based on the last four half-periods, see Section 5.7.1. The following formula describes the output: 𝐿𝑅𝐴 𝑝𝑒𝑟𝑖𝑜𝑑 (𝑚𝑠) × 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝑉𝐸𝑅𝐴𝐺𝐸_𝐻 + 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝑉𝐸𝑅𝐴𝐺𝐸_𝐿) 0x0 Table 64: FRQ_LRA_PER_ACT_H (0x0046) Bit Mode Symbol Description Reset [7:0] RO LRA_PER_ACTUA L_H MS-bits of the actual LRA resonant period based on half- period, see Section 5.5.The following formula describes the output: 𝐿𝑅𝐴 𝑝𝑒𝑟𝑖𝑜𝑑 (𝑚𝑠) × 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝐶𝑇𝑈𝐴𝐿_𝐻 + 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝐶𝑇𝑈𝐴𝐿_𝐿) 0x21 Table 65: FRQ_LRA_PER_ACT_L (0x0047) Bit Mod e Symbol Description Rese t [6:0] RO LRA_PER_ACTUA L_L LSBs of the actual LRA resonant period based on half- period, see Section 5.5.The following formula describes the output: 𝐿𝑅𝐴 𝑝𝑒𝑟𝑖𝑜𝑑 (𝑚𝑠) × 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝐶𝑇𝑈𝐴𝐿_𝐻 + 𝐿𝑅𝐴_𝑃𝐸𝑅_𝐴𝐶𝑇𝑈𝐴𝐿_𝐿) 0x4F

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 78 of 87 © 2022 Renesas Electronics Table 66: FRQ_PHASE_H (0x0048) Bit Mode Symbol Description Reset [7:0] RW DELAY_H Used during custom waveform operation, see Section 5.7.5. Only use the following settings, all other settings are reserved: 0x0 = Setting for wideband mode 0x25 = Setting for closed-loop frequency tracking mode 0x25 Table 67: FRQ_PHASE_L (0x0049) Bit Mode Symbol Description Reset [7] RW DELAY_FREEZE Used during custom waveform operation. Set to 1 only in wideband mode with frequency tracking disabled, see Section 5.7.5 0x0 = Setting for closed-loop frequency tracking mode 0x1 = Setting for wideband mode 0x0 [2:0] RW DELAY_SHIFT_L Used during custom waveform operation, see Section 5.7.5. Only use the following settings, all other settings are reserved: 0x0 = Setting for wideband mode 0x5 = Setting for closed-loop frequency tracking mode 0x5 Table 68: FRQ_CTL (0x004C) Bit Mod e Symbol Description Reset [1] RW FREQ_TRACKING _AUTO_ADJ Enables the auto-scaling of the frequency tracking proportional coefficient, see Section 5.7.1. 0x0 = No auto-scaling 0x1 = Auto-scaling 0x1 [0] RW FREQ_TRACKING _FORCE_ON Force the tracking on when the error exceeds 25 % of initial guess, see Section 5.7.1. 0x0 = Off 0x1 = On 0x0 Table 69: TRIM3 (0x005F) Bit Mode Symbol Description Reset [6] RW LOOP_IDAC_DOU BLE_RANGE Loop IDAC double range control, see Section 5.7.12 0x0 [5] RW LOOP_FILT_LOW _BW Loop filter low bandwidth, see Section 5.7.9 0x0 [4:3] RW REF_UVLO_THRE S UVLO threshold, see Section 5.7.10 00 = 2.7 V 01 = 2.8 V 10 = 2.9 V 11 = 3.0 V 0x1

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 79 of 87 © 2022 Renesas Electronics Table 70: TRIM4 (0x0060) Bit Mode Symbol Description Reset [3:2] RW LOOP_FILT_CAP_ TRIM Loop capacitor trim, see Section 5.7.9 0x3 [1:0] RW LOOP_FILT_RES_ TRIM Loop resistance trim, see Section 5.7.9 0x0 Table 71: TRIM6 0x(0062) Bit Mode Symbol Description Reset [3:2] RW HBRIDGE_ERC_L S_TRIM Low side edge rate control setting, see Section 5.7.11. 00 = 25 mV/ns 01 = 50 mV/ns 10 = 75 mV/ns 11 = 100 mV/ns 0x3 [1:0] RW HBRIDGE_ERC_ HS_TRIM High side edge rate control setting, see Section 5.7.11 00 = 25 mV/ns 01 = 50 mV/ns 10 = 75 mV/ns 11 = 100 mV/ns 0x3 Table 72: D2602_TOP_CFG5 (0x006E) Bit Mode Symbol Description Reset [2] RW DELAY_BYPASS Delay comparator bypass enable 0x0 [1] RW FRQ_PAUSE_ON_ POLARITY_CHAN GE Pause the frequency update when the drive polarity changes (during rapid stop, negative accelaration, negative DRO value) 0x0 = Pause disabled 0x1 = Pause enabled 0x0 [0] RW V2I_FACTOR_OFF SET_EN Apply a 50 mV offset to the V2I factor calculation 0x0 = No offset applied 0x1 = 50 mV offset applied 0x1 Table 73: IRQ_EVENT_ACTUATOR_FAULT (0x0081) Bit Mode Symbol Description Reset [2] RO ADC_SAT_FAULT ADC produced saturated result, which is not expected to happen (write 1 to E_ACTUATOR to clear) 0x0 Table 74: IRQ_STATUS2 (0x0082) Bit Mode Symbol Description Reset [7] RO STA_ADC_SAT Status of ADC saturation fault: ADC_SAT_FAULT 0x0

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 80 of 87 © 2022 Renesas Electronics Table 75: IRQ_MASK2 (0x0083) Bit Mode Symbol Description Reset [7] RW ADC_SAT_M Masking for ADC saturation fault: ADC_SAT_FAULT 0x0 Register SNP_MEM_xx Table 76 shows the first, intermediary, and last snippet memory registers.

The snippet register addresses increment by 1 for each snippet.
The Bit ([7:0]), Mode (RW), and Reset (0x0) are identical for each snippet register.
For further details on the Waveform Memory, see Section 5.8. Table 76: SNP_MEM_xx (0x0084 to 0x00E7) Bit Mode Symbol Description Reset [7:0] RW SNP_MEM_00 Snippet memory byte 0 0x0 [7:0] RW SNP_MEM_xx Snippet memory byte x 0x0 [7:0] RW SNP_MEM_99 Snippet memory byte 99 0x0

7 Package Information

7.1 WLCSP Package Outline

Figure 40: WLCSP Package Outline Drawing

7.2 QFN Package Outline

Figure 41: QFN Package Outline Drawing

7.3 Moisture Sensitivity Level

The Moisture Sensitivity Level (MSL) is an indicator for the maximum allowable time period (floor lifetime) in which a moisture sensitive plastic device, once removed from the dry bag, can be exposed to an environment with a specified maximum temperature and a maximum relative humidity before the solder reflow process. The MSL classification is defined in Table 77. For detailed information on MSL levels refer to the IPC/JEDEC standard J-STD-020, which can be downloaded from http://www.jedec.org. The WLCSP package is qualified for MSL 1. The QFN package is qualified for MSL 3. Table 77: MSL Classification MSL Level Floor Lifetime Conditions MSL 4 72 hours 30 °C / 60 % RH MSL 3 168 hours 30 °C / 60 % RH MSL 2A 4 weeks 30 °C / 60 % RH MSL 2 1 year 30 °C / 60 % RH MSL 1 Unlimited 30 °C / 85 % RH

7.4 WLCSP Handling

Manual handling of WLCSP packages should be reduced to the absolute minimum. In cases where it is still necessary, a vacuum pick-up tool should be used. In extreme cases plastic tweezers could be used, but metal tweezers are not acceptable, since contact may easily damage the silicon chip. Removal of a WLCSP package will cause damage to the solder balls. Therefore a removed sample cannot be reused. WLCSP packages are sensitive to visible and infrared light. Precautions should be taken to properly shield the chip in the final product.

7.5 Soldering Information

Refer to the IPC/JEDEC standard J-STD-020 for relevant soldering information. This document can be downloaded from http://www.jedec.org.

8 Ordering Information

The ordering number consists of the part number followed by a suffix indicating the packing method. For details and availability, please consult Dialog Semiconductor’s customer support portal or your local sales representative. Table 78: Ordering Information Part Number Package Size (mm) Shipment Form Pack Quantity DA7282-00V42 WLCSP 1.35 x 1.75 Tape and reel 4500 DA7282-00V4C WLCSP 1.35 x 1.75 Tape and reel 250 DA7282-00FV2 QFN 3.0 x 3.0 Tape and reel 6000 DA7282-00FVC QFN 3.0 x 3.0 Tape and reel 250

9 Application Information

The Dialog SmartCanvas GUI enables easy access to the device and can be used to accelerate product development time. For further information, contact your Dialog Semiconductor representative. DA7282 GPI_0 / PWM GPI_1 GPI_2 VDDIO/EN GND_2 VDD GND_1 VDD SDA SCL LRA/ ERM nIRQ OUTN OUTP 100 nF VDDIO 5k6 Ω VDDIO 2k2 Ω 2k2 Ω Figure 42: External Components Diagram Note: Drive the GPI pins and the VDDIO/EN pin from the same voltage level. Note: Ground any unused GPI pins. Note: Capacitor C1 should be placed as close as possible to, and between VDD and GND_1 pins. It removes high-frequency noise only; ensure additional decoupling (typ. 10 µF) is included elsewhere in the system.

10 Layout Guidelines

For optimal layout, place the 100 nF capacitor as close to VDD and GND_1 pins as possible. It is also advisable to use solid a ground plane under the device. The QFN can be routed out on a single layer. It is recommended to connect GND_1 and GND_2 to a local ground plane on the top layer with a low-impedance via connection to the main ground plane, see Figure 44. nIRQ VIAVIA VIAVIA VIA TO VDD LAYER VIA TO GND LAYER SOLID GND CONNECTION ON TOP LAYER 100 nF Capacitor 0201 (0603) SCL SDA GPI_1 GPI_2 VDDIO/ EN GPI_0/ PWM OUTN GND_2 VDD OUTP GND_1 Figure 43: WLCSP Example PCB Layout VIAVIA VIAS TO GND LAYER SOLID GND CONNECTION ON TOP LAYER 100 nF Capacitor 0603 (1608) VIAVIA nIRQ SCL SDA VDDIO/EN OUTN GND_1 GND_2 OUTPVDD GPI_2 GPI_1 GPI_0/PWM Figure 44: QFN Example PCB Layout

Revision History

3.1 10-Feb-2022 Updated logo, disclaimer, copyright. 3.0 30-Jul-2019 Final datasheet Change details:

Renamed EN to VDDIO/EN throughout the document to better describe the purpose of the pin
Table 1: Added DA7283 details
Section 2 Pinout ○ Formatting changes to merge tables and use space better
Section 4.3 Electrical Characteristics ○ Table 8 Added parameter VDD_POR_FALL ○ Corrected pin name errors (ADDR to GPI)
Section 5.1 Features Description ○ Minor rewording to better describe part (also reflected on front page)
Section 5.7.1: Frequency Tracking ○ Added sentences regarding use of SmartCanvas GUI to adjust Kp and Ki coefficients ○ Added sentence regarding checking stability of closed loop to step response when optimizing Kp and Ki coefficients with FREQ_TRACK_AUTO_ADJ enabled
Section 5.7.1.9: VDDIO/EN Pin Control ○ Clarified description
Section 5.8: Waveform Memory ○ Added note recommending SmartCanvas GUI is used to construct and upload WM sequences
Section 5.8.1: Waveform Memory Structure ○ Figure 26: Replaced Sequence 1 with Sequence 0 and clarification of explanation
Section 5.8.2: Snippet Definition ○ Clarification of TIME and AMP definitions ○ Added note to explain snippet 0
Section 5.8 3: Frame Definition ○ Clarified Byte 1 and Byte 2 definitions ○ Clarified SNP_ID_LOOP [3:0] definition ○ Added notes explaining updating of frequencies
Section 5.8.4: Sequence Definition ○ Further clarification of sequences ○ Figure 30: Replaced Sequence 1 with Sequence 0
Section 5.9.1: DRO Mode ○ Clarification of full range
Section 5.9.3: RTWM and ETWM Modes ○ Clarification of full range
Section 6: Register Overview ○ Reset values (and associated descriptions) updates for the following addresses: 0x00, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x2C, 0x46, 0x47, and 0x5F
Section 7: Package Information ○ Updated both WLCSP and QFN package outline diagrams to rev E (only change is to title)
Section 9: Application Information

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory Datasheet Revision 3.1 10-Feb-2022 CFR0011-120-00 87 of 87 © 2022 Renesas Electronics Revision Date Description ○ Added Notes to clarify external components recommended

Back page: updated Disclaimer wording 1.0 07-Sept-2018 Initial version (Target datasheet) Status Definitions Revision Datasheet Status Product Status Definition 1.<n> Target Development This datasheet contains the design specifications for product development. Specifications may be changed in any manner without notice. 2.<n> Preliminary Qualification This datasheet contains the specifications and preliminary characterization data for products in pre-production. Specifications may be changed at any time without notice in order to improve the design. 3.<n> Final Production This datasheet contains the final specifications for products in volume production. The specifications may be changed at any time in order to improve the design, manufacturing and supply. Major specification changes are communicated via Customer Product Notifications. Datasheet changes are communicated via www.dialog-semiconductor.com. 4.<n> Obsolete Archived This datasheet contains the specifications for discontinued products. The information is provided for reference only. RoHS Compliance Dialog Semiconductor’s suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous substances in electrical and electronic equipment. RoHS certificates from our suppliers are available on request.

TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com Contact Information For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) © 2021 Renesas Electronics Corporation. All rights reserved.

Product Information

DA7282-00FV2 specifications and overview.

Summary

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory 10-Feb-2022

Description

LRA/ERM Ultra-Low Power Haptic Driver with Multiple Input Triggers and Integrated Waveform Memory 10-Feb-2022

Source title DA7282-00FV2 Datasheet(PDF) - Renesas Technology Corp

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DA7282 RENESAS | Alldatasheet

Document overview

Technical content

Applications

Contents

1 Terms and Definitions

2 Block Diagram

3 Pinout

Description

4 Characteristics

4.1 Absolute Maximum Ratings

4.2 Recommended Operating Conditions

4.3 Electrical Characteristics

10 MΩ, H-bridge switching

4.4 Timing Characteristics

4.5 Thermal Characteristics

5 Functional Description

5.1 Features Description

5.2 Functional Modes

5.2.1 System States

5.2.2 Operating Modes

5.2.3 Inactive Mode

5.2.4 Direct Register Override Mode

5.2.5 Pulse Width Modulation Mode

5.2.6 Register Triggered Waveform Memory Mode

5.2.6.1 I2C Triggering and Sequence Looping

5.2.7 Edge Triggered Waveform Memory Mode

5.3 Resonant Frequency Tracking

5.4 Active Acceleration and Rapid Stop

5.5 Wideband Frequency Control

5.6 Device Configuration and Playback

5.6.1 Boot

5.6.2 Actuator Setup

5.6.3 Automatic Output Control

5.6.4 Waveform Memory Setup

5.6.5 Mode Configuration

5.6.5.1 Inactive Mode

5.6.5.2 Direct Register Override (DRO) Mode

5.6.5.3 PWM Mode

5.6.5.4 Register Triggered Waveform Memory (RTWM) Mode

5.6.5.5 Edge Triggered Waveform Memory (ETWM) Mode

5.6.6 Events and Diagnostics

5.7 Advanced Operation

5.7.1 Frequency Tracking

5.7.2 Rapid Stop

5.7.3 Initial Impedance Update

5.7.4 Amplitude PID

5.7.5 Wideband Operation

5.7.6 Custom Waveform Operation

5.7.7 Embedded Operation

5.7.8 Polarity Change Reporting for Half-Period Control in DRO Mode

5.7.9 Loop Filter Configuration

5.7.10 UVLO Threshold

5.7.11 Edge Rate Control

5.7.12 Double Output Current Range

5.7.13 Supply Monitoring, Reporting, and Automatic Output Limiting

5.7.14 BEMF Fault Limit

5.7.15 Increasing Impedance Detection Accuracy

5.7.16 Frequency Pause during Rapid Stop

5.7.17 Frequency Pause during Rapid Stop

5.7.18 Coin ERM Operation

5.7.19 VDDIO/EN Pin Control

5.8 Waveform Memory

5.8.1 Waveform Memory Structure

100 Bytes

5.8.1.1 Header Section

5.8.1.2 Data Section

5.8.2 Snippet Definition

5.8.3 Frame Definition

1 GAIN[1:0] Gain applied to the snippet identified by SNP_ID_L/H:

1 SNP_ID_L[2:0] SNP_ID_L is mandatory and contains the LSBs of the snippet ID

2 SNP_ID_LOOP[3:0

2 FREQ_CMD If FREQ_CMD = 1, the frame is a 3-byte command with frequency

5.8.4 Sequence Definition

5.8.4.1 Pre-Stored Waveform Memory Example

5.9 General Data Format

5.9.1 DRO Mode

5.9.2 PWM Mode