D78044HGF

UPD78046H NEC | Alldatasheet

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Technical content

Datasheet sections

• 3.1 PORT PINS
• 3.2 PINS OTHER THAN PORT PINS
• 3.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS
• 5.1 PORTS
• 5.2 CLOCK GENERATOR CIRCUIT
• 5.3 TIMER/EVENT COUNTER
• 5.4 CLOCK OUTPUT CONTROL CIRCUIT
• 5.5 BUZZER OUTPUT CONTROL CIRCUIT
• 5.6 A/D CONVERTER
• 5.7 SERIAL INTERFACE
• 5.8 FIP CONTROLLER/DRIVER
• 6.1 INTERRUPT FUNCTION
• 6.2 TEST FUNCTION

8-BIT SINGLE-CHIP MICROCOMPUTER MOS INTEGR ATED CIRCUIT D ATA SHEET µPD78044H, 78045H, 78046H Documen t No. U10865EJ1V0DS00 (1st edition) Date Published August 1996 P Printed in Japan The µPD78044H, µPD78045H, and µPD78046H are µPD78044H sub-series products in the 78K/0 series. These microcomputers are advanced models of the µPD78044A sub-series, featuring the added N-ch open-drain I/O ports. In addition, the µPD78P048B (one-time PROM or EPROM model) that can operate in the same voltage range as that of the mask ROM models, and various development tools are provided. The functions of these microcomputers are described in detail in the following User’s Manual. Be sure to read this manual when you design a system using any of these microcomputers. µPD78044H Sub-Series User’s Manual : To be created 78K/0 Series User's Manual, Instruction: IEU-1372

FEATURES

• I/O ports: 68 (N-ch open-drain I/O: 13)
• High-capacity ROM and RAM Data memory FIP display RAM 48 bytes
• Serial interface: 1 channel
• Timer: 5 channels
• Power supply voltage: V DD = 2.7 to 5.5 V

APPLICATIONS

VCRs, audio systems, etc.

ORDERING INFORMATION

µPD78044HGF- ××× -3B9 80-pin plastic QFP (14 × 20 mm) µPD78045HGF- ××× -3B9 80-pin plastic QFP (14 × 20 mm) µPD78046HGF- ××× -3B9 80-pin plastic QFP (14 × 20 mm) Remar k ××× indicates ROM code number.

• Wide range of instruction execution time: From high-speed (0.4 µs) to ultra low-speed (122 µs)
• FIP controller/driver: total display outputs: 34
• 8-bit resolution A/D converter: 8 channels µPD78044H µPD78045H µPD78046H 32K bytes 40K bytes 48K bytes 1024 bytes Internal high-speed RAM Program memory (ROM)Product name Item The information in this document is subject to change without notice. The mark H shows major revised points. © 19901996

µPD78044H, 78045H, 78046H 78K/0 SERIES PRODUCT DEVELOPMENT The 78K/0 series products were developed as shown below. The sub-series names are indicated in frames. 100-pin 80-pin 80-pin 64-pin 64-pin 64-pin 42-/44-pin PD78078 PD78078Y PD78070A PD78070AY PD78054 PD78054Y PD78018F PD78018FY PD78014 PD78014Y PD780001 PD780208 PD78044F PD78024 100-pin 80-pin 80-pin 64-pin 100-pin 100-pin 100-pin A timer has been added to the PD78054 to enhance external interface functions. The I/O and FIP C/D of the PD78044F have been enhanced. Total indication output pins: 53 N-ch open-drain I/O ports have been added to the PD78044F. Total indication output pins: 34 The SIO of the PD78064 has been enhanced. ROM and RAM have been expanded. Basic sub-series for FIP driving. Total indication output pins: 26 Sub-series for LCD driving. These products include an UART. EMI noise-reduced version of the PD78064 PD780308 PD78098 PD780308Y Products being mass-produced Products under development Y sub-series products are compatible with the I2C bus. Used for control 78K/0 series For FIP driving For LCD driving Compatible with IEBusTM PD78002 PD78083 100-pin 100-pin 64-pin 80-pin ROM-less versions of the PD78078 The serial I/O of the PD78078 has been enhanced. The functions have been limited. EMI noise-reduced version of the PD78054 An UART and D/A converter have been added to the PD78014 to enhance I/O. Low-voltage (1.8 V) versions of the PD78014. ROM and RAM variations have been enhanced. An A/D converter and 16-bit timer have been added to the PD78002. An A/D converter has been added to the PD78002. Basic sub-series for control These products include an UART and can operate at a low voltage (1.8 V). A 6-bit U/D counter has been added to the PD78024. Total indication output pins: 34 PD78002Y µ µ PD780018Yµ µ µ µ µ µ µ PD780018µ PD78058F PD78058FYµµ µ µ µ µ µ µ µ PD78044Hµ µ µ µ PD78064Bµ µ PD78064 PD78064Yµµ µ An IEBus controller has been added to the PD78054. A PWM output, LV digital code decoder, and Hsync counter are incorporated.PD78P0914 For LV 64-pin µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ

µPD78044H, 78045H, 78046H The table below shows the main differences between sub-series. Sub-series name Function For control µPD78078 µPD78070A µPD780018 µPD78058F µPD78054 µPD78018F µPD78014 µPD780001 µPD78002 µPD78083 µPD780208 µPD78044F µPD78044H µPD78024 µPD780308 µPD78064B µPD78064 µPD78098 µPD78P0914 Timer 3ch (UART:1ch) 2ch 3ch (UART:1ch) 2ch 1ch 1ch (UART:1ch) 2ch 1ch 2ch 3ch (UART:1ch) 2ch (UART:1ch) 3ch (UART:1ch) 2ch External expan- sionWatch8-bit WDT ROM capacity 32K-60K 48K-60K 48K-60K 16K-60K 8K-60K 8K-32K 8K-16K 32K-60K 16K-40K 32K-48K 24K-32K 48K-60K 32K 16K-32K 32K-60K 32K 4ch 2ch 2ch 2ch 2ch 6ch 16-bit 1ch 1ch 1ch 1ch 1ch 8ch 8ch 8ch 8ch 8ch 8ch 2ch 2ch 2ch 8-bit A/D 8-bit D/A Serial interface Minimum V DD I/O For LV Compatible with IEBus For LCD driving For FIP driving 1ch 1ch 1ch 1ch 1ch 88 pins 61 pins 88 pins 69 pins 53 pins 39 pins 53 pins 33 pins 74 pins 68 pins 54 pins 57 pins 69 pins 54 pins 1ch 1ch 1ch 1ch 1.8 V 2.7 V 2.0 V 1.8 V 2.7 V 1.8 V 2.7 V 1.8 V 2.0 V 2.7 V 4.5 V

µPD78044H, 78045H, 78046H FUNCTIONAL OUTLINE Internal memory Item Product name Instruction cycle ROM Internal high-speed RAM FIP display RAM General registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Variable instruction execution time For subsystem clock 122 µs (at 32.768 kHz) Instruction set • Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits)

• Bit (set, reset, test, Boolean algebra) I/O ports (including those Total : 68 lines multiplexed with FIP pins) • CMOS input : 2 lines
• CMOS I/O : 19 lines
• N-ch open-drain : 13 lines
• P-ch open-drain I/O : 16 lines
• P-ch open-drain output : 18 lines FIP controller/driver Total : 34 lines
• Segments : 9 to 24 lines
• Digits : 2 to 16 lines A/D converter • 8-bit resolution × 8 channels
• Power supply voltage: AV DD = 4.0 to 5.5 V Serial interface • 3-wire serial I/O mode : 1 channel Timer • 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer : 1 channel
• Watchdog timer : 1 channel Timer output 3 lines (one for 14-bit PWM output) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz (main system clock: when operating at 5.0 MHz) 32.768 kHz (subsystem clock: when operating at 32.768 kHz) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz (main system clock: when operating at 5.0 MHz) Maskable interrupt Internal 8 lines, external 4 lines Non-maskable interrupt Internal 1 line Software interrupt 1 line Text input Internal 1 line Power supply voltage V DD = 2.7 to 5.5 V Package 80-pin plastic QFP (14 × 20 mm) Vectored interrupt µPD78044H µPD78045H µPD78046H 32K bytes 1024 bytes 48 bytes 40K bytes 48K bytes

µPD78044H, 78045H, 78046H 1. PIN CONFIGURATION (TOP VIEW)

• 80-pin plastic QFP (14 × 20 mm) µPD78044HGF- ××× -3B9, µPD78045HGF- ××× -3B9, µPD78046HGF- ××× -3B9 Cautions 1. Connect the IC (Internally Connected) pins directly to the VSS . 2. Connect the AVDD pin to the VDD pin. 3. Connect the AVSS pin to the VSS pin. P34 P33 P37 P36/BUZ P35/PCL 6571 70 69 68 67 6680 79 78 77 76 75 74 73 72 P95/FIP7 P112/FIP20 P96/FIP8 P97/FIP9 P113/FIP21 P100/FIP10 P101/FIP11 P102/FIP12 P103/FIP13 P104/FIP14 P105/FIP15 V LOAD P106/FIP16 P107/FIP17 P110/FIP18 P111/FIP19 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AV DD AV REF P04/XT1 XT2 VSS 25 4026 27 28 29 30 31 32 33 34 35 36 37 38 39 P114/FIP22 P71 P115/FIP23 P116/FIP24 P72 P117/FIP25 P120/FIP26 P121/FIP27 P122/FIP28 P123/FIP29 P124/FIP30 P125/FIP31 P126/FIP32 P127/FIP33 V DD P70 P31/TO1 P32/TO2 IC P00/INTP0/TI0 P01/INTP1 P02/INTP2 P03/INTP3 P30/TO0 P94/FIP6 P21/SO1 P93/FIP5 P92/FIP4 P20/SI1 P91/FIP3 P90/FIP2 P81/FIP1 P80/FIP0 V DD P27 P26 P25 P24 P23 P22/SCK1 P15/ANI5 P14/ANI4 RESET P74 P73 AV SS P17/ANI7 P16/ANI6

µPD78044H, 78045H, 78046H P00-P04 : Port 0 P10-P17 : Port 1 P20-P27 : Port 2 P30-P37 : Port 3 P70-P74 : Port 7 P80, P81 : Port 8 P90-P97 : Port 9 P100-P107 : Port 10 P110-P117 : Port 11 P120-P127 : Port 12 INTP0-INTP3 : Interrupt from peripherals TI0 : Timer input TO0-TO2 : Timer output SI1 : Serial input SO1 : Serial output SCK1 : Serial clock PCL : Programmable clock BUZ : Buzzer clock FIP0-FIP33 : Fluorescent indicator panel V LOAD : Negative power supply X1, X2 : Crystal (main system clock) XT1, XT2 : Crystal (subsystem clock) RESET : Reset ANI0-ANI7 : Analog input AV DD : Analog power supply AV SS : Analog ground AV REF : Analog reference voltage VDD : Power supply VSS : Ground IC : Internally connected

µPD78044H, 78045H, 78046H 2. BLOCK DIAGRAM Remark The capacity of the internal ROM differs depending on the product. TO0/P30 TI0/INTP0/P00 TO1/P31 P33 TO2/P32 P34 SI1/P20 SO1/P21 SCK1/P22 ANI0/P10- ANI7/P17 AV DD AV SS AV REF INTP0/TI0/P00- INTP3/P03 BUZ/P36 PCL/P35 16-bit timer/ event counter 8-bit timer/ event counter 1 8-bit timer/ event counter 2 Watchdog timer Watch timer Serial interface 1 A/D converter Interrupt control Buzzer output Clock output control VDD VSS IC RAM 1024 bytes 78K/0 CPU core ROM Port 0 Port 2 Port 3 Port 7 Port 8 Port 9 Port 10 Port 12 FIP controller/driver System control P00 P01-P03 P04 P10-P17 P20-P27 P30-P37 P70-P74 P80, P81 P90-P97 P100-P107 P110-P117 P120-P127 FIP0-FIP33 V LOAD RESET XT1/P04 XT2 Port 1 Port 11

µPD78044H, 78045H, 78046H 3. PIN FUNCTIONS

3.1 PORT PINS (1/2)

Can be specified for input or output in 1-bit units. When used as an input port pin, a built-in pull-up resistor can be connected through software. Note 2 Port 2 8-bit I/O port Can be specified for input or output in 1-bit units. When used as an input port pin, a built-in pull-up resistor can be connected through software. Notes 1.When the P04/XT1 pin is used as an input port pin, bit 6 (FRC) of the processor clock control register (PCC) must be set to 1. At this time, do not use the feedback resistor of the subsystem clock oscillator circuit. 2. When the P10/ANI0 through P17/ANI7 pins are used as the analog input lines of the A/D converter, be sure to place the port 1 in the input mode. In this case, the built-in pull-up resistors are automatically unused. Pin P00 P01 P02 P03 P04 Note 1 P10-P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 Port 0 5-bit I/O port Input only Can be specified for input or output in 1- bit units. When used as an input port pin, a built-in pull-up resistor can be connected through software. Input only Function Port 3 N-ch open-drain 8-bit I/O port Can be specified for input or output in 1-bit units. Can directly drive LEDs. A built-in pull-up resistor can be connected in 1-bit units by the mask option. Input I/O Input I/O I/O I/O I/O Shared by:On reset Input Input Input Input Input Input INTP0/TI0 INTP1 INTP2 INTP3 XT1 ANI0-ANI7 SI1 SO1 SCK1 TO0 TO1 TO2 PCL BUZ

µPD78044H, 78045H, 78046H

3.1 PORT PINS (2/2)

Pin I/O Function On reset Shared by: P70-P74 I/O Port 7 Input — 5-bit N-ch open-drain I/O port Can be specified for input or output in 1-bit units. Can directly drive LEDs. A pull-up resistor can be connected in 1-bit units by the mask option. P80, P81 Output Port 8 Output FIP0, FIP1 2-bit P-ch open-drain high-voltage output port. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether V LOAD or VSS is connected can be specified in 2-bit units). P90-P97 Output Port 9 Output FIP2-FIP9 8-bit P-ch open-drain high-voltage output port. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether V LOAD or VSS is connected can be specified in 4-bit units). P100-P107 Output Port 10 Output FIP10-FIP17 8-bit P-ch open-drain high-voltage output port. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether V LOAD or VSS is connected can be specified in 4-bit units). P110-P117 I/O Port 11 Input FIP18-FIP25 8-bit P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit units. Can directly drive LEDs A pull-down resistor can be connected in 1-bit units by the mask option (whether V LOAD or VSS is connected can be specified in 4-bit units). P120-P127 I/O Port 12 Input FIP26-FIP33 8-bit P-ch open-drain high-voltage I/O port Can be specified for input or output in 1-bit units. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by the mask option (whether V LOAD or VSS is connected can be specified in 4-bit units).

µPD78044H, 78045H, 78046H

3.2 PINS OTHER THAN PORT PINS

On reset Shared by: Input P00/TI0 P01 P02 Input P03 Input P20 Input P21 Input P22 Input P00/INTP0 Input P30 P31 P32 Input P35 Input P36 Output P80, P81 P90-P97 Output P100-P105 Output P106, P107 Input P110-P117 P120-P127 Input P10-P17 Input P04 ANI0-ANI7 Input A/D converter analog input lines AV REF Input A/D converter reference voltage input line AV DD — Analog power supply to A/D converter. Connected to the VDD pin. AV SS — A/D converter ground line. Connected to the VSS pin. RESET Input System reset input X1 Input Connect crystal for main system clock oscillation X2 — XT1 Input Connect crystal for subsystem clock oscillation XT2 — V DD — Positive power supply VSS — Ground potential IC — Internal connection. Connected directly to the V SS pin. Pin I/O Function INTP0 Input Valid edge (rising, falling, or both rising and falling edges) can INTP1 be specified. INTP2 External interrupt input INTP3 Falling edge-active external interrupt input SI1 Input Serial data input lines of serial interface SO1 Output Serial data output lines of serial interface SCK1 I/O Serial clock I/O lines of serial interface TI0 Input External count clock input to 16-bit timer (TM0) TO0 Output 16-bit timer output (multiplexed with 14-bit PWM output) TO1 8-bit timer (TM1) output TO2 8-bit timer (TM2) output PCL Output Clock output (for trimming main system clock and subsystem clock) BUZ Output Buzzer output FIP0, FIP1 Output High-voltage, high-current digit/segment output of FIP FIP2-FIP9 controller/driver FIP10-FIP15 Output High-voltage, high-current digit/segment output of FIP controller/driver FIP16, FIP17 Output High-voltage segment output of FIP controller/driver FIP18-FIP25 FIP26-FIP33 VLOAD — Connects pull-down resistor to FIP controller/driver

µPD78044H, 78045H, 78046H

3.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS

Table 3-1 shows the I/O circuit type of each pin and the processing of unused pins. For the configuration of the I/O circuit of each type, see Fig. 3-1. Table 3-1 I/O Circuit Type P00/INTP0/TI0 2 Input Connected to V SS . P01/INTP1 8-A I/O Individually connected to V SS with a resistor. P02/INTP2 P03/INTP3 P04/XT1 16 Input Connected to V DD or VSS . P10/ANI0-P17/ANI7 11 I/O Individually connected to VDD or VSS with a resistor. P20/SI1 8-A P21/SO1 5-A P22/SCK1 8-A P23 5-A P24 8-A P25 10-A P26 P27 P30/TO0 13-B P31/TO1 P32/TO2 P33 22-A P34 P35/PCL 13-B P36/BUZ P37 P70-P74 P80/FIP0, P81/FIP1 14-A Output Open P90/FIP2-P97/FIP9 P100/FIP10-P107/FIP17 P110/FIP18-P117/FIP25 15-C I/O Individually connected to VDD or VSS with a resistor. P120/FIP26-P127/FIP33 RESET 2 Input — XT2 16 — Open AV REF — Connected to V SS. AV DD Connected to VDD. AV SS Connected to VSS. VLOAD IC Connected directly to V SS. Pin I/O circuit type I/O Recommended connections when unused

µPD78044H, 78045H, 78046H Fig. 3-1 Pin I/O Circuits (1/2) Type 2 Type 10-A Type 8-A Type 13-B Type 11Type 5-A IN Schmitt trigger input with hysteresis characteristics (Threshold voltage)VREF Pull-up enable Data Output disable VDD P-ch P-ch N-ch P-ch N-ch Input enable VDD IN/OUT Comparator P-ch N-ch VDD Pull-up enable Data IN/OUT Open-drain Output disable VDD P-ch Data Output disable RD Input buffer with intermediate withstand voltage IN/OUT VDD N-ch VDD P-ch (Mask option) VDD VDD P-ch P-ch N-ch IN/OUT Pull-up enable Data Output disable Input enable VDD VDD Pull-up enable Data Output disable P-ch IN/OUT N-ch P-ch

µPD78044H, 78045H, 78046H Fig. 3-1 Pin I/O Circuits (2/2) Type 14-A Type 16 Type 22-AType 15-C VDD VDD P-ch P-ch N-ch Data OUT (Mask option) (Mask option) VLOAD P-ch Feedback cut-off XT1 XT2 Data Output disable RD Input buffer with intermediate withstand voltage IN/OUT VDD N-ch VDD P-ch (Mask option) VDD VDD Data N-ch P-ch P-ch IN/OUT VLOAD (Mask option) (Mask option) N-chRD

µPD78044H, 78045H, 78046H Note The internal ROM capacity varies depending on the product. (See the table below.) 4. MEMORY SPACE Fig. 4-1 shows the memory map for µPD78044H, µPD78045H, and µPD78046H. Fig. 4-1 Memory Map µPD78044H µPD78045H µPD78046H 7FFFH 9FFFH BFFFH Last address of internal ROM nnnnH Product name FFFFH FF00H FEFFH FEE0H FEDFH nnnnH+1 nnnnH 0000H nnnnH 1000H 0FFFH 0800H 07FFH 0080H 007FH 0040H 003FH 0000H Special function register (SFR) 256 × 8 bits General-purpose register 32 × 8 bits Internal high-speed RAM 1024 × 8 bits FIP display RAM 48 × 8 bits Internal ROM Note CALLF entry area Program area CALLT table area Inhibited Program area Vector table area Data memory space Program memory space Inhibited FB00H FAFFH FA80H FA7FH FA50H FA4FH

µPD78044H, 78045H, 78046H 5. PERIPHERAL HARDWARE FUNCTIONS

5.1 PORTS

I/O ports are classified into the following 5 kinds:

• CMOS input (P00, P04) : 2
• CMOS input/output (P01 - P03, ports 1 and 2) : 19
• N-ch open-drain input/output (ports 3 and 7) : 13
• P-ch open-drain output (ports 8 - 10) : 18
• P-ch open-drain input/output (ports 11 and 12) : 16 Total : 68 Table 5-1 Port Function Product Pin Function Port 0 P00, P04 Input port P01-P03 I/O port. Can be specified for input or output in 1-bit units. When used as input port, built-in pull-up resistor can be connected through software. Port 1 P10-P17 I/O port. Can be specified for input or output in 1-bit units. When used as input port, built-in pull-up resistor can be connected through software. Port 2 P20-P27 I/O port. Can be specified for input or output in 1-bit units. When used as input port, built-in pull-up resistor can be connected through software. Port 3 P30-P37 N-ch open-drain I/O port. Can be specified for input or output in 1-bit units. Built-in pull-up resistor can be connected in 1-bit units by the mask option. Can directly drive LED. Port 7 P70-P74 N-ch open-drain I/O port. Can be specified for input or output in 1-bit units. Built-in pull-up resistor can be connected in 1-bit units by the mask option. Can directly drive LED. Port 8 P80, P81 P-ch open-drain high-voltage output port. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 2-bit units). Can directly drive LED. Port 9 P90-P97 P-ch open-drain high-voltage output port. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LED. Port 10 P100-P107 P-ch open-drain high-voltage output port. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LED. Port 11 P110-P117 P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit units. Pull-down resistor can be connected in 1-bit units by the mask option (connection to V LOAD or VSS can be specified in 4-bit units). Can directly drive LED. Port 12 P120-P127 P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit units. Pull-down resistor can be connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LED.

µPD78044H, 78045H, 78046H

5.2 CLOCK GENERATOR CIRCUIT

The clock generator circuit has two kinds of generator circuits: the main system clock and subsystem clock. The instruction time can be changed.

• 0.4
• 122 µs (with subsystem clock: 32.768 kHz) Fig. 5-1 Clock Generator Circuit Block Diagram

5.3 TIMER/EVENT COUNTER

Five channels of timer/event counters are provided.

• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer : 1 channel
• Watchdog timer : 1 channel Table 5-2 Timer/Event Counter Groups and Configurations Function Group 16-bit timer/ 8-bit timer/ Watch Watchdog event counter event counter timer timer Interval timer 1 channel 2 channels 1 channel 1 channel External event counter 1 channel — — — Timer output 1 output 2 outputs — — PWM output 1 output — — — Pulse width measurement 1 input — — — Square wave output 1 output 2 outputs — — Interrupt request 1 2 1 1 Test input — — 1 input — Subsystem clock generator circuit Main system clock generator circuit Pre-scaler Selector Pre-scaler To INTP0 sampling clock Standby control circuit CPU clock ( fCPU ) Clock to hardware peripherals Clock output circuit fXT fX XT1/P04 XT2 fX fX fX fX STOP fXT Selector Noise eliminator Selector Watch timer fX fX

µPD78044H, 78045H, 78046H Fig. 5-2 16-Bit Timer/Event Counter Block Diagram Fig. 5-3 8-Bit Timer/Event Counter Block Diagram Internal bus Internal bus 8-bit compare register (CR10) 8-bit compare register (CR20) 8-bit timer register 2 (TM2) 8-bit timer register 1 (TM1) Output control circuit Match Match SelectorSelector Selector Selector Selector Clear TO1/P31 INTTM2 TO2/P32 INTTM1 fX/212 fX/2 -fX/210 fX/2 -fX/210 fX/212 Clear Output control circuit Internal bus 16-bit compare register (CR00) 16-bit timer register (TM0) 16-bit capture register (CR01) Internal bus PWM pulse output control circuit Selector 16-bit timer/event counter output control circuit Edge detector circuit Match Selector ClearTI0/P00/INTP0 fX/23 fX/22 fX/2 INTP0 TO0/P30 INTTM0 fX

µPD78044H, 78045H, 78046H Fig. 5-5 Watchdog Timer Block Diagram Fig. 5-4 Watch Timer Block Diagram Pre-scaler Selector RESET Selector Control circuit 8-bit counter INTWDT Maskable interrupt request INTWDT Nonmaskable interrupt request fX fX fWDT fWDT fWDT fWDT fWDT fWDT fWDT fWDT Pre-scaler 5-bit counter Selector Selector Selector Selector fX/28 fXT fW fW fW fW fW fW fW fW 213 fW 214 INTWT INTTM3

µPD78044H, 78045H, 78046H

5.4 CLOCK OUTPUT CONTROL CIRCUIT

Clocks of the following frequencies can be output to the clock:

• 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz (with main system clock: 5.0 MHz)
• 32.768 kHz (with subsystem clock: 32.768 kHz) Fig. 5-6 Clock Output Control Circuit Block Diagram

5.5 BUZZER OUTPUT CONTROL CIRCUIT

Clocks of the following frequencies can be output to the buzzer:

• 1.2 kHz/2.4 kHz/4.9 kHz (with main system clock: 5.0 MHz) Fig. 5-7 Buzzer Output Control Circuit Block Diagram fX /23 fX /24 fX /25 fX /26 fX /27 fX /28 fXT Selector PCL/P35Sync circuit Output control circuit fX /2 fX /211 fX /212 Selector Output control circuit BUZ/P36

µPD78044H, 78045H, 78046H

5.6 A/D CONVERTER

An 8-bit resolution 8-channel A/D converter is provided. This A/D converter can be started in the following two modes:

• Hardware start
• Software start Fig. 5-8 A/D Converter Block Diagram ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 INTP3/P03 INTAD INTP3 AV SS AV REF AV DD Sample-and-hold circuit Voltage comparator Successive approximation register (SAR) Series resistor string Falling edge detector circuit Control circuit A/D conversion result register (ADCR) Internal bus Tap selector Selector

µPD78044H, 78045H, 78046H

5.7 SERIAL INTERFACE

One channel of clocked serial interfaces is provided. Serial interface channel 1 can be operated in the 3-wire serial I/O mode, where the MSB or LSB is selectable as the first bit. Fig. 5-9 Serial Interface Channel 1 Block Diagram Internal bus SI1/P20 SCK1/P22 SO1/P21 Serial I/O shift register 1 (SIO1) Serial clock counter Interrupt request signal generator Serial clock control circuit Selector fX/22-fX/29 TO2 INTCSI1

µPD78044H, 78045H, 78046H Caution If the total number of digits and segments exceeds 34, the specified number of digits takes precedence.

5.8 FIP CONTROLLER/DRIVER

An FIP controller/driver having the following features is provided: (a) Automatic output of segment signals (DMA operation) and digit signals by automatically reading display data (b) Display mode registers (DSPM0 and DSPM1) that can control an FIP of 9 to 24 segments and 2 to 16 digits (c) Port pins not used for FIP display can be used as output port or I/O port pins. (d) Display mode register (DSPM1) can adjust luminance in eight steps. (e) Hardware suitable for key scan application using segment pins (f) High-voltage output buffer (FIP driver) that can directly drive an FIP (g) Display output pins can be connected to a pull-down resistor by the mask option. Fig. 5-10 Selecting Display Modes 0 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 6 Selecting number of digits Selecting number of segments

µPD78044H, 78045H, 78046H Fig. 5-11 FIP Controller/Driver Block Diagram Internal bus Display data memory Segment data latchDigit signal generator circuit Port output latch High-voltage buffer FIP0/P80FIP1/P81 FIP33/P127

µPD78044H, 78045H, 78046H Interrupt source 6. INTERRUPT FUNCTION AND TEST FUNCTION

6.1 INTERRUPT FUNCTION

The following three types of interrupt functions are available:

• Non-maskable interrupt : 1
• Maskable interrupt : 12
• Software interrupt : 1 Table 6-1 Interrupt Source List Non-maskable Maskable Software Interrupt type Note 1 Default priority Name Trigger Internal/ external Vector table address Note 2 Basic configura- tion type 0004H 0006H 0008H 000AH 000CH 0010H 0012H 0014H 0016H 0018H 001AH 001CH 003EH Internal External Internal INTWDT INTWDT INTP0 INTP1 INTP2 INTP3 INTCSI1 INTTM3 INTTM0 INTTM1 INTTM2 INTAD INTKS BRK (A) (B) (C) (D) (B) (E) Watchdog timer overflow (with watchdog timer mode 1 selected) Watchdog timer overflow (with interval timer mode selected) Pin input edge detection End of serial interface channel 1 transfer Reference time interval signal from watch timer 16-bit timer/event counter match signal generation 8-bit timer/event counter 1 match signal generation 8-bit timer/event counter 2 match signal generation End of A/D converter conversion Key scan timing from FIP controller/driver Execution of BRK instruction Notes 1.Default priority is the priority order when several maskable interrupts are generated at the same time. 0 is the highest order and the 11 is the lowest order. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Fig. 6-1.

µPD78044H, 78045H, 78046H Fig. 6-1 Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt (B) Internal maskable interrupt (C) External maskable interrupt (INTP0) Internal bus Interrupt request Priority control circuit Vector table address generator circuit Standby release signal Internal bus Interrupt request Priority control circuit Vector table address generator circuit Standby release signal MK IE PR ISP IF Internal bus MK IE PR ISP IFInterrupt request Standby release signal Priority control circuit Vector table address generator circuit Sampling clock select register (SCS) External interrupt mode register (INTM0) Sampling clock Edge detector circuit

µPD78044H, 78045H, 78046H Fig. 6-1 Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except INTP0) (E) Software interrupt IF : Interrupt request flag IE : Interrupt enable flag ISP: In-service priority flag MK: Interrupt mask flag PR : Priority specification flag Internal bus MK IE PR ISP IFInterrupt request Standby release signal Priority control circuit Vector table address generator circuit External interrupt mode register (INTM0) Edge detector circuit Internal bus Priority control circuit Vector table address generator circuit Interrupt request

µPD78044H, 78045H, 78046H IF : Test request flag MK: Test mask flag Test input source Internal/external Name Trigger INTWT Overflow of watch timer Internal Fig. 6-2 Basic Configuration of Test Function

6.2 TEST FUNCTION

The following test function is available. Internal bus MK IF Test input source (INTWT) Standby release signal

µPD78044H, 78045H, 78046H 7. STANDBY FUNCTION The standby function is to reduce the current dissipation of the system and can be effected in the following two modes:

• HALT mode : In this mode, the operating clock of the CPU is stopped. By using this mode in combination with the normal operation mode, the system can be operated intermittently, so that the average current dissipation can be reduced.
• STOP mode : Oscillation of the main system clock is stopped. All the operations on the main system clock are stopped, and therefore, the current dissipation of the system can be minimized with only the subsystem clock oscillating. Fig. 7-1 Standby Function Note By stopping the main system clock, the current dissipation can be reduced. When the CPU operates on the subsystem clock, stop the main system clock by setting bit 7 (MCC) of the processor clock control register (PCC). The STOP instruction cannot be used. Caution When the main system clock is stopped and the subsystem clock is operating, to switch again from the subsystem clock to the main system clock, allow sufficient time for the oscillation to settle before switching, by coding the program accordingly. 8. RESET FUNCTION The system can be reset in the following two modes:
• External reset by RESET pin
• Internal reset by watchdog timer that detects hang up STOP mode (Oscillation of main system clock stopped) Main system clock operation Subsystem clock operationNote HALT mode (Clock supply to CPU stopped. Oscillation continues) HALT mode Note (Clock supply to CPU stopped. Oscillation continues) STOP instruction Interrupt request Interrupt request Interrupt request CSS=0 CSS=1 HALT instruction HALT instruction

µPD78044H, 78045H, 78046H 9. INSTRUCTION SET (1) 8-bit instruction MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Second operand [HL + byte] #byte A r Note sfr saddr !addr16 PSW [DE] [HL] [HL + B] $addr16 1 None First [HL + C] operand A ADD MOV MOV MOV MOV MOV MOV MOV MOV ROR ADDC XCH XCH XCH XCH XCH XCH XCH ROL SUB ADD ADD ADD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP r MOV MOV INC ADD DEC ADDC SUB SUBC AND OR XOR CMP B, C DBNZ sfr MOV MOV saddr MOV MOV DBNZ INC ADD DEC ADDC SUB SUBC AND OR XOR CMP !addr16 MOV PSW MOV MOV PUSH POP [DE] MOV [HL] MOV ROR4 ROL4 [HL + byte] MOV [HL + B] [HL + C] X MULU C DIVUW Note Except for r = A

µPD78044H, 78045H, 78046H Note (2) 16-bit instruction MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second operand #word AX rp Note sfrp saddrp !addr16 SP None First operand AX ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW rp MOVW MOVW INCW DECW PUSH POP sfrp MOVW MOVW saddrp MOVW MOVW !addr16 MOVW SP MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second operand First operand A.bit MOV1 BT SET1 BF CLR1 BTCLR sfr.bit MOV1 BT SET1 BF CLR1 BTCLR saddr.bit MOV1 BT SET1 BF CLR1 BTCLR PSW.bit MOV1 BT SET1 BF CLR1 BTCLR [HL].bit MOV1 BT SET1 BF CLR1 BTCLR CY MOV1 MOV1 MOV1 MOV1 MOV1 SET1 AND1 AND1 AND1 AND1 AND1 CLR1 OR1 OR1 OR1 OR1 OR1 NOT1 XOR1 XOR1 XOR1 XOR1 XOR1

µPD78044H, 78045H, 78046H (4) Call/branch instruction CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second operand AX !addr16 !addr11 [addr5] $addr16 First operand Basic operation BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT operation BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP

µPD78044H, 78045H, 78046H 10. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) Parameter Symbol Conditions Rating Unit Power supply V DD voltage VLOAD AV DD AV REF AV SS Input voltage V I1 P00-P04, P10-P17 (except when used as analog input pins), P20-P27, X1, X2, XT2, RESET VI2 P30-P37, P70-P74 N-ch open drain VI3 P110-P117, P120-P127 P-ch open drain Output voltage V O1 P01-P03, P10-P17, P20-P27 VO2 P30-P37, P70-P74 VO3 P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 Analog input voltageVAN ANI0-ANI7 Analog input pin Output current, IOH P01-P03, P10-P17, P20-P27 per pin high P01-P03, P10-P17, P20-P27 total P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 per pin P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 total Output current, IOL P01-P03, P10-P17, P20-P27, P30-P37, Peak value low P70-P74 per pin rms value P70-P74 total Peak value rms value P01-P03, P10-P17, P20-P27, P30-P37 total Peak value rms value Total power P TNote 3 TA = –40 to +60 °C dissipation T A = +85 °C Operating T A ambient temperature Storage T stg temperature –0.3 to +7.0 VDD – 40 to VDD + 0.3 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –0.3 to +0.3 –0.3 to VDD + 0.3 –0.3 to +16Note 1 VDD – 40 to VDD + 0.3 –0.3 to VDD + 0.3 –0.3 to +16Note 1 VDD – 40 to VDD + 0.3 AV SS – 0.3 to AVREF + 0.3 –10 –30 –30 –120 Note 2 100 60Note 2 100 60Note 2 800 600 –40 to +85 –65 to +150 V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mW mW Caution Exposure to Absolute Maximum Ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics. Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of the correspond- ing port pin. Notes 1.For pins to which pull-up resistors are connected by the mask option, the rating is –0.3 to V DD + 0.3. 2. To obtain the rms value, calculate [rms value] = [peak value] × √duty.

µPD78044H, 78045H, 78046H Notes 3.Permissible total power loss differs depending on the temperature (see the following figure). How to calculate total power loss The power consumption of the µPD78044H, µPD78045H, and µPD78046H can be classified into the three categories shown below. The sum of the three categories should be less than the total power loss PT (80 % or less of ratings is recommended). CPU power consumption: calculate VDD (MAX.) × IDD1 (MAX.). Output pin power consumption: Normal output and display output are available. Power consumption when maximum current flows into each output pin. Pull-down resistor power consumption: Power consumption by pull-down resistor connected to display output pin by the mask option. –40 0 +40 +80 200 400 600 800 Temperature [°C] Total power loss PT [mW]

µPD78044H, 78045H, 78046H The following total power consumption calculation example assumes the case where the characters shown in the figure on the next page are displayed. Example: The operating conditions are as follows: VDD = 5 V ±10 %, operating at 5.0 MHz Supply current (IDD ) = 21.6 mA Display outputs: 11 grids × 10 segments (cut width is 1/16) It is assumed that up to 15 mA flows to each grid pin, and that up to 3 mA flows to each segment pin. It is also assumed that all display outputs are turned off at key scan timings. Display output voltage: grid V O3 = VDD – 2 V (Voltage drop of 2 V is assumed.) segment V O3 = VDD – 0.4 V (Voltage drop of 0.4 V is assumed.) Voltage applied to fluorescent indication panel (VLOAD ) = –30 V Mask-option pull-down resistor = 25 kΩ The total power loss is calculated by determining power consumption 1 to 3 under the above conditions. Power consumption of CPU: 5.5 V × 21.6 mA = 118.8 mW

2 Power consumption at output pins:

total current for all grids Grid: (V DD – VO3 ) × × digit width (1 – cut width) = number of grids + 1 15 mA × 11 grids 2 V × × (1 – 1/16) = 25.8 mW11 grids + 1 total segment current for all dots to be lit Segment: (VDD – VO3 ) × = number of grids + 1 3 mA × 31 dots 0.4 V × = 3.1 mW11 grids + 1

3 Power consumption at pull-down resistors:

Grid: (V O3 – VLOAD )2 number of grids × × digit width =pull-down resistance number of grids + 1 (5.5 V – 2 V – (–30 V))2 11 grids × × (1 – 1/16) = 38.6 mW25 kΩ 11 grids + 1 Segment: (V O3 – VLOAD )2 number of dots to be lit × =pull-down resistance number of grids + 1 (5.5 V – 0.4 V – (–30 V))2 31 dots × = 127.3 mW25 kΩ 11 grids + 1 Total power consumption = 1 In this example, the total power consumption does not exceed the rated value for the permissible total power loss shown in the graph on the previous page. Therefore, the calculation result in this example (313.6 mW) satisfies the requirement. If the total power consumption exceeds the rated value for the permissible total power loss, the power consumption must be reduced, by reducing the number of built-in pull-down resistors.

µPD78044H, 78045H, 78046H 10-Segment/11-Digit Display Example T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 AM i PM j j j f e g d b c aSUN MON TUE WED THU FRI SAT 12345 6 789 1 00 i S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 abcdefgh i j Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 FA7AH FA6AH FA79H FA69H FA78H FA68H FA77H FA67H FA76H FA66H FA75H FA65H FA74H FA64H FA73H FA63H FA72H FA62H FA71H FA61H FA70H FA60H Display data memory FA6 × H FA7 × H h

µPD78044H, 78045H, 78046H MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Notes 1.It indicates only the oscillator characteristics. For the instruction execution time, see the AC Charac- teristics. 2. Time required until oscillation becomes stable after VDD is applied or the STOP mode is disabled. Cautions 1. If the main system clock oscillator is to be used, wire the area inside the broken line square as follows to avoid influence of wiring capacitance:

• Make wiring as short as possible.
• Do not cross other signal lines.
• Do not get close to lines with fluctuating large current.
• Make sure that the connecting points of the capacitor of the oscillator always have the same electric potential as V SS .
• Do not connect the oscillator to a ground pattern that conducts a large current.
• Do not take out signal from the oscillator. 2. When switching to the main system clock again after the subsystem clock has been used with the main system clock stopped, be sure to set the program to provide enough time for the oscillation to stabilize. Resonator Recommended circuit Parameter Conditions MIN. TYP. MAX. Unit Ceramic Oscillation frequency 1 5 MHz resonator (f X)Note 1 Oscillation settling 4 ms time Note 2 Crystal Oscillation frequency 1 4.19 5 MHz (fX)Note 1 Oscillation settling V DD = 4.5 to 5.5 V 10 ms timeNote 2 External X1 input frequency 1 5 MHz clock (f X)Note 1 X1 input high, low-level 100 500 ns width (tXH , tXL) X1 X2 PD74HCU04µ VSS X1 X2 C2C1 VSS X1 X2 C2C1

µPD78044H, 78045H, 78046H SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Notes 1.It indicates only the oscillator characteristics. For the instruction execution time, see the AC Charac- teristics. 2. Time required until oscillation becomes stable after VDD reaching MIN. of oscillation voltage range. Cautions 1. If the subsystem clock oscillator is to be used, wire the area inside the broken line square as follows to avoid influence of wiring capacitance:

• Make wiring as short as possible.
• Do not cross other signal lines.
• Do not get close to lines with fluctuating large current.
• Make sure that the connecting points of the capacitor of the oscillator always have the same electric potential as V SS .
• Do not connect the oscillator to a ground pattern that conducts a large current.
• Do not take out signal from the oscillator. 2. The subsystem clock oscillator is more likely to have malfunctions due to noise than the main system clock oscillator because gain for the subsystem clock oscillator is made lower to reduce current consumption. When using the subsystem clock, be careful about how to connect wires. XT1 XT2 Resonator Recommended circuit Parameter Conditions MIN. TYP. MAX. Unit Crystal Oscillation frequency 32 32.768 35 kHz (fXT )Note 1 Oscillation settling V DD = 4.5 to 5.5 V 1.2 2 s timeNote 2 External XT1 input frequency 32 100 kHz (fXT )Note 1 XT1 input high, low- 5 15 µs level width (tXTH , tXTL ) XT1 XT2 C4C3 VSS R

µPD78044H, 78045H, 78046H Manufacturer Product name Frequency Recommended Oscillator voltage range Remark (MHz) circuit constant C1 (pF) C2 (pF) MIN. (V) MAX. (V) CSA2.00MG040 2.00 100 100 2.7 5.5 CST2.00MG040 2.00 — — 2.7 5.5 Built-in capacitor CSA4.00MG 4.00 30 30 2.7 5.5 CST4.00MGW 4.00 — — 2.7 5.5 Built-in capacitor CSA5.00MG 5.00 30 30 2.7 5.5 CST5.00MGW 5.00 — — 2.7 5.5 Built-in capacitor TDK Corp. CCR1000K2 1.00 150 150 2.7 5.5 Surface-mount type CCR2.0MC3 2.00 — — 2.7 5.5 Built-in capacitor, surface-mount type CCR4.0MC3 4.00 — — 2.7 5.5 Built-in capacitor, surface-mount type FCR4.0MC5 4.00 — — 2.7 5.5 Built-in capacitor CCR5.0MC3 5.00 — — 2.7 5.5 Built-in capacitor, surface-mount type FCR5.0MC5 5.00 — — 2.7 5.5 Built-in capacitor Matsushita Electronics EFOEC2004A4 2.00 33 33 2.7 5.5 Built-in capacitor surface-mount type EFOEC3584A4 3.58 33 33 2.7 5.5 Built-in capacitor EFOS3584B5 3.58 33 33 2.7 5.5 Built-in capacitor, surface-mount type EFOEC4004A4 4.00 33 33 2.7 5.5 Built-in capacitor EFOS4004B5 4.00 33 33 2.7 5.5 Built-in capacitor, surface-mount type EFOEC5004A4 5.00 33 33 2.7 5.5 Built-in capacitor EFOS5004B5 5.00 33 33 2.7 5.5 Built-in capacitor, surface-mount type RECOMMENDED OSCILLATOR CONSTANT MAIN SYSTEM CLOCK: CERAMIC RESONATOR (T A = –40 to +85 °C) Note When the CSB1000J (1.00 MHz) manufactured by Murata Mfg. is used, a limiting resistor (4.7 kΩ ) is necessary (see the figure in the next page). When one of other resonators is used, no limiting resistor is required. Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator that being used.

µPD78044H, 78045H, 78046H Recommended sample circuit for the main system clock when the CSB1000J manufactured by Murata Mfg. is used CAPACITANCE (TA = 25 °C, VDD = VSS = 0 V) Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of the correspond- ing port pin. POWER SUPPLY VOLTAGE (TA = –40 to +85 °C) Notes 1.Except for system clock oscillator, display controller/driver, and PWM. 2. Operating power supply voltage differs depending on the cycle time. See the AC Characteristics. CSB1000J VSS VDD X2X1 Rd C2C1 Parameter Symbol Conditions MIN. TYP. MAX. Unit Input C IN f = 1 MHz Unmeasured pins returned to 0 V 15 pF capacitance Output C OUT f = 1 MHz Unmeasured pins returned to 0 V 35 pF capacitance Input/output C IO f = 1 MHz P01-P03, P10-P17, 15 pF capacitance Unmeasured pins returned to 0 V P20-P27 P30-P37, P70-P74 20 pF P110-P117, P120-P127 35 pF Parameter Conditions MIN. TYP. MAX. Unit CPU Note 1 2.7Note 2 5.5 V Display controller/driver 4.5 5.5 V PWM mode of 16-bit 4.5 5.5 V timer/event counter (TM0) A/D converter 4.0 5.5 V Other hardware 2.7 5.5 V

µPD78044H, 78045H, 78046H DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Notes 1.Pins to which pull-up resistors are connected by the mask option become VDD . 2. If the X1 pin is used for high-level voltage input, the X2 pin is used for low-level voltage input, or vice versa. This is also true for the XT1/P04 pin and XT2 pin. Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of the correspond- ing port pin. Conditions High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage V IH1 VIH2 VIH3 VIH4 VIH5 VIH6 VIH7 VIL1 VIL2 VIL3 VIL4 VIL5 VIL6 VIL7 VOH VOL1 VOL2 P21, P23 P00-P03, P20, P22, P24-P27, RESET P30-P37, P70-P74 N-ch open drain X1, X2Note 2 XT1/P04, XT2Note 2 VDD = 4.5 to 5.5 V P10-P17 V DD = 4.5 to 5.5 V P110-P117, P120-P127 V DD = 4.5 to 5.5 V P21, P23 P00-P03, P20, P22, P24-P27, RESET P30-P37, P70-P74 V DD = 4.5 to 5.5 V X1, X2Note 2 XT1/P04, XT2Note 2 VDD = 4.5 to 5.5 V P10-P17 P110-P117, P120-P127 P01-P03, P10-P17, P20-P27, P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 P30-P37, P70-P74 P01-P03, P10-P17, P20-P27 I OL = 400 µA VDD = 4.5 to 5.5 V IOH = –1 mA IOH = –100 µA VDD = 4.5 to 5.5 V, IOL = 15 mA VDD = 4.5 to 5.5 V, IOL = 1.6 mA Parameter Symbol MAX. 0.7VDD 0.8VDD 0.7VDD VDD – 0.5 VDD – 0.5 VDD – 0.3 0.65VDD 0.7VDD 0.7VDD VDD – 0.5 VDD – 35 VDD – 1.0 VDD – 0.5 VDD VDD 15Note 1 VDD VDD VDD VDD VDD VDD VDD 0.3VDD 0.2VDD 0.3VDD 0.2VDD 0.4 0.4 0.3 0.3VDD 0.3VDD 2.0 0.4 0.5 V V V V V V V V V V V V V V V V V V V V V V V V 0.4 UnitTYP.MIN.

µPD78044H, 78045H, 78046H DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Notes 1.When P110 to P117 and P120 to P127 do not contain the pull-down resistors (according to the specification of the mask option), a high-level input leakage current of 150 µA (MAX.) flows only during 1.5 clocks after a read instruction has been executed to read out port 11 or 12 (P11 or P12) or port mode register 11 or 12 (PM11 or PM12). Outside the 1.5 clocks after a read instruction, the current is 3 µA (MAX.). 2. When P110 to P117 and P120 to P127 do not contain the pull-down resistors (according to the specification of the mask option), a high-level input leakage current of 90 µA (MAX.) flows only during 1.5 clocks after a read instruction has been executed to read out P11, P12, PM11, or PM12. Outside the 1.5 clocks after a read instruction, the current is 3 µA (MAX.). 3. When P30 to P37 and P70 to P74 do not contain the pull-down resistors (according to the specification of the mask option), a low-level input leakage current of –150 µA (MAX.) flows only during 1.5 clocks after a read instruction has been executed to read out port 3 or 7 (P3 or P7) or port mode register 3 or 7 (PM3 or PM7). Outside the 1.5 clocks after a read out instruction, the current is –3 µA (MAX.). 4. Current which flows in the built-in pull-up or pull-down resistor is not included. Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin. ILIH1 ILIH2 ILIH3 ILIH4 ILIL1 ILIL2 ILIL3 ILIL4 ILOH1 ILOH2 ILOL1 ILOL2 IOD R 1 R 2 R 3 R 4 Parameter Symbol High-level input leakage current Low-level input leakage current High-level output leakage current Note 4 Low-level output leakage current Note 4 Display output current Mask option pull-up resistor Software pull- up resistor Mask option pull-down resistor Conditions Unit 3Note 1 3Note 2 –20 –3Note 3 –10 –10 500 135 150 –15 –25 TYP.MIN. MAX. µA µA µA µA µA µA µA µA µA µA µA µA µA mA kΩ kΩ kΩ kΩ kΩ kΩ VIN = VDD VIN = 15 V P110-P117, P120-P127, VIN = VDD VIN = 0 V VOUT = VDD VOUT = 15 V VOUT = 0 V VOUT = VLOAD = VDD – 35 V VDD = 4.5 to 5.5 V, VO3 = VDD – 2 V VIN = 0 V, P30-P37, P70-P74 VIN = 0 V, P01-P03, P10-P17, P20-P27 P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 V IN = VDD P00-P03, P10-P17, P20-P27, RESET X1, X2, XT1/P04, XT2 P30-P37, P70-P74 VDD = 4.5 to 5.5 V P00-P03, P10-P17, P20-P27, RESET X1, X2, XT1/P04, XT2 P30-P37, P70-P74 P110-P117, P120-P127 P01-P03, P10-P17, P20-P27, P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 P30-P37, P70-P74 P01-P03, P10-P17, P20-P27, P30-P37, P70-P74 P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 VDD = 4.5 to 5.5 V VO3 – VLOAD = 35 V VO3 – VSS = 5 V

µPD78044H, 78045H, 78046H DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power supply IDD1 5.0 MHz crystal oscillation V DD = 5.0 V ±10 % Note 2 7.2 21.6 mA currentNote 1 Operating mode VDD = 3.0 V ±10 % Note 3 0.9 2.7 mA IDD2 5.0 MHz crystal oscillation V DD = 5.0 V ±10 % 1.3 3.9 mA HALT mode VDD = 3.0 V ±10 % 550 1650 µA IDD3 32.768 kHz crystal oscillation VDD = 5.0 V ±10 % 60 120 µA Operating modeNote 4 VDD = 3.0 V ±10 % 35 70 µA IDD4 32.768 kHz crystal oscillation VDD = 5.0 V ±10 % 25 50 µA HALT mode Note 4 VDD = 3.0 V ±10 % 5 10 µA IDD5 XT1 = 0 V VDD = 5.0 V ±10 % 1 20 µA STOP mode Feedback resistor connected VDD = 3.0 V ±10 % 0.5 10 µA IDD6 XT1 = 0 V VDD = 5.0 V ±10 % 0.1 20 µA STOP mode Feedback resistor not connectedVDD = 3.0 V ±10 % 0.05 10 µA Notes 1.This current excludes the AVREF current, port current, and current which flows in the built-in pull-down resistor (mask option). 2. When operating in high-speed mode (when the processor clock control register (PCC) is set to 00H) 3. When operating in low-speed mode (when the PCC is set to 04H) 4. When the main system clock is stopped

µPD78044H, 78045H, 78046H AC CHARACTERISTICS (1) Basic operation (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) Notes 1.Value when external clock input is used as subsystem clock. When a crystal is used, the value becomes 114 µs. 2. Selection of fsam = fX/2N+1 , fX/64, or fX/128 is available (N = 0 to 4) by bits 0 and 1 (SCS0, SCS1) of the sampling clock select register (SCS). TCY vs. VDD (with main system clock operated) Conditions VDD = 4.5 to 5.5 V SymbolParameter Unit 122 MIN. TYP. MAX. Cycle time (minimum instruction execution time) Interrupt input high, low-level width RESET low- level width T CY tINTH tINTL tRSL Operated with main system clock Operated with subsystem clock INTP0 INTP1-INTP3 0.4 0.8 Note 1 8/fsam Note 2 125 µs µs µs µs µs µs 6531 2.0 Power supply voltage VDD [V] Cycle time TCY [ s] 1.0 0.5 0.4 Operation guarantee range µ

µPD78044H, 78045H, 78046H (2) Serial interface channel 1 (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V) (a) Three-wire serial I/O mode (SCK1: Internal clock output) Note C is a load capacitance of the SCK1 or SO1 output line. (b) Three-wire serial I/O mode (SCK1: External clock input) Note C is a load capacitance of the SO1 output line. Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK1 cycle time t KCY1 VDD = 4.5 to 5.5 V 800 ns 3200 ns SCK1 high, low-level width t KH1 VDD = 4.5 to 5.5 V tKCY1 /2 – 50 ns tKL1 tKCY1 /2 – 150 ns SI1 setup time to SCK1↑ tSIK1 100 ns SI1 hold time from SCK1↑ tKSI1 400 ns SCK1 ↓→ SO1 output delay t KSO1 C = 100 pFNote VDD = 4.5 to 5.5 V 300 ns time 1000 ns Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK1 cycle time t KCY2 VDD = 4.5 to 5.5 V 800 ns 3200 ns SCK1 high, low-level width t KH2 VDD = 4.5 to 5.5 V 400 ns tKL2 1600 ns SI1 setup time to SCK1↑ tSIK2 VDD = 4.5 to 5.5 V 100 ns SI1 hold time from SCK1↑ tKSI2 400 ns SCK1 ↓→ SO1 output delay t KSO2 C = 100 pFNote VDD = 4.5 to 5.5 V 300 ns time 1000 ns SCK1 rise time and fall time tR2 160 ns tF2

µPD78044H, 78045H, 78046H AC timing test points (except X1, XT1 input) Clock timing Serial transfer timing 3-wire serial I/O mode: 0.8VDD 0.2VDD 0.8VDD 0.2VDD Test points 1/fX tXL tXH VIH4 (Min.) VIL4 (Max.)X1 input XT1 input VIH5 (Min.) VIL5 (Max.) 1/fXT tXTL tXTH Input data tKSO1, 2 Output dataSO1 SI1 SCK1 tR2 tF2 tKCY1, 2 tKL1, 2 tSIK1, 2 tKH1, 2 tKSI1, 2

µPD78044H, 78045H, 78046H A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, AVDD = VDD = 4.0 to 5.5 V, AVSS = VSS = 0 V) Notes 1.Quantization error (±1/2LSB) is not included. This parameter is indicated as the ratio to the full-scale value. 2. Set the A/D conversion time to 19.1 µs or more. 3. Sampling time depends on the conversion time. Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 8 8 8 bit Total errorNote 1 0.8 % Conversion timeNote 2 tCONV 1 MHz ≤ fX ≤ 5.0 MHz 19.1 200 µs Sampling timeNote 3 tSAMP 2.86 30 µs Analog signal input V IAN AV SS AV REF V voltage Reference voltage AV REF 4.0 AV DD V AV REF resistor R AVREF 41 4 k Ω AV DD current AI DD 200 400 µA

µPD78044H, 78045H, 78046H DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = –40 to +85 °C) Note Selection of 212/fX, 214/fX to 217/fX is available by bits 0 to 2 (OSTS0 to OSTS2) of the oscillation settling time select register (OSTS). Data retention timing (STOP mode release by RESET) Data retention timing (standby release signal: STOP mode release by interrupt signal) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply VDDDR 2.0 5.5 V voltage Data retention supply IDDDR VDDDR = 2.0 V 0.1 10 µA current Subsystem clock stopped Feedback resistor not connected Release signal set time tSREL 0 µs Oscillation settling time tWAIT Release by RESET 2 17/fX ms Release by interrupt Note ms STOP mode Data retention mode tWAIT Operating mode HALT mode STOP instruction execution VDDDR VDD Standby release signal (interrupt request) tSREL STOP mode Data retention mode tWAIT Operating mode HALT mode Internal reset operation STOP instruction execution VDDDR VDD RESET tSREL

µPD78044H, 78045H, 78046H Interrupt input timing RESET input timing tINTL INTP0-INTP2 tINTH tINTL INTP3 RESET tRSL

µPD78044H, 78045H, 78046H 11. PACKAGE DRAWING Remark The shape and material of the ES version are the same as those of the corresponding mass-produced product. NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. detail of lead end M F G H I J K M LN P Q R ITEM MILLIMETERS INCHES S P80GF-80-3B9-3 3.0 MAX. 0.119 MAX. –0.009 –0.008 P 2.7 0.106 N 0.10 0.004 M 0.15 0.006 +0.004 –0.003 –0.008 –0.008 G F 0.8 1.0 0.031 0.039 I 0.15 0.006 H 0.35±0.10 0.014 +0.004 –0.005 +0.10 –0.05 65 40 A B CD S R5 °±5° 5°±5°

80 PIN PLASTIC QFP (14 20)

µPD78044H, 78045H, 78046H 12. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the µ PD78044H, µPD78045H, or µPD78046H. For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Table 12-1 Soldering Conditions for Surface-Mount Devices µPD78044HGF- ××× -3B9: 80-pin plastic QFP (14 × 20 mm) µPD78045HGF- ××× -3B9: 80-pin plastic QFP (14 × 20 mm) µPD78046HGF- ××× -3B9: 80-pin plastic QFP (14 × 20 mm) Caution Do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections). Soldering process Soldering conditions Recommended conditions Infrared ray reflow Peak package's surface temperature: 235 °C IR35-00-3 Reflow time: 30 seconds or less (210 °C or more) Maximum allowable number of reflow processes: 3 VPS Peak package's surface temperature: 215 °C VP15-00-3 Reflow time: 40 seconds or less (200 °C or more) Maximum allowable number of reflow processes: 3 Wave soldering Solder temperature: 260 °C or less WS60-00-1 Flow time: 10 seconds or less Number of flow processes: 1 Preheating temperature : 120 °C max. (measured on the package surface) Partial heating method Terminal temperature: 300 °C or less — Heat time: 3 seconds or less (for one side of a device)

µPD78044H, 78045H, 78046H APPENDIX A DEVELOPMENT TOOLS The following tools are available for development of systems using the µPD78044H, µPD78045H, or µPD78046H. Language processing software RA78K/0 Notes 1, 2, 3, 4 Assembler package common to 78K/0 series CC78K/0 Notes 1, 2, 3, 4 C compiler package common to 78K/0 series DF78044 Notes 1, 2, 3, 4 Device file used in common with µPD78044A subseries CC78K/0-LNotes 1, 2, 3, 4 C compiler library source file common to 78K/0 series PROM writing tools PG-1500 PROM programmer PA-78P048GF Programmer adapter connected to PG-1500 PA-78P048KL-S PG-1500 controllerNotes 1, 2 Control program for PG-1500 Debugging tools IE-78000-R In-circuit emulator common to 78K/0 series IE-78000-R-ANote 8 In-circuit emulator common to 78K/0 series (for integrated debugger) IE-78000-R-BK Break board common to 78K/0 series IE-78044-R-EM Emulation board used in common with µPD78044A subseries EP-78130GF-R Emulation probe used in common with µPD78134 EV-9200G-80 Socket mounted on target system created for 80-pin plastic QFP SM78K0 Notes 5, 6, 7 System simulator common to 78K/0 series ID78K0Notes 4, 5, 6, 7, 8 Integrated debugger for IE-78000-R-A SD78K/0 Notes 1, 2 Screen debugger for IE-78000-R DF78044 Notes 1, 2, 5, 6, 7 Device file used in common with µPD78044A subseries Real-time OS RX78K/0 Notes 1, 2, 3, 4 Real-time OS for 78K/0 series MX78K0 Notes 1, 2, 3, 4 OS for 78K/0 series Notes 1.PC-9800 series (MS-DOSTM ) based 2. IBM PC/AT TM and compatible (PC DOSTM /IBM DOS TM /MS-DOS) based 3. HP9000 series 300TM (HP-UXTM ) based 4. HP9000 series 700 TM (HP-UX) based, SPARCstationTM (SunOS TM ) based, EWS4800 series (EWS-UX/V) based 5. PC-9800 series (MS-DOS + WindowsTM ) based 6. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based 7. NEWS TM (NEWS-OS TM ) based 8. Under development

µPD78044H, 78045H, 78046H Fuzzy inference development support system FE9000 Note 1/FE9200Note 3 Fuzzy knowledge data creation tool FT9080 Note 1/FT9085Note 2 Translator FI78K0Notes 1, 2 Fuzzy inference module FD78K0 Notes 1, 2 Fuzzy inference debugger Notes 1.PC-9800 series (MS-DOS) based 2. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS) based 3. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party develop- ment tools. 2. RA78K/0, CC78K/0, SM78K/0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF78044.

µPD78044H, 78045H, 78046H APPENDIX B RELATED DOCUMENTS

• Documents Related to Devices Document name Document No. Japanese English µPD78044H Sub-Series User’s Manual To be prepared To be prepared µPD78044H, 78045H, 78046H Data Sheet U10865J This manual µPD78P048B Product Information To be prepared To be prepared 78K/0 Series User’s Manual, Instruction IEU-849 IEU-1372 78K/0 Series Instruction Summary Sheet U10903J — 78K/0 Series Instruction Set U10904J —
• Documents Related to Development Tools (User’s Manual) Document name Document No. Japanese English RA78K Series Assembler Package Operation EEU-809 EEU-1399 Language EEU-815 EEU-1404 RA78K Series Structured Assembler Preprocessor EEU-817 EEU-1402 CC78K Series C Compiler Operation EEU-656 EEU-1280 Language EEU-655 EEU-1284 CC78K/0 Compiler Application Note Programming Know-How EEA-618 EEA-1208 CC78K Series Library Source File EEU-777 — PG-1500 PROM Programmer EEU-651 EEU-1335 PG-1500 Controller PC-9800 Series (MS-DOS) Base EEU-704 EEU-1291 PG-1500 Controller IBM PC Series (PC DOS) Base EEU-5008 U10540E IE-78000-R EEU-810 U11376E IE-78000-R-A U10057J U10057E IE-78000-R-BK EEU-867 EEU-1427 IE-78044-R-EM EEU-833 EEU-1424 EP-78130GF-R EEU-943 EEU-1470 SM78K0 System Simulator Reference EEU-5002 U10181E SM78K Series System Simulator External Parts User Open U10092J U10092E Interface Specifications ID78K0 Integrated Debugger Reference U11151J — SD78K/0 Screen Debugger Tutorial EEU-852 U10539E PC-9800 Series (MS-DOS) Base Reference U10952J — SD78K/0 Screen Debugger Tutorial EEU-5024 EEU-1414 IBM PC/AT (PC DOS) Base Reference U11279J EEU-1413 Caution The above documents may be revised without notice. Use the latest versions when you design an application system.

µPD78044H, 78045H, 78046H

• Documents Related to Software to Be Incorporated into the Product (User’s Manual) Document name Document No. Japanese English 78K/0 Series Real-Time OS Basic EEU-912 — Installation EEU-911 — Technical EEU-913 — OS for 78K/0 Series MX78K0 Basic EEU-5010 — Tool for Creating Fuzzy Knowledge Data EEU-829 EEU-1438 78K/0, 78K/II, and 87AD Series Fuzzy Inference Development EEU-862 EEU-1444 Support System, Translator 78K/0 Series Fuzzy Inference Development Support System, EEU-858 EEU-1441 Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System, EEU-921 EEU-1458 Fuzzy Inference Debugger
• Other Documents Document name Document No. Japanese English IC PACKAGE MANUAL C10943X SMD Surface Mount Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Device IEI-620 IEI-1209 NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Electrostatic Discharge (ESD) Test MEM-539 — Guide to Quality Assurance for Semiconductor Device MEI-603 MEI-1202 Guide for Products Related to Micro-Computer: Other Companies MEI-604 — Caution The above documents may be revised without notice. Use the latest versions when you design an application system.

µPD78044H, 78045H, 78046H Cautions on CMOS Devices Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins. Also handle boards on which MOS devices are mounted in the same way.

2 CMOS-specific handling of unused input pins

Caution Hold CMOS devices at a fixed input level. Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediate- level input may be caused by noise. This allows current to flow in the CMOS device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the V DD or GND pin through a resistor. If handling of unused pins is documented, follow the instructions in the document.

3 Statuses of all MOS devices at initialization

Caution The initial status of a MOS device is unpredictable when power is turned on. Since characteristics of a MOS device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. NEC has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. However, NEC assures operation after reset and items for mode setting if they are defined. When you turn on a device having a reset function, be sure to reset the device first. FIP is a trademark of NEC Corporation. IEBus is trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of SONY Corporation.

µPD78044H, 78045H, 78046H NEC Electronics Inc. (U.S.) Mountain View, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics (France) S.A. France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics (Germany) GmbH Scandinavia Office Taeby Sweden Tel: 8-63 80 820 Fax: 8-63 80 388 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:

• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. J96. 3

µPD78044H, 78045H, 78046H Note that “preliminary” is not indicated in this document, even though the related documents may be preliminary versions. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5